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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Processors: MK64FN1M0VDC12
Kojto 90:cb3d968589d8 4 ** MK64FN1M0VLL12
Kojto 90:cb3d968589d8 5 ** MK64FN1M0VLQ12
Kojto 90:cb3d968589d8 6 ** MK64FN1M0VMD12
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 9 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 10 ** GNU C Compiler
Kojto 90:cb3d968589d8 11 ** GNU C Compiler - CodeSourcery Sourcery G++
Kojto 90:cb3d968589d8 12 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 13 **
Kojto 90:cb3d968589d8 14 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 15 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 16 ** Build: b140604
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Abstract:
Kojto 90:cb3d968589d8 19 ** CMSIS Peripheral Access Layer for MK64F12
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 22 ** All rights reserved.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 25 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 26 **
Kojto 90:cb3d968589d8 27 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 28 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 29 **
Kojto 90:cb3d968589d8 30 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 31 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 32 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 33 **
Kojto 90:cb3d968589d8 34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 35 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 36 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 37 **
Kojto 90:cb3d968589d8 38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 48 **
Kojto 90:cb3d968589d8 49 ** http: www.freescale.com
Kojto 90:cb3d968589d8 50 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 51 **
Kojto 90:cb3d968589d8 52 ** Revisions:
Kojto 90:cb3d968589d8 53 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 54 ** Initial version.
Kojto 90:cb3d968589d8 55 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 56 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 57 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 58 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 59 ** System initialization updated.
Kojto 90:cb3d968589d8 60 ** MCG - registers updated.
Kojto 90:cb3d968589d8 61 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 62 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 63 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 64 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 65 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 66 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 67 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 68 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 69 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 70 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 73 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 76 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 77 **
Kojto 90:cb3d968589d8 78 ** ###################################################################
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80
Kojto 90:cb3d968589d8 81 /*!
Kojto 90:cb3d968589d8 82 * @file MK64F12.h
Kojto 90:cb3d968589d8 83 * @version 2.5
Kojto 90:cb3d968589d8 84 * @date 2014-02-10
Kojto 90:cb3d968589d8 85 * @brief CMSIS Peripheral Access Layer for MK64F12
Kojto 90:cb3d968589d8 86 *
Kojto 90:cb3d968589d8 87 * CMSIS Peripheral Access Layer for MK64F12
Kojto 90:cb3d968589d8 88 */
Kojto 90:cb3d968589d8 89
Kojto 90:cb3d968589d8 90
Kojto 90:cb3d968589d8 91 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 92 -- MCU activation
Kojto 90:cb3d968589d8 93 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 94
Kojto 90:cb3d968589d8 95 /* Prevention from multiple including the same memory map */
Kojto 90:cb3d968589d8 96 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */
Kojto 90:cb3d968589d8 97 #define MK64F12_H_
Kojto 90:cb3d968589d8 98 #define MCU_MK64F12
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100 /* Check if another memory map has not been also included */
Kojto 90:cb3d968589d8 101 #if (defined(MCU_ACTIVE))
Kojto 90:cb3d968589d8 102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
Kojto 90:cb3d968589d8 103 #endif /* (defined(MCU_ACTIVE)) */
Kojto 90:cb3d968589d8 104 #define MCU_ACTIVE
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 #include <stdint.h>
Kojto 90:cb3d968589d8 107
Kojto 90:cb3d968589d8 108 /** Memory map major version (memory maps with equal major version number are
Kojto 90:cb3d968589d8 109 * compatible) */
Kojto 90:cb3d968589d8 110 #define MCU_MEM_MAP_VERSION 0x0200u
Kojto 90:cb3d968589d8 111 /** Memory map minor version */
Kojto 90:cb3d968589d8 112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
Kojto 90:cb3d968589d8 113
Kojto 90:cb3d968589d8 114 /**
Kojto 90:cb3d968589d8 115 * @brief Macro to calculate address of an aliased word in the peripheral
Kojto 90:cb3d968589d8 116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
Kojto 90:cb3d968589d8 117 * 0x400FFFFF).
Kojto 90:cb3d968589d8 118 * @param Reg Register to access.
Kojto 90:cb3d968589d8 119 * @param Bit Bit number to access.
Kojto 90:cb3d968589d8 120 * @return Address of the aliased word in the peripheral bitband area.
Kojto 90:cb3d968589d8 121 */
Kojto 90:cb3d968589d8 122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
Kojto 90:cb3d968589d8 123 /**
Kojto 90:cb3d968589d8 124 * @brief Macro to access a single bit of a peripheral register (bit band region
Kojto 90:cb3d968589d8 125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Kojto 90:cb3d968589d8 126 * be used for peripherals with 32bit access allowed.
Kojto 90:cb3d968589d8 127 * @param Reg Register to access.
Kojto 90:cb3d968589d8 128 * @param Bit Bit number to access.
Kojto 90:cb3d968589d8 129 * @return Value of the targeted bit in the bit band region.
Kojto 90:cb3d968589d8 130 */
Kojto 90:cb3d968589d8 131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Kojto 90:cb3d968589d8 132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
Kojto 90:cb3d968589d8 133 /**
Kojto 90:cb3d968589d8 134 * @brief Macro to access a single bit of a peripheral register (bit band region
Kojto 90:cb3d968589d8 135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Kojto 90:cb3d968589d8 136 * be used for peripherals with 16bit access allowed.
Kojto 90:cb3d968589d8 137 * @param Reg Register to access.
Kojto 90:cb3d968589d8 138 * @param Bit Bit number to access.
Kojto 90:cb3d968589d8 139 * @return Value of the targeted bit in the bit band region.
Kojto 90:cb3d968589d8 140 */
Kojto 90:cb3d968589d8 141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Kojto 90:cb3d968589d8 142 /**
Kojto 90:cb3d968589d8 143 * @brief Macro to access a single bit of a peripheral register (bit band region
Kojto 90:cb3d968589d8 144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Kojto 90:cb3d968589d8 145 * be used for peripherals with 8bit access allowed.
Kojto 90:cb3d968589d8 146 * @param Reg Register to access.
Kojto 90:cb3d968589d8 147 * @param Bit Bit number to access.
Kojto 90:cb3d968589d8 148 * @return Value of the targeted bit in the bit band region.
Kojto 90:cb3d968589d8 149 */
Kojto 90:cb3d968589d8 150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Kojto 90:cb3d968589d8 151
Kojto 90:cb3d968589d8 152 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 153 -- Interrupt vector numbers
Kojto 90:cb3d968589d8 154 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 /*!
Kojto 90:cb3d968589d8 157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Kojto 90:cb3d968589d8 158 * @{
Kojto 90:cb3d968589d8 159 */
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /** Interrupt Number Definitions */
Kojto 90:cb3d968589d8 162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 typedef enum IRQn {
Kojto 90:cb3d968589d8 165 /* Core interrupts */
Kojto 90:cb3d968589d8 166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
Kojto 90:cb3d968589d8 167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
Kojto 90:cb3d968589d8 168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
Kojto 90:cb3d968589d8 169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
Kojto 90:cb3d968589d8 170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
Kojto 90:cb3d968589d8 171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
Kojto 90:cb3d968589d8 172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
Kojto 90:cb3d968589d8 173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
Kojto 90:cb3d968589d8 174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 /* Device specific interrupts */
Kojto 90:cb3d968589d8 177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
Kojto 90:cb3d968589d8 178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
Kojto 90:cb3d968589d8 179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
Kojto 90:cb3d968589d8 180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
Kojto 90:cb3d968589d8 181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
Kojto 90:cb3d968589d8 182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
Kojto 90:cb3d968589d8 183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
Kojto 90:cb3d968589d8 184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
Kojto 90:cb3d968589d8 185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
Kojto 90:cb3d968589d8 186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
Kojto 90:cb3d968589d8 187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
Kojto 90:cb3d968589d8 188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
Kojto 90:cb3d968589d8 189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
Kojto 90:cb3d968589d8 190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
Kojto 90:cb3d968589d8 191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
Kojto 90:cb3d968589d8 192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
Kojto 90:cb3d968589d8 193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
Kojto 90:cb3d968589d8 194 MCM_IRQn = 17, /**< Normal Interrupt */
Kojto 90:cb3d968589d8 195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
Kojto 90:cb3d968589d8 196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
Kojto 90:cb3d968589d8 197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
Kojto 90:cb3d968589d8 198 LLW_IRQn = 21, /**< Low Leakage Wakeup */
Kojto 90:cb3d968589d8 199 Watchdog_IRQn = 22, /**< WDOG Interrupt */
Kojto 90:cb3d968589d8 200 RNG_IRQn = 23, /**< RNG Interrupt */
Kojto 90:cb3d968589d8 201 I2C0_IRQn = 24, /**< I2C0 interrupt */
Kojto 90:cb3d968589d8 202 I2C1_IRQn = 25, /**< I2C1 interrupt */
Kojto 90:cb3d968589d8 203 SPI0_IRQn = 26, /**< SPI0 Interrupt */
Kojto 90:cb3d968589d8 204 SPI1_IRQn = 27, /**< SPI1 Interrupt */
Kojto 90:cb3d968589d8 205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
Kojto 90:cb3d968589d8 206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
Kojto 90:cb3d968589d8 207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
Kojto 90:cb3d968589d8 208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
Kojto 90:cb3d968589d8 210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
Kojto 90:cb3d968589d8 212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
Kojto 90:cb3d968589d8 214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
Kojto 90:cb3d968589d8 216 ADC0_IRQn = 39, /**< ADC0 interrupt */
Kojto 90:cb3d968589d8 217 CMP0_IRQn = 40, /**< CMP0 interrupt */
Kojto 90:cb3d968589d8 218 CMP1_IRQn = 41, /**< CMP1 interrupt */
Kojto 90:cb3d968589d8 219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
Kojto 90:cb3d968589d8 220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
Kojto 90:cb3d968589d8 221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
Kojto 90:cb3d968589d8 222 CMT_IRQn = 45, /**< CMT interrupt */
Kojto 90:cb3d968589d8 223 RTC_IRQn = 46, /**< RTC interrupt */
Kojto 90:cb3d968589d8 224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
Kojto 90:cb3d968589d8 225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
Kojto 90:cb3d968589d8 226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
Kojto 90:cb3d968589d8 227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
Kojto 90:cb3d968589d8 228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
Kojto 90:cb3d968589d8 229 PDB0_IRQn = 52, /**< PDB0 Interrupt */
Kojto 90:cb3d968589d8 230 USB0_IRQn = 53, /**< USB0 interrupt */
Kojto 90:cb3d968589d8 231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
Kojto 90:cb3d968589d8 232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
Kojto 90:cb3d968589d8 233 DAC0_IRQn = 56, /**< DAC0 interrupt */
Kojto 90:cb3d968589d8 234 MCG_IRQn = 57, /**< MCG Interrupt */
Kojto 90:cb3d968589d8 235 LPTimer_IRQn = 58, /**< LPTimer interrupt */
Kojto 90:cb3d968589d8 236 PORTA_IRQn = 59, /**< Port A interrupt */
Kojto 90:cb3d968589d8 237 PORTB_IRQn = 60, /**< Port B interrupt */
Kojto 90:cb3d968589d8 238 PORTC_IRQn = 61, /**< Port C interrupt */
Kojto 90:cb3d968589d8 239 PORTD_IRQn = 62, /**< Port D interrupt */
Kojto 90:cb3d968589d8 240 PORTE_IRQn = 63, /**< Port E interrupt */
Kojto 90:cb3d968589d8 241 SWI_IRQn = 64, /**< Software interrupt */
Kojto 90:cb3d968589d8 242 SPI2_IRQn = 65, /**< SPI2 Interrupt */
Kojto 90:cb3d968589d8 243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
Kojto 90:cb3d968589d8 245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
Kojto 90:cb3d968589d8 246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
Kojto 90:cb3d968589d8 247 CMP2_IRQn = 70, /**< CMP2 interrupt */
Kojto 90:cb3d968589d8 248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
Kojto 90:cb3d968589d8 249 DAC1_IRQn = 72, /**< DAC1 interrupt */
Kojto 90:cb3d968589d8 250 ADC1_IRQn = 73, /**< ADC1 interrupt */
Kojto 90:cb3d968589d8 251 I2C2_IRQn = 74, /**< I2C2 interrupt */
Kojto 90:cb3d968589d8 252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
Kojto 90:cb3d968589d8 253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
Kojto 90:cb3d968589d8 254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
Kojto 90:cb3d968589d8 255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
Kojto 90:cb3d968589d8 256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
Kojto 90:cb3d968589d8 257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
Kojto 90:cb3d968589d8 258 SDHC_IRQn = 81, /**< SDHC interrupt */
Kojto 90:cb3d968589d8 259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
Kojto 90:cb3d968589d8 260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
Kojto 90:cb3d968589d8 261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
Kojto 90:cb3d968589d8 262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
Kojto 90:cb3d968589d8 263 } IRQn_Type;
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265 /*!
Kojto 90:cb3d968589d8 266 * @}
Kojto 90:cb3d968589d8 267 */ /* end of group Interrupt_vector_numbers */
Kojto 90:cb3d968589d8 268
Kojto 90:cb3d968589d8 269
Kojto 90:cb3d968589d8 270 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 271 -- Cortex M4 Core Configuration
Kojto 90:cb3d968589d8 272 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 273
Kojto 90:cb3d968589d8 274 /*!
Kojto 90:cb3d968589d8 275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
Kojto 90:cb3d968589d8 276 * @{
Kojto 90:cb3d968589d8 277 */
Kojto 90:cb3d968589d8 278
Kojto 90:cb3d968589d8 279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
Kojto 90:cb3d968589d8 280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
Kojto 90:cb3d968589d8 281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
Kojto 90:cb3d968589d8 282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
Kojto 90:cb3d968589d8 283
Kojto 90:cb3d968589d8 284 #include "core_cm4.h" /* Core Peripheral Access Layer */
Kojto 90:cb3d968589d8 285 #include "system_MK64F12.h" /* Device specific configuration file */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /*!
Kojto 90:cb3d968589d8 288 * @}
Kojto 90:cb3d968589d8 289 */ /* end of group Cortex_Core_Configuration */
Kojto 90:cb3d968589d8 290
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 293 -- Device Peripheral Access Layer
Kojto 90:cb3d968589d8 294 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 295
Kojto 90:cb3d968589d8 296 /*!
Kojto 90:cb3d968589d8 297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Kojto 90:cb3d968589d8 298 * @{
Kojto 90:cb3d968589d8 299 */
Kojto 90:cb3d968589d8 300
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /*
Kojto 90:cb3d968589d8 303 ** Start of section using anonymous unions
Kojto 90:cb3d968589d8 304 */
Kojto 90:cb3d968589d8 305
Kojto 90:cb3d968589d8 306 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 307 #pragma push
Kojto 90:cb3d968589d8 308 #pragma anon_unions
Kojto 90:cb3d968589d8 309 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 310 #pragma push
Kojto 90:cb3d968589d8 311 #pragma cpp_extensions on
Kojto 90:cb3d968589d8 312 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 313 /* anonymous unions are enabled by default */
Kojto 90:cb3d968589d8 314 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 315 #pragma language=extended
Kojto 90:cb3d968589d8 316 #else
Kojto 90:cb3d968589d8 317 #error Not supported compiler type
Kojto 90:cb3d968589d8 318 #endif
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 321 -- ADC Peripheral Access Layer
Kojto 90:cb3d968589d8 322 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 323
Kojto 90:cb3d968589d8 324 /*!
Kojto 90:cb3d968589d8 325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Kojto 90:cb3d968589d8 326 * @{
Kojto 90:cb3d968589d8 327 */
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 /** ADC - Register Layout Typedef */
Kojto 90:cb3d968589d8 330 typedef struct {
Kojto 90:cb3d968589d8 331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
Kojto 90:cb3d968589d8 333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
Kojto 90:cb3d968589d8 334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
Kojto 90:cb3d968589d8 335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
Kojto 90:cb3d968589d8 336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
Kojto 90:cb3d968589d8 337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
Kojto 90:cb3d968589d8 338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
Kojto 90:cb3d968589d8 339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
Kojto 90:cb3d968589d8 340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
Kojto 90:cb3d968589d8 341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
Kojto 90:cb3d968589d8 342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
Kojto 90:cb3d968589d8 343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
Kojto 90:cb3d968589d8 344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
Kojto 90:cb3d968589d8 345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
Kojto 90:cb3d968589d8 346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
Kojto 90:cb3d968589d8 347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
Kojto 90:cb3d968589d8 348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
Kojto 90:cb3d968589d8 349 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
Kojto 90:cb3d968589d8 351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
Kojto 90:cb3d968589d8 352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
Kojto 90:cb3d968589d8 353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
Kojto 90:cb3d968589d8 354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
Kojto 90:cb3d968589d8 355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
Kojto 90:cb3d968589d8 356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
Kojto 90:cb3d968589d8 357 } ADC_Type, *ADC_MemMapPtr;
Kojto 90:cb3d968589d8 358
Kojto 90:cb3d968589d8 359 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 360 -- ADC - Register accessor macros
Kojto 90:cb3d968589d8 361 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 362
Kojto 90:cb3d968589d8 363 /*!
Kojto 90:cb3d968589d8 364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Kojto 90:cb3d968589d8 365 * @{
Kojto 90:cb3d968589d8 366 */
Kojto 90:cb3d968589d8 367
Kojto 90:cb3d968589d8 368
Kojto 90:cb3d968589d8 369 /* ADC - Register accessors */
Kojto 90:cb3d968589d8 370 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
Kojto 90:cb3d968589d8 371 #define ADC_CFG1_REG(base) ((base)->CFG1)
Kojto 90:cb3d968589d8 372 #define ADC_CFG2_REG(base) ((base)->CFG2)
Kojto 90:cb3d968589d8 373 #define ADC_R_REG(base,index) ((base)->R[index])
Kojto 90:cb3d968589d8 374 #define ADC_CV1_REG(base) ((base)->CV1)
Kojto 90:cb3d968589d8 375 #define ADC_CV2_REG(base) ((base)->CV2)
Kojto 90:cb3d968589d8 376 #define ADC_SC2_REG(base) ((base)->SC2)
Kojto 90:cb3d968589d8 377 #define ADC_SC3_REG(base) ((base)->SC3)
Kojto 90:cb3d968589d8 378 #define ADC_OFS_REG(base) ((base)->OFS)
Kojto 90:cb3d968589d8 379 #define ADC_PG_REG(base) ((base)->PG)
Kojto 90:cb3d968589d8 380 #define ADC_MG_REG(base) ((base)->MG)
Kojto 90:cb3d968589d8 381 #define ADC_CLPD_REG(base) ((base)->CLPD)
Kojto 90:cb3d968589d8 382 #define ADC_CLPS_REG(base) ((base)->CLPS)
Kojto 90:cb3d968589d8 383 #define ADC_CLP4_REG(base) ((base)->CLP4)
Kojto 90:cb3d968589d8 384 #define ADC_CLP3_REG(base) ((base)->CLP3)
Kojto 90:cb3d968589d8 385 #define ADC_CLP2_REG(base) ((base)->CLP2)
Kojto 90:cb3d968589d8 386 #define ADC_CLP1_REG(base) ((base)->CLP1)
Kojto 90:cb3d968589d8 387 #define ADC_CLP0_REG(base) ((base)->CLP0)
Kojto 90:cb3d968589d8 388 #define ADC_CLMD_REG(base) ((base)->CLMD)
Kojto 90:cb3d968589d8 389 #define ADC_CLMS_REG(base) ((base)->CLMS)
Kojto 90:cb3d968589d8 390 #define ADC_CLM4_REG(base) ((base)->CLM4)
Kojto 90:cb3d968589d8 391 #define ADC_CLM3_REG(base) ((base)->CLM3)
Kojto 90:cb3d968589d8 392 #define ADC_CLM2_REG(base) ((base)->CLM2)
Kojto 90:cb3d968589d8 393 #define ADC_CLM1_REG(base) ((base)->CLM1)
Kojto 90:cb3d968589d8 394 #define ADC_CLM0_REG(base) ((base)->CLM0)
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 /*!
Kojto 90:cb3d968589d8 397 * @}
Kojto 90:cb3d968589d8 398 */ /* end of group ADC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400
Kojto 90:cb3d968589d8 401 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 402 -- ADC Register Masks
Kojto 90:cb3d968589d8 403 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 404
Kojto 90:cb3d968589d8 405 /*!
Kojto 90:cb3d968589d8 406 * @addtogroup ADC_Register_Masks ADC Register Masks
Kojto 90:cb3d968589d8 407 * @{
Kojto 90:cb3d968589d8 408 */
Kojto 90:cb3d968589d8 409
Kojto 90:cb3d968589d8 410 /* SC1 Bit Fields */
Kojto 90:cb3d968589d8 411 #define ADC_SC1_ADCH_MASK 0x1Fu
Kojto 90:cb3d968589d8 412 #define ADC_SC1_ADCH_SHIFT 0
Kojto 90:cb3d968589d8 413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
Kojto 90:cb3d968589d8 414 #define ADC_SC1_DIFF_MASK 0x20u
Kojto 90:cb3d968589d8 415 #define ADC_SC1_DIFF_SHIFT 5
Kojto 90:cb3d968589d8 416 #define ADC_SC1_AIEN_MASK 0x40u
Kojto 90:cb3d968589d8 417 #define ADC_SC1_AIEN_SHIFT 6
Kojto 90:cb3d968589d8 418 #define ADC_SC1_COCO_MASK 0x80u
Kojto 90:cb3d968589d8 419 #define ADC_SC1_COCO_SHIFT 7
Kojto 90:cb3d968589d8 420 /* CFG1 Bit Fields */
Kojto 90:cb3d968589d8 421 #define ADC_CFG1_ADICLK_MASK 0x3u
Kojto 90:cb3d968589d8 422 #define ADC_CFG1_ADICLK_SHIFT 0
Kojto 90:cb3d968589d8 423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
Kojto 90:cb3d968589d8 424 #define ADC_CFG1_MODE_MASK 0xCu
Kojto 90:cb3d968589d8 425 #define ADC_CFG1_MODE_SHIFT 2
Kojto 90:cb3d968589d8 426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
Kojto 90:cb3d968589d8 427 #define ADC_CFG1_ADLSMP_MASK 0x10u
Kojto 90:cb3d968589d8 428 #define ADC_CFG1_ADLSMP_SHIFT 4
Kojto 90:cb3d968589d8 429 #define ADC_CFG1_ADIV_MASK 0x60u
Kojto 90:cb3d968589d8 430 #define ADC_CFG1_ADIV_SHIFT 5
Kojto 90:cb3d968589d8 431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
Kojto 90:cb3d968589d8 432 #define ADC_CFG1_ADLPC_MASK 0x80u
Kojto 90:cb3d968589d8 433 #define ADC_CFG1_ADLPC_SHIFT 7
Kojto 90:cb3d968589d8 434 /* CFG2 Bit Fields */
Kojto 90:cb3d968589d8 435 #define ADC_CFG2_ADLSTS_MASK 0x3u
Kojto 90:cb3d968589d8 436 #define ADC_CFG2_ADLSTS_SHIFT 0
Kojto 90:cb3d968589d8 437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
Kojto 90:cb3d968589d8 438 #define ADC_CFG2_ADHSC_MASK 0x4u
Kojto 90:cb3d968589d8 439 #define ADC_CFG2_ADHSC_SHIFT 2
Kojto 90:cb3d968589d8 440 #define ADC_CFG2_ADACKEN_MASK 0x8u
Kojto 90:cb3d968589d8 441 #define ADC_CFG2_ADACKEN_SHIFT 3
Kojto 90:cb3d968589d8 442 #define ADC_CFG2_MUXSEL_MASK 0x10u
Kojto 90:cb3d968589d8 443 #define ADC_CFG2_MUXSEL_SHIFT 4
Kojto 90:cb3d968589d8 444 /* R Bit Fields */
Kojto 90:cb3d968589d8 445 #define ADC_R_D_MASK 0xFFFFu
Kojto 90:cb3d968589d8 446 #define ADC_R_D_SHIFT 0
Kojto 90:cb3d968589d8 447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
Kojto 90:cb3d968589d8 448 /* CV1 Bit Fields */
Kojto 90:cb3d968589d8 449 #define ADC_CV1_CV_MASK 0xFFFFu
Kojto 90:cb3d968589d8 450 #define ADC_CV1_CV_SHIFT 0
Kojto 90:cb3d968589d8 451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
Kojto 90:cb3d968589d8 452 /* CV2 Bit Fields */
Kojto 90:cb3d968589d8 453 #define ADC_CV2_CV_MASK 0xFFFFu
Kojto 90:cb3d968589d8 454 #define ADC_CV2_CV_SHIFT 0
Kojto 90:cb3d968589d8 455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
Kojto 90:cb3d968589d8 456 /* SC2 Bit Fields */
Kojto 90:cb3d968589d8 457 #define ADC_SC2_REFSEL_MASK 0x3u
Kojto 90:cb3d968589d8 458 #define ADC_SC2_REFSEL_SHIFT 0
Kojto 90:cb3d968589d8 459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
Kojto 90:cb3d968589d8 460 #define ADC_SC2_DMAEN_MASK 0x4u
Kojto 90:cb3d968589d8 461 #define ADC_SC2_DMAEN_SHIFT 2
Kojto 90:cb3d968589d8 462 #define ADC_SC2_ACREN_MASK 0x8u
Kojto 90:cb3d968589d8 463 #define ADC_SC2_ACREN_SHIFT 3
Kojto 90:cb3d968589d8 464 #define ADC_SC2_ACFGT_MASK 0x10u
Kojto 90:cb3d968589d8 465 #define ADC_SC2_ACFGT_SHIFT 4
Kojto 90:cb3d968589d8 466 #define ADC_SC2_ACFE_MASK 0x20u
Kojto 90:cb3d968589d8 467 #define ADC_SC2_ACFE_SHIFT 5
Kojto 90:cb3d968589d8 468 #define ADC_SC2_ADTRG_MASK 0x40u
Kojto 90:cb3d968589d8 469 #define ADC_SC2_ADTRG_SHIFT 6
Kojto 90:cb3d968589d8 470 #define ADC_SC2_ADACT_MASK 0x80u
Kojto 90:cb3d968589d8 471 #define ADC_SC2_ADACT_SHIFT 7
Kojto 90:cb3d968589d8 472 /* SC3 Bit Fields */
Kojto 90:cb3d968589d8 473 #define ADC_SC3_AVGS_MASK 0x3u
Kojto 90:cb3d968589d8 474 #define ADC_SC3_AVGS_SHIFT 0
Kojto 90:cb3d968589d8 475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
Kojto 90:cb3d968589d8 476 #define ADC_SC3_AVGE_MASK 0x4u
Kojto 90:cb3d968589d8 477 #define ADC_SC3_AVGE_SHIFT 2
Kojto 90:cb3d968589d8 478 #define ADC_SC3_ADCO_MASK 0x8u
Kojto 90:cb3d968589d8 479 #define ADC_SC3_ADCO_SHIFT 3
Kojto 90:cb3d968589d8 480 #define ADC_SC3_CALF_MASK 0x40u
Kojto 90:cb3d968589d8 481 #define ADC_SC3_CALF_SHIFT 6
Kojto 90:cb3d968589d8 482 #define ADC_SC3_CAL_MASK 0x80u
Kojto 90:cb3d968589d8 483 #define ADC_SC3_CAL_SHIFT 7
Kojto 90:cb3d968589d8 484 /* OFS Bit Fields */
Kojto 90:cb3d968589d8 485 #define ADC_OFS_OFS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 486 #define ADC_OFS_OFS_SHIFT 0
Kojto 90:cb3d968589d8 487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
Kojto 90:cb3d968589d8 488 /* PG Bit Fields */
Kojto 90:cb3d968589d8 489 #define ADC_PG_PG_MASK 0xFFFFu
Kojto 90:cb3d968589d8 490 #define ADC_PG_PG_SHIFT 0
Kojto 90:cb3d968589d8 491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
Kojto 90:cb3d968589d8 492 /* MG Bit Fields */
Kojto 90:cb3d968589d8 493 #define ADC_MG_MG_MASK 0xFFFFu
Kojto 90:cb3d968589d8 494 #define ADC_MG_MG_SHIFT 0
Kojto 90:cb3d968589d8 495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
Kojto 90:cb3d968589d8 496 /* CLPD Bit Fields */
Kojto 90:cb3d968589d8 497 #define ADC_CLPD_CLPD_MASK 0x3Fu
Kojto 90:cb3d968589d8 498 #define ADC_CLPD_CLPD_SHIFT 0
Kojto 90:cb3d968589d8 499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
Kojto 90:cb3d968589d8 500 /* CLPS Bit Fields */
Kojto 90:cb3d968589d8 501 #define ADC_CLPS_CLPS_MASK 0x3Fu
Kojto 90:cb3d968589d8 502 #define ADC_CLPS_CLPS_SHIFT 0
Kojto 90:cb3d968589d8 503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
Kojto 90:cb3d968589d8 504 /* CLP4 Bit Fields */
Kojto 90:cb3d968589d8 505 #define ADC_CLP4_CLP4_MASK 0x3FFu
Kojto 90:cb3d968589d8 506 #define ADC_CLP4_CLP4_SHIFT 0
Kojto 90:cb3d968589d8 507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
Kojto 90:cb3d968589d8 508 /* CLP3 Bit Fields */
Kojto 90:cb3d968589d8 509 #define ADC_CLP3_CLP3_MASK 0x1FFu
Kojto 90:cb3d968589d8 510 #define ADC_CLP3_CLP3_SHIFT 0
Kojto 90:cb3d968589d8 511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
Kojto 90:cb3d968589d8 512 /* CLP2 Bit Fields */
Kojto 90:cb3d968589d8 513 #define ADC_CLP2_CLP2_MASK 0xFFu
Kojto 90:cb3d968589d8 514 #define ADC_CLP2_CLP2_SHIFT 0
Kojto 90:cb3d968589d8 515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
Kojto 90:cb3d968589d8 516 /* CLP1 Bit Fields */
Kojto 90:cb3d968589d8 517 #define ADC_CLP1_CLP1_MASK 0x7Fu
Kojto 90:cb3d968589d8 518 #define ADC_CLP1_CLP1_SHIFT 0
Kojto 90:cb3d968589d8 519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
Kojto 90:cb3d968589d8 520 /* CLP0 Bit Fields */
Kojto 90:cb3d968589d8 521 #define ADC_CLP0_CLP0_MASK 0x3Fu
Kojto 90:cb3d968589d8 522 #define ADC_CLP0_CLP0_SHIFT 0
Kojto 90:cb3d968589d8 523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
Kojto 90:cb3d968589d8 524 /* CLMD Bit Fields */
Kojto 90:cb3d968589d8 525 #define ADC_CLMD_CLMD_MASK 0x3Fu
Kojto 90:cb3d968589d8 526 #define ADC_CLMD_CLMD_SHIFT 0
Kojto 90:cb3d968589d8 527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
Kojto 90:cb3d968589d8 528 /* CLMS Bit Fields */
Kojto 90:cb3d968589d8 529 #define ADC_CLMS_CLMS_MASK 0x3Fu
Kojto 90:cb3d968589d8 530 #define ADC_CLMS_CLMS_SHIFT 0
Kojto 90:cb3d968589d8 531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
Kojto 90:cb3d968589d8 532 /* CLM4 Bit Fields */
Kojto 90:cb3d968589d8 533 #define ADC_CLM4_CLM4_MASK 0x3FFu
Kojto 90:cb3d968589d8 534 #define ADC_CLM4_CLM4_SHIFT 0
Kojto 90:cb3d968589d8 535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
Kojto 90:cb3d968589d8 536 /* CLM3 Bit Fields */
Kojto 90:cb3d968589d8 537 #define ADC_CLM3_CLM3_MASK 0x1FFu
Kojto 90:cb3d968589d8 538 #define ADC_CLM3_CLM3_SHIFT 0
Kojto 90:cb3d968589d8 539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
Kojto 90:cb3d968589d8 540 /* CLM2 Bit Fields */
Kojto 90:cb3d968589d8 541 #define ADC_CLM2_CLM2_MASK 0xFFu
Kojto 90:cb3d968589d8 542 #define ADC_CLM2_CLM2_SHIFT 0
Kojto 90:cb3d968589d8 543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
Kojto 90:cb3d968589d8 544 /* CLM1 Bit Fields */
Kojto 90:cb3d968589d8 545 #define ADC_CLM1_CLM1_MASK 0x7Fu
Kojto 90:cb3d968589d8 546 #define ADC_CLM1_CLM1_SHIFT 0
Kojto 90:cb3d968589d8 547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
Kojto 90:cb3d968589d8 548 /* CLM0 Bit Fields */
Kojto 90:cb3d968589d8 549 #define ADC_CLM0_CLM0_MASK 0x3Fu
Kojto 90:cb3d968589d8 550 #define ADC_CLM0_CLM0_SHIFT 0
Kojto 90:cb3d968589d8 551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
Kojto 90:cb3d968589d8 552
Kojto 90:cb3d968589d8 553 /*!
Kojto 90:cb3d968589d8 554 * @}
Kojto 90:cb3d968589d8 555 */ /* end of group ADC_Register_Masks */
Kojto 90:cb3d968589d8 556
Kojto 90:cb3d968589d8 557
Kojto 90:cb3d968589d8 558 /* ADC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 559 /** Peripheral ADC0 base address */
Kojto 90:cb3d968589d8 560 #define ADC0_BASE (0x4003B000u)
Kojto 90:cb3d968589d8 561 /** Peripheral ADC0 base pointer */
Kojto 90:cb3d968589d8 562 #define ADC0 ((ADC_Type *)ADC0_BASE)
Kojto 90:cb3d968589d8 563 #define ADC0_BASE_PTR (ADC0)
Kojto 90:cb3d968589d8 564 /** Peripheral ADC1 base address */
Kojto 90:cb3d968589d8 565 #define ADC1_BASE (0x400BB000u)
Kojto 90:cb3d968589d8 566 /** Peripheral ADC1 base pointer */
Kojto 90:cb3d968589d8 567 #define ADC1 ((ADC_Type *)ADC1_BASE)
Kojto 90:cb3d968589d8 568 #define ADC1_BASE_PTR (ADC1)
Kojto 90:cb3d968589d8 569 /** Array initializer of ADC peripheral base addresses */
Kojto 90:cb3d968589d8 570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
Kojto 90:cb3d968589d8 571 /** Array initializer of ADC peripheral base pointers */
Kojto 90:cb3d968589d8 572 #define ADC_BASE_PTRS { ADC0, ADC1 }
Kojto 90:cb3d968589d8 573 /** Interrupt vectors for the ADC peripheral type */
Kojto 90:cb3d968589d8 574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
Kojto 90:cb3d968589d8 575
Kojto 90:cb3d968589d8 576 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 577 -- ADC - Register accessor macros
Kojto 90:cb3d968589d8 578 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 579
Kojto 90:cb3d968589d8 580 /*!
Kojto 90:cb3d968589d8 581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Kojto 90:cb3d968589d8 582 * @{
Kojto 90:cb3d968589d8 583 */
Kojto 90:cb3d968589d8 584
Kojto 90:cb3d968589d8 585
Kojto 90:cb3d968589d8 586 /* ADC - Register instance definitions */
Kojto 90:cb3d968589d8 587 /* ADC0 */
Kojto 90:cb3d968589d8 588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
Kojto 90:cb3d968589d8 589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
Kojto 90:cb3d968589d8 590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
Kojto 90:cb3d968589d8 591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
Kojto 90:cb3d968589d8 592 #define ADC0_RA ADC_R_REG(ADC0,0)
Kojto 90:cb3d968589d8 593 #define ADC0_RB ADC_R_REG(ADC0,1)
Kojto 90:cb3d968589d8 594 #define ADC0_CV1 ADC_CV1_REG(ADC0)
Kojto 90:cb3d968589d8 595 #define ADC0_CV2 ADC_CV2_REG(ADC0)
Kojto 90:cb3d968589d8 596 #define ADC0_SC2 ADC_SC2_REG(ADC0)
Kojto 90:cb3d968589d8 597 #define ADC0_SC3 ADC_SC3_REG(ADC0)
Kojto 90:cb3d968589d8 598 #define ADC0_OFS ADC_OFS_REG(ADC0)
Kojto 90:cb3d968589d8 599 #define ADC0_PG ADC_PG_REG(ADC0)
Kojto 90:cb3d968589d8 600 #define ADC0_MG ADC_MG_REG(ADC0)
Kojto 90:cb3d968589d8 601 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
Kojto 90:cb3d968589d8 602 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
Kojto 90:cb3d968589d8 603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
Kojto 90:cb3d968589d8 604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
Kojto 90:cb3d968589d8 605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
Kojto 90:cb3d968589d8 606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
Kojto 90:cb3d968589d8 607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
Kojto 90:cb3d968589d8 608 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
Kojto 90:cb3d968589d8 609 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
Kojto 90:cb3d968589d8 610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
Kojto 90:cb3d968589d8 611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
Kojto 90:cb3d968589d8 612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
Kojto 90:cb3d968589d8 613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
Kojto 90:cb3d968589d8 614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
Kojto 90:cb3d968589d8 615 /* ADC1 */
Kojto 90:cb3d968589d8 616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
Kojto 90:cb3d968589d8 617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
Kojto 90:cb3d968589d8 618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
Kojto 90:cb3d968589d8 619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
Kojto 90:cb3d968589d8 620 #define ADC1_RA ADC_R_REG(ADC1,0)
Kojto 90:cb3d968589d8 621 #define ADC1_RB ADC_R_REG(ADC1,1)
Kojto 90:cb3d968589d8 622 #define ADC1_CV1 ADC_CV1_REG(ADC1)
Kojto 90:cb3d968589d8 623 #define ADC1_CV2 ADC_CV2_REG(ADC1)
Kojto 90:cb3d968589d8 624 #define ADC1_SC2 ADC_SC2_REG(ADC1)
Kojto 90:cb3d968589d8 625 #define ADC1_SC3 ADC_SC3_REG(ADC1)
Kojto 90:cb3d968589d8 626 #define ADC1_OFS ADC_OFS_REG(ADC1)
Kojto 90:cb3d968589d8 627 #define ADC1_PG ADC_PG_REG(ADC1)
Kojto 90:cb3d968589d8 628 #define ADC1_MG ADC_MG_REG(ADC1)
Kojto 90:cb3d968589d8 629 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
Kojto 90:cb3d968589d8 630 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
Kojto 90:cb3d968589d8 631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
Kojto 90:cb3d968589d8 632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
Kojto 90:cb3d968589d8 633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
Kojto 90:cb3d968589d8 634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
Kojto 90:cb3d968589d8 635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
Kojto 90:cb3d968589d8 636 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
Kojto 90:cb3d968589d8 637 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
Kojto 90:cb3d968589d8 638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
Kojto 90:cb3d968589d8 639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
Kojto 90:cb3d968589d8 640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
Kojto 90:cb3d968589d8 641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
Kojto 90:cb3d968589d8 642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
Kojto 90:cb3d968589d8 643
Kojto 90:cb3d968589d8 644 /* ADC - Register array accessors */
Kojto 90:cb3d968589d8 645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
Kojto 90:cb3d968589d8 646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
Kojto 90:cb3d968589d8 647 #define ADC0_R(index) ADC_R_REG(ADC0,index)
Kojto 90:cb3d968589d8 648 #define ADC1_R(index) ADC_R_REG(ADC1,index)
Kojto 90:cb3d968589d8 649
Kojto 90:cb3d968589d8 650 /*!
Kojto 90:cb3d968589d8 651 * @}
Kojto 90:cb3d968589d8 652 */ /* end of group ADC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 653
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 /*!
Kojto 90:cb3d968589d8 656 * @}
Kojto 90:cb3d968589d8 657 */ /* end of group ADC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659
Kojto 90:cb3d968589d8 660 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 661 -- AIPS Peripheral Access Layer
Kojto 90:cb3d968589d8 662 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 663
Kojto 90:cb3d968589d8 664 /*!
Kojto 90:cb3d968589d8 665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
Kojto 90:cb3d968589d8 666 * @{
Kojto 90:cb3d968589d8 667 */
Kojto 90:cb3d968589d8 668
Kojto 90:cb3d968589d8 669 /** AIPS - Register Layout Typedef */
Kojto 90:cb3d968589d8 670 typedef struct {
Kojto 90:cb3d968589d8 671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
Kojto 90:cb3d968589d8 672 uint8_t RESERVED_0[28];
Kojto 90:cb3d968589d8 673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
Kojto 90:cb3d968589d8 674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
Kojto 90:cb3d968589d8 675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
Kojto 90:cb3d968589d8 676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
Kojto 90:cb3d968589d8 677 uint8_t RESERVED_1[16];
Kojto 90:cb3d968589d8 678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
Kojto 90:cb3d968589d8 679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
Kojto 90:cb3d968589d8 680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
Kojto 90:cb3d968589d8 681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
Kojto 90:cb3d968589d8 682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
Kojto 90:cb3d968589d8 683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
Kojto 90:cb3d968589d8 684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
Kojto 90:cb3d968589d8 685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
Kojto 90:cb3d968589d8 686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
Kojto 90:cb3d968589d8 687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
Kojto 90:cb3d968589d8 688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
Kojto 90:cb3d968589d8 689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
Kojto 90:cb3d968589d8 690 uint8_t RESERVED_2[16];
Kojto 90:cb3d968589d8 691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
Kojto 90:cb3d968589d8 692 } AIPS_Type, *AIPS_MemMapPtr;
Kojto 90:cb3d968589d8 693
Kojto 90:cb3d968589d8 694 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 695 -- AIPS - Register accessor macros
Kojto 90:cb3d968589d8 696 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 697
Kojto 90:cb3d968589d8 698 /*!
Kojto 90:cb3d968589d8 699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
Kojto 90:cb3d968589d8 700 * @{
Kojto 90:cb3d968589d8 701 */
Kojto 90:cb3d968589d8 702
Kojto 90:cb3d968589d8 703
Kojto 90:cb3d968589d8 704 /* AIPS - Register accessors */
Kojto 90:cb3d968589d8 705 #define AIPS_MPRA_REG(base) ((base)->MPRA)
Kojto 90:cb3d968589d8 706 #define AIPS_PACRA_REG(base) ((base)->PACRA)
Kojto 90:cb3d968589d8 707 #define AIPS_PACRB_REG(base) ((base)->PACRB)
Kojto 90:cb3d968589d8 708 #define AIPS_PACRC_REG(base) ((base)->PACRC)
Kojto 90:cb3d968589d8 709 #define AIPS_PACRD_REG(base) ((base)->PACRD)
Kojto 90:cb3d968589d8 710 #define AIPS_PACRE_REG(base) ((base)->PACRE)
Kojto 90:cb3d968589d8 711 #define AIPS_PACRF_REG(base) ((base)->PACRF)
Kojto 90:cb3d968589d8 712 #define AIPS_PACRG_REG(base) ((base)->PACRG)
Kojto 90:cb3d968589d8 713 #define AIPS_PACRH_REG(base) ((base)->PACRH)
Kojto 90:cb3d968589d8 714 #define AIPS_PACRI_REG(base) ((base)->PACRI)
Kojto 90:cb3d968589d8 715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
Kojto 90:cb3d968589d8 716 #define AIPS_PACRK_REG(base) ((base)->PACRK)
Kojto 90:cb3d968589d8 717 #define AIPS_PACRL_REG(base) ((base)->PACRL)
Kojto 90:cb3d968589d8 718 #define AIPS_PACRM_REG(base) ((base)->PACRM)
Kojto 90:cb3d968589d8 719 #define AIPS_PACRN_REG(base) ((base)->PACRN)
Kojto 90:cb3d968589d8 720 #define AIPS_PACRO_REG(base) ((base)->PACRO)
Kojto 90:cb3d968589d8 721 #define AIPS_PACRP_REG(base) ((base)->PACRP)
Kojto 90:cb3d968589d8 722 #define AIPS_PACRU_REG(base) ((base)->PACRU)
Kojto 90:cb3d968589d8 723
Kojto 90:cb3d968589d8 724 /*!
Kojto 90:cb3d968589d8 725 * @}
Kojto 90:cb3d968589d8 726 */ /* end of group AIPS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 727
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 730 -- AIPS Register Masks
Kojto 90:cb3d968589d8 731 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 732
Kojto 90:cb3d968589d8 733 /*!
Kojto 90:cb3d968589d8 734 * @addtogroup AIPS_Register_Masks AIPS Register Masks
Kojto 90:cb3d968589d8 735 * @{
Kojto 90:cb3d968589d8 736 */
Kojto 90:cb3d968589d8 737
Kojto 90:cb3d968589d8 738 /* MPRA Bit Fields */
Kojto 90:cb3d968589d8 739 #define AIPS_MPRA_MPL5_MASK 0x100u
Kojto 90:cb3d968589d8 740 #define AIPS_MPRA_MPL5_SHIFT 8
Kojto 90:cb3d968589d8 741 #define AIPS_MPRA_MTW5_MASK 0x200u
Kojto 90:cb3d968589d8 742 #define AIPS_MPRA_MTW5_SHIFT 9
Kojto 90:cb3d968589d8 743 #define AIPS_MPRA_MTR5_MASK 0x400u
Kojto 90:cb3d968589d8 744 #define AIPS_MPRA_MTR5_SHIFT 10
Kojto 90:cb3d968589d8 745 #define AIPS_MPRA_MPL4_MASK 0x1000u
Kojto 90:cb3d968589d8 746 #define AIPS_MPRA_MPL4_SHIFT 12
Kojto 90:cb3d968589d8 747 #define AIPS_MPRA_MTW4_MASK 0x2000u
Kojto 90:cb3d968589d8 748 #define AIPS_MPRA_MTW4_SHIFT 13
Kojto 90:cb3d968589d8 749 #define AIPS_MPRA_MTR4_MASK 0x4000u
Kojto 90:cb3d968589d8 750 #define AIPS_MPRA_MTR4_SHIFT 14
Kojto 90:cb3d968589d8 751 #define AIPS_MPRA_MPL3_MASK 0x10000u
Kojto 90:cb3d968589d8 752 #define AIPS_MPRA_MPL3_SHIFT 16
Kojto 90:cb3d968589d8 753 #define AIPS_MPRA_MTW3_MASK 0x20000u
Kojto 90:cb3d968589d8 754 #define AIPS_MPRA_MTW3_SHIFT 17
Kojto 90:cb3d968589d8 755 #define AIPS_MPRA_MTR3_MASK 0x40000u
Kojto 90:cb3d968589d8 756 #define AIPS_MPRA_MTR3_SHIFT 18
Kojto 90:cb3d968589d8 757 #define AIPS_MPRA_MPL2_MASK 0x100000u
Kojto 90:cb3d968589d8 758 #define AIPS_MPRA_MPL2_SHIFT 20
Kojto 90:cb3d968589d8 759 #define AIPS_MPRA_MTW2_MASK 0x200000u
Kojto 90:cb3d968589d8 760 #define AIPS_MPRA_MTW2_SHIFT 21
Kojto 90:cb3d968589d8 761 #define AIPS_MPRA_MTR2_MASK 0x400000u
Kojto 90:cb3d968589d8 762 #define AIPS_MPRA_MTR2_SHIFT 22
Kojto 90:cb3d968589d8 763 #define AIPS_MPRA_MPL1_MASK 0x1000000u
Kojto 90:cb3d968589d8 764 #define AIPS_MPRA_MPL1_SHIFT 24
Kojto 90:cb3d968589d8 765 #define AIPS_MPRA_MTW1_MASK 0x2000000u
Kojto 90:cb3d968589d8 766 #define AIPS_MPRA_MTW1_SHIFT 25
Kojto 90:cb3d968589d8 767 #define AIPS_MPRA_MTR1_MASK 0x4000000u
Kojto 90:cb3d968589d8 768 #define AIPS_MPRA_MTR1_SHIFT 26
Kojto 90:cb3d968589d8 769 #define AIPS_MPRA_MPL0_MASK 0x10000000u
Kojto 90:cb3d968589d8 770 #define AIPS_MPRA_MPL0_SHIFT 28
Kojto 90:cb3d968589d8 771 #define AIPS_MPRA_MTW0_MASK 0x20000000u
Kojto 90:cb3d968589d8 772 #define AIPS_MPRA_MTW0_SHIFT 29
Kojto 90:cb3d968589d8 773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
Kojto 90:cb3d968589d8 774 #define AIPS_MPRA_MTR0_SHIFT 30
Kojto 90:cb3d968589d8 775 /* PACRA Bit Fields */
Kojto 90:cb3d968589d8 776 #define AIPS_PACRA_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 777 #define AIPS_PACRA_TP7_SHIFT 0
Kojto 90:cb3d968589d8 778 #define AIPS_PACRA_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 779 #define AIPS_PACRA_WP7_SHIFT 1
Kojto 90:cb3d968589d8 780 #define AIPS_PACRA_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 781 #define AIPS_PACRA_SP7_SHIFT 2
Kojto 90:cb3d968589d8 782 #define AIPS_PACRA_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 783 #define AIPS_PACRA_TP6_SHIFT 4
Kojto 90:cb3d968589d8 784 #define AIPS_PACRA_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 785 #define AIPS_PACRA_WP6_SHIFT 5
Kojto 90:cb3d968589d8 786 #define AIPS_PACRA_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 787 #define AIPS_PACRA_SP6_SHIFT 6
Kojto 90:cb3d968589d8 788 #define AIPS_PACRA_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 789 #define AIPS_PACRA_TP5_SHIFT 8
Kojto 90:cb3d968589d8 790 #define AIPS_PACRA_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 791 #define AIPS_PACRA_WP5_SHIFT 9
Kojto 90:cb3d968589d8 792 #define AIPS_PACRA_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 793 #define AIPS_PACRA_SP5_SHIFT 10
Kojto 90:cb3d968589d8 794 #define AIPS_PACRA_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 795 #define AIPS_PACRA_TP4_SHIFT 12
Kojto 90:cb3d968589d8 796 #define AIPS_PACRA_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 797 #define AIPS_PACRA_WP4_SHIFT 13
Kojto 90:cb3d968589d8 798 #define AIPS_PACRA_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 799 #define AIPS_PACRA_SP4_SHIFT 14
Kojto 90:cb3d968589d8 800 #define AIPS_PACRA_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 801 #define AIPS_PACRA_TP3_SHIFT 16
Kojto 90:cb3d968589d8 802 #define AIPS_PACRA_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 803 #define AIPS_PACRA_WP3_SHIFT 17
Kojto 90:cb3d968589d8 804 #define AIPS_PACRA_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 805 #define AIPS_PACRA_SP3_SHIFT 18
Kojto 90:cb3d968589d8 806 #define AIPS_PACRA_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 807 #define AIPS_PACRA_TP2_SHIFT 20
Kojto 90:cb3d968589d8 808 #define AIPS_PACRA_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 809 #define AIPS_PACRA_WP2_SHIFT 21
Kojto 90:cb3d968589d8 810 #define AIPS_PACRA_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 811 #define AIPS_PACRA_SP2_SHIFT 22
Kojto 90:cb3d968589d8 812 #define AIPS_PACRA_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 813 #define AIPS_PACRA_TP1_SHIFT 24
Kojto 90:cb3d968589d8 814 #define AIPS_PACRA_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 815 #define AIPS_PACRA_WP1_SHIFT 25
Kojto 90:cb3d968589d8 816 #define AIPS_PACRA_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 817 #define AIPS_PACRA_SP1_SHIFT 26
Kojto 90:cb3d968589d8 818 #define AIPS_PACRA_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 819 #define AIPS_PACRA_TP0_SHIFT 28
Kojto 90:cb3d968589d8 820 #define AIPS_PACRA_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 821 #define AIPS_PACRA_WP0_SHIFT 29
Kojto 90:cb3d968589d8 822 #define AIPS_PACRA_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 823 #define AIPS_PACRA_SP0_SHIFT 30
Kojto 90:cb3d968589d8 824 /* PACRB Bit Fields */
Kojto 90:cb3d968589d8 825 #define AIPS_PACRB_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 826 #define AIPS_PACRB_TP7_SHIFT 0
Kojto 90:cb3d968589d8 827 #define AIPS_PACRB_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 828 #define AIPS_PACRB_WP7_SHIFT 1
Kojto 90:cb3d968589d8 829 #define AIPS_PACRB_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 830 #define AIPS_PACRB_SP7_SHIFT 2
Kojto 90:cb3d968589d8 831 #define AIPS_PACRB_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 832 #define AIPS_PACRB_TP6_SHIFT 4
Kojto 90:cb3d968589d8 833 #define AIPS_PACRB_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 834 #define AIPS_PACRB_WP6_SHIFT 5
Kojto 90:cb3d968589d8 835 #define AIPS_PACRB_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 836 #define AIPS_PACRB_SP6_SHIFT 6
Kojto 90:cb3d968589d8 837 #define AIPS_PACRB_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 838 #define AIPS_PACRB_TP5_SHIFT 8
Kojto 90:cb3d968589d8 839 #define AIPS_PACRB_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 840 #define AIPS_PACRB_WP5_SHIFT 9
Kojto 90:cb3d968589d8 841 #define AIPS_PACRB_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 842 #define AIPS_PACRB_SP5_SHIFT 10
Kojto 90:cb3d968589d8 843 #define AIPS_PACRB_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 844 #define AIPS_PACRB_TP4_SHIFT 12
Kojto 90:cb3d968589d8 845 #define AIPS_PACRB_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 846 #define AIPS_PACRB_WP4_SHIFT 13
Kojto 90:cb3d968589d8 847 #define AIPS_PACRB_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 848 #define AIPS_PACRB_SP4_SHIFT 14
Kojto 90:cb3d968589d8 849 #define AIPS_PACRB_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 850 #define AIPS_PACRB_TP3_SHIFT 16
Kojto 90:cb3d968589d8 851 #define AIPS_PACRB_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 852 #define AIPS_PACRB_WP3_SHIFT 17
Kojto 90:cb3d968589d8 853 #define AIPS_PACRB_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 854 #define AIPS_PACRB_SP3_SHIFT 18
Kojto 90:cb3d968589d8 855 #define AIPS_PACRB_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 856 #define AIPS_PACRB_TP2_SHIFT 20
Kojto 90:cb3d968589d8 857 #define AIPS_PACRB_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 858 #define AIPS_PACRB_WP2_SHIFT 21
Kojto 90:cb3d968589d8 859 #define AIPS_PACRB_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 860 #define AIPS_PACRB_SP2_SHIFT 22
Kojto 90:cb3d968589d8 861 #define AIPS_PACRB_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 862 #define AIPS_PACRB_TP1_SHIFT 24
Kojto 90:cb3d968589d8 863 #define AIPS_PACRB_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 864 #define AIPS_PACRB_WP1_SHIFT 25
Kojto 90:cb3d968589d8 865 #define AIPS_PACRB_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 866 #define AIPS_PACRB_SP1_SHIFT 26
Kojto 90:cb3d968589d8 867 #define AIPS_PACRB_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 868 #define AIPS_PACRB_TP0_SHIFT 28
Kojto 90:cb3d968589d8 869 #define AIPS_PACRB_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 870 #define AIPS_PACRB_WP0_SHIFT 29
Kojto 90:cb3d968589d8 871 #define AIPS_PACRB_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 872 #define AIPS_PACRB_SP0_SHIFT 30
Kojto 90:cb3d968589d8 873 /* PACRC Bit Fields */
Kojto 90:cb3d968589d8 874 #define AIPS_PACRC_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 875 #define AIPS_PACRC_TP7_SHIFT 0
Kojto 90:cb3d968589d8 876 #define AIPS_PACRC_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 877 #define AIPS_PACRC_WP7_SHIFT 1
Kojto 90:cb3d968589d8 878 #define AIPS_PACRC_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 879 #define AIPS_PACRC_SP7_SHIFT 2
Kojto 90:cb3d968589d8 880 #define AIPS_PACRC_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 881 #define AIPS_PACRC_TP6_SHIFT 4
Kojto 90:cb3d968589d8 882 #define AIPS_PACRC_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 883 #define AIPS_PACRC_WP6_SHIFT 5
Kojto 90:cb3d968589d8 884 #define AIPS_PACRC_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 885 #define AIPS_PACRC_SP6_SHIFT 6
Kojto 90:cb3d968589d8 886 #define AIPS_PACRC_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 887 #define AIPS_PACRC_TP5_SHIFT 8
Kojto 90:cb3d968589d8 888 #define AIPS_PACRC_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 889 #define AIPS_PACRC_WP5_SHIFT 9
Kojto 90:cb3d968589d8 890 #define AIPS_PACRC_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 891 #define AIPS_PACRC_SP5_SHIFT 10
Kojto 90:cb3d968589d8 892 #define AIPS_PACRC_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 893 #define AIPS_PACRC_TP4_SHIFT 12
Kojto 90:cb3d968589d8 894 #define AIPS_PACRC_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 895 #define AIPS_PACRC_WP4_SHIFT 13
Kojto 90:cb3d968589d8 896 #define AIPS_PACRC_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 897 #define AIPS_PACRC_SP4_SHIFT 14
Kojto 90:cb3d968589d8 898 #define AIPS_PACRC_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 899 #define AIPS_PACRC_TP3_SHIFT 16
Kojto 90:cb3d968589d8 900 #define AIPS_PACRC_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 901 #define AIPS_PACRC_WP3_SHIFT 17
Kojto 90:cb3d968589d8 902 #define AIPS_PACRC_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 903 #define AIPS_PACRC_SP3_SHIFT 18
Kojto 90:cb3d968589d8 904 #define AIPS_PACRC_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 905 #define AIPS_PACRC_TP2_SHIFT 20
Kojto 90:cb3d968589d8 906 #define AIPS_PACRC_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 907 #define AIPS_PACRC_WP2_SHIFT 21
Kojto 90:cb3d968589d8 908 #define AIPS_PACRC_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 909 #define AIPS_PACRC_SP2_SHIFT 22
Kojto 90:cb3d968589d8 910 #define AIPS_PACRC_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 911 #define AIPS_PACRC_TP1_SHIFT 24
Kojto 90:cb3d968589d8 912 #define AIPS_PACRC_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 913 #define AIPS_PACRC_WP1_SHIFT 25
Kojto 90:cb3d968589d8 914 #define AIPS_PACRC_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 915 #define AIPS_PACRC_SP1_SHIFT 26
Kojto 90:cb3d968589d8 916 #define AIPS_PACRC_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 917 #define AIPS_PACRC_TP0_SHIFT 28
Kojto 90:cb3d968589d8 918 #define AIPS_PACRC_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 919 #define AIPS_PACRC_WP0_SHIFT 29
Kojto 90:cb3d968589d8 920 #define AIPS_PACRC_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 921 #define AIPS_PACRC_SP0_SHIFT 30
Kojto 90:cb3d968589d8 922 /* PACRD Bit Fields */
Kojto 90:cb3d968589d8 923 #define AIPS_PACRD_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 924 #define AIPS_PACRD_TP7_SHIFT 0
Kojto 90:cb3d968589d8 925 #define AIPS_PACRD_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 926 #define AIPS_PACRD_WP7_SHIFT 1
Kojto 90:cb3d968589d8 927 #define AIPS_PACRD_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 928 #define AIPS_PACRD_SP7_SHIFT 2
Kojto 90:cb3d968589d8 929 #define AIPS_PACRD_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 930 #define AIPS_PACRD_TP6_SHIFT 4
Kojto 90:cb3d968589d8 931 #define AIPS_PACRD_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 932 #define AIPS_PACRD_WP6_SHIFT 5
Kojto 90:cb3d968589d8 933 #define AIPS_PACRD_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 934 #define AIPS_PACRD_SP6_SHIFT 6
Kojto 90:cb3d968589d8 935 #define AIPS_PACRD_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 936 #define AIPS_PACRD_TP5_SHIFT 8
Kojto 90:cb3d968589d8 937 #define AIPS_PACRD_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 938 #define AIPS_PACRD_WP5_SHIFT 9
Kojto 90:cb3d968589d8 939 #define AIPS_PACRD_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 940 #define AIPS_PACRD_SP5_SHIFT 10
Kojto 90:cb3d968589d8 941 #define AIPS_PACRD_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 942 #define AIPS_PACRD_TP4_SHIFT 12
Kojto 90:cb3d968589d8 943 #define AIPS_PACRD_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 944 #define AIPS_PACRD_WP4_SHIFT 13
Kojto 90:cb3d968589d8 945 #define AIPS_PACRD_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 946 #define AIPS_PACRD_SP4_SHIFT 14
Kojto 90:cb3d968589d8 947 #define AIPS_PACRD_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 948 #define AIPS_PACRD_TP3_SHIFT 16
Kojto 90:cb3d968589d8 949 #define AIPS_PACRD_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 950 #define AIPS_PACRD_WP3_SHIFT 17
Kojto 90:cb3d968589d8 951 #define AIPS_PACRD_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 952 #define AIPS_PACRD_SP3_SHIFT 18
Kojto 90:cb3d968589d8 953 #define AIPS_PACRD_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 954 #define AIPS_PACRD_TP2_SHIFT 20
Kojto 90:cb3d968589d8 955 #define AIPS_PACRD_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 956 #define AIPS_PACRD_WP2_SHIFT 21
Kojto 90:cb3d968589d8 957 #define AIPS_PACRD_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 958 #define AIPS_PACRD_SP2_SHIFT 22
Kojto 90:cb3d968589d8 959 #define AIPS_PACRD_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 960 #define AIPS_PACRD_TP1_SHIFT 24
Kojto 90:cb3d968589d8 961 #define AIPS_PACRD_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 962 #define AIPS_PACRD_WP1_SHIFT 25
Kojto 90:cb3d968589d8 963 #define AIPS_PACRD_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 964 #define AIPS_PACRD_SP1_SHIFT 26
Kojto 90:cb3d968589d8 965 #define AIPS_PACRD_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 966 #define AIPS_PACRD_TP0_SHIFT 28
Kojto 90:cb3d968589d8 967 #define AIPS_PACRD_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 968 #define AIPS_PACRD_WP0_SHIFT 29
Kojto 90:cb3d968589d8 969 #define AIPS_PACRD_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 970 #define AIPS_PACRD_SP0_SHIFT 30
Kojto 90:cb3d968589d8 971 /* PACRE Bit Fields */
Kojto 90:cb3d968589d8 972 #define AIPS_PACRE_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 973 #define AIPS_PACRE_TP7_SHIFT 0
Kojto 90:cb3d968589d8 974 #define AIPS_PACRE_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 975 #define AIPS_PACRE_WP7_SHIFT 1
Kojto 90:cb3d968589d8 976 #define AIPS_PACRE_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 977 #define AIPS_PACRE_SP7_SHIFT 2
Kojto 90:cb3d968589d8 978 #define AIPS_PACRE_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 979 #define AIPS_PACRE_TP6_SHIFT 4
Kojto 90:cb3d968589d8 980 #define AIPS_PACRE_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 981 #define AIPS_PACRE_WP6_SHIFT 5
Kojto 90:cb3d968589d8 982 #define AIPS_PACRE_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 983 #define AIPS_PACRE_SP6_SHIFT 6
Kojto 90:cb3d968589d8 984 #define AIPS_PACRE_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 985 #define AIPS_PACRE_TP5_SHIFT 8
Kojto 90:cb3d968589d8 986 #define AIPS_PACRE_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 987 #define AIPS_PACRE_WP5_SHIFT 9
Kojto 90:cb3d968589d8 988 #define AIPS_PACRE_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 989 #define AIPS_PACRE_SP5_SHIFT 10
Kojto 90:cb3d968589d8 990 #define AIPS_PACRE_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 991 #define AIPS_PACRE_TP4_SHIFT 12
Kojto 90:cb3d968589d8 992 #define AIPS_PACRE_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 993 #define AIPS_PACRE_WP4_SHIFT 13
Kojto 90:cb3d968589d8 994 #define AIPS_PACRE_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 995 #define AIPS_PACRE_SP4_SHIFT 14
Kojto 90:cb3d968589d8 996 #define AIPS_PACRE_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 997 #define AIPS_PACRE_TP3_SHIFT 16
Kojto 90:cb3d968589d8 998 #define AIPS_PACRE_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 999 #define AIPS_PACRE_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1000 #define AIPS_PACRE_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1001 #define AIPS_PACRE_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1002 #define AIPS_PACRE_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1003 #define AIPS_PACRE_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1004 #define AIPS_PACRE_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1005 #define AIPS_PACRE_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1006 #define AIPS_PACRE_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1007 #define AIPS_PACRE_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1008 #define AIPS_PACRE_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1009 #define AIPS_PACRE_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1010 #define AIPS_PACRE_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1011 #define AIPS_PACRE_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1012 #define AIPS_PACRE_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1013 #define AIPS_PACRE_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1014 #define AIPS_PACRE_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1015 #define AIPS_PACRE_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1016 #define AIPS_PACRE_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1017 #define AIPS_PACRE_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1018 #define AIPS_PACRE_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1019 #define AIPS_PACRE_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1020 /* PACRF Bit Fields */
Kojto 90:cb3d968589d8 1021 #define AIPS_PACRF_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1022 #define AIPS_PACRF_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1023 #define AIPS_PACRF_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1024 #define AIPS_PACRF_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1025 #define AIPS_PACRF_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1026 #define AIPS_PACRF_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1027 #define AIPS_PACRF_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1028 #define AIPS_PACRF_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1029 #define AIPS_PACRF_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1030 #define AIPS_PACRF_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1031 #define AIPS_PACRF_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1032 #define AIPS_PACRF_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1033 #define AIPS_PACRF_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1034 #define AIPS_PACRF_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1035 #define AIPS_PACRF_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1036 #define AIPS_PACRF_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1037 #define AIPS_PACRF_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1038 #define AIPS_PACRF_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1039 #define AIPS_PACRF_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1040 #define AIPS_PACRF_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1041 #define AIPS_PACRF_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1042 #define AIPS_PACRF_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1043 #define AIPS_PACRF_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1044 #define AIPS_PACRF_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1045 #define AIPS_PACRF_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1046 #define AIPS_PACRF_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1047 #define AIPS_PACRF_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1048 #define AIPS_PACRF_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1049 #define AIPS_PACRF_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1050 #define AIPS_PACRF_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1051 #define AIPS_PACRF_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1052 #define AIPS_PACRF_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1053 #define AIPS_PACRF_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1054 #define AIPS_PACRF_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1055 #define AIPS_PACRF_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1056 #define AIPS_PACRF_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1057 #define AIPS_PACRF_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1058 #define AIPS_PACRF_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1059 #define AIPS_PACRF_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1060 #define AIPS_PACRF_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1061 #define AIPS_PACRF_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1062 #define AIPS_PACRF_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1063 #define AIPS_PACRF_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1064 #define AIPS_PACRF_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1065 #define AIPS_PACRF_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1066 #define AIPS_PACRF_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1067 #define AIPS_PACRF_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1068 #define AIPS_PACRF_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1069 /* PACRG Bit Fields */
Kojto 90:cb3d968589d8 1070 #define AIPS_PACRG_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1071 #define AIPS_PACRG_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1072 #define AIPS_PACRG_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1073 #define AIPS_PACRG_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1074 #define AIPS_PACRG_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1075 #define AIPS_PACRG_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1076 #define AIPS_PACRG_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1077 #define AIPS_PACRG_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1078 #define AIPS_PACRG_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1079 #define AIPS_PACRG_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1080 #define AIPS_PACRG_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1081 #define AIPS_PACRG_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1082 #define AIPS_PACRG_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1083 #define AIPS_PACRG_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1084 #define AIPS_PACRG_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1085 #define AIPS_PACRG_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1086 #define AIPS_PACRG_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1087 #define AIPS_PACRG_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1088 #define AIPS_PACRG_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1089 #define AIPS_PACRG_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1090 #define AIPS_PACRG_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1091 #define AIPS_PACRG_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1092 #define AIPS_PACRG_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1093 #define AIPS_PACRG_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1094 #define AIPS_PACRG_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1095 #define AIPS_PACRG_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1096 #define AIPS_PACRG_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1097 #define AIPS_PACRG_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1098 #define AIPS_PACRG_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1099 #define AIPS_PACRG_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1100 #define AIPS_PACRG_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1101 #define AIPS_PACRG_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1102 #define AIPS_PACRG_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1103 #define AIPS_PACRG_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1104 #define AIPS_PACRG_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1105 #define AIPS_PACRG_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1106 #define AIPS_PACRG_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1107 #define AIPS_PACRG_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1108 #define AIPS_PACRG_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1109 #define AIPS_PACRG_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1110 #define AIPS_PACRG_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1111 #define AIPS_PACRG_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1112 #define AIPS_PACRG_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1113 #define AIPS_PACRG_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1114 #define AIPS_PACRG_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1115 #define AIPS_PACRG_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1116 #define AIPS_PACRG_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1117 #define AIPS_PACRG_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1118 /* PACRH Bit Fields */
Kojto 90:cb3d968589d8 1119 #define AIPS_PACRH_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1120 #define AIPS_PACRH_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1121 #define AIPS_PACRH_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1122 #define AIPS_PACRH_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1123 #define AIPS_PACRH_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1124 #define AIPS_PACRH_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1125 #define AIPS_PACRH_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1126 #define AIPS_PACRH_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1127 #define AIPS_PACRH_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1128 #define AIPS_PACRH_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1129 #define AIPS_PACRH_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1130 #define AIPS_PACRH_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1131 #define AIPS_PACRH_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1132 #define AIPS_PACRH_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1133 #define AIPS_PACRH_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1134 #define AIPS_PACRH_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1135 #define AIPS_PACRH_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1136 #define AIPS_PACRH_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1137 #define AIPS_PACRH_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1138 #define AIPS_PACRH_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1139 #define AIPS_PACRH_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1140 #define AIPS_PACRH_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1141 #define AIPS_PACRH_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1142 #define AIPS_PACRH_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1143 #define AIPS_PACRH_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1144 #define AIPS_PACRH_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1145 #define AIPS_PACRH_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1146 #define AIPS_PACRH_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1147 #define AIPS_PACRH_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1148 #define AIPS_PACRH_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1149 #define AIPS_PACRH_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1150 #define AIPS_PACRH_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1151 #define AIPS_PACRH_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1152 #define AIPS_PACRH_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1153 #define AIPS_PACRH_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1154 #define AIPS_PACRH_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1155 #define AIPS_PACRH_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1156 #define AIPS_PACRH_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1157 #define AIPS_PACRH_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1158 #define AIPS_PACRH_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1159 #define AIPS_PACRH_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1160 #define AIPS_PACRH_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1161 #define AIPS_PACRH_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1162 #define AIPS_PACRH_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1163 #define AIPS_PACRH_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1164 #define AIPS_PACRH_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1165 #define AIPS_PACRH_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1166 #define AIPS_PACRH_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1167 /* PACRI Bit Fields */
Kojto 90:cb3d968589d8 1168 #define AIPS_PACRI_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1169 #define AIPS_PACRI_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1170 #define AIPS_PACRI_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1171 #define AIPS_PACRI_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1172 #define AIPS_PACRI_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1173 #define AIPS_PACRI_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1174 #define AIPS_PACRI_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1175 #define AIPS_PACRI_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1176 #define AIPS_PACRI_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1177 #define AIPS_PACRI_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1178 #define AIPS_PACRI_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1179 #define AIPS_PACRI_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1180 #define AIPS_PACRI_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1181 #define AIPS_PACRI_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1182 #define AIPS_PACRI_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1183 #define AIPS_PACRI_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1184 #define AIPS_PACRI_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1185 #define AIPS_PACRI_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1186 #define AIPS_PACRI_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1187 #define AIPS_PACRI_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1188 #define AIPS_PACRI_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1189 #define AIPS_PACRI_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1190 #define AIPS_PACRI_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1191 #define AIPS_PACRI_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1192 #define AIPS_PACRI_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1193 #define AIPS_PACRI_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1194 #define AIPS_PACRI_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1195 #define AIPS_PACRI_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1196 #define AIPS_PACRI_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1197 #define AIPS_PACRI_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1198 #define AIPS_PACRI_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1199 #define AIPS_PACRI_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1200 #define AIPS_PACRI_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1201 #define AIPS_PACRI_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1202 #define AIPS_PACRI_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1203 #define AIPS_PACRI_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1204 #define AIPS_PACRI_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1205 #define AIPS_PACRI_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1206 #define AIPS_PACRI_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1207 #define AIPS_PACRI_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1208 #define AIPS_PACRI_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1209 #define AIPS_PACRI_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1210 #define AIPS_PACRI_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1211 #define AIPS_PACRI_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1212 #define AIPS_PACRI_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1213 #define AIPS_PACRI_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1214 #define AIPS_PACRI_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1215 #define AIPS_PACRI_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1216 /* PACRJ Bit Fields */
Kojto 90:cb3d968589d8 1217 #define AIPS_PACRJ_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1218 #define AIPS_PACRJ_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1219 #define AIPS_PACRJ_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1220 #define AIPS_PACRJ_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1221 #define AIPS_PACRJ_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1222 #define AIPS_PACRJ_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1223 #define AIPS_PACRJ_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1224 #define AIPS_PACRJ_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1225 #define AIPS_PACRJ_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1226 #define AIPS_PACRJ_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1227 #define AIPS_PACRJ_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1228 #define AIPS_PACRJ_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1229 #define AIPS_PACRJ_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1230 #define AIPS_PACRJ_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1231 #define AIPS_PACRJ_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1232 #define AIPS_PACRJ_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1233 #define AIPS_PACRJ_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1234 #define AIPS_PACRJ_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1235 #define AIPS_PACRJ_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1236 #define AIPS_PACRJ_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1237 #define AIPS_PACRJ_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1238 #define AIPS_PACRJ_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1239 #define AIPS_PACRJ_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1240 #define AIPS_PACRJ_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1241 #define AIPS_PACRJ_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1242 #define AIPS_PACRJ_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1243 #define AIPS_PACRJ_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1244 #define AIPS_PACRJ_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1245 #define AIPS_PACRJ_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1246 #define AIPS_PACRJ_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1247 #define AIPS_PACRJ_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1248 #define AIPS_PACRJ_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1249 #define AIPS_PACRJ_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1250 #define AIPS_PACRJ_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1251 #define AIPS_PACRJ_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1252 #define AIPS_PACRJ_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1253 #define AIPS_PACRJ_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1254 #define AIPS_PACRJ_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1255 #define AIPS_PACRJ_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1256 #define AIPS_PACRJ_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1257 #define AIPS_PACRJ_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1258 #define AIPS_PACRJ_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1259 #define AIPS_PACRJ_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1260 #define AIPS_PACRJ_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1261 #define AIPS_PACRJ_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1262 #define AIPS_PACRJ_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1263 #define AIPS_PACRJ_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1264 #define AIPS_PACRJ_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1265 /* PACRK Bit Fields */
Kojto 90:cb3d968589d8 1266 #define AIPS_PACRK_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1267 #define AIPS_PACRK_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1268 #define AIPS_PACRK_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1269 #define AIPS_PACRK_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1270 #define AIPS_PACRK_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1271 #define AIPS_PACRK_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1272 #define AIPS_PACRK_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1273 #define AIPS_PACRK_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1274 #define AIPS_PACRK_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1275 #define AIPS_PACRK_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1276 #define AIPS_PACRK_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1277 #define AIPS_PACRK_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1278 #define AIPS_PACRK_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1279 #define AIPS_PACRK_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1280 #define AIPS_PACRK_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1281 #define AIPS_PACRK_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1282 #define AIPS_PACRK_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1283 #define AIPS_PACRK_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1284 #define AIPS_PACRK_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1285 #define AIPS_PACRK_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1286 #define AIPS_PACRK_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1287 #define AIPS_PACRK_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1288 #define AIPS_PACRK_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1289 #define AIPS_PACRK_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1290 #define AIPS_PACRK_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1291 #define AIPS_PACRK_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1292 #define AIPS_PACRK_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1293 #define AIPS_PACRK_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1294 #define AIPS_PACRK_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1295 #define AIPS_PACRK_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1296 #define AIPS_PACRK_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1297 #define AIPS_PACRK_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1298 #define AIPS_PACRK_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1299 #define AIPS_PACRK_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1300 #define AIPS_PACRK_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1301 #define AIPS_PACRK_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1302 #define AIPS_PACRK_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1303 #define AIPS_PACRK_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1304 #define AIPS_PACRK_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1305 #define AIPS_PACRK_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1306 #define AIPS_PACRK_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1307 #define AIPS_PACRK_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1308 #define AIPS_PACRK_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1309 #define AIPS_PACRK_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1310 #define AIPS_PACRK_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1311 #define AIPS_PACRK_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1312 #define AIPS_PACRK_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1313 #define AIPS_PACRK_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1314 /* PACRL Bit Fields */
Kojto 90:cb3d968589d8 1315 #define AIPS_PACRL_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1316 #define AIPS_PACRL_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1317 #define AIPS_PACRL_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1318 #define AIPS_PACRL_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1319 #define AIPS_PACRL_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1320 #define AIPS_PACRL_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1321 #define AIPS_PACRL_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1322 #define AIPS_PACRL_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1323 #define AIPS_PACRL_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1324 #define AIPS_PACRL_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1325 #define AIPS_PACRL_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1326 #define AIPS_PACRL_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1327 #define AIPS_PACRL_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1328 #define AIPS_PACRL_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1329 #define AIPS_PACRL_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1330 #define AIPS_PACRL_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1331 #define AIPS_PACRL_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1332 #define AIPS_PACRL_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1333 #define AIPS_PACRL_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1334 #define AIPS_PACRL_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1335 #define AIPS_PACRL_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1336 #define AIPS_PACRL_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1337 #define AIPS_PACRL_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1338 #define AIPS_PACRL_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1339 #define AIPS_PACRL_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1340 #define AIPS_PACRL_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1341 #define AIPS_PACRL_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1342 #define AIPS_PACRL_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1343 #define AIPS_PACRL_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1344 #define AIPS_PACRL_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1345 #define AIPS_PACRL_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1346 #define AIPS_PACRL_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1347 #define AIPS_PACRL_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1348 #define AIPS_PACRL_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1349 #define AIPS_PACRL_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1350 #define AIPS_PACRL_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1351 #define AIPS_PACRL_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1352 #define AIPS_PACRL_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1353 #define AIPS_PACRL_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1354 #define AIPS_PACRL_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1355 #define AIPS_PACRL_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1356 #define AIPS_PACRL_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1357 #define AIPS_PACRL_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1358 #define AIPS_PACRL_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1359 #define AIPS_PACRL_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1360 #define AIPS_PACRL_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1361 #define AIPS_PACRL_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1362 #define AIPS_PACRL_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1363 /* PACRM Bit Fields */
Kojto 90:cb3d968589d8 1364 #define AIPS_PACRM_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1365 #define AIPS_PACRM_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1366 #define AIPS_PACRM_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1367 #define AIPS_PACRM_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1368 #define AIPS_PACRM_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1369 #define AIPS_PACRM_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1370 #define AIPS_PACRM_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1371 #define AIPS_PACRM_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1372 #define AIPS_PACRM_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1373 #define AIPS_PACRM_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1374 #define AIPS_PACRM_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1375 #define AIPS_PACRM_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1376 #define AIPS_PACRM_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1377 #define AIPS_PACRM_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1378 #define AIPS_PACRM_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1379 #define AIPS_PACRM_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1380 #define AIPS_PACRM_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1381 #define AIPS_PACRM_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1382 #define AIPS_PACRM_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1383 #define AIPS_PACRM_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1384 #define AIPS_PACRM_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1385 #define AIPS_PACRM_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1386 #define AIPS_PACRM_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1387 #define AIPS_PACRM_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1388 #define AIPS_PACRM_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1389 #define AIPS_PACRM_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1390 #define AIPS_PACRM_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1391 #define AIPS_PACRM_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1392 #define AIPS_PACRM_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1393 #define AIPS_PACRM_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1394 #define AIPS_PACRM_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1395 #define AIPS_PACRM_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1396 #define AIPS_PACRM_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1397 #define AIPS_PACRM_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1398 #define AIPS_PACRM_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1399 #define AIPS_PACRM_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1400 #define AIPS_PACRM_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1401 #define AIPS_PACRM_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1402 #define AIPS_PACRM_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1403 #define AIPS_PACRM_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1404 #define AIPS_PACRM_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1405 #define AIPS_PACRM_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1406 #define AIPS_PACRM_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1407 #define AIPS_PACRM_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1408 #define AIPS_PACRM_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1409 #define AIPS_PACRM_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1410 #define AIPS_PACRM_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1411 #define AIPS_PACRM_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1412 /* PACRN Bit Fields */
Kojto 90:cb3d968589d8 1413 #define AIPS_PACRN_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1414 #define AIPS_PACRN_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1415 #define AIPS_PACRN_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1416 #define AIPS_PACRN_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1417 #define AIPS_PACRN_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1418 #define AIPS_PACRN_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1419 #define AIPS_PACRN_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1420 #define AIPS_PACRN_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1421 #define AIPS_PACRN_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1422 #define AIPS_PACRN_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1423 #define AIPS_PACRN_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1424 #define AIPS_PACRN_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1425 #define AIPS_PACRN_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1426 #define AIPS_PACRN_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1427 #define AIPS_PACRN_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1428 #define AIPS_PACRN_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1429 #define AIPS_PACRN_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1430 #define AIPS_PACRN_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1431 #define AIPS_PACRN_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1432 #define AIPS_PACRN_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1433 #define AIPS_PACRN_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1434 #define AIPS_PACRN_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1435 #define AIPS_PACRN_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1436 #define AIPS_PACRN_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1437 #define AIPS_PACRN_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1438 #define AIPS_PACRN_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1439 #define AIPS_PACRN_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1440 #define AIPS_PACRN_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1441 #define AIPS_PACRN_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1442 #define AIPS_PACRN_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1443 #define AIPS_PACRN_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1444 #define AIPS_PACRN_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1445 #define AIPS_PACRN_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1446 #define AIPS_PACRN_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1447 #define AIPS_PACRN_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1448 #define AIPS_PACRN_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1449 #define AIPS_PACRN_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1450 #define AIPS_PACRN_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1451 #define AIPS_PACRN_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1452 #define AIPS_PACRN_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1453 #define AIPS_PACRN_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1454 #define AIPS_PACRN_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1455 #define AIPS_PACRN_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1456 #define AIPS_PACRN_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1457 #define AIPS_PACRN_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1458 #define AIPS_PACRN_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1459 #define AIPS_PACRN_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1460 #define AIPS_PACRN_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1461 /* PACRO Bit Fields */
Kojto 90:cb3d968589d8 1462 #define AIPS_PACRO_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1463 #define AIPS_PACRO_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1464 #define AIPS_PACRO_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1465 #define AIPS_PACRO_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1466 #define AIPS_PACRO_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1467 #define AIPS_PACRO_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1468 #define AIPS_PACRO_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1469 #define AIPS_PACRO_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1470 #define AIPS_PACRO_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1471 #define AIPS_PACRO_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1472 #define AIPS_PACRO_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1473 #define AIPS_PACRO_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1474 #define AIPS_PACRO_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1475 #define AIPS_PACRO_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1476 #define AIPS_PACRO_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1477 #define AIPS_PACRO_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1478 #define AIPS_PACRO_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1479 #define AIPS_PACRO_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1480 #define AIPS_PACRO_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1481 #define AIPS_PACRO_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1482 #define AIPS_PACRO_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1483 #define AIPS_PACRO_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1484 #define AIPS_PACRO_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1485 #define AIPS_PACRO_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1486 #define AIPS_PACRO_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1487 #define AIPS_PACRO_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1488 #define AIPS_PACRO_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1489 #define AIPS_PACRO_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1490 #define AIPS_PACRO_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1491 #define AIPS_PACRO_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1492 #define AIPS_PACRO_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1493 #define AIPS_PACRO_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1494 #define AIPS_PACRO_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1495 #define AIPS_PACRO_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1496 #define AIPS_PACRO_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1497 #define AIPS_PACRO_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1498 #define AIPS_PACRO_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1499 #define AIPS_PACRO_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1500 #define AIPS_PACRO_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1501 #define AIPS_PACRO_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1502 #define AIPS_PACRO_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1503 #define AIPS_PACRO_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1504 #define AIPS_PACRO_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1505 #define AIPS_PACRO_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1506 #define AIPS_PACRO_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1507 #define AIPS_PACRO_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1508 #define AIPS_PACRO_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1509 #define AIPS_PACRO_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1510 /* PACRP Bit Fields */
Kojto 90:cb3d968589d8 1511 #define AIPS_PACRP_TP7_MASK 0x1u
Kojto 90:cb3d968589d8 1512 #define AIPS_PACRP_TP7_SHIFT 0
Kojto 90:cb3d968589d8 1513 #define AIPS_PACRP_WP7_MASK 0x2u
Kojto 90:cb3d968589d8 1514 #define AIPS_PACRP_WP7_SHIFT 1
Kojto 90:cb3d968589d8 1515 #define AIPS_PACRP_SP7_MASK 0x4u
Kojto 90:cb3d968589d8 1516 #define AIPS_PACRP_SP7_SHIFT 2
Kojto 90:cb3d968589d8 1517 #define AIPS_PACRP_TP6_MASK 0x10u
Kojto 90:cb3d968589d8 1518 #define AIPS_PACRP_TP6_SHIFT 4
Kojto 90:cb3d968589d8 1519 #define AIPS_PACRP_WP6_MASK 0x20u
Kojto 90:cb3d968589d8 1520 #define AIPS_PACRP_WP6_SHIFT 5
Kojto 90:cb3d968589d8 1521 #define AIPS_PACRP_SP6_MASK 0x40u
Kojto 90:cb3d968589d8 1522 #define AIPS_PACRP_SP6_SHIFT 6
Kojto 90:cb3d968589d8 1523 #define AIPS_PACRP_TP5_MASK 0x100u
Kojto 90:cb3d968589d8 1524 #define AIPS_PACRP_TP5_SHIFT 8
Kojto 90:cb3d968589d8 1525 #define AIPS_PACRP_WP5_MASK 0x200u
Kojto 90:cb3d968589d8 1526 #define AIPS_PACRP_WP5_SHIFT 9
Kojto 90:cb3d968589d8 1527 #define AIPS_PACRP_SP5_MASK 0x400u
Kojto 90:cb3d968589d8 1528 #define AIPS_PACRP_SP5_SHIFT 10
Kojto 90:cb3d968589d8 1529 #define AIPS_PACRP_TP4_MASK 0x1000u
Kojto 90:cb3d968589d8 1530 #define AIPS_PACRP_TP4_SHIFT 12
Kojto 90:cb3d968589d8 1531 #define AIPS_PACRP_WP4_MASK 0x2000u
Kojto 90:cb3d968589d8 1532 #define AIPS_PACRP_WP4_SHIFT 13
Kojto 90:cb3d968589d8 1533 #define AIPS_PACRP_SP4_MASK 0x4000u
Kojto 90:cb3d968589d8 1534 #define AIPS_PACRP_SP4_SHIFT 14
Kojto 90:cb3d968589d8 1535 #define AIPS_PACRP_TP3_MASK 0x10000u
Kojto 90:cb3d968589d8 1536 #define AIPS_PACRP_TP3_SHIFT 16
Kojto 90:cb3d968589d8 1537 #define AIPS_PACRP_WP3_MASK 0x20000u
Kojto 90:cb3d968589d8 1538 #define AIPS_PACRP_WP3_SHIFT 17
Kojto 90:cb3d968589d8 1539 #define AIPS_PACRP_SP3_MASK 0x40000u
Kojto 90:cb3d968589d8 1540 #define AIPS_PACRP_SP3_SHIFT 18
Kojto 90:cb3d968589d8 1541 #define AIPS_PACRP_TP2_MASK 0x100000u
Kojto 90:cb3d968589d8 1542 #define AIPS_PACRP_TP2_SHIFT 20
Kojto 90:cb3d968589d8 1543 #define AIPS_PACRP_WP2_MASK 0x200000u
Kojto 90:cb3d968589d8 1544 #define AIPS_PACRP_WP2_SHIFT 21
Kojto 90:cb3d968589d8 1545 #define AIPS_PACRP_SP2_MASK 0x400000u
Kojto 90:cb3d968589d8 1546 #define AIPS_PACRP_SP2_SHIFT 22
Kojto 90:cb3d968589d8 1547 #define AIPS_PACRP_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1548 #define AIPS_PACRP_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1549 #define AIPS_PACRP_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1550 #define AIPS_PACRP_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1551 #define AIPS_PACRP_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1552 #define AIPS_PACRP_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1553 #define AIPS_PACRP_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1554 #define AIPS_PACRP_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1555 #define AIPS_PACRP_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1556 #define AIPS_PACRP_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1557 #define AIPS_PACRP_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1558 #define AIPS_PACRP_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1559 /* PACRU Bit Fields */
Kojto 90:cb3d968589d8 1560 #define AIPS_PACRU_TP1_MASK 0x1000000u
Kojto 90:cb3d968589d8 1561 #define AIPS_PACRU_TP1_SHIFT 24
Kojto 90:cb3d968589d8 1562 #define AIPS_PACRU_WP1_MASK 0x2000000u
Kojto 90:cb3d968589d8 1563 #define AIPS_PACRU_WP1_SHIFT 25
Kojto 90:cb3d968589d8 1564 #define AIPS_PACRU_SP1_MASK 0x4000000u
Kojto 90:cb3d968589d8 1565 #define AIPS_PACRU_SP1_SHIFT 26
Kojto 90:cb3d968589d8 1566 #define AIPS_PACRU_TP0_MASK 0x10000000u
Kojto 90:cb3d968589d8 1567 #define AIPS_PACRU_TP0_SHIFT 28
Kojto 90:cb3d968589d8 1568 #define AIPS_PACRU_WP0_MASK 0x20000000u
Kojto 90:cb3d968589d8 1569 #define AIPS_PACRU_WP0_SHIFT 29
Kojto 90:cb3d968589d8 1570 #define AIPS_PACRU_SP0_MASK 0x40000000u
Kojto 90:cb3d968589d8 1571 #define AIPS_PACRU_SP0_SHIFT 30
Kojto 90:cb3d968589d8 1572
Kojto 90:cb3d968589d8 1573 /*!
Kojto 90:cb3d968589d8 1574 * @}
Kojto 90:cb3d968589d8 1575 */ /* end of group AIPS_Register_Masks */
Kojto 90:cb3d968589d8 1576
Kojto 90:cb3d968589d8 1577
Kojto 90:cb3d968589d8 1578 /* AIPS - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1579 /** Peripheral AIPS0 base address */
Kojto 90:cb3d968589d8 1580 #define AIPS0_BASE (0x40000000u)
Kojto 90:cb3d968589d8 1581 /** Peripheral AIPS0 base pointer */
Kojto 90:cb3d968589d8 1582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
Kojto 90:cb3d968589d8 1583 #define AIPS0_BASE_PTR (AIPS0)
Kojto 90:cb3d968589d8 1584 /** Peripheral AIPS1 base address */
Kojto 90:cb3d968589d8 1585 #define AIPS1_BASE (0x40080000u)
Kojto 90:cb3d968589d8 1586 /** Peripheral AIPS1 base pointer */
Kojto 90:cb3d968589d8 1587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
Kojto 90:cb3d968589d8 1588 #define AIPS1_BASE_PTR (AIPS1)
Kojto 90:cb3d968589d8 1589 /** Array initializer of AIPS peripheral base addresses */
Kojto 90:cb3d968589d8 1590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
Kojto 90:cb3d968589d8 1591 /** Array initializer of AIPS peripheral base pointers */
Kojto 90:cb3d968589d8 1592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
Kojto 90:cb3d968589d8 1593
Kojto 90:cb3d968589d8 1594 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1595 -- AIPS - Register accessor macros
Kojto 90:cb3d968589d8 1596 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1597
Kojto 90:cb3d968589d8 1598 /*!
Kojto 90:cb3d968589d8 1599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
Kojto 90:cb3d968589d8 1600 * @{
Kojto 90:cb3d968589d8 1601 */
Kojto 90:cb3d968589d8 1602
Kojto 90:cb3d968589d8 1603
Kojto 90:cb3d968589d8 1604 /* AIPS - Register instance definitions */
Kojto 90:cb3d968589d8 1605 /* AIPS0 */
Kojto 90:cb3d968589d8 1606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
Kojto 90:cb3d968589d8 1607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
Kojto 90:cb3d968589d8 1608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
Kojto 90:cb3d968589d8 1609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
Kojto 90:cb3d968589d8 1610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
Kojto 90:cb3d968589d8 1611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
Kojto 90:cb3d968589d8 1612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
Kojto 90:cb3d968589d8 1613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
Kojto 90:cb3d968589d8 1614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
Kojto 90:cb3d968589d8 1615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
Kojto 90:cb3d968589d8 1616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
Kojto 90:cb3d968589d8 1617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
Kojto 90:cb3d968589d8 1618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
Kojto 90:cb3d968589d8 1619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
Kojto 90:cb3d968589d8 1620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
Kojto 90:cb3d968589d8 1621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
Kojto 90:cb3d968589d8 1622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
Kojto 90:cb3d968589d8 1623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
Kojto 90:cb3d968589d8 1624 /* AIPS1 */
Kojto 90:cb3d968589d8 1625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
Kojto 90:cb3d968589d8 1626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
Kojto 90:cb3d968589d8 1627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
Kojto 90:cb3d968589d8 1628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
Kojto 90:cb3d968589d8 1629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
Kojto 90:cb3d968589d8 1630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
Kojto 90:cb3d968589d8 1631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
Kojto 90:cb3d968589d8 1632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
Kojto 90:cb3d968589d8 1633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
Kojto 90:cb3d968589d8 1634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
Kojto 90:cb3d968589d8 1635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
Kojto 90:cb3d968589d8 1636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
Kojto 90:cb3d968589d8 1637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
Kojto 90:cb3d968589d8 1638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
Kojto 90:cb3d968589d8 1639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
Kojto 90:cb3d968589d8 1640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
Kojto 90:cb3d968589d8 1641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
Kojto 90:cb3d968589d8 1642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
Kojto 90:cb3d968589d8 1643
Kojto 90:cb3d968589d8 1644 /*!
Kojto 90:cb3d968589d8 1645 * @}
Kojto 90:cb3d968589d8 1646 */ /* end of group AIPS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1647
Kojto 90:cb3d968589d8 1648
Kojto 90:cb3d968589d8 1649 /*!
Kojto 90:cb3d968589d8 1650 * @}
Kojto 90:cb3d968589d8 1651 */ /* end of group AIPS_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1652
Kojto 90:cb3d968589d8 1653
Kojto 90:cb3d968589d8 1654 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1655 -- AXBS Peripheral Access Layer
Kojto 90:cb3d968589d8 1656 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1657
Kojto 90:cb3d968589d8 1658 /*!
Kojto 90:cb3d968589d8 1659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
Kojto 90:cb3d968589d8 1660 * @{
Kojto 90:cb3d968589d8 1661 */
Kojto 90:cb3d968589d8 1662
Kojto 90:cb3d968589d8 1663 /** AXBS - Register Layout Typedef */
Kojto 90:cb3d968589d8 1664 typedef struct {
Kojto 90:cb3d968589d8 1665 struct { /* offset: 0x0, array step: 0x100 */
Kojto 90:cb3d968589d8 1666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
Kojto 90:cb3d968589d8 1667 uint8_t RESERVED_0[12];
Kojto 90:cb3d968589d8 1668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
Kojto 90:cb3d968589d8 1669 uint8_t RESERVED_1[236];
Kojto 90:cb3d968589d8 1670 } SLAVE[5];
Kojto 90:cb3d968589d8 1671 uint8_t RESERVED_0[768];
Kojto 90:cb3d968589d8 1672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
Kojto 90:cb3d968589d8 1673 uint8_t RESERVED_1[252];
Kojto 90:cb3d968589d8 1674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
Kojto 90:cb3d968589d8 1675 uint8_t RESERVED_2[252];
Kojto 90:cb3d968589d8 1676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
Kojto 90:cb3d968589d8 1677 uint8_t RESERVED_3[252];
Kojto 90:cb3d968589d8 1678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
Kojto 90:cb3d968589d8 1679 uint8_t RESERVED_4[252];
Kojto 90:cb3d968589d8 1680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
Kojto 90:cb3d968589d8 1681 uint8_t RESERVED_5[252];
Kojto 90:cb3d968589d8 1682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
Kojto 90:cb3d968589d8 1683 } AXBS_Type, *AXBS_MemMapPtr;
Kojto 90:cb3d968589d8 1684
Kojto 90:cb3d968589d8 1685 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1686 -- AXBS - Register accessor macros
Kojto 90:cb3d968589d8 1687 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1688
Kojto 90:cb3d968589d8 1689 /*!
Kojto 90:cb3d968589d8 1690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
Kojto 90:cb3d968589d8 1691 * @{
Kojto 90:cb3d968589d8 1692 */
Kojto 90:cb3d968589d8 1693
Kojto 90:cb3d968589d8 1694
Kojto 90:cb3d968589d8 1695 /* AXBS - Register accessors */
Kojto 90:cb3d968589d8 1696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
Kojto 90:cb3d968589d8 1697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
Kojto 90:cb3d968589d8 1698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
Kojto 90:cb3d968589d8 1699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
Kojto 90:cb3d968589d8 1700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
Kojto 90:cb3d968589d8 1701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
Kojto 90:cb3d968589d8 1702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
Kojto 90:cb3d968589d8 1703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
Kojto 90:cb3d968589d8 1704
Kojto 90:cb3d968589d8 1705 /*!
Kojto 90:cb3d968589d8 1706 * @}
Kojto 90:cb3d968589d8 1707 */ /* end of group AXBS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1708
Kojto 90:cb3d968589d8 1709
Kojto 90:cb3d968589d8 1710 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1711 -- AXBS Register Masks
Kojto 90:cb3d968589d8 1712 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1713
Kojto 90:cb3d968589d8 1714 /*!
Kojto 90:cb3d968589d8 1715 * @addtogroup AXBS_Register_Masks AXBS Register Masks
Kojto 90:cb3d968589d8 1716 * @{
Kojto 90:cb3d968589d8 1717 */
Kojto 90:cb3d968589d8 1718
Kojto 90:cb3d968589d8 1719 /* PRS Bit Fields */
Kojto 90:cb3d968589d8 1720 #define AXBS_PRS_M0_MASK 0x7u
Kojto 90:cb3d968589d8 1721 #define AXBS_PRS_M0_SHIFT 0
Kojto 90:cb3d968589d8 1722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
Kojto 90:cb3d968589d8 1723 #define AXBS_PRS_M1_MASK 0x70u
Kojto 90:cb3d968589d8 1724 #define AXBS_PRS_M1_SHIFT 4
Kojto 90:cb3d968589d8 1725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
Kojto 90:cb3d968589d8 1726 #define AXBS_PRS_M2_MASK 0x700u
Kojto 90:cb3d968589d8 1727 #define AXBS_PRS_M2_SHIFT 8
Kojto 90:cb3d968589d8 1728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
Kojto 90:cb3d968589d8 1729 #define AXBS_PRS_M3_MASK 0x7000u
Kojto 90:cb3d968589d8 1730 #define AXBS_PRS_M3_SHIFT 12
Kojto 90:cb3d968589d8 1731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
Kojto 90:cb3d968589d8 1732 #define AXBS_PRS_M4_MASK 0x70000u
Kojto 90:cb3d968589d8 1733 #define AXBS_PRS_M4_SHIFT 16
Kojto 90:cb3d968589d8 1734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
Kojto 90:cb3d968589d8 1735 #define AXBS_PRS_M5_MASK 0x700000u
Kojto 90:cb3d968589d8 1736 #define AXBS_PRS_M5_SHIFT 20
Kojto 90:cb3d968589d8 1737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
Kojto 90:cb3d968589d8 1738 /* CRS Bit Fields */
Kojto 90:cb3d968589d8 1739 #define AXBS_CRS_PARK_MASK 0x7u
Kojto 90:cb3d968589d8 1740 #define AXBS_CRS_PARK_SHIFT 0
Kojto 90:cb3d968589d8 1741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
Kojto 90:cb3d968589d8 1742 #define AXBS_CRS_PCTL_MASK 0x30u
Kojto 90:cb3d968589d8 1743 #define AXBS_CRS_PCTL_SHIFT 4
Kojto 90:cb3d968589d8 1744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
Kojto 90:cb3d968589d8 1745 #define AXBS_CRS_ARB_MASK 0x300u
Kojto 90:cb3d968589d8 1746 #define AXBS_CRS_ARB_SHIFT 8
Kojto 90:cb3d968589d8 1747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
Kojto 90:cb3d968589d8 1748 #define AXBS_CRS_HLP_MASK 0x40000000u
Kojto 90:cb3d968589d8 1749 #define AXBS_CRS_HLP_SHIFT 30
Kojto 90:cb3d968589d8 1750 #define AXBS_CRS_RO_MASK 0x80000000u
Kojto 90:cb3d968589d8 1751 #define AXBS_CRS_RO_SHIFT 31
Kojto 90:cb3d968589d8 1752 /* MGPCR0 Bit Fields */
Kojto 90:cb3d968589d8 1753 #define AXBS_MGPCR0_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1754 #define AXBS_MGPCR0_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
Kojto 90:cb3d968589d8 1756 /* MGPCR1 Bit Fields */
Kojto 90:cb3d968589d8 1757 #define AXBS_MGPCR1_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1758 #define AXBS_MGPCR1_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
Kojto 90:cb3d968589d8 1760 /* MGPCR2 Bit Fields */
Kojto 90:cb3d968589d8 1761 #define AXBS_MGPCR2_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1762 #define AXBS_MGPCR2_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
Kojto 90:cb3d968589d8 1764 /* MGPCR3 Bit Fields */
Kojto 90:cb3d968589d8 1765 #define AXBS_MGPCR3_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1766 #define AXBS_MGPCR3_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
Kojto 90:cb3d968589d8 1768 /* MGPCR4 Bit Fields */
Kojto 90:cb3d968589d8 1769 #define AXBS_MGPCR4_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1770 #define AXBS_MGPCR4_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
Kojto 90:cb3d968589d8 1772 /* MGPCR5 Bit Fields */
Kojto 90:cb3d968589d8 1773 #define AXBS_MGPCR5_AULB_MASK 0x7u
Kojto 90:cb3d968589d8 1774 #define AXBS_MGPCR5_AULB_SHIFT 0
Kojto 90:cb3d968589d8 1775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
Kojto 90:cb3d968589d8 1776
Kojto 90:cb3d968589d8 1777 /*!
Kojto 90:cb3d968589d8 1778 * @}
Kojto 90:cb3d968589d8 1779 */ /* end of group AXBS_Register_Masks */
Kojto 90:cb3d968589d8 1780
Kojto 90:cb3d968589d8 1781
Kojto 90:cb3d968589d8 1782 /* AXBS - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1783 /** Peripheral AXBS base address */
Kojto 90:cb3d968589d8 1784 #define AXBS_BASE (0x40004000u)
Kojto 90:cb3d968589d8 1785 /** Peripheral AXBS base pointer */
Kojto 90:cb3d968589d8 1786 #define AXBS ((AXBS_Type *)AXBS_BASE)
Kojto 90:cb3d968589d8 1787 #define AXBS_BASE_PTR (AXBS)
Kojto 90:cb3d968589d8 1788 /** Array initializer of AXBS peripheral base addresses */
Kojto 90:cb3d968589d8 1789 #define AXBS_BASE_ADDRS { AXBS_BASE }
Kojto 90:cb3d968589d8 1790 /** Array initializer of AXBS peripheral base pointers */
Kojto 90:cb3d968589d8 1791 #define AXBS_BASE_PTRS { AXBS }
Kojto 90:cb3d968589d8 1792
Kojto 90:cb3d968589d8 1793 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1794 -- AXBS - Register accessor macros
Kojto 90:cb3d968589d8 1795 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1796
Kojto 90:cb3d968589d8 1797 /*!
Kojto 90:cb3d968589d8 1798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
Kojto 90:cb3d968589d8 1799 * @{
Kojto 90:cb3d968589d8 1800 */
Kojto 90:cb3d968589d8 1801
Kojto 90:cb3d968589d8 1802
Kojto 90:cb3d968589d8 1803 /* AXBS - Register instance definitions */
Kojto 90:cb3d968589d8 1804 /* AXBS */
Kojto 90:cb3d968589d8 1805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
Kojto 90:cb3d968589d8 1806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
Kojto 90:cb3d968589d8 1807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
Kojto 90:cb3d968589d8 1808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
Kojto 90:cb3d968589d8 1809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
Kojto 90:cb3d968589d8 1810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
Kojto 90:cb3d968589d8 1811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
Kojto 90:cb3d968589d8 1812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
Kojto 90:cb3d968589d8 1813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
Kojto 90:cb3d968589d8 1814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
Kojto 90:cb3d968589d8 1815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
Kojto 90:cb3d968589d8 1816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
Kojto 90:cb3d968589d8 1817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
Kojto 90:cb3d968589d8 1818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
Kojto 90:cb3d968589d8 1819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
Kojto 90:cb3d968589d8 1820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
Kojto 90:cb3d968589d8 1821
Kojto 90:cb3d968589d8 1822 /* AXBS - Register array accessors */
Kojto 90:cb3d968589d8 1823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
Kojto 90:cb3d968589d8 1824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
Kojto 90:cb3d968589d8 1825
Kojto 90:cb3d968589d8 1826 /*!
Kojto 90:cb3d968589d8 1827 * @}
Kojto 90:cb3d968589d8 1828 */ /* end of group AXBS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1829
Kojto 90:cb3d968589d8 1830
Kojto 90:cb3d968589d8 1831 /*!
Kojto 90:cb3d968589d8 1832 * @}
Kojto 90:cb3d968589d8 1833 */ /* end of group AXBS_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1834
Kojto 90:cb3d968589d8 1835
Kojto 90:cb3d968589d8 1836 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1837 -- CAN Peripheral Access Layer
Kojto 90:cb3d968589d8 1838 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1839
Kojto 90:cb3d968589d8 1840 /*!
Kojto 90:cb3d968589d8 1841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
Kojto 90:cb3d968589d8 1842 * @{
Kojto 90:cb3d968589d8 1843 */
Kojto 90:cb3d968589d8 1844
Kojto 90:cb3d968589d8 1845 /** CAN - Register Layout Typedef */
Kojto 90:cb3d968589d8 1846 typedef struct {
Kojto 90:cb3d968589d8 1847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
Kojto 90:cb3d968589d8 1848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
Kojto 90:cb3d968589d8 1849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
Kojto 90:cb3d968589d8 1850 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 1851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
Kojto 90:cb3d968589d8 1852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
Kojto 90:cb3d968589d8 1853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
Kojto 90:cb3d968589d8 1854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
Kojto 90:cb3d968589d8 1855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
Kojto 90:cb3d968589d8 1856 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 1857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
Kojto 90:cb3d968589d8 1858 uint8_t RESERVED_2[4];
Kojto 90:cb3d968589d8 1859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
Kojto 90:cb3d968589d8 1860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
Kojto 90:cb3d968589d8 1861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
Kojto 90:cb3d968589d8 1862 uint8_t RESERVED_3[8];
Kojto 90:cb3d968589d8 1863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
Kojto 90:cb3d968589d8 1864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
Kojto 90:cb3d968589d8 1865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
Kojto 90:cb3d968589d8 1866 uint8_t RESERVED_4[48];
Kojto 90:cb3d968589d8 1867 struct { /* offset: 0x80, array step: 0x10 */
Kojto 90:cb3d968589d8 1868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
Kojto 90:cb3d968589d8 1869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
Kojto 90:cb3d968589d8 1870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
Kojto 90:cb3d968589d8 1871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
Kojto 90:cb3d968589d8 1872 } MB[16];
Kojto 90:cb3d968589d8 1873 uint8_t RESERVED_5[1792];
Kojto 90:cb3d968589d8 1874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
Kojto 90:cb3d968589d8 1875 } CAN_Type, *CAN_MemMapPtr;
Kojto 90:cb3d968589d8 1876
Kojto 90:cb3d968589d8 1877 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1878 -- CAN - Register accessor macros
Kojto 90:cb3d968589d8 1879 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1880
Kojto 90:cb3d968589d8 1881 /*!
Kojto 90:cb3d968589d8 1882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
Kojto 90:cb3d968589d8 1883 * @{
Kojto 90:cb3d968589d8 1884 */
Kojto 90:cb3d968589d8 1885
Kojto 90:cb3d968589d8 1886
Kojto 90:cb3d968589d8 1887 /* CAN - Register accessors */
Kojto 90:cb3d968589d8 1888 #define CAN_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 1889 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
Kojto 90:cb3d968589d8 1890 #define CAN_TIMER_REG(base) ((base)->TIMER)
Kojto 90:cb3d968589d8 1891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
Kojto 90:cb3d968589d8 1892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
Kojto 90:cb3d968589d8 1893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
Kojto 90:cb3d968589d8 1894 #define CAN_ECR_REG(base) ((base)->ECR)
Kojto 90:cb3d968589d8 1895 #define CAN_ESR1_REG(base) ((base)->ESR1)
Kojto 90:cb3d968589d8 1896 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
Kojto 90:cb3d968589d8 1897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
Kojto 90:cb3d968589d8 1898 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
Kojto 90:cb3d968589d8 1899 #define CAN_ESR2_REG(base) ((base)->ESR2)
Kojto 90:cb3d968589d8 1900 #define CAN_CRCR_REG(base) ((base)->CRCR)
Kojto 90:cb3d968589d8 1901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
Kojto 90:cb3d968589d8 1902 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
Kojto 90:cb3d968589d8 1903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
Kojto 90:cb3d968589d8 1904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
Kojto 90:cb3d968589d8 1905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
Kojto 90:cb3d968589d8 1906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
Kojto 90:cb3d968589d8 1907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
Kojto 90:cb3d968589d8 1908
Kojto 90:cb3d968589d8 1909 /*!
Kojto 90:cb3d968589d8 1910 * @}
Kojto 90:cb3d968589d8 1911 */ /* end of group CAN_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1912
Kojto 90:cb3d968589d8 1913
Kojto 90:cb3d968589d8 1914 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1915 -- CAN Register Masks
Kojto 90:cb3d968589d8 1916 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1917
Kojto 90:cb3d968589d8 1918 /*!
Kojto 90:cb3d968589d8 1919 * @addtogroup CAN_Register_Masks CAN Register Masks
Kojto 90:cb3d968589d8 1920 * @{
Kojto 90:cb3d968589d8 1921 */
Kojto 90:cb3d968589d8 1922
Kojto 90:cb3d968589d8 1923 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 1924 #define CAN_MCR_MAXMB_MASK 0x7Fu
Kojto 90:cb3d968589d8 1925 #define CAN_MCR_MAXMB_SHIFT 0
Kojto 90:cb3d968589d8 1926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
Kojto 90:cb3d968589d8 1927 #define CAN_MCR_IDAM_MASK 0x300u
Kojto 90:cb3d968589d8 1928 #define CAN_MCR_IDAM_SHIFT 8
Kojto 90:cb3d968589d8 1929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
Kojto 90:cb3d968589d8 1930 #define CAN_MCR_AEN_MASK 0x1000u
Kojto 90:cb3d968589d8 1931 #define CAN_MCR_AEN_SHIFT 12
Kojto 90:cb3d968589d8 1932 #define CAN_MCR_LPRIOEN_MASK 0x2000u
Kojto 90:cb3d968589d8 1933 #define CAN_MCR_LPRIOEN_SHIFT 13
Kojto 90:cb3d968589d8 1934 #define CAN_MCR_IRMQ_MASK 0x10000u
Kojto 90:cb3d968589d8 1935 #define CAN_MCR_IRMQ_SHIFT 16
Kojto 90:cb3d968589d8 1936 #define CAN_MCR_SRXDIS_MASK 0x20000u
Kojto 90:cb3d968589d8 1937 #define CAN_MCR_SRXDIS_SHIFT 17
Kojto 90:cb3d968589d8 1938 #define CAN_MCR_WAKSRC_MASK 0x80000u
Kojto 90:cb3d968589d8 1939 #define CAN_MCR_WAKSRC_SHIFT 19
Kojto 90:cb3d968589d8 1940 #define CAN_MCR_LPMACK_MASK 0x100000u
Kojto 90:cb3d968589d8 1941 #define CAN_MCR_LPMACK_SHIFT 20
Kojto 90:cb3d968589d8 1942 #define CAN_MCR_WRNEN_MASK 0x200000u
Kojto 90:cb3d968589d8 1943 #define CAN_MCR_WRNEN_SHIFT 21
Kojto 90:cb3d968589d8 1944 #define CAN_MCR_SLFWAK_MASK 0x400000u
Kojto 90:cb3d968589d8 1945 #define CAN_MCR_SLFWAK_SHIFT 22
Kojto 90:cb3d968589d8 1946 #define CAN_MCR_SUPV_MASK 0x800000u
Kojto 90:cb3d968589d8 1947 #define CAN_MCR_SUPV_SHIFT 23
Kojto 90:cb3d968589d8 1948 #define CAN_MCR_FRZACK_MASK 0x1000000u
Kojto 90:cb3d968589d8 1949 #define CAN_MCR_FRZACK_SHIFT 24
Kojto 90:cb3d968589d8 1950 #define CAN_MCR_SOFTRST_MASK 0x2000000u
Kojto 90:cb3d968589d8 1951 #define CAN_MCR_SOFTRST_SHIFT 25
Kojto 90:cb3d968589d8 1952 #define CAN_MCR_WAKMSK_MASK 0x4000000u
Kojto 90:cb3d968589d8 1953 #define CAN_MCR_WAKMSK_SHIFT 26
Kojto 90:cb3d968589d8 1954 #define CAN_MCR_NOTRDY_MASK 0x8000000u
Kojto 90:cb3d968589d8 1955 #define CAN_MCR_NOTRDY_SHIFT 27
Kojto 90:cb3d968589d8 1956 #define CAN_MCR_HALT_MASK 0x10000000u
Kojto 90:cb3d968589d8 1957 #define CAN_MCR_HALT_SHIFT 28
Kojto 90:cb3d968589d8 1958 #define CAN_MCR_RFEN_MASK 0x20000000u
Kojto 90:cb3d968589d8 1959 #define CAN_MCR_RFEN_SHIFT 29
Kojto 90:cb3d968589d8 1960 #define CAN_MCR_FRZ_MASK 0x40000000u
Kojto 90:cb3d968589d8 1961 #define CAN_MCR_FRZ_SHIFT 30
Kojto 90:cb3d968589d8 1962 #define CAN_MCR_MDIS_MASK 0x80000000u
Kojto 90:cb3d968589d8 1963 #define CAN_MCR_MDIS_SHIFT 31
Kojto 90:cb3d968589d8 1964 /* CTRL1 Bit Fields */
Kojto 90:cb3d968589d8 1965 #define CAN_CTRL1_PROPSEG_MASK 0x7u
Kojto 90:cb3d968589d8 1966 #define CAN_CTRL1_PROPSEG_SHIFT 0
Kojto 90:cb3d968589d8 1967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
Kojto 90:cb3d968589d8 1968 #define CAN_CTRL1_LOM_MASK 0x8u
Kojto 90:cb3d968589d8 1969 #define CAN_CTRL1_LOM_SHIFT 3
Kojto 90:cb3d968589d8 1970 #define CAN_CTRL1_LBUF_MASK 0x10u
Kojto 90:cb3d968589d8 1971 #define CAN_CTRL1_LBUF_SHIFT 4
Kojto 90:cb3d968589d8 1972 #define CAN_CTRL1_TSYN_MASK 0x20u
Kojto 90:cb3d968589d8 1973 #define CAN_CTRL1_TSYN_SHIFT 5
Kojto 90:cb3d968589d8 1974 #define CAN_CTRL1_BOFFREC_MASK 0x40u
Kojto 90:cb3d968589d8 1975 #define CAN_CTRL1_BOFFREC_SHIFT 6
Kojto 90:cb3d968589d8 1976 #define CAN_CTRL1_SMP_MASK 0x80u
Kojto 90:cb3d968589d8 1977 #define CAN_CTRL1_SMP_SHIFT 7
Kojto 90:cb3d968589d8 1978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
Kojto 90:cb3d968589d8 1979 #define CAN_CTRL1_RWRNMSK_SHIFT 10
Kojto 90:cb3d968589d8 1980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
Kojto 90:cb3d968589d8 1981 #define CAN_CTRL1_TWRNMSK_SHIFT 11
Kojto 90:cb3d968589d8 1982 #define CAN_CTRL1_LPB_MASK 0x1000u
Kojto 90:cb3d968589d8 1983 #define CAN_CTRL1_LPB_SHIFT 12
Kojto 90:cb3d968589d8 1984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
Kojto 90:cb3d968589d8 1985 #define CAN_CTRL1_CLKSRC_SHIFT 13
Kojto 90:cb3d968589d8 1986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
Kojto 90:cb3d968589d8 1987 #define CAN_CTRL1_ERRMSK_SHIFT 14
Kojto 90:cb3d968589d8 1988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
Kojto 90:cb3d968589d8 1989 #define CAN_CTRL1_BOFFMSK_SHIFT 15
Kojto 90:cb3d968589d8 1990 #define CAN_CTRL1_PSEG2_MASK 0x70000u
Kojto 90:cb3d968589d8 1991 #define CAN_CTRL1_PSEG2_SHIFT 16
Kojto 90:cb3d968589d8 1992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
Kojto 90:cb3d968589d8 1993 #define CAN_CTRL1_PSEG1_MASK 0x380000u
Kojto 90:cb3d968589d8 1994 #define CAN_CTRL1_PSEG1_SHIFT 19
Kojto 90:cb3d968589d8 1995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
Kojto 90:cb3d968589d8 1996 #define CAN_CTRL1_RJW_MASK 0xC00000u
Kojto 90:cb3d968589d8 1997 #define CAN_CTRL1_RJW_SHIFT 22
Kojto 90:cb3d968589d8 1998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
Kojto 90:cb3d968589d8 1999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2000 #define CAN_CTRL1_PRESDIV_SHIFT 24
Kojto 90:cb3d968589d8 2001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
Kojto 90:cb3d968589d8 2002 /* TIMER Bit Fields */
Kojto 90:cb3d968589d8 2003 #define CAN_TIMER_TIMER_MASK 0xFFFFu
Kojto 90:cb3d968589d8 2004 #define CAN_TIMER_TIMER_SHIFT 0
Kojto 90:cb3d968589d8 2005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
Kojto 90:cb3d968589d8 2006 /* RXMGMASK Bit Fields */
Kojto 90:cb3d968589d8 2007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2008 #define CAN_RXMGMASK_MG_SHIFT 0
Kojto 90:cb3d968589d8 2009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
Kojto 90:cb3d968589d8 2010 /* RX14MASK Bit Fields */
Kojto 90:cb3d968589d8 2011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2012 #define CAN_RX14MASK_RX14M_SHIFT 0
Kojto 90:cb3d968589d8 2013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
Kojto 90:cb3d968589d8 2014 /* RX15MASK Bit Fields */
Kojto 90:cb3d968589d8 2015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2016 #define CAN_RX15MASK_RX15M_SHIFT 0
Kojto 90:cb3d968589d8 2017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
Kojto 90:cb3d968589d8 2018 /* ECR Bit Fields */
Kojto 90:cb3d968589d8 2019 #define CAN_ECR_TXERRCNT_MASK 0xFFu
Kojto 90:cb3d968589d8 2020 #define CAN_ECR_TXERRCNT_SHIFT 0
Kojto 90:cb3d968589d8 2021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
Kojto 90:cb3d968589d8 2022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
Kojto 90:cb3d968589d8 2023 #define CAN_ECR_RXERRCNT_SHIFT 8
Kojto 90:cb3d968589d8 2024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
Kojto 90:cb3d968589d8 2025 /* ESR1 Bit Fields */
Kojto 90:cb3d968589d8 2026 #define CAN_ESR1_WAKINT_MASK 0x1u
Kojto 90:cb3d968589d8 2027 #define CAN_ESR1_WAKINT_SHIFT 0
Kojto 90:cb3d968589d8 2028 #define CAN_ESR1_ERRINT_MASK 0x2u
Kojto 90:cb3d968589d8 2029 #define CAN_ESR1_ERRINT_SHIFT 1
Kojto 90:cb3d968589d8 2030 #define CAN_ESR1_BOFFINT_MASK 0x4u
Kojto 90:cb3d968589d8 2031 #define CAN_ESR1_BOFFINT_SHIFT 2
Kojto 90:cb3d968589d8 2032 #define CAN_ESR1_RX_MASK 0x8u
Kojto 90:cb3d968589d8 2033 #define CAN_ESR1_RX_SHIFT 3
Kojto 90:cb3d968589d8 2034 #define CAN_ESR1_FLTCONF_MASK 0x30u
Kojto 90:cb3d968589d8 2035 #define CAN_ESR1_FLTCONF_SHIFT 4
Kojto 90:cb3d968589d8 2036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
Kojto 90:cb3d968589d8 2037 #define CAN_ESR1_TX_MASK 0x40u
Kojto 90:cb3d968589d8 2038 #define CAN_ESR1_TX_SHIFT 6
Kojto 90:cb3d968589d8 2039 #define CAN_ESR1_IDLE_MASK 0x80u
Kojto 90:cb3d968589d8 2040 #define CAN_ESR1_IDLE_SHIFT 7
Kojto 90:cb3d968589d8 2041 #define CAN_ESR1_RXWRN_MASK 0x100u
Kojto 90:cb3d968589d8 2042 #define CAN_ESR1_RXWRN_SHIFT 8
Kojto 90:cb3d968589d8 2043 #define CAN_ESR1_TXWRN_MASK 0x200u
Kojto 90:cb3d968589d8 2044 #define CAN_ESR1_TXWRN_SHIFT 9
Kojto 90:cb3d968589d8 2045 #define CAN_ESR1_STFERR_MASK 0x400u
Kojto 90:cb3d968589d8 2046 #define CAN_ESR1_STFERR_SHIFT 10
Kojto 90:cb3d968589d8 2047 #define CAN_ESR1_FRMERR_MASK 0x800u
Kojto 90:cb3d968589d8 2048 #define CAN_ESR1_FRMERR_SHIFT 11
Kojto 90:cb3d968589d8 2049 #define CAN_ESR1_CRCERR_MASK 0x1000u
Kojto 90:cb3d968589d8 2050 #define CAN_ESR1_CRCERR_SHIFT 12
Kojto 90:cb3d968589d8 2051 #define CAN_ESR1_ACKERR_MASK 0x2000u
Kojto 90:cb3d968589d8 2052 #define CAN_ESR1_ACKERR_SHIFT 13
Kojto 90:cb3d968589d8 2053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
Kojto 90:cb3d968589d8 2054 #define CAN_ESR1_BIT0ERR_SHIFT 14
Kojto 90:cb3d968589d8 2055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
Kojto 90:cb3d968589d8 2056 #define CAN_ESR1_BIT1ERR_SHIFT 15
Kojto 90:cb3d968589d8 2057 #define CAN_ESR1_RWRNINT_MASK 0x10000u
Kojto 90:cb3d968589d8 2058 #define CAN_ESR1_RWRNINT_SHIFT 16
Kojto 90:cb3d968589d8 2059 #define CAN_ESR1_TWRNINT_MASK 0x20000u
Kojto 90:cb3d968589d8 2060 #define CAN_ESR1_TWRNINT_SHIFT 17
Kojto 90:cb3d968589d8 2061 #define CAN_ESR1_SYNCH_MASK 0x40000u
Kojto 90:cb3d968589d8 2062 #define CAN_ESR1_SYNCH_SHIFT 18
Kojto 90:cb3d968589d8 2063 /* IMASK1 Bit Fields */
Kojto 90:cb3d968589d8 2064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2065 #define CAN_IMASK1_BUFLM_SHIFT 0
Kojto 90:cb3d968589d8 2066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
Kojto 90:cb3d968589d8 2067 /* IFLAG1 Bit Fields */
Kojto 90:cb3d968589d8 2068 #define CAN_IFLAG1_BUF0I_MASK 0x1u
Kojto 90:cb3d968589d8 2069 #define CAN_IFLAG1_BUF0I_SHIFT 0
Kojto 90:cb3d968589d8 2070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
Kojto 90:cb3d968589d8 2071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
Kojto 90:cb3d968589d8 2072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
Kojto 90:cb3d968589d8 2073 #define CAN_IFLAG1_BUF5I_MASK 0x20u
Kojto 90:cb3d968589d8 2074 #define CAN_IFLAG1_BUF5I_SHIFT 5
Kojto 90:cb3d968589d8 2075 #define CAN_IFLAG1_BUF6I_MASK 0x40u
Kojto 90:cb3d968589d8 2076 #define CAN_IFLAG1_BUF6I_SHIFT 6
Kojto 90:cb3d968589d8 2077 #define CAN_IFLAG1_BUF7I_MASK 0x80u
Kojto 90:cb3d968589d8 2078 #define CAN_IFLAG1_BUF7I_SHIFT 7
Kojto 90:cb3d968589d8 2079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
Kojto 90:cb3d968589d8 2080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
Kojto 90:cb3d968589d8 2081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
Kojto 90:cb3d968589d8 2082 /* CTRL2 Bit Fields */
Kojto 90:cb3d968589d8 2083 #define CAN_CTRL2_EACEN_MASK 0x10000u
Kojto 90:cb3d968589d8 2084 #define CAN_CTRL2_EACEN_SHIFT 16
Kojto 90:cb3d968589d8 2085 #define CAN_CTRL2_RRS_MASK 0x20000u
Kojto 90:cb3d968589d8 2086 #define CAN_CTRL2_RRS_SHIFT 17
Kojto 90:cb3d968589d8 2087 #define CAN_CTRL2_MRP_MASK 0x40000u
Kojto 90:cb3d968589d8 2088 #define CAN_CTRL2_MRP_SHIFT 18
Kojto 90:cb3d968589d8 2089 #define CAN_CTRL2_TASD_MASK 0xF80000u
Kojto 90:cb3d968589d8 2090 #define CAN_CTRL2_TASD_SHIFT 19
Kojto 90:cb3d968589d8 2091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
Kojto 90:cb3d968589d8 2092 #define CAN_CTRL2_RFFN_MASK 0xF000000u
Kojto 90:cb3d968589d8 2093 #define CAN_CTRL2_RFFN_SHIFT 24
Kojto 90:cb3d968589d8 2094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
Kojto 90:cb3d968589d8 2095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
Kojto 90:cb3d968589d8 2096 #define CAN_CTRL2_WRMFRZ_SHIFT 28
Kojto 90:cb3d968589d8 2097 /* ESR2 Bit Fields */
Kojto 90:cb3d968589d8 2098 #define CAN_ESR2_IMB_MASK 0x2000u
Kojto 90:cb3d968589d8 2099 #define CAN_ESR2_IMB_SHIFT 13
Kojto 90:cb3d968589d8 2100 #define CAN_ESR2_VPS_MASK 0x4000u
Kojto 90:cb3d968589d8 2101 #define CAN_ESR2_VPS_SHIFT 14
Kojto 90:cb3d968589d8 2102 #define CAN_ESR2_LPTM_MASK 0x7F0000u
Kojto 90:cb3d968589d8 2103 #define CAN_ESR2_LPTM_SHIFT 16
Kojto 90:cb3d968589d8 2104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
Kojto 90:cb3d968589d8 2105 /* CRCR Bit Fields */
Kojto 90:cb3d968589d8 2106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
Kojto 90:cb3d968589d8 2107 #define CAN_CRCR_TXCRC_SHIFT 0
Kojto 90:cb3d968589d8 2108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
Kojto 90:cb3d968589d8 2109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
Kojto 90:cb3d968589d8 2110 #define CAN_CRCR_MBCRC_SHIFT 16
Kojto 90:cb3d968589d8 2111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
Kojto 90:cb3d968589d8 2112 /* RXFGMASK Bit Fields */
Kojto 90:cb3d968589d8 2113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2114 #define CAN_RXFGMASK_FGM_SHIFT 0
Kojto 90:cb3d968589d8 2115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
Kojto 90:cb3d968589d8 2116 /* RXFIR Bit Fields */
Kojto 90:cb3d968589d8 2117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
Kojto 90:cb3d968589d8 2118 #define CAN_RXFIR_IDHIT_SHIFT 0
Kojto 90:cb3d968589d8 2119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
Kojto 90:cb3d968589d8 2120 /* CS Bit Fields */
Kojto 90:cb3d968589d8 2121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
Kojto 90:cb3d968589d8 2122 #define CAN_CS_TIME_STAMP_SHIFT 0
Kojto 90:cb3d968589d8 2123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
Kojto 90:cb3d968589d8 2124 #define CAN_CS_DLC_MASK 0xF0000u
Kojto 90:cb3d968589d8 2125 #define CAN_CS_DLC_SHIFT 16
Kojto 90:cb3d968589d8 2126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
Kojto 90:cb3d968589d8 2127 #define CAN_CS_RTR_MASK 0x100000u
Kojto 90:cb3d968589d8 2128 #define CAN_CS_RTR_SHIFT 20
Kojto 90:cb3d968589d8 2129 #define CAN_CS_IDE_MASK 0x200000u
Kojto 90:cb3d968589d8 2130 #define CAN_CS_IDE_SHIFT 21
Kojto 90:cb3d968589d8 2131 #define CAN_CS_SRR_MASK 0x400000u
Kojto 90:cb3d968589d8 2132 #define CAN_CS_SRR_SHIFT 22
Kojto 90:cb3d968589d8 2133 #define CAN_CS_CODE_MASK 0xF000000u
Kojto 90:cb3d968589d8 2134 #define CAN_CS_CODE_SHIFT 24
Kojto 90:cb3d968589d8 2135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
Kojto 90:cb3d968589d8 2136 /* ID Bit Fields */
Kojto 90:cb3d968589d8 2137 #define CAN_ID_EXT_MASK 0x3FFFFu
Kojto 90:cb3d968589d8 2138 #define CAN_ID_EXT_SHIFT 0
Kojto 90:cb3d968589d8 2139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
Kojto 90:cb3d968589d8 2140 #define CAN_ID_STD_MASK 0x1FFC0000u
Kojto 90:cb3d968589d8 2141 #define CAN_ID_STD_SHIFT 18
Kojto 90:cb3d968589d8 2142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
Kojto 90:cb3d968589d8 2143 #define CAN_ID_PRIO_MASK 0xE0000000u
Kojto 90:cb3d968589d8 2144 #define CAN_ID_PRIO_SHIFT 29
Kojto 90:cb3d968589d8 2145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
Kojto 90:cb3d968589d8 2146 /* WORD0 Bit Fields */
Kojto 90:cb3d968589d8 2147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
Kojto 90:cb3d968589d8 2148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
Kojto 90:cb3d968589d8 2149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
Kojto 90:cb3d968589d8 2150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
Kojto 90:cb3d968589d8 2151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
Kojto 90:cb3d968589d8 2152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
Kojto 90:cb3d968589d8 2153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
Kojto 90:cb3d968589d8 2155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
Kojto 90:cb3d968589d8 2156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
Kojto 90:cb3d968589d8 2158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
Kojto 90:cb3d968589d8 2159 /* WORD1 Bit Fields */
Kojto 90:cb3d968589d8 2160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
Kojto 90:cb3d968589d8 2161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
Kojto 90:cb3d968589d8 2162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
Kojto 90:cb3d968589d8 2163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
Kojto 90:cb3d968589d8 2164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
Kojto 90:cb3d968589d8 2165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
Kojto 90:cb3d968589d8 2166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
Kojto 90:cb3d968589d8 2168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
Kojto 90:cb3d968589d8 2169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
Kojto 90:cb3d968589d8 2171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
Kojto 90:cb3d968589d8 2172 /* RXIMR Bit Fields */
Kojto 90:cb3d968589d8 2173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2174 #define CAN_RXIMR_MI_SHIFT 0
Kojto 90:cb3d968589d8 2175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
Kojto 90:cb3d968589d8 2176
Kojto 90:cb3d968589d8 2177 /*!
Kojto 90:cb3d968589d8 2178 * @}
Kojto 90:cb3d968589d8 2179 */ /* end of group CAN_Register_Masks */
Kojto 90:cb3d968589d8 2180
Kojto 90:cb3d968589d8 2181
Kojto 90:cb3d968589d8 2182 /* CAN - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 2183 /** Peripheral CAN0 base address */
Kojto 90:cb3d968589d8 2184 #define CAN0_BASE (0x40024000u)
Kojto 90:cb3d968589d8 2185 /** Peripheral CAN0 base pointer */
Kojto 90:cb3d968589d8 2186 #define CAN0 ((CAN_Type *)CAN0_BASE)
Kojto 90:cb3d968589d8 2187 #define CAN0_BASE_PTR (CAN0)
Kojto 90:cb3d968589d8 2188 /** Array initializer of CAN peripheral base addresses */
Kojto 90:cb3d968589d8 2189 #define CAN_BASE_ADDRS { CAN0_BASE }
Kojto 90:cb3d968589d8 2190 /** Array initializer of CAN peripheral base pointers */
Kojto 90:cb3d968589d8 2191 #define CAN_BASE_PTRS { CAN0 }
Kojto 90:cb3d968589d8 2192 /** Interrupt vectors for the CAN peripheral type */
Kojto 90:cb3d968589d8 2193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
Kojto 90:cb3d968589d8 2194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
Kojto 90:cb3d968589d8 2195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
Kojto 90:cb3d968589d8 2196 #define CAN_Error_IRQS { CAN0_Error_IRQn }
Kojto 90:cb3d968589d8 2197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
Kojto 90:cb3d968589d8 2198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
Kojto 90:cb3d968589d8 2199
Kojto 90:cb3d968589d8 2200 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2201 -- CAN - Register accessor macros
Kojto 90:cb3d968589d8 2202 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2203
Kojto 90:cb3d968589d8 2204 /*!
Kojto 90:cb3d968589d8 2205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
Kojto 90:cb3d968589d8 2206 * @{
Kojto 90:cb3d968589d8 2207 */
Kojto 90:cb3d968589d8 2208
Kojto 90:cb3d968589d8 2209
Kojto 90:cb3d968589d8 2210 /* CAN - Register instance definitions */
Kojto 90:cb3d968589d8 2211 /* CAN0 */
Kojto 90:cb3d968589d8 2212 #define CAN0_MCR CAN_MCR_REG(CAN0)
Kojto 90:cb3d968589d8 2213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
Kojto 90:cb3d968589d8 2214 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
Kojto 90:cb3d968589d8 2215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
Kojto 90:cb3d968589d8 2216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
Kojto 90:cb3d968589d8 2217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
Kojto 90:cb3d968589d8 2218 #define CAN0_ECR CAN_ECR_REG(CAN0)
Kojto 90:cb3d968589d8 2219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
Kojto 90:cb3d968589d8 2220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
Kojto 90:cb3d968589d8 2221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
Kojto 90:cb3d968589d8 2222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
Kojto 90:cb3d968589d8 2223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
Kojto 90:cb3d968589d8 2224 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
Kojto 90:cb3d968589d8 2225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
Kojto 90:cb3d968589d8 2226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
Kojto 90:cb3d968589d8 2227 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
Kojto 90:cb3d968589d8 2228 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
Kojto 90:cb3d968589d8 2229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
Kojto 90:cb3d968589d8 2230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
Kojto 90:cb3d968589d8 2231 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
Kojto 90:cb3d968589d8 2232 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
Kojto 90:cb3d968589d8 2233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
Kojto 90:cb3d968589d8 2234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
Kojto 90:cb3d968589d8 2235 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
Kojto 90:cb3d968589d8 2236 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
Kojto 90:cb3d968589d8 2237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
Kojto 90:cb3d968589d8 2238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
Kojto 90:cb3d968589d8 2239 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
Kojto 90:cb3d968589d8 2240 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
Kojto 90:cb3d968589d8 2241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
Kojto 90:cb3d968589d8 2242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
Kojto 90:cb3d968589d8 2243 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
Kojto 90:cb3d968589d8 2244 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
Kojto 90:cb3d968589d8 2245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
Kojto 90:cb3d968589d8 2246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
Kojto 90:cb3d968589d8 2247 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
Kojto 90:cb3d968589d8 2248 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
Kojto 90:cb3d968589d8 2249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
Kojto 90:cb3d968589d8 2250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
Kojto 90:cb3d968589d8 2251 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
Kojto 90:cb3d968589d8 2252 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
Kojto 90:cb3d968589d8 2253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
Kojto 90:cb3d968589d8 2254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
Kojto 90:cb3d968589d8 2255 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
Kojto 90:cb3d968589d8 2256 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
Kojto 90:cb3d968589d8 2257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
Kojto 90:cb3d968589d8 2258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
Kojto 90:cb3d968589d8 2259 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
Kojto 90:cb3d968589d8 2260 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
Kojto 90:cb3d968589d8 2261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
Kojto 90:cb3d968589d8 2262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
Kojto 90:cb3d968589d8 2263 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
Kojto 90:cb3d968589d8 2264 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
Kojto 90:cb3d968589d8 2265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
Kojto 90:cb3d968589d8 2266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
Kojto 90:cb3d968589d8 2267 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
Kojto 90:cb3d968589d8 2268 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
Kojto 90:cb3d968589d8 2269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
Kojto 90:cb3d968589d8 2270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
Kojto 90:cb3d968589d8 2271 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
Kojto 90:cb3d968589d8 2272 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
Kojto 90:cb3d968589d8 2273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
Kojto 90:cb3d968589d8 2274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
Kojto 90:cb3d968589d8 2275 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
Kojto 90:cb3d968589d8 2276 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
Kojto 90:cb3d968589d8 2277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
Kojto 90:cb3d968589d8 2278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
Kojto 90:cb3d968589d8 2279 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
Kojto 90:cb3d968589d8 2280 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
Kojto 90:cb3d968589d8 2281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
Kojto 90:cb3d968589d8 2282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
Kojto 90:cb3d968589d8 2283 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
Kojto 90:cb3d968589d8 2284 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
Kojto 90:cb3d968589d8 2285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
Kojto 90:cb3d968589d8 2286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
Kojto 90:cb3d968589d8 2287 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
Kojto 90:cb3d968589d8 2288 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
Kojto 90:cb3d968589d8 2289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
Kojto 90:cb3d968589d8 2290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
Kojto 90:cb3d968589d8 2291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
Kojto 90:cb3d968589d8 2292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
Kojto 90:cb3d968589d8 2293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
Kojto 90:cb3d968589d8 2294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
Kojto 90:cb3d968589d8 2295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
Kojto 90:cb3d968589d8 2296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
Kojto 90:cb3d968589d8 2297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
Kojto 90:cb3d968589d8 2298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
Kojto 90:cb3d968589d8 2299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
Kojto 90:cb3d968589d8 2300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
Kojto 90:cb3d968589d8 2301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
Kojto 90:cb3d968589d8 2302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
Kojto 90:cb3d968589d8 2303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
Kojto 90:cb3d968589d8 2304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
Kojto 90:cb3d968589d8 2305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
Kojto 90:cb3d968589d8 2306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
Kojto 90:cb3d968589d8 2307
Kojto 90:cb3d968589d8 2308 /* CAN - Register array accessors */
Kojto 90:cb3d968589d8 2309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
Kojto 90:cb3d968589d8 2310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
Kojto 90:cb3d968589d8 2311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
Kojto 90:cb3d968589d8 2312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
Kojto 90:cb3d968589d8 2313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
Kojto 90:cb3d968589d8 2314
Kojto 90:cb3d968589d8 2315 /*!
Kojto 90:cb3d968589d8 2316 * @}
Kojto 90:cb3d968589d8 2317 */ /* end of group CAN_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2318
Kojto 90:cb3d968589d8 2319
Kojto 90:cb3d968589d8 2320 /*!
Kojto 90:cb3d968589d8 2321 * @}
Kojto 90:cb3d968589d8 2322 */ /* end of group CAN_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 2323
Kojto 90:cb3d968589d8 2324
Kojto 90:cb3d968589d8 2325 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2326 -- CAU Peripheral Access Layer
Kojto 90:cb3d968589d8 2327 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2328
Kojto 90:cb3d968589d8 2329 /*!
Kojto 90:cb3d968589d8 2330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
Kojto 90:cb3d968589d8 2331 * @{
Kojto 90:cb3d968589d8 2332 */
Kojto 90:cb3d968589d8 2333
Kojto 90:cb3d968589d8 2334 /** CAU - Register Layout Typedef */
Kojto 90:cb3d968589d8 2335 typedef struct {
Kojto 90:cb3d968589d8 2336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 2337 uint8_t RESERVED_0[2048];
Kojto 90:cb3d968589d8 2338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
Kojto 90:cb3d968589d8 2339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
Kojto 90:cb3d968589d8 2340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
Kojto 90:cb3d968589d8 2341 uint8_t RESERVED_1[20];
Kojto 90:cb3d968589d8 2342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
Kojto 90:cb3d968589d8 2343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
Kojto 90:cb3d968589d8 2344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
Kojto 90:cb3d968589d8 2345 uint8_t RESERVED_2[20];
Kojto 90:cb3d968589d8 2346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
Kojto 90:cb3d968589d8 2347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
Kojto 90:cb3d968589d8 2348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
Kojto 90:cb3d968589d8 2349 uint8_t RESERVED_3[20];
Kojto 90:cb3d968589d8 2350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
Kojto 90:cb3d968589d8 2351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
Kojto 90:cb3d968589d8 2352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
Kojto 90:cb3d968589d8 2353 uint8_t RESERVED_4[84];
Kojto 90:cb3d968589d8 2354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
Kojto 90:cb3d968589d8 2355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
Kojto 90:cb3d968589d8 2356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
Kojto 90:cb3d968589d8 2357 uint8_t RESERVED_5[20];
Kojto 90:cb3d968589d8 2358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
Kojto 90:cb3d968589d8 2359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
Kojto 90:cb3d968589d8 2360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
Kojto 90:cb3d968589d8 2361 uint8_t RESERVED_6[276];
Kojto 90:cb3d968589d8 2362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
Kojto 90:cb3d968589d8 2363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
Kojto 90:cb3d968589d8 2364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
Kojto 90:cb3d968589d8 2365 uint8_t RESERVED_7[20];
Kojto 90:cb3d968589d8 2366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
Kojto 90:cb3d968589d8 2367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
Kojto 90:cb3d968589d8 2368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
Kojto 90:cb3d968589d8 2369 } CAU_Type, *CAU_MemMapPtr;
Kojto 90:cb3d968589d8 2370
Kojto 90:cb3d968589d8 2371 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2372 -- CAU - Register accessor macros
Kojto 90:cb3d968589d8 2373 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2374
Kojto 90:cb3d968589d8 2375 /*!
Kojto 90:cb3d968589d8 2376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
Kojto 90:cb3d968589d8 2377 * @{
Kojto 90:cb3d968589d8 2378 */
Kojto 90:cb3d968589d8 2379
Kojto 90:cb3d968589d8 2380
Kojto 90:cb3d968589d8 2381 /* CAU - Register accessors */
Kojto 90:cb3d968589d8 2382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
Kojto 90:cb3d968589d8 2383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
Kojto 90:cb3d968589d8 2384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
Kojto 90:cb3d968589d8 2385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
Kojto 90:cb3d968589d8 2386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
Kojto 90:cb3d968589d8 2387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
Kojto 90:cb3d968589d8 2388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
Kojto 90:cb3d968589d8 2389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
Kojto 90:cb3d968589d8 2390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
Kojto 90:cb3d968589d8 2391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
Kojto 90:cb3d968589d8 2392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
Kojto 90:cb3d968589d8 2393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
Kojto 90:cb3d968589d8 2394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
Kojto 90:cb3d968589d8 2395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
Kojto 90:cb3d968589d8 2396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
Kojto 90:cb3d968589d8 2397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
Kojto 90:cb3d968589d8 2398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
Kojto 90:cb3d968589d8 2399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
Kojto 90:cb3d968589d8 2400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
Kojto 90:cb3d968589d8 2401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
Kojto 90:cb3d968589d8 2402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
Kojto 90:cb3d968589d8 2403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
Kojto 90:cb3d968589d8 2404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
Kojto 90:cb3d968589d8 2405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
Kojto 90:cb3d968589d8 2406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
Kojto 90:cb3d968589d8 2407
Kojto 90:cb3d968589d8 2408 /*!
Kojto 90:cb3d968589d8 2409 * @}
Kojto 90:cb3d968589d8 2410 */ /* end of group CAU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2411
Kojto 90:cb3d968589d8 2412
Kojto 90:cb3d968589d8 2413 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2414 -- CAU Register Masks
Kojto 90:cb3d968589d8 2415 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2416
Kojto 90:cb3d968589d8 2417 /*!
Kojto 90:cb3d968589d8 2418 * @addtogroup CAU_Register_Masks CAU Register Masks
Kojto 90:cb3d968589d8 2419 * @{
Kojto 90:cb3d968589d8 2420 */
Kojto 90:cb3d968589d8 2421
Kojto 90:cb3d968589d8 2422 /* DIRECT Bit Fields */
Kojto 90:cb3d968589d8 2423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
Kojto 90:cb3d968589d8 2425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
Kojto 90:cb3d968589d8 2426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
Kojto 90:cb3d968589d8 2428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
Kojto 90:cb3d968589d8 2429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
Kojto 90:cb3d968589d8 2431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
Kojto 90:cb3d968589d8 2432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
Kojto 90:cb3d968589d8 2434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
Kojto 90:cb3d968589d8 2435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
Kojto 90:cb3d968589d8 2437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
Kojto 90:cb3d968589d8 2438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
Kojto 90:cb3d968589d8 2440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
Kojto 90:cb3d968589d8 2441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
Kojto 90:cb3d968589d8 2443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
Kojto 90:cb3d968589d8 2444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
Kojto 90:cb3d968589d8 2446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
Kojto 90:cb3d968589d8 2447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
Kojto 90:cb3d968589d8 2449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
Kojto 90:cb3d968589d8 2450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
Kojto 90:cb3d968589d8 2452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
Kojto 90:cb3d968589d8 2453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
Kojto 90:cb3d968589d8 2455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
Kojto 90:cb3d968589d8 2456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
Kojto 90:cb3d968589d8 2458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
Kojto 90:cb3d968589d8 2459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
Kojto 90:cb3d968589d8 2461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
Kojto 90:cb3d968589d8 2462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
Kojto 90:cb3d968589d8 2464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
Kojto 90:cb3d968589d8 2465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
Kojto 90:cb3d968589d8 2467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
Kojto 90:cb3d968589d8 2468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
Kojto 90:cb3d968589d8 2470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
Kojto 90:cb3d968589d8 2471 /* LDR_CASR Bit Fields */
Kojto 90:cb3d968589d8 2472 #define CAU_LDR_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2473 #define CAU_LDR_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2474 #define CAU_LDR_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2475 #define CAU_LDR_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2477 #define CAU_LDR_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2479 /* LDR_CAA Bit Fields */
Kojto 90:cb3d968589d8 2480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2481 #define CAU_LDR_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2483 /* LDR_CA Bit Fields */
Kojto 90:cb3d968589d8 2484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2485 #define CAU_LDR_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2488 #define CAU_LDR_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2491 #define CAU_LDR_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2494 #define CAU_LDR_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2497 #define CAU_LDR_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2500 #define CAU_LDR_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2503 #define CAU_LDR_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2506 #define CAU_LDR_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2509 #define CAU_LDR_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2511 /* STR_CASR Bit Fields */
Kojto 90:cb3d968589d8 2512 #define CAU_STR_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2513 #define CAU_STR_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2514 #define CAU_STR_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2515 #define CAU_STR_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2516 #define CAU_STR_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2517 #define CAU_STR_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2519 /* STR_CAA Bit Fields */
Kojto 90:cb3d968589d8 2520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2521 #define CAU_STR_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2523 /* STR_CA Bit Fields */
Kojto 90:cb3d968589d8 2524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2525 #define CAU_STR_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2528 #define CAU_STR_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2531 #define CAU_STR_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2534 #define CAU_STR_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2537 #define CAU_STR_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2540 #define CAU_STR_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2543 #define CAU_STR_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2546 #define CAU_STR_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2549 #define CAU_STR_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2551 /* ADR_CASR Bit Fields */
Kojto 90:cb3d968589d8 2552 #define CAU_ADR_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2553 #define CAU_ADR_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2554 #define CAU_ADR_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2555 #define CAU_ADR_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2557 #define CAU_ADR_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2559 /* ADR_CAA Bit Fields */
Kojto 90:cb3d968589d8 2560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2561 #define CAU_ADR_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2563 /* ADR_CA Bit Fields */
Kojto 90:cb3d968589d8 2564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2565 #define CAU_ADR_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2568 #define CAU_ADR_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2571 #define CAU_ADR_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2574 #define CAU_ADR_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2577 #define CAU_ADR_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2580 #define CAU_ADR_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2583 #define CAU_ADR_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2586 #define CAU_ADR_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2589 #define CAU_ADR_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2591 /* RADR_CASR Bit Fields */
Kojto 90:cb3d968589d8 2592 #define CAU_RADR_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2593 #define CAU_RADR_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2594 #define CAU_RADR_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2595 #define CAU_RADR_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2597 #define CAU_RADR_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2599 /* RADR_CAA Bit Fields */
Kojto 90:cb3d968589d8 2600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2601 #define CAU_RADR_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2603 /* RADR_CA Bit Fields */
Kojto 90:cb3d968589d8 2604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2605 #define CAU_RADR_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2608 #define CAU_RADR_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2611 #define CAU_RADR_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2614 #define CAU_RADR_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2617 #define CAU_RADR_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2620 #define CAU_RADR_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2623 #define CAU_RADR_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2626 #define CAU_RADR_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2629 #define CAU_RADR_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2631 /* XOR_CASR Bit Fields */
Kojto 90:cb3d968589d8 2632 #define CAU_XOR_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2633 #define CAU_XOR_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2634 #define CAU_XOR_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2635 #define CAU_XOR_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2637 #define CAU_XOR_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2639 /* XOR_CAA Bit Fields */
Kojto 90:cb3d968589d8 2640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2641 #define CAU_XOR_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2643 /* XOR_CA Bit Fields */
Kojto 90:cb3d968589d8 2644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2645 #define CAU_XOR_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2648 #define CAU_XOR_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2651 #define CAU_XOR_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2654 #define CAU_XOR_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2657 #define CAU_XOR_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2660 #define CAU_XOR_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2663 #define CAU_XOR_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2666 #define CAU_XOR_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2669 #define CAU_XOR_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2671 /* ROTL_CASR Bit Fields */
Kojto 90:cb3d968589d8 2672 #define CAU_ROTL_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2673 #define CAU_ROTL_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2674 #define CAU_ROTL_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2675 #define CAU_ROTL_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2677 #define CAU_ROTL_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2679 /* ROTL_CAA Bit Fields */
Kojto 90:cb3d968589d8 2680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2681 #define CAU_ROTL_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2683 /* ROTL_CA Bit Fields */
Kojto 90:cb3d968589d8 2684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2685 #define CAU_ROTL_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2688 #define CAU_ROTL_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2691 #define CAU_ROTL_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2694 #define CAU_ROTL_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2697 #define CAU_ROTL_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2700 #define CAU_ROTL_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2703 #define CAU_ROTL_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2706 #define CAU_ROTL_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2709 #define CAU_ROTL_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2711 /* AESC_CASR Bit Fields */
Kojto 90:cb3d968589d8 2712 #define CAU_AESC_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2713 #define CAU_AESC_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2714 #define CAU_AESC_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2715 #define CAU_AESC_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2717 #define CAU_AESC_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2719 /* AESC_CAA Bit Fields */
Kojto 90:cb3d968589d8 2720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2721 #define CAU_AESC_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2723 /* AESC_CA Bit Fields */
Kojto 90:cb3d968589d8 2724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2725 #define CAU_AESC_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2728 #define CAU_AESC_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2731 #define CAU_AESC_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2734 #define CAU_AESC_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2737 #define CAU_AESC_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2740 #define CAU_AESC_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2743 #define CAU_AESC_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2746 #define CAU_AESC_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2749 #define CAU_AESC_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2751 /* AESIC_CASR Bit Fields */
Kojto 90:cb3d968589d8 2752 #define CAU_AESIC_CASR_IC_MASK 0x1u
Kojto 90:cb3d968589d8 2753 #define CAU_AESIC_CASR_IC_SHIFT 0
Kojto 90:cb3d968589d8 2754 #define CAU_AESIC_CASR_DPE_MASK 0x2u
Kojto 90:cb3d968589d8 2755 #define CAU_AESIC_CASR_DPE_SHIFT 1
Kojto 90:cb3d968589d8 2756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
Kojto 90:cb3d968589d8 2757 #define CAU_AESIC_CASR_VER_SHIFT 28
Kojto 90:cb3d968589d8 2758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
Kojto 90:cb3d968589d8 2759 /* AESIC_CAA Bit Fields */
Kojto 90:cb3d968589d8 2760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2761 #define CAU_AESIC_CAA_ACC_SHIFT 0
Kojto 90:cb3d968589d8 2762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
Kojto 90:cb3d968589d8 2763 /* AESIC_CA Bit Fields */
Kojto 90:cb3d968589d8 2764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2765 #define CAU_AESIC_CA_CA0_SHIFT 0
Kojto 90:cb3d968589d8 2766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
Kojto 90:cb3d968589d8 2767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2768 #define CAU_AESIC_CA_CA1_SHIFT 0
Kojto 90:cb3d968589d8 2769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
Kojto 90:cb3d968589d8 2770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2771 #define CAU_AESIC_CA_CA2_SHIFT 0
Kojto 90:cb3d968589d8 2772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
Kojto 90:cb3d968589d8 2773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2774 #define CAU_AESIC_CA_CA3_SHIFT 0
Kojto 90:cb3d968589d8 2775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
Kojto 90:cb3d968589d8 2776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2777 #define CAU_AESIC_CA_CA4_SHIFT 0
Kojto 90:cb3d968589d8 2778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
Kojto 90:cb3d968589d8 2779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2780 #define CAU_AESIC_CA_CA5_SHIFT 0
Kojto 90:cb3d968589d8 2781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
Kojto 90:cb3d968589d8 2782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2783 #define CAU_AESIC_CA_CA6_SHIFT 0
Kojto 90:cb3d968589d8 2784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
Kojto 90:cb3d968589d8 2785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2786 #define CAU_AESIC_CA_CA7_SHIFT 0
Kojto 90:cb3d968589d8 2787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
Kojto 90:cb3d968589d8 2788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2789 #define CAU_AESIC_CA_CA8_SHIFT 0
Kojto 90:cb3d968589d8 2790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
Kojto 90:cb3d968589d8 2791
Kojto 90:cb3d968589d8 2792 /*!
Kojto 90:cb3d968589d8 2793 * @}
Kojto 90:cb3d968589d8 2794 */ /* end of group CAU_Register_Masks */
Kojto 90:cb3d968589d8 2795
Kojto 90:cb3d968589d8 2796
Kojto 90:cb3d968589d8 2797 /* CAU - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 2798 /** Peripheral CAU base address */
Kojto 90:cb3d968589d8 2799 #define CAU_BASE (0xE0081000u)
Kojto 90:cb3d968589d8 2800 /** Peripheral CAU base pointer */
Kojto 90:cb3d968589d8 2801 #define CAU ((CAU_Type *)CAU_BASE)
Kojto 90:cb3d968589d8 2802 #define CAU_BASE_PTR (CAU)
Kojto 90:cb3d968589d8 2803 /** Array initializer of CAU peripheral base addresses */
Kojto 90:cb3d968589d8 2804 #define CAU_BASE_ADDRS { CAU_BASE }
Kojto 90:cb3d968589d8 2805 /** Array initializer of CAU peripheral base pointers */
Kojto 90:cb3d968589d8 2806 #define CAU_BASE_PTRS { CAU }
Kojto 90:cb3d968589d8 2807
Kojto 90:cb3d968589d8 2808 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2809 -- CAU - Register accessor macros
Kojto 90:cb3d968589d8 2810 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2811
Kojto 90:cb3d968589d8 2812 /*!
Kojto 90:cb3d968589d8 2813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
Kojto 90:cb3d968589d8 2814 * @{
Kojto 90:cb3d968589d8 2815 */
Kojto 90:cb3d968589d8 2816
Kojto 90:cb3d968589d8 2817
Kojto 90:cb3d968589d8 2818 /* CAU - Register instance definitions */
Kojto 90:cb3d968589d8 2819 /* CAU */
Kojto 90:cb3d968589d8 2820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
Kojto 90:cb3d968589d8 2821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
Kojto 90:cb3d968589d8 2822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
Kojto 90:cb3d968589d8 2823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
Kojto 90:cb3d968589d8 2824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
Kojto 90:cb3d968589d8 2825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
Kojto 90:cb3d968589d8 2826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
Kojto 90:cb3d968589d8 2827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
Kojto 90:cb3d968589d8 2828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
Kojto 90:cb3d968589d8 2829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
Kojto 90:cb3d968589d8 2830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
Kojto 90:cb3d968589d8 2831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
Kojto 90:cb3d968589d8 2832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
Kojto 90:cb3d968589d8 2833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
Kojto 90:cb3d968589d8 2834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
Kojto 90:cb3d968589d8 2835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
Kojto 90:cb3d968589d8 2836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
Kojto 90:cb3d968589d8 2914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
Kojto 90:cb3d968589d8 2915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
Kojto 90:cb3d968589d8 2916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
Kojto 90:cb3d968589d8 2917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
Kojto 90:cb3d968589d8 2918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
Kojto 90:cb3d968589d8 2919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
Kojto 90:cb3d968589d8 2920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
Kojto 90:cb3d968589d8 2921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
Kojto 90:cb3d968589d8 2922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
Kojto 90:cb3d968589d8 2923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
Kojto 90:cb3d968589d8 2924
Kojto 90:cb3d968589d8 2925 /* CAU - Register array accessors */
Kojto 90:cb3d968589d8 2926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
Kojto 90:cb3d968589d8 2927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
Kojto 90:cb3d968589d8 2935
Kojto 90:cb3d968589d8 2936 /*!
Kojto 90:cb3d968589d8 2937 * @}
Kojto 90:cb3d968589d8 2938 */ /* end of group CAU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2939
Kojto 90:cb3d968589d8 2940
Kojto 90:cb3d968589d8 2941 /*!
Kojto 90:cb3d968589d8 2942 * @}
Kojto 90:cb3d968589d8 2943 */ /* end of group CAU_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 2944
Kojto 90:cb3d968589d8 2945
Kojto 90:cb3d968589d8 2946 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2947 -- CMP Peripheral Access Layer
Kojto 90:cb3d968589d8 2948 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2949
Kojto 90:cb3d968589d8 2950 /*!
Kojto 90:cb3d968589d8 2951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Kojto 90:cb3d968589d8 2952 * @{
Kojto 90:cb3d968589d8 2953 */
Kojto 90:cb3d968589d8 2954
Kojto 90:cb3d968589d8 2955 /** CMP - Register Layout Typedef */
Kojto 90:cb3d968589d8 2956 typedef struct {
Kojto 90:cb3d968589d8 2957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
Kojto 90:cb3d968589d8 2958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
Kojto 90:cb3d968589d8 2959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
Kojto 90:cb3d968589d8 2960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
Kojto 90:cb3d968589d8 2961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
Kojto 90:cb3d968589d8 2962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
Kojto 90:cb3d968589d8 2963 } CMP_Type, *CMP_MemMapPtr;
Kojto 90:cb3d968589d8 2964
Kojto 90:cb3d968589d8 2965 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2966 -- CMP - Register accessor macros
Kojto 90:cb3d968589d8 2967 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2968
Kojto 90:cb3d968589d8 2969 /*!
Kojto 90:cb3d968589d8 2970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Kojto 90:cb3d968589d8 2971 * @{
Kojto 90:cb3d968589d8 2972 */
Kojto 90:cb3d968589d8 2973
Kojto 90:cb3d968589d8 2974
Kojto 90:cb3d968589d8 2975 /* CMP - Register accessors */
Kojto 90:cb3d968589d8 2976 #define CMP_CR0_REG(base) ((base)->CR0)
Kojto 90:cb3d968589d8 2977 #define CMP_CR1_REG(base) ((base)->CR1)
Kojto 90:cb3d968589d8 2978 #define CMP_FPR_REG(base) ((base)->FPR)
Kojto 90:cb3d968589d8 2979 #define CMP_SCR_REG(base) ((base)->SCR)
Kojto 90:cb3d968589d8 2980 #define CMP_DACCR_REG(base) ((base)->DACCR)
Kojto 90:cb3d968589d8 2981 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
Kojto 90:cb3d968589d8 2982
Kojto 90:cb3d968589d8 2983 /*!
Kojto 90:cb3d968589d8 2984 * @}
Kojto 90:cb3d968589d8 2985 */ /* end of group CMP_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2986
Kojto 90:cb3d968589d8 2987
Kojto 90:cb3d968589d8 2988 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2989 -- CMP Register Masks
Kojto 90:cb3d968589d8 2990 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2991
Kojto 90:cb3d968589d8 2992 /*!
Kojto 90:cb3d968589d8 2993 * @addtogroup CMP_Register_Masks CMP Register Masks
Kojto 90:cb3d968589d8 2994 * @{
Kojto 90:cb3d968589d8 2995 */
Kojto 90:cb3d968589d8 2996
Kojto 90:cb3d968589d8 2997 /* CR0 Bit Fields */
Kojto 90:cb3d968589d8 2998 #define CMP_CR0_HYSTCTR_MASK 0x3u
Kojto 90:cb3d968589d8 2999 #define CMP_CR0_HYSTCTR_SHIFT 0
Kojto 90:cb3d968589d8 3000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
Kojto 90:cb3d968589d8 3001 #define CMP_CR0_FILTER_CNT_MASK 0x70u
Kojto 90:cb3d968589d8 3002 #define CMP_CR0_FILTER_CNT_SHIFT 4
Kojto 90:cb3d968589d8 3003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
Kojto 90:cb3d968589d8 3004 /* CR1 Bit Fields */
Kojto 90:cb3d968589d8 3005 #define CMP_CR1_EN_MASK 0x1u
Kojto 90:cb3d968589d8 3006 #define CMP_CR1_EN_SHIFT 0
Kojto 90:cb3d968589d8 3007 #define CMP_CR1_OPE_MASK 0x2u
Kojto 90:cb3d968589d8 3008 #define CMP_CR1_OPE_SHIFT 1
Kojto 90:cb3d968589d8 3009 #define CMP_CR1_COS_MASK 0x4u
Kojto 90:cb3d968589d8 3010 #define CMP_CR1_COS_SHIFT 2
Kojto 90:cb3d968589d8 3011 #define CMP_CR1_INV_MASK 0x8u
Kojto 90:cb3d968589d8 3012 #define CMP_CR1_INV_SHIFT 3
Kojto 90:cb3d968589d8 3013 #define CMP_CR1_PMODE_MASK 0x10u
Kojto 90:cb3d968589d8 3014 #define CMP_CR1_PMODE_SHIFT 4
Kojto 90:cb3d968589d8 3015 #define CMP_CR1_WE_MASK 0x40u
Kojto 90:cb3d968589d8 3016 #define CMP_CR1_WE_SHIFT 6
Kojto 90:cb3d968589d8 3017 #define CMP_CR1_SE_MASK 0x80u
Kojto 90:cb3d968589d8 3018 #define CMP_CR1_SE_SHIFT 7
Kojto 90:cb3d968589d8 3019 /* FPR Bit Fields */
Kojto 90:cb3d968589d8 3020 #define CMP_FPR_FILT_PER_MASK 0xFFu
Kojto 90:cb3d968589d8 3021 #define CMP_FPR_FILT_PER_SHIFT 0
Kojto 90:cb3d968589d8 3022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
Kojto 90:cb3d968589d8 3023 /* SCR Bit Fields */
Kojto 90:cb3d968589d8 3024 #define CMP_SCR_COUT_MASK 0x1u
Kojto 90:cb3d968589d8 3025 #define CMP_SCR_COUT_SHIFT 0
Kojto 90:cb3d968589d8 3026 #define CMP_SCR_CFF_MASK 0x2u
Kojto 90:cb3d968589d8 3027 #define CMP_SCR_CFF_SHIFT 1
Kojto 90:cb3d968589d8 3028 #define CMP_SCR_CFR_MASK 0x4u
Kojto 90:cb3d968589d8 3029 #define CMP_SCR_CFR_SHIFT 2
Kojto 90:cb3d968589d8 3030 #define CMP_SCR_IEF_MASK 0x8u
Kojto 90:cb3d968589d8 3031 #define CMP_SCR_IEF_SHIFT 3
Kojto 90:cb3d968589d8 3032 #define CMP_SCR_IER_MASK 0x10u
Kojto 90:cb3d968589d8 3033 #define CMP_SCR_IER_SHIFT 4
Kojto 90:cb3d968589d8 3034 #define CMP_SCR_DMAEN_MASK 0x40u
Kojto 90:cb3d968589d8 3035 #define CMP_SCR_DMAEN_SHIFT 6
Kojto 90:cb3d968589d8 3036 /* DACCR Bit Fields */
Kojto 90:cb3d968589d8 3037 #define CMP_DACCR_VOSEL_MASK 0x3Fu
Kojto 90:cb3d968589d8 3038 #define CMP_DACCR_VOSEL_SHIFT 0
Kojto 90:cb3d968589d8 3039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
Kojto 90:cb3d968589d8 3040 #define CMP_DACCR_VRSEL_MASK 0x40u
Kojto 90:cb3d968589d8 3041 #define CMP_DACCR_VRSEL_SHIFT 6
Kojto 90:cb3d968589d8 3042 #define CMP_DACCR_DACEN_MASK 0x80u
Kojto 90:cb3d968589d8 3043 #define CMP_DACCR_DACEN_SHIFT 7
Kojto 90:cb3d968589d8 3044 /* MUXCR Bit Fields */
Kojto 90:cb3d968589d8 3045 #define CMP_MUXCR_MSEL_MASK 0x7u
Kojto 90:cb3d968589d8 3046 #define CMP_MUXCR_MSEL_SHIFT 0
Kojto 90:cb3d968589d8 3047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
Kojto 90:cb3d968589d8 3048 #define CMP_MUXCR_PSEL_MASK 0x38u
Kojto 90:cb3d968589d8 3049 #define CMP_MUXCR_PSEL_SHIFT 3
Kojto 90:cb3d968589d8 3050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
Kojto 90:cb3d968589d8 3051 #define CMP_MUXCR_PSTM_MASK 0x80u
Kojto 90:cb3d968589d8 3052 #define CMP_MUXCR_PSTM_SHIFT 7
Kojto 90:cb3d968589d8 3053
Kojto 90:cb3d968589d8 3054 /*!
Kojto 90:cb3d968589d8 3055 * @}
Kojto 90:cb3d968589d8 3056 */ /* end of group CMP_Register_Masks */
Kojto 90:cb3d968589d8 3057
Kojto 90:cb3d968589d8 3058
Kojto 90:cb3d968589d8 3059 /* CMP - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 3060 /** Peripheral CMP0 base address */
Kojto 90:cb3d968589d8 3061 #define CMP0_BASE (0x40073000u)
Kojto 90:cb3d968589d8 3062 /** Peripheral CMP0 base pointer */
Kojto 90:cb3d968589d8 3063 #define CMP0 ((CMP_Type *)CMP0_BASE)
Kojto 90:cb3d968589d8 3064 #define CMP0_BASE_PTR (CMP0)
Kojto 90:cb3d968589d8 3065 /** Peripheral CMP1 base address */
Kojto 90:cb3d968589d8 3066 #define CMP1_BASE (0x40073008u)
Kojto 90:cb3d968589d8 3067 /** Peripheral CMP1 base pointer */
Kojto 90:cb3d968589d8 3068 #define CMP1 ((CMP_Type *)CMP1_BASE)
Kojto 90:cb3d968589d8 3069 #define CMP1_BASE_PTR (CMP1)
Kojto 90:cb3d968589d8 3070 /** Peripheral CMP2 base address */
Kojto 90:cb3d968589d8 3071 #define CMP2_BASE (0x40073010u)
Kojto 90:cb3d968589d8 3072 /** Peripheral CMP2 base pointer */
Kojto 90:cb3d968589d8 3073 #define CMP2 ((CMP_Type *)CMP2_BASE)
Kojto 90:cb3d968589d8 3074 #define CMP2_BASE_PTR (CMP2)
Kojto 90:cb3d968589d8 3075 /** Array initializer of CMP peripheral base addresses */
Kojto 90:cb3d968589d8 3076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
Kojto 90:cb3d968589d8 3077 /** Array initializer of CMP peripheral base pointers */
Kojto 90:cb3d968589d8 3078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
Kojto 90:cb3d968589d8 3079 /** Interrupt vectors for the CMP peripheral type */
Kojto 90:cb3d968589d8 3080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
Kojto 90:cb3d968589d8 3081
Kojto 90:cb3d968589d8 3082 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3083 -- CMP - Register accessor macros
Kojto 90:cb3d968589d8 3084 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3085
Kojto 90:cb3d968589d8 3086 /*!
Kojto 90:cb3d968589d8 3087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Kojto 90:cb3d968589d8 3088 * @{
Kojto 90:cb3d968589d8 3089 */
Kojto 90:cb3d968589d8 3090
Kojto 90:cb3d968589d8 3091
Kojto 90:cb3d968589d8 3092 /* CMP - Register instance definitions */
Kojto 90:cb3d968589d8 3093 /* CMP0 */
Kojto 90:cb3d968589d8 3094 #define CMP0_CR0 CMP_CR0_REG(CMP0)
Kojto 90:cb3d968589d8 3095 #define CMP0_CR1 CMP_CR1_REG(CMP0)
Kojto 90:cb3d968589d8 3096 #define CMP0_FPR CMP_FPR_REG(CMP0)
Kojto 90:cb3d968589d8 3097 #define CMP0_SCR CMP_SCR_REG(CMP0)
Kojto 90:cb3d968589d8 3098 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
Kojto 90:cb3d968589d8 3099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
Kojto 90:cb3d968589d8 3100 /* CMP1 */
Kojto 90:cb3d968589d8 3101 #define CMP1_CR0 CMP_CR0_REG(CMP1)
Kojto 90:cb3d968589d8 3102 #define CMP1_CR1 CMP_CR1_REG(CMP1)
Kojto 90:cb3d968589d8 3103 #define CMP1_FPR CMP_FPR_REG(CMP1)
Kojto 90:cb3d968589d8 3104 #define CMP1_SCR CMP_SCR_REG(CMP1)
Kojto 90:cb3d968589d8 3105 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
Kojto 90:cb3d968589d8 3106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
Kojto 90:cb3d968589d8 3107 /* CMP2 */
Kojto 90:cb3d968589d8 3108 #define CMP2_CR0 CMP_CR0_REG(CMP2)
Kojto 90:cb3d968589d8 3109 #define CMP2_CR1 CMP_CR1_REG(CMP2)
Kojto 90:cb3d968589d8 3110 #define CMP2_FPR CMP_FPR_REG(CMP2)
Kojto 90:cb3d968589d8 3111 #define CMP2_SCR CMP_SCR_REG(CMP2)
Kojto 90:cb3d968589d8 3112 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
Kojto 90:cb3d968589d8 3113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
Kojto 90:cb3d968589d8 3114
Kojto 90:cb3d968589d8 3115 /*!
Kojto 90:cb3d968589d8 3116 * @}
Kojto 90:cb3d968589d8 3117 */ /* end of group CMP_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3118
Kojto 90:cb3d968589d8 3119
Kojto 90:cb3d968589d8 3120 /*!
Kojto 90:cb3d968589d8 3121 * @}
Kojto 90:cb3d968589d8 3122 */ /* end of group CMP_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 3123
Kojto 90:cb3d968589d8 3124
Kojto 90:cb3d968589d8 3125 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3126 -- CMT Peripheral Access Layer
Kojto 90:cb3d968589d8 3127 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3128
Kojto 90:cb3d968589d8 3129 /*!
Kojto 90:cb3d968589d8 3130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
Kojto 90:cb3d968589d8 3131 * @{
Kojto 90:cb3d968589d8 3132 */
Kojto 90:cb3d968589d8 3133
Kojto 90:cb3d968589d8 3134 /** CMT - Register Layout Typedef */
Kojto 90:cb3d968589d8 3135 typedef struct {
Kojto 90:cb3d968589d8 3136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 3137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
Kojto 90:cb3d968589d8 3138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
Kojto 90:cb3d968589d8 3139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
Kojto 90:cb3d968589d8 3140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
Kojto 90:cb3d968589d8 3141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
Kojto 90:cb3d968589d8 3142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
Kojto 90:cb3d968589d8 3143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
Kojto 90:cb3d968589d8 3144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
Kojto 90:cb3d968589d8 3145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
Kojto 90:cb3d968589d8 3146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
Kojto 90:cb3d968589d8 3147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
Kojto 90:cb3d968589d8 3148 } CMT_Type, *CMT_MemMapPtr;
Kojto 90:cb3d968589d8 3149
Kojto 90:cb3d968589d8 3150 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3151 -- CMT - Register accessor macros
Kojto 90:cb3d968589d8 3152 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3153
Kojto 90:cb3d968589d8 3154 /*!
Kojto 90:cb3d968589d8 3155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
Kojto 90:cb3d968589d8 3156 * @{
Kojto 90:cb3d968589d8 3157 */
Kojto 90:cb3d968589d8 3158
Kojto 90:cb3d968589d8 3159
Kojto 90:cb3d968589d8 3160 /* CMT - Register accessors */
Kojto 90:cb3d968589d8 3161 #define CMT_CGH1_REG(base) ((base)->CGH1)
Kojto 90:cb3d968589d8 3162 #define CMT_CGL1_REG(base) ((base)->CGL1)
Kojto 90:cb3d968589d8 3163 #define CMT_CGH2_REG(base) ((base)->CGH2)
Kojto 90:cb3d968589d8 3164 #define CMT_CGL2_REG(base) ((base)->CGL2)
Kojto 90:cb3d968589d8 3165 #define CMT_OC_REG(base) ((base)->OC)
Kojto 90:cb3d968589d8 3166 #define CMT_MSC_REG(base) ((base)->MSC)
Kojto 90:cb3d968589d8 3167 #define CMT_CMD1_REG(base) ((base)->CMD1)
Kojto 90:cb3d968589d8 3168 #define CMT_CMD2_REG(base) ((base)->CMD2)
Kojto 90:cb3d968589d8 3169 #define CMT_CMD3_REG(base) ((base)->CMD3)
Kojto 90:cb3d968589d8 3170 #define CMT_CMD4_REG(base) ((base)->CMD4)
Kojto 90:cb3d968589d8 3171 #define CMT_PPS_REG(base) ((base)->PPS)
Kojto 90:cb3d968589d8 3172 #define CMT_DMA_REG(base) ((base)->DMA)
Kojto 90:cb3d968589d8 3173
Kojto 90:cb3d968589d8 3174 /*!
Kojto 90:cb3d968589d8 3175 * @}
Kojto 90:cb3d968589d8 3176 */ /* end of group CMT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3177
Kojto 90:cb3d968589d8 3178
Kojto 90:cb3d968589d8 3179 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3180 -- CMT Register Masks
Kojto 90:cb3d968589d8 3181 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3182
Kojto 90:cb3d968589d8 3183 /*!
Kojto 90:cb3d968589d8 3184 * @addtogroup CMT_Register_Masks CMT Register Masks
Kojto 90:cb3d968589d8 3185 * @{
Kojto 90:cb3d968589d8 3186 */
Kojto 90:cb3d968589d8 3187
Kojto 90:cb3d968589d8 3188 /* CGH1 Bit Fields */
Kojto 90:cb3d968589d8 3189 #define CMT_CGH1_PH_MASK 0xFFu
Kojto 90:cb3d968589d8 3190 #define CMT_CGH1_PH_SHIFT 0
Kojto 90:cb3d968589d8 3191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
Kojto 90:cb3d968589d8 3192 /* CGL1 Bit Fields */
Kojto 90:cb3d968589d8 3193 #define CMT_CGL1_PL_MASK 0xFFu
Kojto 90:cb3d968589d8 3194 #define CMT_CGL1_PL_SHIFT 0
Kojto 90:cb3d968589d8 3195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
Kojto 90:cb3d968589d8 3196 /* CGH2 Bit Fields */
Kojto 90:cb3d968589d8 3197 #define CMT_CGH2_SH_MASK 0xFFu
Kojto 90:cb3d968589d8 3198 #define CMT_CGH2_SH_SHIFT 0
Kojto 90:cb3d968589d8 3199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
Kojto 90:cb3d968589d8 3200 /* CGL2 Bit Fields */
Kojto 90:cb3d968589d8 3201 #define CMT_CGL2_SL_MASK 0xFFu
Kojto 90:cb3d968589d8 3202 #define CMT_CGL2_SL_SHIFT 0
Kojto 90:cb3d968589d8 3203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
Kojto 90:cb3d968589d8 3204 /* OC Bit Fields */
Kojto 90:cb3d968589d8 3205 #define CMT_OC_IROPEN_MASK 0x20u
Kojto 90:cb3d968589d8 3206 #define CMT_OC_IROPEN_SHIFT 5
Kojto 90:cb3d968589d8 3207 #define CMT_OC_CMTPOL_MASK 0x40u
Kojto 90:cb3d968589d8 3208 #define CMT_OC_CMTPOL_SHIFT 6
Kojto 90:cb3d968589d8 3209 #define CMT_OC_IROL_MASK 0x80u
Kojto 90:cb3d968589d8 3210 #define CMT_OC_IROL_SHIFT 7
Kojto 90:cb3d968589d8 3211 /* MSC Bit Fields */
Kojto 90:cb3d968589d8 3212 #define CMT_MSC_MCGEN_MASK 0x1u
Kojto 90:cb3d968589d8 3213 #define CMT_MSC_MCGEN_SHIFT 0
Kojto 90:cb3d968589d8 3214 #define CMT_MSC_EOCIE_MASK 0x2u
Kojto 90:cb3d968589d8 3215 #define CMT_MSC_EOCIE_SHIFT 1
Kojto 90:cb3d968589d8 3216 #define CMT_MSC_FSK_MASK 0x4u
Kojto 90:cb3d968589d8 3217 #define CMT_MSC_FSK_SHIFT 2
Kojto 90:cb3d968589d8 3218 #define CMT_MSC_BASE_MASK 0x8u
Kojto 90:cb3d968589d8 3219 #define CMT_MSC_BASE_SHIFT 3
Kojto 90:cb3d968589d8 3220 #define CMT_MSC_EXSPC_MASK 0x10u
Kojto 90:cb3d968589d8 3221 #define CMT_MSC_EXSPC_SHIFT 4
Kojto 90:cb3d968589d8 3222 #define CMT_MSC_CMTDIV_MASK 0x60u
Kojto 90:cb3d968589d8 3223 #define CMT_MSC_CMTDIV_SHIFT 5
Kojto 90:cb3d968589d8 3224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
Kojto 90:cb3d968589d8 3225 #define CMT_MSC_EOCF_MASK 0x80u
Kojto 90:cb3d968589d8 3226 #define CMT_MSC_EOCF_SHIFT 7
Kojto 90:cb3d968589d8 3227 /* CMD1 Bit Fields */
Kojto 90:cb3d968589d8 3228 #define CMT_CMD1_MB_MASK 0xFFu
Kojto 90:cb3d968589d8 3229 #define CMT_CMD1_MB_SHIFT 0
Kojto 90:cb3d968589d8 3230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
Kojto 90:cb3d968589d8 3231 /* CMD2 Bit Fields */
Kojto 90:cb3d968589d8 3232 #define CMT_CMD2_MB_MASK 0xFFu
Kojto 90:cb3d968589d8 3233 #define CMT_CMD2_MB_SHIFT 0
Kojto 90:cb3d968589d8 3234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
Kojto 90:cb3d968589d8 3235 /* CMD3 Bit Fields */
Kojto 90:cb3d968589d8 3236 #define CMT_CMD3_SB_MASK 0xFFu
Kojto 90:cb3d968589d8 3237 #define CMT_CMD3_SB_SHIFT 0
Kojto 90:cb3d968589d8 3238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
Kojto 90:cb3d968589d8 3239 /* CMD4 Bit Fields */
Kojto 90:cb3d968589d8 3240 #define CMT_CMD4_SB_MASK 0xFFu
Kojto 90:cb3d968589d8 3241 #define CMT_CMD4_SB_SHIFT 0
Kojto 90:cb3d968589d8 3242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
Kojto 90:cb3d968589d8 3243 /* PPS Bit Fields */
Kojto 90:cb3d968589d8 3244 #define CMT_PPS_PPSDIV_MASK 0xFu
Kojto 90:cb3d968589d8 3245 #define CMT_PPS_PPSDIV_SHIFT 0
Kojto 90:cb3d968589d8 3246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
Kojto 90:cb3d968589d8 3247 /* DMA Bit Fields */
Kojto 90:cb3d968589d8 3248 #define CMT_DMA_DMA_MASK 0x1u
Kojto 90:cb3d968589d8 3249 #define CMT_DMA_DMA_SHIFT 0
Kojto 90:cb3d968589d8 3250
Kojto 90:cb3d968589d8 3251 /*!
Kojto 90:cb3d968589d8 3252 * @}
Kojto 90:cb3d968589d8 3253 */ /* end of group CMT_Register_Masks */
Kojto 90:cb3d968589d8 3254
Kojto 90:cb3d968589d8 3255
Kojto 90:cb3d968589d8 3256 /* CMT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 3257 /** Peripheral CMT base address */
Kojto 90:cb3d968589d8 3258 #define CMT_BASE (0x40062000u)
Kojto 90:cb3d968589d8 3259 /** Peripheral CMT base pointer */
Kojto 90:cb3d968589d8 3260 #define CMT ((CMT_Type *)CMT_BASE)
Kojto 90:cb3d968589d8 3261 #define CMT_BASE_PTR (CMT)
Kojto 90:cb3d968589d8 3262 /** Array initializer of CMT peripheral base addresses */
Kojto 90:cb3d968589d8 3263 #define CMT_BASE_ADDRS { CMT_BASE }
Kojto 90:cb3d968589d8 3264 /** Array initializer of CMT peripheral base pointers */
Kojto 90:cb3d968589d8 3265 #define CMT_BASE_PTRS { CMT }
Kojto 90:cb3d968589d8 3266 /** Interrupt vectors for the CMT peripheral type */
Kojto 90:cb3d968589d8 3267 #define CMT_IRQS { CMT_IRQn }
Kojto 90:cb3d968589d8 3268
Kojto 90:cb3d968589d8 3269 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3270 -- CMT - Register accessor macros
Kojto 90:cb3d968589d8 3271 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3272
Kojto 90:cb3d968589d8 3273 /*!
Kojto 90:cb3d968589d8 3274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
Kojto 90:cb3d968589d8 3275 * @{
Kojto 90:cb3d968589d8 3276 */
Kojto 90:cb3d968589d8 3277
Kojto 90:cb3d968589d8 3278
Kojto 90:cb3d968589d8 3279 /* CMT - Register instance definitions */
Kojto 90:cb3d968589d8 3280 /* CMT */
Kojto 90:cb3d968589d8 3281 #define CMT_CGH1 CMT_CGH1_REG(CMT)
Kojto 90:cb3d968589d8 3282 #define CMT_CGL1 CMT_CGL1_REG(CMT)
Kojto 90:cb3d968589d8 3283 #define CMT_CGH2 CMT_CGH2_REG(CMT)
Kojto 90:cb3d968589d8 3284 #define CMT_CGL2 CMT_CGL2_REG(CMT)
Kojto 90:cb3d968589d8 3285 #define CMT_OC CMT_OC_REG(CMT)
Kojto 90:cb3d968589d8 3286 #define CMT_MSC CMT_MSC_REG(CMT)
Kojto 90:cb3d968589d8 3287 #define CMT_CMD1 CMT_CMD1_REG(CMT)
Kojto 90:cb3d968589d8 3288 #define CMT_CMD2 CMT_CMD2_REG(CMT)
Kojto 90:cb3d968589d8 3289 #define CMT_CMD3 CMT_CMD3_REG(CMT)
Kojto 90:cb3d968589d8 3290 #define CMT_CMD4 CMT_CMD4_REG(CMT)
Kojto 90:cb3d968589d8 3291 #define CMT_PPS CMT_PPS_REG(CMT)
Kojto 90:cb3d968589d8 3292 #define CMT_DMA CMT_DMA_REG(CMT)
Kojto 90:cb3d968589d8 3293
Kojto 90:cb3d968589d8 3294 /*!
Kojto 90:cb3d968589d8 3295 * @}
Kojto 90:cb3d968589d8 3296 */ /* end of group CMT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3297
Kojto 90:cb3d968589d8 3298
Kojto 90:cb3d968589d8 3299 /*!
Kojto 90:cb3d968589d8 3300 * @}
Kojto 90:cb3d968589d8 3301 */ /* end of group CMT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 3302
Kojto 90:cb3d968589d8 3303
Kojto 90:cb3d968589d8 3304 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3305 -- CRC Peripheral Access Layer
Kojto 90:cb3d968589d8 3306 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3307
Kojto 90:cb3d968589d8 3308 /*!
Kojto 90:cb3d968589d8 3309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
Kojto 90:cb3d968589d8 3310 * @{
Kojto 90:cb3d968589d8 3311 */
Kojto 90:cb3d968589d8 3312
Kojto 90:cb3d968589d8 3313 /** CRC - Register Layout Typedef */
Kojto 90:cb3d968589d8 3314 typedef struct {
Kojto 90:cb3d968589d8 3315 union { /* offset: 0x0 */
Kojto 90:cb3d968589d8 3316 struct { /* offset: 0x0 */
Kojto 90:cb3d968589d8 3317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
Kojto 90:cb3d968589d8 3318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
Kojto 90:cb3d968589d8 3319 } ACCESS16BIT;
Kojto 90:cb3d968589d8 3320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
Kojto 90:cb3d968589d8 3321 struct { /* offset: 0x0 */
Kojto 90:cb3d968589d8 3322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
Kojto 90:cb3d968589d8 3323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
Kojto 90:cb3d968589d8 3324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
Kojto 90:cb3d968589d8 3325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
Kojto 90:cb3d968589d8 3326 } ACCESS8BIT;
Kojto 90:cb3d968589d8 3327 };
Kojto 90:cb3d968589d8 3328 union { /* offset: 0x4 */
Kojto 90:cb3d968589d8 3329 struct { /* offset: 0x4 */
Kojto 90:cb3d968589d8 3330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
Kojto 90:cb3d968589d8 3331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
Kojto 90:cb3d968589d8 3332 } GPOLY_ACCESS16BIT;
Kojto 90:cb3d968589d8 3333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
Kojto 90:cb3d968589d8 3334 struct { /* offset: 0x4 */
Kojto 90:cb3d968589d8 3335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
Kojto 90:cb3d968589d8 3336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
Kojto 90:cb3d968589d8 3337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
Kojto 90:cb3d968589d8 3338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
Kojto 90:cb3d968589d8 3339 } GPOLY_ACCESS8BIT;
Kojto 90:cb3d968589d8 3340 };
Kojto 90:cb3d968589d8 3341 union { /* offset: 0x8 */
Kojto 90:cb3d968589d8 3342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
Kojto 90:cb3d968589d8 3343 struct { /* offset: 0x8 */
Kojto 90:cb3d968589d8 3344 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 3345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
Kojto 90:cb3d968589d8 3346 } CTRL_ACCESS8BIT;
Kojto 90:cb3d968589d8 3347 };
Kojto 90:cb3d968589d8 3348 } CRC_Type, *CRC_MemMapPtr;
Kojto 90:cb3d968589d8 3349
Kojto 90:cb3d968589d8 3350 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3351 -- CRC - Register accessor macros
Kojto 90:cb3d968589d8 3352 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3353
Kojto 90:cb3d968589d8 3354 /*!
Kojto 90:cb3d968589d8 3355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
Kojto 90:cb3d968589d8 3356 * @{
Kojto 90:cb3d968589d8 3357 */
Kojto 90:cb3d968589d8 3358
Kojto 90:cb3d968589d8 3359
Kojto 90:cb3d968589d8 3360 /* CRC - Register accessors */
Kojto 90:cb3d968589d8 3361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
Kojto 90:cb3d968589d8 3362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
Kojto 90:cb3d968589d8 3363 #define CRC_DATA_REG(base) ((base)->DATA)
Kojto 90:cb3d968589d8 3364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
Kojto 90:cb3d968589d8 3365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
Kojto 90:cb3d968589d8 3366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
Kojto 90:cb3d968589d8 3367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
Kojto 90:cb3d968589d8 3368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
Kojto 90:cb3d968589d8 3369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
Kojto 90:cb3d968589d8 3370 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
Kojto 90:cb3d968589d8 3371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
Kojto 90:cb3d968589d8 3372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
Kojto 90:cb3d968589d8 3373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
Kojto 90:cb3d968589d8 3374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
Kojto 90:cb3d968589d8 3375 #define CRC_CTRL_REG(base) ((base)->CTRL)
Kojto 90:cb3d968589d8 3376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
Kojto 90:cb3d968589d8 3377
Kojto 90:cb3d968589d8 3378 /*!
Kojto 90:cb3d968589d8 3379 * @}
Kojto 90:cb3d968589d8 3380 */ /* end of group CRC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3381
Kojto 90:cb3d968589d8 3382
Kojto 90:cb3d968589d8 3383 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3384 -- CRC Register Masks
Kojto 90:cb3d968589d8 3385 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3386
Kojto 90:cb3d968589d8 3387 /*!
Kojto 90:cb3d968589d8 3388 * @addtogroup CRC_Register_Masks CRC Register Masks
Kojto 90:cb3d968589d8 3389 * @{
Kojto 90:cb3d968589d8 3390 */
Kojto 90:cb3d968589d8 3391
Kojto 90:cb3d968589d8 3392 /* DATAL Bit Fields */
Kojto 90:cb3d968589d8 3393 #define CRC_DATAL_DATAL_MASK 0xFFFFu
Kojto 90:cb3d968589d8 3394 #define CRC_DATAL_DATAL_SHIFT 0
Kojto 90:cb3d968589d8 3395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
Kojto 90:cb3d968589d8 3396 /* DATAH Bit Fields */
Kojto 90:cb3d968589d8 3397 #define CRC_DATAH_DATAH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 3398 #define CRC_DATAH_DATAH_SHIFT 0
Kojto 90:cb3d968589d8 3399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
Kojto 90:cb3d968589d8 3400 /* DATA Bit Fields */
Kojto 90:cb3d968589d8 3401 #define CRC_DATA_LL_MASK 0xFFu
Kojto 90:cb3d968589d8 3402 #define CRC_DATA_LL_SHIFT 0
Kojto 90:cb3d968589d8 3403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
Kojto 90:cb3d968589d8 3404 #define CRC_DATA_LU_MASK 0xFF00u
Kojto 90:cb3d968589d8 3405 #define CRC_DATA_LU_SHIFT 8
Kojto 90:cb3d968589d8 3406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
Kojto 90:cb3d968589d8 3407 #define CRC_DATA_HL_MASK 0xFF0000u
Kojto 90:cb3d968589d8 3408 #define CRC_DATA_HL_SHIFT 16
Kojto 90:cb3d968589d8 3409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
Kojto 90:cb3d968589d8 3410 #define CRC_DATA_HU_MASK 0xFF000000u
Kojto 90:cb3d968589d8 3411 #define CRC_DATA_HU_SHIFT 24
Kojto 90:cb3d968589d8 3412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
Kojto 90:cb3d968589d8 3413 /* DATALL Bit Fields */
Kojto 90:cb3d968589d8 3414 #define CRC_DATALL_DATALL_MASK 0xFFu
Kojto 90:cb3d968589d8 3415 #define CRC_DATALL_DATALL_SHIFT 0
Kojto 90:cb3d968589d8 3416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
Kojto 90:cb3d968589d8 3417 /* DATALU Bit Fields */
Kojto 90:cb3d968589d8 3418 #define CRC_DATALU_DATALU_MASK 0xFFu
Kojto 90:cb3d968589d8 3419 #define CRC_DATALU_DATALU_SHIFT 0
Kojto 90:cb3d968589d8 3420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
Kojto 90:cb3d968589d8 3421 /* DATAHL Bit Fields */
Kojto 90:cb3d968589d8 3422 #define CRC_DATAHL_DATAHL_MASK 0xFFu
Kojto 90:cb3d968589d8 3423 #define CRC_DATAHL_DATAHL_SHIFT 0
Kojto 90:cb3d968589d8 3424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
Kojto 90:cb3d968589d8 3425 /* DATAHU Bit Fields */
Kojto 90:cb3d968589d8 3426 #define CRC_DATAHU_DATAHU_MASK 0xFFu
Kojto 90:cb3d968589d8 3427 #define CRC_DATAHU_DATAHU_SHIFT 0
Kojto 90:cb3d968589d8 3428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
Kojto 90:cb3d968589d8 3429 /* GPOLYL Bit Fields */
Kojto 90:cb3d968589d8 3430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
Kojto 90:cb3d968589d8 3431 #define CRC_GPOLYL_GPOLYL_SHIFT 0
Kojto 90:cb3d968589d8 3432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
Kojto 90:cb3d968589d8 3433 /* GPOLYH Bit Fields */
Kojto 90:cb3d968589d8 3434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 3435 #define CRC_GPOLYH_GPOLYH_SHIFT 0
Kojto 90:cb3d968589d8 3436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
Kojto 90:cb3d968589d8 3437 /* GPOLY Bit Fields */
Kojto 90:cb3d968589d8 3438 #define CRC_GPOLY_LOW_MASK 0xFFFFu
Kojto 90:cb3d968589d8 3439 #define CRC_GPOLY_LOW_SHIFT 0
Kojto 90:cb3d968589d8 3440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
Kojto 90:cb3d968589d8 3441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 3442 #define CRC_GPOLY_HIGH_SHIFT 16
Kojto 90:cb3d968589d8 3443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
Kojto 90:cb3d968589d8 3444 /* GPOLYLL Bit Fields */
Kojto 90:cb3d968589d8 3445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
Kojto 90:cb3d968589d8 3446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
Kojto 90:cb3d968589d8 3447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
Kojto 90:cb3d968589d8 3448 /* GPOLYLU Bit Fields */
Kojto 90:cb3d968589d8 3449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
Kojto 90:cb3d968589d8 3450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
Kojto 90:cb3d968589d8 3451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
Kojto 90:cb3d968589d8 3452 /* GPOLYHL Bit Fields */
Kojto 90:cb3d968589d8 3453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
Kojto 90:cb3d968589d8 3454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
Kojto 90:cb3d968589d8 3455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
Kojto 90:cb3d968589d8 3456 /* GPOLYHU Bit Fields */
Kojto 90:cb3d968589d8 3457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
Kojto 90:cb3d968589d8 3458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
Kojto 90:cb3d968589d8 3459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
Kojto 90:cb3d968589d8 3460 /* CTRL Bit Fields */
Kojto 90:cb3d968589d8 3461 #define CRC_CTRL_TCRC_MASK 0x1000000u
Kojto 90:cb3d968589d8 3462 #define CRC_CTRL_TCRC_SHIFT 24
Kojto 90:cb3d968589d8 3463 #define CRC_CTRL_WAS_MASK 0x2000000u
Kojto 90:cb3d968589d8 3464 #define CRC_CTRL_WAS_SHIFT 25
Kojto 90:cb3d968589d8 3465 #define CRC_CTRL_FXOR_MASK 0x4000000u
Kojto 90:cb3d968589d8 3466 #define CRC_CTRL_FXOR_SHIFT 26
Kojto 90:cb3d968589d8 3467 #define CRC_CTRL_TOTR_MASK 0x30000000u
Kojto 90:cb3d968589d8 3468 #define CRC_CTRL_TOTR_SHIFT 28
Kojto 90:cb3d968589d8 3469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
Kojto 90:cb3d968589d8 3470 #define CRC_CTRL_TOT_MASK 0xC0000000u
Kojto 90:cb3d968589d8 3471 #define CRC_CTRL_TOT_SHIFT 30
Kojto 90:cb3d968589d8 3472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
Kojto 90:cb3d968589d8 3473 /* CTRLHU Bit Fields */
Kojto 90:cb3d968589d8 3474 #define CRC_CTRLHU_TCRC_MASK 0x1u
Kojto 90:cb3d968589d8 3475 #define CRC_CTRLHU_TCRC_SHIFT 0
Kojto 90:cb3d968589d8 3476 #define CRC_CTRLHU_WAS_MASK 0x2u
Kojto 90:cb3d968589d8 3477 #define CRC_CTRLHU_WAS_SHIFT 1
Kojto 90:cb3d968589d8 3478 #define CRC_CTRLHU_FXOR_MASK 0x4u
Kojto 90:cb3d968589d8 3479 #define CRC_CTRLHU_FXOR_SHIFT 2
Kojto 90:cb3d968589d8 3480 #define CRC_CTRLHU_TOTR_MASK 0x30u
Kojto 90:cb3d968589d8 3481 #define CRC_CTRLHU_TOTR_SHIFT 4
Kojto 90:cb3d968589d8 3482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
Kojto 90:cb3d968589d8 3483 #define CRC_CTRLHU_TOT_MASK 0xC0u
Kojto 90:cb3d968589d8 3484 #define CRC_CTRLHU_TOT_SHIFT 6
Kojto 90:cb3d968589d8 3485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
Kojto 90:cb3d968589d8 3486
Kojto 90:cb3d968589d8 3487 /*!
Kojto 90:cb3d968589d8 3488 * @}
Kojto 90:cb3d968589d8 3489 */ /* end of group CRC_Register_Masks */
Kojto 90:cb3d968589d8 3490
Kojto 90:cb3d968589d8 3491
Kojto 90:cb3d968589d8 3492 /* CRC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 3493 /** Peripheral CRC base address */
Kojto 90:cb3d968589d8 3494 #define CRC_BASE (0x40032000u)
Kojto 90:cb3d968589d8 3495 /** Peripheral CRC base pointer */
Kojto 90:cb3d968589d8 3496 #define CRC0 ((CRC_Type *)CRC_BASE)
Kojto 90:cb3d968589d8 3497 #define CRC_BASE_PTR (CRC0)
Kojto 90:cb3d968589d8 3498 /** Array initializer of CRC peripheral base addresses */
Kojto 90:cb3d968589d8 3499 #define CRC_BASE_ADDRS { CRC_BASE }
Kojto 90:cb3d968589d8 3500 /** Array initializer of CRC peripheral base pointers */
Kojto 90:cb3d968589d8 3501 #define CRC_BASE_PTRS { CRC0 }
Kojto 90:cb3d968589d8 3502
Kojto 90:cb3d968589d8 3503 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3504 -- CRC - Register accessor macros
Kojto 90:cb3d968589d8 3505 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3506
Kojto 90:cb3d968589d8 3507 /*!
Kojto 90:cb3d968589d8 3508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
Kojto 90:cb3d968589d8 3509 * @{
Kojto 90:cb3d968589d8 3510 */
Kojto 90:cb3d968589d8 3511
Kojto 90:cb3d968589d8 3512
Kojto 90:cb3d968589d8 3513 /* CRC - Register instance definitions */
Kojto 90:cb3d968589d8 3514 /* CRC */
Kojto 90:cb3d968589d8 3515 #define CRC_DATA CRC_DATA_REG(CRC0)
Kojto 90:cb3d968589d8 3516 #define CRC_DATAL CRC_DATAL_REG(CRC0)
Kojto 90:cb3d968589d8 3517 #define CRC_DATALL CRC_DATALL_REG(CRC0)
Kojto 90:cb3d968589d8 3518 #define CRC_DATALU CRC_DATALU_REG(CRC0)
Kojto 90:cb3d968589d8 3519 #define CRC_DATAH CRC_DATAH_REG(CRC0)
Kojto 90:cb3d968589d8 3520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
Kojto 90:cb3d968589d8 3521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
Kojto 90:cb3d968589d8 3522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
Kojto 90:cb3d968589d8 3523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
Kojto 90:cb3d968589d8 3524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
Kojto 90:cb3d968589d8 3525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
Kojto 90:cb3d968589d8 3526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
Kojto 90:cb3d968589d8 3527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
Kojto 90:cb3d968589d8 3528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
Kojto 90:cb3d968589d8 3529 #define CRC_CTRL CRC_CTRL_REG(CRC0)
Kojto 90:cb3d968589d8 3530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
Kojto 90:cb3d968589d8 3531
Kojto 90:cb3d968589d8 3532 /*!
Kojto 90:cb3d968589d8 3533 * @}
Kojto 90:cb3d968589d8 3534 */ /* end of group CRC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3535
Kojto 90:cb3d968589d8 3536
Kojto 90:cb3d968589d8 3537 /*!
Kojto 90:cb3d968589d8 3538 * @}
Kojto 90:cb3d968589d8 3539 */ /* end of group CRC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 3540
Kojto 90:cb3d968589d8 3541
Kojto 90:cb3d968589d8 3542 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3543 -- DAC Peripheral Access Layer
Kojto 90:cb3d968589d8 3544 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3545
Kojto 90:cb3d968589d8 3546 /*!
Kojto 90:cb3d968589d8 3547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
Kojto 90:cb3d968589d8 3548 * @{
Kojto 90:cb3d968589d8 3549 */
Kojto 90:cb3d968589d8 3550
Kojto 90:cb3d968589d8 3551 /** DAC - Register Layout Typedef */
Kojto 90:cb3d968589d8 3552 typedef struct {
Kojto 90:cb3d968589d8 3553 struct { /* offset: 0x0, array step: 0x2 */
Kojto 90:cb3d968589d8 3554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
Kojto 90:cb3d968589d8 3555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
Kojto 90:cb3d968589d8 3556 } DAT[16];
Kojto 90:cb3d968589d8 3557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
Kojto 90:cb3d968589d8 3558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
Kojto 90:cb3d968589d8 3559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
Kojto 90:cb3d968589d8 3560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
Kojto 90:cb3d968589d8 3561 } DAC_Type, *DAC_MemMapPtr;
Kojto 90:cb3d968589d8 3562
Kojto 90:cb3d968589d8 3563 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3564 -- DAC - Register accessor macros
Kojto 90:cb3d968589d8 3565 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3566
Kojto 90:cb3d968589d8 3567 /*!
Kojto 90:cb3d968589d8 3568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Kojto 90:cb3d968589d8 3569 * @{
Kojto 90:cb3d968589d8 3570 */
Kojto 90:cb3d968589d8 3571
Kojto 90:cb3d968589d8 3572
Kojto 90:cb3d968589d8 3573 /* DAC - Register accessors */
Kojto 90:cb3d968589d8 3574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
Kojto 90:cb3d968589d8 3575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
Kojto 90:cb3d968589d8 3576 #define DAC_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 3577 #define DAC_C0_REG(base) ((base)->C0)
Kojto 90:cb3d968589d8 3578 #define DAC_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 3579 #define DAC_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 3580
Kojto 90:cb3d968589d8 3581 /*!
Kojto 90:cb3d968589d8 3582 * @}
Kojto 90:cb3d968589d8 3583 */ /* end of group DAC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3584
Kojto 90:cb3d968589d8 3585
Kojto 90:cb3d968589d8 3586 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3587 -- DAC Register Masks
Kojto 90:cb3d968589d8 3588 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3589
Kojto 90:cb3d968589d8 3590 /*!
Kojto 90:cb3d968589d8 3591 * @addtogroup DAC_Register_Masks DAC Register Masks
Kojto 90:cb3d968589d8 3592 * @{
Kojto 90:cb3d968589d8 3593 */
Kojto 90:cb3d968589d8 3594
Kojto 90:cb3d968589d8 3595 /* DATL Bit Fields */
Kojto 90:cb3d968589d8 3596 #define DAC_DATL_DATA0_MASK 0xFFu
Kojto 90:cb3d968589d8 3597 #define DAC_DATL_DATA0_SHIFT 0
Kojto 90:cb3d968589d8 3598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
Kojto 90:cb3d968589d8 3599 /* DATH Bit Fields */
Kojto 90:cb3d968589d8 3600 #define DAC_DATH_DATA1_MASK 0xFu
Kojto 90:cb3d968589d8 3601 #define DAC_DATH_DATA1_SHIFT 0
Kojto 90:cb3d968589d8 3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
Kojto 90:cb3d968589d8 3603 /* SR Bit Fields */
Kojto 90:cb3d968589d8 3604 #define DAC_SR_DACBFRPBF_MASK 0x1u
Kojto 90:cb3d968589d8 3605 #define DAC_SR_DACBFRPBF_SHIFT 0
Kojto 90:cb3d968589d8 3606 #define DAC_SR_DACBFRPTF_MASK 0x2u
Kojto 90:cb3d968589d8 3607 #define DAC_SR_DACBFRPTF_SHIFT 1
Kojto 90:cb3d968589d8 3608 #define DAC_SR_DACBFWMF_MASK 0x4u
Kojto 90:cb3d968589d8 3609 #define DAC_SR_DACBFWMF_SHIFT 2
Kojto 90:cb3d968589d8 3610 /* C0 Bit Fields */
Kojto 90:cb3d968589d8 3611 #define DAC_C0_DACBBIEN_MASK 0x1u
Kojto 90:cb3d968589d8 3612 #define DAC_C0_DACBBIEN_SHIFT 0
Kojto 90:cb3d968589d8 3613 #define DAC_C0_DACBTIEN_MASK 0x2u
Kojto 90:cb3d968589d8 3614 #define DAC_C0_DACBTIEN_SHIFT 1
Kojto 90:cb3d968589d8 3615 #define DAC_C0_DACBWIEN_MASK 0x4u
Kojto 90:cb3d968589d8 3616 #define DAC_C0_DACBWIEN_SHIFT 2
Kojto 90:cb3d968589d8 3617 #define DAC_C0_LPEN_MASK 0x8u
Kojto 90:cb3d968589d8 3618 #define DAC_C0_LPEN_SHIFT 3
Kojto 90:cb3d968589d8 3619 #define DAC_C0_DACSWTRG_MASK 0x10u
Kojto 90:cb3d968589d8 3620 #define DAC_C0_DACSWTRG_SHIFT 4
Kojto 90:cb3d968589d8 3621 #define DAC_C0_DACTRGSEL_MASK 0x20u
Kojto 90:cb3d968589d8 3622 #define DAC_C0_DACTRGSEL_SHIFT 5
Kojto 90:cb3d968589d8 3623 #define DAC_C0_DACRFS_MASK 0x40u
Kojto 90:cb3d968589d8 3624 #define DAC_C0_DACRFS_SHIFT 6
Kojto 90:cb3d968589d8 3625 #define DAC_C0_DACEN_MASK 0x80u
Kojto 90:cb3d968589d8 3626 #define DAC_C0_DACEN_SHIFT 7
Kojto 90:cb3d968589d8 3627 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 3628 #define DAC_C1_DACBFEN_MASK 0x1u
Kojto 90:cb3d968589d8 3629 #define DAC_C1_DACBFEN_SHIFT 0
Kojto 90:cb3d968589d8 3630 #define DAC_C1_DACBFMD_MASK 0x6u
Kojto 90:cb3d968589d8 3631 #define DAC_C1_DACBFMD_SHIFT 1
Kojto 90:cb3d968589d8 3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
Kojto 90:cb3d968589d8 3633 #define DAC_C1_DACBFWM_MASK 0x18u
Kojto 90:cb3d968589d8 3634 #define DAC_C1_DACBFWM_SHIFT 3
Kojto 90:cb3d968589d8 3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
Kojto 90:cb3d968589d8 3636 #define DAC_C1_DMAEN_MASK 0x80u
Kojto 90:cb3d968589d8 3637 #define DAC_C1_DMAEN_SHIFT 7
Kojto 90:cb3d968589d8 3638 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 3639 #define DAC_C2_DACBFUP_MASK 0xFu
Kojto 90:cb3d968589d8 3640 #define DAC_C2_DACBFUP_SHIFT 0
Kojto 90:cb3d968589d8 3641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
Kojto 90:cb3d968589d8 3642 #define DAC_C2_DACBFRP_MASK 0xF0u
Kojto 90:cb3d968589d8 3643 #define DAC_C2_DACBFRP_SHIFT 4
Kojto 90:cb3d968589d8 3644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
Kojto 90:cb3d968589d8 3645
Kojto 90:cb3d968589d8 3646 /*!
Kojto 90:cb3d968589d8 3647 * @}
Kojto 90:cb3d968589d8 3648 */ /* end of group DAC_Register_Masks */
Kojto 90:cb3d968589d8 3649
Kojto 90:cb3d968589d8 3650
Kojto 90:cb3d968589d8 3651 /* DAC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 3652 /** Peripheral DAC0 base address */
Kojto 90:cb3d968589d8 3653 #define DAC0_BASE (0x400CC000u)
Kojto 90:cb3d968589d8 3654 /** Peripheral DAC0 base pointer */
Kojto 90:cb3d968589d8 3655 #define DAC0 ((DAC_Type *)DAC0_BASE)
Kojto 90:cb3d968589d8 3656 #define DAC0_BASE_PTR (DAC0)
Kojto 90:cb3d968589d8 3657 /** Peripheral DAC1 base address */
Kojto 90:cb3d968589d8 3658 #define DAC1_BASE (0x400CD000u)
Kojto 90:cb3d968589d8 3659 /** Peripheral DAC1 base pointer */
Kojto 90:cb3d968589d8 3660 #define DAC1 ((DAC_Type *)DAC1_BASE)
Kojto 90:cb3d968589d8 3661 #define DAC1_BASE_PTR (DAC1)
Kojto 90:cb3d968589d8 3662 /** Array initializer of DAC peripheral base addresses */
Kojto 90:cb3d968589d8 3663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
Kojto 90:cb3d968589d8 3664 /** Array initializer of DAC peripheral base pointers */
Kojto 90:cb3d968589d8 3665 #define DAC_BASE_PTRS { DAC0, DAC1 }
Kojto 90:cb3d968589d8 3666 /** Interrupt vectors for the DAC peripheral type */
Kojto 90:cb3d968589d8 3667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
Kojto 90:cb3d968589d8 3668
Kojto 90:cb3d968589d8 3669 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3670 -- DAC - Register accessor macros
Kojto 90:cb3d968589d8 3671 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3672
Kojto 90:cb3d968589d8 3673 /*!
Kojto 90:cb3d968589d8 3674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Kojto 90:cb3d968589d8 3675 * @{
Kojto 90:cb3d968589d8 3676 */
Kojto 90:cb3d968589d8 3677
Kojto 90:cb3d968589d8 3678
Kojto 90:cb3d968589d8 3679 /* DAC - Register instance definitions */
Kojto 90:cb3d968589d8 3680 /* DAC0 */
Kojto 90:cb3d968589d8 3681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
Kojto 90:cb3d968589d8 3682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
Kojto 90:cb3d968589d8 3683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
Kojto 90:cb3d968589d8 3684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
Kojto 90:cb3d968589d8 3685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
Kojto 90:cb3d968589d8 3686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
Kojto 90:cb3d968589d8 3687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
Kojto 90:cb3d968589d8 3688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
Kojto 90:cb3d968589d8 3689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
Kojto 90:cb3d968589d8 3690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
Kojto 90:cb3d968589d8 3691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
Kojto 90:cb3d968589d8 3692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
Kojto 90:cb3d968589d8 3693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
Kojto 90:cb3d968589d8 3694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
Kojto 90:cb3d968589d8 3695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
Kojto 90:cb3d968589d8 3696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
Kojto 90:cb3d968589d8 3697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
Kojto 90:cb3d968589d8 3698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
Kojto 90:cb3d968589d8 3699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
Kojto 90:cb3d968589d8 3700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
Kojto 90:cb3d968589d8 3701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
Kojto 90:cb3d968589d8 3702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
Kojto 90:cb3d968589d8 3703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
Kojto 90:cb3d968589d8 3704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
Kojto 90:cb3d968589d8 3705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
Kojto 90:cb3d968589d8 3706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
Kojto 90:cb3d968589d8 3707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
Kojto 90:cb3d968589d8 3708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
Kojto 90:cb3d968589d8 3709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
Kojto 90:cb3d968589d8 3710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
Kojto 90:cb3d968589d8 3711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
Kojto 90:cb3d968589d8 3712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
Kojto 90:cb3d968589d8 3713 #define DAC0_SR DAC_SR_REG(DAC0)
Kojto 90:cb3d968589d8 3714 #define DAC0_C0 DAC_C0_REG(DAC0)
Kojto 90:cb3d968589d8 3715 #define DAC0_C1 DAC_C1_REG(DAC0)
Kojto 90:cb3d968589d8 3716 #define DAC0_C2 DAC_C2_REG(DAC0)
Kojto 90:cb3d968589d8 3717 /* DAC1 */
Kojto 90:cb3d968589d8 3718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
Kojto 90:cb3d968589d8 3719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
Kojto 90:cb3d968589d8 3720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
Kojto 90:cb3d968589d8 3721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
Kojto 90:cb3d968589d8 3722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
Kojto 90:cb3d968589d8 3723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
Kojto 90:cb3d968589d8 3724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
Kojto 90:cb3d968589d8 3725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
Kojto 90:cb3d968589d8 3726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
Kojto 90:cb3d968589d8 3727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
Kojto 90:cb3d968589d8 3728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
Kojto 90:cb3d968589d8 3729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
Kojto 90:cb3d968589d8 3730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
Kojto 90:cb3d968589d8 3731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
Kojto 90:cb3d968589d8 3732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
Kojto 90:cb3d968589d8 3733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
Kojto 90:cb3d968589d8 3734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
Kojto 90:cb3d968589d8 3735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
Kojto 90:cb3d968589d8 3736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
Kojto 90:cb3d968589d8 3737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
Kojto 90:cb3d968589d8 3738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
Kojto 90:cb3d968589d8 3739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
Kojto 90:cb3d968589d8 3740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
Kojto 90:cb3d968589d8 3741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
Kojto 90:cb3d968589d8 3742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
Kojto 90:cb3d968589d8 3743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
Kojto 90:cb3d968589d8 3744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
Kojto 90:cb3d968589d8 3745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
Kojto 90:cb3d968589d8 3746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
Kojto 90:cb3d968589d8 3747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
Kojto 90:cb3d968589d8 3748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
Kojto 90:cb3d968589d8 3749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
Kojto 90:cb3d968589d8 3750 #define DAC1_SR DAC_SR_REG(DAC1)
Kojto 90:cb3d968589d8 3751 #define DAC1_C0 DAC_C0_REG(DAC1)
Kojto 90:cb3d968589d8 3752 #define DAC1_C1 DAC_C1_REG(DAC1)
Kojto 90:cb3d968589d8 3753 #define DAC1_C2 DAC_C2_REG(DAC1)
Kojto 90:cb3d968589d8 3754
Kojto 90:cb3d968589d8 3755 /* DAC - Register array accessors */
Kojto 90:cb3d968589d8 3756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
Kojto 90:cb3d968589d8 3757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
Kojto 90:cb3d968589d8 3758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
Kojto 90:cb3d968589d8 3759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
Kojto 90:cb3d968589d8 3760
Kojto 90:cb3d968589d8 3761 /*!
Kojto 90:cb3d968589d8 3762 * @}
Kojto 90:cb3d968589d8 3763 */ /* end of group DAC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3764
Kojto 90:cb3d968589d8 3765
Kojto 90:cb3d968589d8 3766 /*!
Kojto 90:cb3d968589d8 3767 * @}
Kojto 90:cb3d968589d8 3768 */ /* end of group DAC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 3769
Kojto 90:cb3d968589d8 3770
Kojto 90:cb3d968589d8 3771 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3772 -- DMA Peripheral Access Layer
Kojto 90:cb3d968589d8 3773 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3774
Kojto 90:cb3d968589d8 3775 /*!
Kojto 90:cb3d968589d8 3776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Kojto 90:cb3d968589d8 3777 * @{
Kojto 90:cb3d968589d8 3778 */
Kojto 90:cb3d968589d8 3779
Kojto 90:cb3d968589d8 3780 /** DMA - Register Layout Typedef */
Kojto 90:cb3d968589d8 3781 typedef struct {
Kojto 90:cb3d968589d8 3782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 3783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
Kojto 90:cb3d968589d8 3784 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 3785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
Kojto 90:cb3d968589d8 3786 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 3787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
Kojto 90:cb3d968589d8 3788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
Kojto 90:cb3d968589d8 3789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
Kojto 90:cb3d968589d8 3790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
Kojto 90:cb3d968589d8 3791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
Kojto 90:cb3d968589d8 3792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
Kojto 90:cb3d968589d8 3793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
Kojto 90:cb3d968589d8 3794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
Kojto 90:cb3d968589d8 3795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
Kojto 90:cb3d968589d8 3796 uint8_t RESERVED_2[4];
Kojto 90:cb3d968589d8 3797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
Kojto 90:cb3d968589d8 3798 uint8_t RESERVED_3[4];
Kojto 90:cb3d968589d8 3799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
Kojto 90:cb3d968589d8 3800 uint8_t RESERVED_4[4];
Kojto 90:cb3d968589d8 3801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
Kojto 90:cb3d968589d8 3802 uint8_t RESERVED_5[200];
Kojto 90:cb3d968589d8 3803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
Kojto 90:cb3d968589d8 3804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
Kojto 90:cb3d968589d8 3805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
Kojto 90:cb3d968589d8 3806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
Kojto 90:cb3d968589d8 3807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
Kojto 90:cb3d968589d8 3808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
Kojto 90:cb3d968589d8 3809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
Kojto 90:cb3d968589d8 3810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
Kojto 90:cb3d968589d8 3811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
Kojto 90:cb3d968589d8 3812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
Kojto 90:cb3d968589d8 3813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
Kojto 90:cb3d968589d8 3814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
Kojto 90:cb3d968589d8 3815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
Kojto 90:cb3d968589d8 3816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
Kojto 90:cb3d968589d8 3817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
Kojto 90:cb3d968589d8 3818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
Kojto 90:cb3d968589d8 3819 uint8_t RESERVED_6[3824];
Kojto 90:cb3d968589d8 3820 struct { /* offset: 0x1000, array step: 0x20 */
Kojto 90:cb3d968589d8 3821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
Kojto 90:cb3d968589d8 3822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
Kojto 90:cb3d968589d8 3823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
Kojto 90:cb3d968589d8 3824 union { /* offset: 0x1008, array step: 0x20 */
Kojto 90:cb3d968589d8 3825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
Kojto 90:cb3d968589d8 3826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
Kojto 90:cb3d968589d8 3827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
Kojto 90:cb3d968589d8 3828 };
Kojto 90:cb3d968589d8 3829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
Kojto 90:cb3d968589d8 3830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
Kojto 90:cb3d968589d8 3831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
Kojto 90:cb3d968589d8 3832 union { /* offset: 0x1016, array step: 0x20 */
Kojto 90:cb3d968589d8 3833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
Kojto 90:cb3d968589d8 3834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
Kojto 90:cb3d968589d8 3835 };
Kojto 90:cb3d968589d8 3836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
Kojto 90:cb3d968589d8 3837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
Kojto 90:cb3d968589d8 3838 union { /* offset: 0x101E, array step: 0x20 */
Kojto 90:cb3d968589d8 3839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
Kojto 90:cb3d968589d8 3840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
Kojto 90:cb3d968589d8 3841 };
Kojto 90:cb3d968589d8 3842 } TCD[16];
Kojto 90:cb3d968589d8 3843 } DMA_Type, *DMA_MemMapPtr;
Kojto 90:cb3d968589d8 3844
Kojto 90:cb3d968589d8 3845 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3846 -- DMA - Register accessor macros
Kojto 90:cb3d968589d8 3847 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3848
Kojto 90:cb3d968589d8 3849 /*!
Kojto 90:cb3d968589d8 3850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Kojto 90:cb3d968589d8 3851 * @{
Kojto 90:cb3d968589d8 3852 */
Kojto 90:cb3d968589d8 3853
Kojto 90:cb3d968589d8 3854
Kojto 90:cb3d968589d8 3855 /* DMA - Register accessors */
Kojto 90:cb3d968589d8 3856 #define DMA_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 3857 #define DMA_ES_REG(base) ((base)->ES)
Kojto 90:cb3d968589d8 3858 #define DMA_ERQ_REG(base) ((base)->ERQ)
Kojto 90:cb3d968589d8 3859 #define DMA_EEI_REG(base) ((base)->EEI)
Kojto 90:cb3d968589d8 3860 #define DMA_CEEI_REG(base) ((base)->CEEI)
Kojto 90:cb3d968589d8 3861 #define DMA_SEEI_REG(base) ((base)->SEEI)
Kojto 90:cb3d968589d8 3862 #define DMA_CERQ_REG(base) ((base)->CERQ)
Kojto 90:cb3d968589d8 3863 #define DMA_SERQ_REG(base) ((base)->SERQ)
Kojto 90:cb3d968589d8 3864 #define DMA_CDNE_REG(base) ((base)->CDNE)
Kojto 90:cb3d968589d8 3865 #define DMA_SSRT_REG(base) ((base)->SSRT)
Kojto 90:cb3d968589d8 3866 #define DMA_CERR_REG(base) ((base)->CERR)
Kojto 90:cb3d968589d8 3867 #define DMA_CINT_REG(base) ((base)->CINT)
Kojto 90:cb3d968589d8 3868 #define DMA_INT_REG(base) ((base)->INT)
Kojto 90:cb3d968589d8 3869 #define DMA_ERR_REG(base) ((base)->ERR)
Kojto 90:cb3d968589d8 3870 #define DMA_HRS_REG(base) ((base)->HRS)
Kojto 90:cb3d968589d8 3871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
Kojto 90:cb3d968589d8 3872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
Kojto 90:cb3d968589d8 3873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
Kojto 90:cb3d968589d8 3874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
Kojto 90:cb3d968589d8 3875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
Kojto 90:cb3d968589d8 3876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
Kojto 90:cb3d968589d8 3877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
Kojto 90:cb3d968589d8 3878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
Kojto 90:cb3d968589d8 3879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
Kojto 90:cb3d968589d8 3880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
Kojto 90:cb3d968589d8 3881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
Kojto 90:cb3d968589d8 3882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
Kojto 90:cb3d968589d8 3883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
Kojto 90:cb3d968589d8 3884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
Kojto 90:cb3d968589d8 3885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
Kojto 90:cb3d968589d8 3886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
Kojto 90:cb3d968589d8 3887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
Kojto 90:cb3d968589d8 3888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
Kojto 90:cb3d968589d8 3889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
Kojto 90:cb3d968589d8 3890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
Kojto 90:cb3d968589d8 3891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
Kojto 90:cb3d968589d8 3892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
Kojto 90:cb3d968589d8 3893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
Kojto 90:cb3d968589d8 3894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
Kojto 90:cb3d968589d8 3895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
Kojto 90:cb3d968589d8 3896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
Kojto 90:cb3d968589d8 3897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
Kojto 90:cb3d968589d8 3898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
Kojto 90:cb3d968589d8 3899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
Kojto 90:cb3d968589d8 3900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
Kojto 90:cb3d968589d8 3901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
Kojto 90:cb3d968589d8 3902
Kojto 90:cb3d968589d8 3903 /*!
Kojto 90:cb3d968589d8 3904 * @}
Kojto 90:cb3d968589d8 3905 */ /* end of group DMA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3906
Kojto 90:cb3d968589d8 3907
Kojto 90:cb3d968589d8 3908 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3909 -- DMA Register Masks
Kojto 90:cb3d968589d8 3910 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3911
Kojto 90:cb3d968589d8 3912 /*!
Kojto 90:cb3d968589d8 3913 * @addtogroup DMA_Register_Masks DMA Register Masks
Kojto 90:cb3d968589d8 3914 * @{
Kojto 90:cb3d968589d8 3915 */
Kojto 90:cb3d968589d8 3916
Kojto 90:cb3d968589d8 3917 /* CR Bit Fields */
Kojto 90:cb3d968589d8 3918 #define DMA_CR_EDBG_MASK 0x2u
Kojto 90:cb3d968589d8 3919 #define DMA_CR_EDBG_SHIFT 1
Kojto 90:cb3d968589d8 3920 #define DMA_CR_ERCA_MASK 0x4u
Kojto 90:cb3d968589d8 3921 #define DMA_CR_ERCA_SHIFT 2
Kojto 90:cb3d968589d8 3922 #define DMA_CR_HOE_MASK 0x10u
Kojto 90:cb3d968589d8 3923 #define DMA_CR_HOE_SHIFT 4
Kojto 90:cb3d968589d8 3924 #define DMA_CR_HALT_MASK 0x20u
Kojto 90:cb3d968589d8 3925 #define DMA_CR_HALT_SHIFT 5
Kojto 90:cb3d968589d8 3926 #define DMA_CR_CLM_MASK 0x40u
Kojto 90:cb3d968589d8 3927 #define DMA_CR_CLM_SHIFT 6
Kojto 90:cb3d968589d8 3928 #define DMA_CR_EMLM_MASK 0x80u
Kojto 90:cb3d968589d8 3929 #define DMA_CR_EMLM_SHIFT 7
Kojto 90:cb3d968589d8 3930 #define DMA_CR_ECX_MASK 0x10000u
Kojto 90:cb3d968589d8 3931 #define DMA_CR_ECX_SHIFT 16
Kojto 90:cb3d968589d8 3932 #define DMA_CR_CX_MASK 0x20000u
Kojto 90:cb3d968589d8 3933 #define DMA_CR_CX_SHIFT 17
Kojto 90:cb3d968589d8 3934 /* ES Bit Fields */
Kojto 90:cb3d968589d8 3935 #define DMA_ES_DBE_MASK 0x1u
Kojto 90:cb3d968589d8 3936 #define DMA_ES_DBE_SHIFT 0
Kojto 90:cb3d968589d8 3937 #define DMA_ES_SBE_MASK 0x2u
Kojto 90:cb3d968589d8 3938 #define DMA_ES_SBE_SHIFT 1
Kojto 90:cb3d968589d8 3939 #define DMA_ES_SGE_MASK 0x4u
Kojto 90:cb3d968589d8 3940 #define DMA_ES_SGE_SHIFT 2
Kojto 90:cb3d968589d8 3941 #define DMA_ES_NCE_MASK 0x8u
Kojto 90:cb3d968589d8 3942 #define DMA_ES_NCE_SHIFT 3
Kojto 90:cb3d968589d8 3943 #define DMA_ES_DOE_MASK 0x10u
Kojto 90:cb3d968589d8 3944 #define DMA_ES_DOE_SHIFT 4
Kojto 90:cb3d968589d8 3945 #define DMA_ES_DAE_MASK 0x20u
Kojto 90:cb3d968589d8 3946 #define DMA_ES_DAE_SHIFT 5
Kojto 90:cb3d968589d8 3947 #define DMA_ES_SOE_MASK 0x40u
Kojto 90:cb3d968589d8 3948 #define DMA_ES_SOE_SHIFT 6
Kojto 90:cb3d968589d8 3949 #define DMA_ES_SAE_MASK 0x80u
Kojto 90:cb3d968589d8 3950 #define DMA_ES_SAE_SHIFT 7
Kojto 90:cb3d968589d8 3951 #define DMA_ES_ERRCHN_MASK 0xF00u
Kojto 90:cb3d968589d8 3952 #define DMA_ES_ERRCHN_SHIFT 8
Kojto 90:cb3d968589d8 3953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
Kojto 90:cb3d968589d8 3954 #define DMA_ES_CPE_MASK 0x4000u
Kojto 90:cb3d968589d8 3955 #define DMA_ES_CPE_SHIFT 14
Kojto 90:cb3d968589d8 3956 #define DMA_ES_ECX_MASK 0x10000u
Kojto 90:cb3d968589d8 3957 #define DMA_ES_ECX_SHIFT 16
Kojto 90:cb3d968589d8 3958 #define DMA_ES_VLD_MASK 0x80000000u
Kojto 90:cb3d968589d8 3959 #define DMA_ES_VLD_SHIFT 31
Kojto 90:cb3d968589d8 3960 /* ERQ Bit Fields */
Kojto 90:cb3d968589d8 3961 #define DMA_ERQ_ERQ0_MASK 0x1u
Kojto 90:cb3d968589d8 3962 #define DMA_ERQ_ERQ0_SHIFT 0
Kojto 90:cb3d968589d8 3963 #define DMA_ERQ_ERQ1_MASK 0x2u
Kojto 90:cb3d968589d8 3964 #define DMA_ERQ_ERQ1_SHIFT 1
Kojto 90:cb3d968589d8 3965 #define DMA_ERQ_ERQ2_MASK 0x4u
Kojto 90:cb3d968589d8 3966 #define DMA_ERQ_ERQ2_SHIFT 2
Kojto 90:cb3d968589d8 3967 #define DMA_ERQ_ERQ3_MASK 0x8u
Kojto 90:cb3d968589d8 3968 #define DMA_ERQ_ERQ3_SHIFT 3
Kojto 90:cb3d968589d8 3969 #define DMA_ERQ_ERQ4_MASK 0x10u
Kojto 90:cb3d968589d8 3970 #define DMA_ERQ_ERQ4_SHIFT 4
Kojto 90:cb3d968589d8 3971 #define DMA_ERQ_ERQ5_MASK 0x20u
Kojto 90:cb3d968589d8 3972 #define DMA_ERQ_ERQ5_SHIFT 5
Kojto 90:cb3d968589d8 3973 #define DMA_ERQ_ERQ6_MASK 0x40u
Kojto 90:cb3d968589d8 3974 #define DMA_ERQ_ERQ6_SHIFT 6
Kojto 90:cb3d968589d8 3975 #define DMA_ERQ_ERQ7_MASK 0x80u
Kojto 90:cb3d968589d8 3976 #define DMA_ERQ_ERQ7_SHIFT 7
Kojto 90:cb3d968589d8 3977 #define DMA_ERQ_ERQ8_MASK 0x100u
Kojto 90:cb3d968589d8 3978 #define DMA_ERQ_ERQ8_SHIFT 8
Kojto 90:cb3d968589d8 3979 #define DMA_ERQ_ERQ9_MASK 0x200u
Kojto 90:cb3d968589d8 3980 #define DMA_ERQ_ERQ9_SHIFT 9
Kojto 90:cb3d968589d8 3981 #define DMA_ERQ_ERQ10_MASK 0x400u
Kojto 90:cb3d968589d8 3982 #define DMA_ERQ_ERQ10_SHIFT 10
Kojto 90:cb3d968589d8 3983 #define DMA_ERQ_ERQ11_MASK 0x800u
Kojto 90:cb3d968589d8 3984 #define DMA_ERQ_ERQ11_SHIFT 11
Kojto 90:cb3d968589d8 3985 #define DMA_ERQ_ERQ12_MASK 0x1000u
Kojto 90:cb3d968589d8 3986 #define DMA_ERQ_ERQ12_SHIFT 12
Kojto 90:cb3d968589d8 3987 #define DMA_ERQ_ERQ13_MASK 0x2000u
Kojto 90:cb3d968589d8 3988 #define DMA_ERQ_ERQ13_SHIFT 13
Kojto 90:cb3d968589d8 3989 #define DMA_ERQ_ERQ14_MASK 0x4000u
Kojto 90:cb3d968589d8 3990 #define DMA_ERQ_ERQ14_SHIFT 14
Kojto 90:cb3d968589d8 3991 #define DMA_ERQ_ERQ15_MASK 0x8000u
Kojto 90:cb3d968589d8 3992 #define DMA_ERQ_ERQ15_SHIFT 15
Kojto 90:cb3d968589d8 3993 /* EEI Bit Fields */
Kojto 90:cb3d968589d8 3994 #define DMA_EEI_EEI0_MASK 0x1u
Kojto 90:cb3d968589d8 3995 #define DMA_EEI_EEI0_SHIFT 0
Kojto 90:cb3d968589d8 3996 #define DMA_EEI_EEI1_MASK 0x2u
Kojto 90:cb3d968589d8 3997 #define DMA_EEI_EEI1_SHIFT 1
Kojto 90:cb3d968589d8 3998 #define DMA_EEI_EEI2_MASK 0x4u
Kojto 90:cb3d968589d8 3999 #define DMA_EEI_EEI2_SHIFT 2
Kojto 90:cb3d968589d8 4000 #define DMA_EEI_EEI3_MASK 0x8u
Kojto 90:cb3d968589d8 4001 #define DMA_EEI_EEI3_SHIFT 3
Kojto 90:cb3d968589d8 4002 #define DMA_EEI_EEI4_MASK 0x10u
Kojto 90:cb3d968589d8 4003 #define DMA_EEI_EEI4_SHIFT 4
Kojto 90:cb3d968589d8 4004 #define DMA_EEI_EEI5_MASK 0x20u
Kojto 90:cb3d968589d8 4005 #define DMA_EEI_EEI5_SHIFT 5
Kojto 90:cb3d968589d8 4006 #define DMA_EEI_EEI6_MASK 0x40u
Kojto 90:cb3d968589d8 4007 #define DMA_EEI_EEI6_SHIFT 6
Kojto 90:cb3d968589d8 4008 #define DMA_EEI_EEI7_MASK 0x80u
Kojto 90:cb3d968589d8 4009 #define DMA_EEI_EEI7_SHIFT 7
Kojto 90:cb3d968589d8 4010 #define DMA_EEI_EEI8_MASK 0x100u
Kojto 90:cb3d968589d8 4011 #define DMA_EEI_EEI8_SHIFT 8
Kojto 90:cb3d968589d8 4012 #define DMA_EEI_EEI9_MASK 0x200u
Kojto 90:cb3d968589d8 4013 #define DMA_EEI_EEI9_SHIFT 9
Kojto 90:cb3d968589d8 4014 #define DMA_EEI_EEI10_MASK 0x400u
Kojto 90:cb3d968589d8 4015 #define DMA_EEI_EEI10_SHIFT 10
Kojto 90:cb3d968589d8 4016 #define DMA_EEI_EEI11_MASK 0x800u
Kojto 90:cb3d968589d8 4017 #define DMA_EEI_EEI11_SHIFT 11
Kojto 90:cb3d968589d8 4018 #define DMA_EEI_EEI12_MASK 0x1000u
Kojto 90:cb3d968589d8 4019 #define DMA_EEI_EEI12_SHIFT 12
Kojto 90:cb3d968589d8 4020 #define DMA_EEI_EEI13_MASK 0x2000u
Kojto 90:cb3d968589d8 4021 #define DMA_EEI_EEI13_SHIFT 13
Kojto 90:cb3d968589d8 4022 #define DMA_EEI_EEI14_MASK 0x4000u
Kojto 90:cb3d968589d8 4023 #define DMA_EEI_EEI14_SHIFT 14
Kojto 90:cb3d968589d8 4024 #define DMA_EEI_EEI15_MASK 0x8000u
Kojto 90:cb3d968589d8 4025 #define DMA_EEI_EEI15_SHIFT 15
Kojto 90:cb3d968589d8 4026 /* CEEI Bit Fields */
Kojto 90:cb3d968589d8 4027 #define DMA_CEEI_CEEI_MASK 0xFu
Kojto 90:cb3d968589d8 4028 #define DMA_CEEI_CEEI_SHIFT 0
Kojto 90:cb3d968589d8 4029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
Kojto 90:cb3d968589d8 4030 #define DMA_CEEI_CAEE_MASK 0x40u
Kojto 90:cb3d968589d8 4031 #define DMA_CEEI_CAEE_SHIFT 6
Kojto 90:cb3d968589d8 4032 #define DMA_CEEI_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4033 #define DMA_CEEI_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4034 /* SEEI Bit Fields */
Kojto 90:cb3d968589d8 4035 #define DMA_SEEI_SEEI_MASK 0xFu
Kojto 90:cb3d968589d8 4036 #define DMA_SEEI_SEEI_SHIFT 0
Kojto 90:cb3d968589d8 4037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
Kojto 90:cb3d968589d8 4038 #define DMA_SEEI_SAEE_MASK 0x40u
Kojto 90:cb3d968589d8 4039 #define DMA_SEEI_SAEE_SHIFT 6
Kojto 90:cb3d968589d8 4040 #define DMA_SEEI_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4041 #define DMA_SEEI_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4042 /* CERQ Bit Fields */
Kojto 90:cb3d968589d8 4043 #define DMA_CERQ_CERQ_MASK 0xFu
Kojto 90:cb3d968589d8 4044 #define DMA_CERQ_CERQ_SHIFT 0
Kojto 90:cb3d968589d8 4045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
Kojto 90:cb3d968589d8 4046 #define DMA_CERQ_CAER_MASK 0x40u
Kojto 90:cb3d968589d8 4047 #define DMA_CERQ_CAER_SHIFT 6
Kojto 90:cb3d968589d8 4048 #define DMA_CERQ_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4049 #define DMA_CERQ_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4050 /* SERQ Bit Fields */
Kojto 90:cb3d968589d8 4051 #define DMA_SERQ_SERQ_MASK 0xFu
Kojto 90:cb3d968589d8 4052 #define DMA_SERQ_SERQ_SHIFT 0
Kojto 90:cb3d968589d8 4053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
Kojto 90:cb3d968589d8 4054 #define DMA_SERQ_SAER_MASK 0x40u
Kojto 90:cb3d968589d8 4055 #define DMA_SERQ_SAER_SHIFT 6
Kojto 90:cb3d968589d8 4056 #define DMA_SERQ_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4057 #define DMA_SERQ_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4058 /* CDNE Bit Fields */
Kojto 90:cb3d968589d8 4059 #define DMA_CDNE_CDNE_MASK 0xFu
Kojto 90:cb3d968589d8 4060 #define DMA_CDNE_CDNE_SHIFT 0
Kojto 90:cb3d968589d8 4061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
Kojto 90:cb3d968589d8 4062 #define DMA_CDNE_CADN_MASK 0x40u
Kojto 90:cb3d968589d8 4063 #define DMA_CDNE_CADN_SHIFT 6
Kojto 90:cb3d968589d8 4064 #define DMA_CDNE_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4065 #define DMA_CDNE_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4066 /* SSRT Bit Fields */
Kojto 90:cb3d968589d8 4067 #define DMA_SSRT_SSRT_MASK 0xFu
Kojto 90:cb3d968589d8 4068 #define DMA_SSRT_SSRT_SHIFT 0
Kojto 90:cb3d968589d8 4069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
Kojto 90:cb3d968589d8 4070 #define DMA_SSRT_SAST_MASK 0x40u
Kojto 90:cb3d968589d8 4071 #define DMA_SSRT_SAST_SHIFT 6
Kojto 90:cb3d968589d8 4072 #define DMA_SSRT_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4073 #define DMA_SSRT_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4074 /* CERR Bit Fields */
Kojto 90:cb3d968589d8 4075 #define DMA_CERR_CERR_MASK 0xFu
Kojto 90:cb3d968589d8 4076 #define DMA_CERR_CERR_SHIFT 0
Kojto 90:cb3d968589d8 4077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
Kojto 90:cb3d968589d8 4078 #define DMA_CERR_CAEI_MASK 0x40u
Kojto 90:cb3d968589d8 4079 #define DMA_CERR_CAEI_SHIFT 6
Kojto 90:cb3d968589d8 4080 #define DMA_CERR_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4081 #define DMA_CERR_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4082 /* CINT Bit Fields */
Kojto 90:cb3d968589d8 4083 #define DMA_CINT_CINT_MASK 0xFu
Kojto 90:cb3d968589d8 4084 #define DMA_CINT_CINT_SHIFT 0
Kojto 90:cb3d968589d8 4085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
Kojto 90:cb3d968589d8 4086 #define DMA_CINT_CAIR_MASK 0x40u
Kojto 90:cb3d968589d8 4087 #define DMA_CINT_CAIR_SHIFT 6
Kojto 90:cb3d968589d8 4088 #define DMA_CINT_NOP_MASK 0x80u
Kojto 90:cb3d968589d8 4089 #define DMA_CINT_NOP_SHIFT 7
Kojto 90:cb3d968589d8 4090 /* INT Bit Fields */
Kojto 90:cb3d968589d8 4091 #define DMA_INT_INT0_MASK 0x1u
Kojto 90:cb3d968589d8 4092 #define DMA_INT_INT0_SHIFT 0
Kojto 90:cb3d968589d8 4093 #define DMA_INT_INT1_MASK 0x2u
Kojto 90:cb3d968589d8 4094 #define DMA_INT_INT1_SHIFT 1
Kojto 90:cb3d968589d8 4095 #define DMA_INT_INT2_MASK 0x4u
Kojto 90:cb3d968589d8 4096 #define DMA_INT_INT2_SHIFT 2
Kojto 90:cb3d968589d8 4097 #define DMA_INT_INT3_MASK 0x8u
Kojto 90:cb3d968589d8 4098 #define DMA_INT_INT3_SHIFT 3
Kojto 90:cb3d968589d8 4099 #define DMA_INT_INT4_MASK 0x10u
Kojto 90:cb3d968589d8 4100 #define DMA_INT_INT4_SHIFT 4
Kojto 90:cb3d968589d8 4101 #define DMA_INT_INT5_MASK 0x20u
Kojto 90:cb3d968589d8 4102 #define DMA_INT_INT5_SHIFT 5
Kojto 90:cb3d968589d8 4103 #define DMA_INT_INT6_MASK 0x40u
Kojto 90:cb3d968589d8 4104 #define DMA_INT_INT6_SHIFT 6
Kojto 90:cb3d968589d8 4105 #define DMA_INT_INT7_MASK 0x80u
Kojto 90:cb3d968589d8 4106 #define DMA_INT_INT7_SHIFT 7
Kojto 90:cb3d968589d8 4107 #define DMA_INT_INT8_MASK 0x100u
Kojto 90:cb3d968589d8 4108 #define DMA_INT_INT8_SHIFT 8
Kojto 90:cb3d968589d8 4109 #define DMA_INT_INT9_MASK 0x200u
Kojto 90:cb3d968589d8 4110 #define DMA_INT_INT9_SHIFT 9
Kojto 90:cb3d968589d8 4111 #define DMA_INT_INT10_MASK 0x400u
Kojto 90:cb3d968589d8 4112 #define DMA_INT_INT10_SHIFT 10
Kojto 90:cb3d968589d8 4113 #define DMA_INT_INT11_MASK 0x800u
Kojto 90:cb3d968589d8 4114 #define DMA_INT_INT11_SHIFT 11
Kojto 90:cb3d968589d8 4115 #define DMA_INT_INT12_MASK 0x1000u
Kojto 90:cb3d968589d8 4116 #define DMA_INT_INT12_SHIFT 12
Kojto 90:cb3d968589d8 4117 #define DMA_INT_INT13_MASK 0x2000u
Kojto 90:cb3d968589d8 4118 #define DMA_INT_INT13_SHIFT 13
Kojto 90:cb3d968589d8 4119 #define DMA_INT_INT14_MASK 0x4000u
Kojto 90:cb3d968589d8 4120 #define DMA_INT_INT14_SHIFT 14
Kojto 90:cb3d968589d8 4121 #define DMA_INT_INT15_MASK 0x8000u
Kojto 90:cb3d968589d8 4122 #define DMA_INT_INT15_SHIFT 15
Kojto 90:cb3d968589d8 4123 /* ERR Bit Fields */
Kojto 90:cb3d968589d8 4124 #define DMA_ERR_ERR0_MASK 0x1u
Kojto 90:cb3d968589d8 4125 #define DMA_ERR_ERR0_SHIFT 0
Kojto 90:cb3d968589d8 4126 #define DMA_ERR_ERR1_MASK 0x2u
Kojto 90:cb3d968589d8 4127 #define DMA_ERR_ERR1_SHIFT 1
Kojto 90:cb3d968589d8 4128 #define DMA_ERR_ERR2_MASK 0x4u
Kojto 90:cb3d968589d8 4129 #define DMA_ERR_ERR2_SHIFT 2
Kojto 90:cb3d968589d8 4130 #define DMA_ERR_ERR3_MASK 0x8u
Kojto 90:cb3d968589d8 4131 #define DMA_ERR_ERR3_SHIFT 3
Kojto 90:cb3d968589d8 4132 #define DMA_ERR_ERR4_MASK 0x10u
Kojto 90:cb3d968589d8 4133 #define DMA_ERR_ERR4_SHIFT 4
Kojto 90:cb3d968589d8 4134 #define DMA_ERR_ERR5_MASK 0x20u
Kojto 90:cb3d968589d8 4135 #define DMA_ERR_ERR5_SHIFT 5
Kojto 90:cb3d968589d8 4136 #define DMA_ERR_ERR6_MASK 0x40u
Kojto 90:cb3d968589d8 4137 #define DMA_ERR_ERR6_SHIFT 6
Kojto 90:cb3d968589d8 4138 #define DMA_ERR_ERR7_MASK 0x80u
Kojto 90:cb3d968589d8 4139 #define DMA_ERR_ERR7_SHIFT 7
Kojto 90:cb3d968589d8 4140 #define DMA_ERR_ERR8_MASK 0x100u
Kojto 90:cb3d968589d8 4141 #define DMA_ERR_ERR8_SHIFT 8
Kojto 90:cb3d968589d8 4142 #define DMA_ERR_ERR9_MASK 0x200u
Kojto 90:cb3d968589d8 4143 #define DMA_ERR_ERR9_SHIFT 9
Kojto 90:cb3d968589d8 4144 #define DMA_ERR_ERR10_MASK 0x400u
Kojto 90:cb3d968589d8 4145 #define DMA_ERR_ERR10_SHIFT 10
Kojto 90:cb3d968589d8 4146 #define DMA_ERR_ERR11_MASK 0x800u
Kojto 90:cb3d968589d8 4147 #define DMA_ERR_ERR11_SHIFT 11
Kojto 90:cb3d968589d8 4148 #define DMA_ERR_ERR12_MASK 0x1000u
Kojto 90:cb3d968589d8 4149 #define DMA_ERR_ERR12_SHIFT 12
Kojto 90:cb3d968589d8 4150 #define DMA_ERR_ERR13_MASK 0x2000u
Kojto 90:cb3d968589d8 4151 #define DMA_ERR_ERR13_SHIFT 13
Kojto 90:cb3d968589d8 4152 #define DMA_ERR_ERR14_MASK 0x4000u
Kojto 90:cb3d968589d8 4153 #define DMA_ERR_ERR14_SHIFT 14
Kojto 90:cb3d968589d8 4154 #define DMA_ERR_ERR15_MASK 0x8000u
Kojto 90:cb3d968589d8 4155 #define DMA_ERR_ERR15_SHIFT 15
Kojto 90:cb3d968589d8 4156 /* HRS Bit Fields */
Kojto 90:cb3d968589d8 4157 #define DMA_HRS_HRS0_MASK 0x1u
Kojto 90:cb3d968589d8 4158 #define DMA_HRS_HRS0_SHIFT 0
Kojto 90:cb3d968589d8 4159 #define DMA_HRS_HRS1_MASK 0x2u
Kojto 90:cb3d968589d8 4160 #define DMA_HRS_HRS1_SHIFT 1
Kojto 90:cb3d968589d8 4161 #define DMA_HRS_HRS2_MASK 0x4u
Kojto 90:cb3d968589d8 4162 #define DMA_HRS_HRS2_SHIFT 2
Kojto 90:cb3d968589d8 4163 #define DMA_HRS_HRS3_MASK 0x8u
Kojto 90:cb3d968589d8 4164 #define DMA_HRS_HRS3_SHIFT 3
Kojto 90:cb3d968589d8 4165 #define DMA_HRS_HRS4_MASK 0x10u
Kojto 90:cb3d968589d8 4166 #define DMA_HRS_HRS4_SHIFT 4
Kojto 90:cb3d968589d8 4167 #define DMA_HRS_HRS5_MASK 0x20u
Kojto 90:cb3d968589d8 4168 #define DMA_HRS_HRS5_SHIFT 5
Kojto 90:cb3d968589d8 4169 #define DMA_HRS_HRS6_MASK 0x40u
Kojto 90:cb3d968589d8 4170 #define DMA_HRS_HRS6_SHIFT 6
Kojto 90:cb3d968589d8 4171 #define DMA_HRS_HRS7_MASK 0x80u
Kojto 90:cb3d968589d8 4172 #define DMA_HRS_HRS7_SHIFT 7
Kojto 90:cb3d968589d8 4173 #define DMA_HRS_HRS8_MASK 0x100u
Kojto 90:cb3d968589d8 4174 #define DMA_HRS_HRS8_SHIFT 8
Kojto 90:cb3d968589d8 4175 #define DMA_HRS_HRS9_MASK 0x200u
Kojto 90:cb3d968589d8 4176 #define DMA_HRS_HRS9_SHIFT 9
Kojto 90:cb3d968589d8 4177 #define DMA_HRS_HRS10_MASK 0x400u
Kojto 90:cb3d968589d8 4178 #define DMA_HRS_HRS10_SHIFT 10
Kojto 90:cb3d968589d8 4179 #define DMA_HRS_HRS11_MASK 0x800u
Kojto 90:cb3d968589d8 4180 #define DMA_HRS_HRS11_SHIFT 11
Kojto 90:cb3d968589d8 4181 #define DMA_HRS_HRS12_MASK 0x1000u
Kojto 90:cb3d968589d8 4182 #define DMA_HRS_HRS12_SHIFT 12
Kojto 90:cb3d968589d8 4183 #define DMA_HRS_HRS13_MASK 0x2000u
Kojto 90:cb3d968589d8 4184 #define DMA_HRS_HRS13_SHIFT 13
Kojto 90:cb3d968589d8 4185 #define DMA_HRS_HRS14_MASK 0x4000u
Kojto 90:cb3d968589d8 4186 #define DMA_HRS_HRS14_SHIFT 14
Kojto 90:cb3d968589d8 4187 #define DMA_HRS_HRS15_MASK 0x8000u
Kojto 90:cb3d968589d8 4188 #define DMA_HRS_HRS15_SHIFT 15
Kojto 90:cb3d968589d8 4189 /* DCHPRI3 Bit Fields */
Kojto 90:cb3d968589d8 4190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4191 #define DMA_DCHPRI3_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
Kojto 90:cb3d968589d8 4193 #define DMA_DCHPRI3_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4194 #define DMA_DCHPRI3_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4195 #define DMA_DCHPRI3_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4196 #define DMA_DCHPRI3_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4197 /* DCHPRI2 Bit Fields */
Kojto 90:cb3d968589d8 4198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4199 #define DMA_DCHPRI2_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
Kojto 90:cb3d968589d8 4201 #define DMA_DCHPRI2_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4202 #define DMA_DCHPRI2_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4203 #define DMA_DCHPRI2_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4204 #define DMA_DCHPRI2_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4205 /* DCHPRI1 Bit Fields */
Kojto 90:cb3d968589d8 4206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4207 #define DMA_DCHPRI1_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
Kojto 90:cb3d968589d8 4209 #define DMA_DCHPRI1_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4210 #define DMA_DCHPRI1_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4211 #define DMA_DCHPRI1_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4212 #define DMA_DCHPRI1_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4213 /* DCHPRI0 Bit Fields */
Kojto 90:cb3d968589d8 4214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4215 #define DMA_DCHPRI0_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
Kojto 90:cb3d968589d8 4217 #define DMA_DCHPRI0_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4218 #define DMA_DCHPRI0_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4219 #define DMA_DCHPRI0_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4220 #define DMA_DCHPRI0_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4221 /* DCHPRI7 Bit Fields */
Kojto 90:cb3d968589d8 4222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4223 #define DMA_DCHPRI7_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
Kojto 90:cb3d968589d8 4225 #define DMA_DCHPRI7_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4226 #define DMA_DCHPRI7_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4227 #define DMA_DCHPRI7_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4228 #define DMA_DCHPRI7_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4229 /* DCHPRI6 Bit Fields */
Kojto 90:cb3d968589d8 4230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4231 #define DMA_DCHPRI6_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
Kojto 90:cb3d968589d8 4233 #define DMA_DCHPRI6_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4234 #define DMA_DCHPRI6_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4235 #define DMA_DCHPRI6_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4236 #define DMA_DCHPRI6_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4237 /* DCHPRI5 Bit Fields */
Kojto 90:cb3d968589d8 4238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4239 #define DMA_DCHPRI5_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
Kojto 90:cb3d968589d8 4241 #define DMA_DCHPRI5_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4242 #define DMA_DCHPRI5_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4243 #define DMA_DCHPRI5_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4244 #define DMA_DCHPRI5_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4245 /* DCHPRI4 Bit Fields */
Kojto 90:cb3d968589d8 4246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4247 #define DMA_DCHPRI4_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
Kojto 90:cb3d968589d8 4249 #define DMA_DCHPRI4_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4250 #define DMA_DCHPRI4_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4251 #define DMA_DCHPRI4_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4252 #define DMA_DCHPRI4_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4253 /* DCHPRI11 Bit Fields */
Kojto 90:cb3d968589d8 4254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4255 #define DMA_DCHPRI11_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
Kojto 90:cb3d968589d8 4257 #define DMA_DCHPRI11_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4258 #define DMA_DCHPRI11_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4259 #define DMA_DCHPRI11_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4260 #define DMA_DCHPRI11_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4261 /* DCHPRI10 Bit Fields */
Kojto 90:cb3d968589d8 4262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4263 #define DMA_DCHPRI10_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
Kojto 90:cb3d968589d8 4265 #define DMA_DCHPRI10_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4266 #define DMA_DCHPRI10_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4267 #define DMA_DCHPRI10_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4268 #define DMA_DCHPRI10_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4269 /* DCHPRI9 Bit Fields */
Kojto 90:cb3d968589d8 4270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4271 #define DMA_DCHPRI9_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
Kojto 90:cb3d968589d8 4273 #define DMA_DCHPRI9_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4274 #define DMA_DCHPRI9_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4275 #define DMA_DCHPRI9_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4276 #define DMA_DCHPRI9_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4277 /* DCHPRI8 Bit Fields */
Kojto 90:cb3d968589d8 4278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4279 #define DMA_DCHPRI8_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
Kojto 90:cb3d968589d8 4281 #define DMA_DCHPRI8_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4282 #define DMA_DCHPRI8_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4283 #define DMA_DCHPRI8_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4284 #define DMA_DCHPRI8_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4285 /* DCHPRI15 Bit Fields */
Kojto 90:cb3d968589d8 4286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4287 #define DMA_DCHPRI15_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
Kojto 90:cb3d968589d8 4289 #define DMA_DCHPRI15_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4290 #define DMA_DCHPRI15_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4291 #define DMA_DCHPRI15_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4292 #define DMA_DCHPRI15_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4293 /* DCHPRI14 Bit Fields */
Kojto 90:cb3d968589d8 4294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4295 #define DMA_DCHPRI14_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
Kojto 90:cb3d968589d8 4297 #define DMA_DCHPRI14_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4298 #define DMA_DCHPRI14_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4299 #define DMA_DCHPRI14_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4300 #define DMA_DCHPRI14_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4301 /* DCHPRI13 Bit Fields */
Kojto 90:cb3d968589d8 4302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4303 #define DMA_DCHPRI13_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
Kojto 90:cb3d968589d8 4305 #define DMA_DCHPRI13_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4306 #define DMA_DCHPRI13_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4307 #define DMA_DCHPRI13_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4308 #define DMA_DCHPRI13_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4309 /* DCHPRI12 Bit Fields */
Kojto 90:cb3d968589d8 4310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
Kojto 90:cb3d968589d8 4311 #define DMA_DCHPRI12_CHPRI_SHIFT 0
Kojto 90:cb3d968589d8 4312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
Kojto 90:cb3d968589d8 4313 #define DMA_DCHPRI12_DPA_MASK 0x40u
Kojto 90:cb3d968589d8 4314 #define DMA_DCHPRI12_DPA_SHIFT 6
Kojto 90:cb3d968589d8 4315 #define DMA_DCHPRI12_ECP_MASK 0x80u
Kojto 90:cb3d968589d8 4316 #define DMA_DCHPRI12_ECP_SHIFT 7
Kojto 90:cb3d968589d8 4317 /* SADDR Bit Fields */
Kojto 90:cb3d968589d8 4318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 4319 #define DMA_SADDR_SADDR_SHIFT 0
Kojto 90:cb3d968589d8 4320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
Kojto 90:cb3d968589d8 4321 /* SOFF Bit Fields */
Kojto 90:cb3d968589d8 4322 #define DMA_SOFF_SOFF_MASK 0xFFFFu
Kojto 90:cb3d968589d8 4323 #define DMA_SOFF_SOFF_SHIFT 0
Kojto 90:cb3d968589d8 4324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
Kojto 90:cb3d968589d8 4325 /* ATTR Bit Fields */
Kojto 90:cb3d968589d8 4326 #define DMA_ATTR_DSIZE_MASK 0x7u
Kojto 90:cb3d968589d8 4327 #define DMA_ATTR_DSIZE_SHIFT 0
Kojto 90:cb3d968589d8 4328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
Kojto 90:cb3d968589d8 4329 #define DMA_ATTR_DMOD_MASK 0xF8u
Kojto 90:cb3d968589d8 4330 #define DMA_ATTR_DMOD_SHIFT 3
Kojto 90:cb3d968589d8 4331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
Kojto 90:cb3d968589d8 4332 #define DMA_ATTR_SSIZE_MASK 0x700u
Kojto 90:cb3d968589d8 4333 #define DMA_ATTR_SSIZE_SHIFT 8
Kojto 90:cb3d968589d8 4334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
Kojto 90:cb3d968589d8 4335 #define DMA_ATTR_SMOD_MASK 0xF800u
Kojto 90:cb3d968589d8 4336 #define DMA_ATTR_SMOD_SHIFT 11
Kojto 90:cb3d968589d8 4337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
Kojto 90:cb3d968589d8 4338 /* NBYTES_MLNO Bit Fields */
Kojto 90:cb3d968589d8 4339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 4340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
Kojto 90:cb3d968589d8 4341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
Kojto 90:cb3d968589d8 4342 /* NBYTES_MLOFFNO Bit Fields */
Kojto 90:cb3d968589d8 4343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
Kojto 90:cb3d968589d8 4344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
Kojto 90:cb3d968589d8 4345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
Kojto 90:cb3d968589d8 4346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
Kojto 90:cb3d968589d8 4347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
Kojto 90:cb3d968589d8 4348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
Kojto 90:cb3d968589d8 4349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
Kojto 90:cb3d968589d8 4350 /* NBYTES_MLOFFYES Bit Fields */
Kojto 90:cb3d968589d8 4351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
Kojto 90:cb3d968589d8 4352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
Kojto 90:cb3d968589d8 4353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
Kojto 90:cb3d968589d8 4354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
Kojto 90:cb3d968589d8 4355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
Kojto 90:cb3d968589d8 4356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
Kojto 90:cb3d968589d8 4357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
Kojto 90:cb3d968589d8 4358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
Kojto 90:cb3d968589d8 4359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
Kojto 90:cb3d968589d8 4360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
Kojto 90:cb3d968589d8 4361 /* SLAST Bit Fields */
Kojto 90:cb3d968589d8 4362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 4363 #define DMA_SLAST_SLAST_SHIFT 0
Kojto 90:cb3d968589d8 4364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
Kojto 90:cb3d968589d8 4365 /* DADDR Bit Fields */
Kojto 90:cb3d968589d8 4366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 4367 #define DMA_DADDR_DADDR_SHIFT 0
Kojto 90:cb3d968589d8 4368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
Kojto 90:cb3d968589d8 4369 /* DOFF Bit Fields */
Kojto 90:cb3d968589d8 4370 #define DMA_DOFF_DOFF_MASK 0xFFFFu
Kojto 90:cb3d968589d8 4371 #define DMA_DOFF_DOFF_SHIFT 0
Kojto 90:cb3d968589d8 4372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
Kojto 90:cb3d968589d8 4373 /* CITER_ELINKNO Bit Fields */
Kojto 90:cb3d968589d8 4374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
Kojto 90:cb3d968589d8 4375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
Kojto 90:cb3d968589d8 4376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
Kojto 90:cb3d968589d8 4377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
Kojto 90:cb3d968589d8 4378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
Kojto 90:cb3d968589d8 4379 /* CITER_ELINKYES Bit Fields */
Kojto 90:cb3d968589d8 4380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
Kojto 90:cb3d968589d8 4381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
Kojto 90:cb3d968589d8 4382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
Kojto 90:cb3d968589d8 4383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
Kojto 90:cb3d968589d8 4384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
Kojto 90:cb3d968589d8 4385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
Kojto 90:cb3d968589d8 4386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
Kojto 90:cb3d968589d8 4387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
Kojto 90:cb3d968589d8 4388 /* DLAST_SGA Bit Fields */
Kojto 90:cb3d968589d8 4389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 4390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
Kojto 90:cb3d968589d8 4391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
Kojto 90:cb3d968589d8 4392 /* CSR Bit Fields */
Kojto 90:cb3d968589d8 4393 #define DMA_CSR_START_MASK 0x1u
Kojto 90:cb3d968589d8 4394 #define DMA_CSR_START_SHIFT 0
Kojto 90:cb3d968589d8 4395 #define DMA_CSR_INTMAJOR_MASK 0x2u
Kojto 90:cb3d968589d8 4396 #define DMA_CSR_INTMAJOR_SHIFT 1
Kojto 90:cb3d968589d8 4397 #define DMA_CSR_INTHALF_MASK 0x4u
Kojto 90:cb3d968589d8 4398 #define DMA_CSR_INTHALF_SHIFT 2
Kojto 90:cb3d968589d8 4399 #define DMA_CSR_DREQ_MASK 0x8u
Kojto 90:cb3d968589d8 4400 #define DMA_CSR_DREQ_SHIFT 3
Kojto 90:cb3d968589d8 4401 #define DMA_CSR_ESG_MASK 0x10u
Kojto 90:cb3d968589d8 4402 #define DMA_CSR_ESG_SHIFT 4
Kojto 90:cb3d968589d8 4403 #define DMA_CSR_MAJORELINK_MASK 0x20u
Kojto 90:cb3d968589d8 4404 #define DMA_CSR_MAJORELINK_SHIFT 5
Kojto 90:cb3d968589d8 4405 #define DMA_CSR_ACTIVE_MASK 0x40u
Kojto 90:cb3d968589d8 4406 #define DMA_CSR_ACTIVE_SHIFT 6
Kojto 90:cb3d968589d8 4407 #define DMA_CSR_DONE_MASK 0x80u
Kojto 90:cb3d968589d8 4408 #define DMA_CSR_DONE_SHIFT 7
Kojto 90:cb3d968589d8 4409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
Kojto 90:cb3d968589d8 4410 #define DMA_CSR_MAJORLINKCH_SHIFT 8
Kojto 90:cb3d968589d8 4411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
Kojto 90:cb3d968589d8 4412 #define DMA_CSR_BWC_MASK 0xC000u
Kojto 90:cb3d968589d8 4413 #define DMA_CSR_BWC_SHIFT 14
Kojto 90:cb3d968589d8 4414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
Kojto 90:cb3d968589d8 4415 /* BITER_ELINKNO Bit Fields */
Kojto 90:cb3d968589d8 4416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
Kojto 90:cb3d968589d8 4417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
Kojto 90:cb3d968589d8 4418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
Kojto 90:cb3d968589d8 4419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
Kojto 90:cb3d968589d8 4420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
Kojto 90:cb3d968589d8 4421 /* BITER_ELINKYES Bit Fields */
Kojto 90:cb3d968589d8 4422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
Kojto 90:cb3d968589d8 4423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
Kojto 90:cb3d968589d8 4424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
Kojto 90:cb3d968589d8 4425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
Kojto 90:cb3d968589d8 4426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
Kojto 90:cb3d968589d8 4427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
Kojto 90:cb3d968589d8 4428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
Kojto 90:cb3d968589d8 4429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
Kojto 90:cb3d968589d8 4430
Kojto 90:cb3d968589d8 4431 /*!
Kojto 90:cb3d968589d8 4432 * @}
Kojto 90:cb3d968589d8 4433 */ /* end of group DMA_Register_Masks */
Kojto 90:cb3d968589d8 4434
Kojto 90:cb3d968589d8 4435
Kojto 90:cb3d968589d8 4436 /* DMA - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4437 /** Peripheral DMA base address */
Kojto 90:cb3d968589d8 4438 #define DMA_BASE (0x40008000u)
Kojto 90:cb3d968589d8 4439 /** Peripheral DMA base pointer */
Kojto 90:cb3d968589d8 4440 #define DMA0 ((DMA_Type *)DMA_BASE)
Kojto 90:cb3d968589d8 4441 #define DMA_BASE_PTR (DMA0)
Kojto 90:cb3d968589d8 4442 /** Array initializer of DMA peripheral base addresses */
Kojto 90:cb3d968589d8 4443 #define DMA_BASE_ADDRS { DMA_BASE }
Kojto 90:cb3d968589d8 4444 /** Array initializer of DMA peripheral base pointers */
Kojto 90:cb3d968589d8 4445 #define DMA_BASE_PTRS { DMA0 }
Kojto 90:cb3d968589d8 4446 /** Interrupt vectors for the DMA peripheral type */
Kojto 90:cb3d968589d8 4447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
Kojto 90:cb3d968589d8 4448 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
Kojto 90:cb3d968589d8 4449
Kojto 90:cb3d968589d8 4450 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4451 -- DMA - Register accessor macros
Kojto 90:cb3d968589d8 4452 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4453
Kojto 90:cb3d968589d8 4454 /*!
Kojto 90:cb3d968589d8 4455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Kojto 90:cb3d968589d8 4456 * @{
Kojto 90:cb3d968589d8 4457 */
Kojto 90:cb3d968589d8 4458
Kojto 90:cb3d968589d8 4459
Kojto 90:cb3d968589d8 4460 /* DMA - Register instance definitions */
Kojto 90:cb3d968589d8 4461 /* DMA */
Kojto 90:cb3d968589d8 4462 #define DMA_CR DMA_CR_REG(DMA0)
Kojto 90:cb3d968589d8 4463 #define DMA_ES DMA_ES_REG(DMA0)
Kojto 90:cb3d968589d8 4464 #define DMA_ERQ DMA_ERQ_REG(DMA0)
Kojto 90:cb3d968589d8 4465 #define DMA_EEI DMA_EEI_REG(DMA0)
Kojto 90:cb3d968589d8 4466 #define DMA_CEEI DMA_CEEI_REG(DMA0)
Kojto 90:cb3d968589d8 4467 #define DMA_SEEI DMA_SEEI_REG(DMA0)
Kojto 90:cb3d968589d8 4468 #define DMA_CERQ DMA_CERQ_REG(DMA0)
Kojto 90:cb3d968589d8 4469 #define DMA_SERQ DMA_SERQ_REG(DMA0)
Kojto 90:cb3d968589d8 4470 #define DMA_CDNE DMA_CDNE_REG(DMA0)
Kojto 90:cb3d968589d8 4471 #define DMA_SSRT DMA_SSRT_REG(DMA0)
Kojto 90:cb3d968589d8 4472 #define DMA_CERR DMA_CERR_REG(DMA0)
Kojto 90:cb3d968589d8 4473 #define DMA_CINT DMA_CINT_REG(DMA0)
Kojto 90:cb3d968589d8 4474 #define DMA_INT DMA_INT_REG(DMA0)
Kojto 90:cb3d968589d8 4475 #define DMA_ERR DMA_ERR_REG(DMA0)
Kojto 90:cb3d968589d8 4476 #define DMA_HRS DMA_HRS_REG(DMA0)
Kojto 90:cb3d968589d8 4477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
Kojto 90:cb3d968589d8 4478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
Kojto 90:cb3d968589d8 4479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
Kojto 90:cb3d968589d8 4480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
Kojto 90:cb3d968589d8 4481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
Kojto 90:cb3d968589d8 4482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
Kojto 90:cb3d968589d8 4483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
Kojto 90:cb3d968589d8 4484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
Kojto 90:cb3d968589d8 4485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
Kojto 90:cb3d968589d8 4486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
Kojto 90:cb3d968589d8 4487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
Kojto 90:cb3d968589d8 4488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
Kojto 90:cb3d968589d8 4489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
Kojto 90:cb3d968589d8 4490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
Kojto 90:cb3d968589d8 4491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
Kojto 90:cb3d968589d8 4492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
Kojto 90:cb3d968589d8 4493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
Kojto 90:cb3d968589d8 4494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
Kojto 90:cb3d968589d8 4495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
Kojto 90:cb3d968589d8 4496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
Kojto 90:cb3d968589d8 4497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
Kojto 90:cb3d968589d8 4498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
Kojto 90:cb3d968589d8 4499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
Kojto 90:cb3d968589d8 4500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
Kojto 90:cb3d968589d8 4501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
Kojto 90:cb3d968589d8 4502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
Kojto 90:cb3d968589d8 4503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
Kojto 90:cb3d968589d8 4504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
Kojto 90:cb3d968589d8 4505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
Kojto 90:cb3d968589d8 4506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
Kojto 90:cb3d968589d8 4507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
Kojto 90:cb3d968589d8 4508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
Kojto 90:cb3d968589d8 4509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
Kojto 90:cb3d968589d8 4510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
Kojto 90:cb3d968589d8 4511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
Kojto 90:cb3d968589d8 4512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
Kojto 90:cb3d968589d8 4513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
Kojto 90:cb3d968589d8 4514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
Kojto 90:cb3d968589d8 4515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
Kojto 90:cb3d968589d8 4516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
Kojto 90:cb3d968589d8 4517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
Kojto 90:cb3d968589d8 4518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
Kojto 90:cb3d968589d8 4519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
Kojto 90:cb3d968589d8 4520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
Kojto 90:cb3d968589d8 4521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
Kojto 90:cb3d968589d8 4522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
Kojto 90:cb3d968589d8 4523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
Kojto 90:cb3d968589d8 4524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
Kojto 90:cb3d968589d8 4525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
Kojto 90:cb3d968589d8 4526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
Kojto 90:cb3d968589d8 4527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
Kojto 90:cb3d968589d8 4528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
Kojto 90:cb3d968589d8 4529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
Kojto 90:cb3d968589d8 4530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
Kojto 90:cb3d968589d8 4531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
Kojto 90:cb3d968589d8 4532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
Kojto 90:cb3d968589d8 4533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
Kojto 90:cb3d968589d8 4534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
Kojto 90:cb3d968589d8 4535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
Kojto 90:cb3d968589d8 4536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
Kojto 90:cb3d968589d8 4537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
Kojto 90:cb3d968589d8 4538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
Kojto 90:cb3d968589d8 4539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
Kojto 90:cb3d968589d8 4540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
Kojto 90:cb3d968589d8 4541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
Kojto 90:cb3d968589d8 4542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
Kojto 90:cb3d968589d8 4543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
Kojto 90:cb3d968589d8 4544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
Kojto 90:cb3d968589d8 4545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
Kojto 90:cb3d968589d8 4546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
Kojto 90:cb3d968589d8 4547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
Kojto 90:cb3d968589d8 4548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
Kojto 90:cb3d968589d8 4549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
Kojto 90:cb3d968589d8 4550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
Kojto 90:cb3d968589d8 4551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
Kojto 90:cb3d968589d8 4552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
Kojto 90:cb3d968589d8 4553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
Kojto 90:cb3d968589d8 4554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
Kojto 90:cb3d968589d8 4555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
Kojto 90:cb3d968589d8 4556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
Kojto 90:cb3d968589d8 4557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
Kojto 90:cb3d968589d8 4558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
Kojto 90:cb3d968589d8 4559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
Kojto 90:cb3d968589d8 4560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
Kojto 90:cb3d968589d8 4561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
Kojto 90:cb3d968589d8 4562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
Kojto 90:cb3d968589d8 4563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
Kojto 90:cb3d968589d8 4564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
Kojto 90:cb3d968589d8 4565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
Kojto 90:cb3d968589d8 4566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
Kojto 90:cb3d968589d8 4567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
Kojto 90:cb3d968589d8 4568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
Kojto 90:cb3d968589d8 4569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
Kojto 90:cb3d968589d8 4570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
Kojto 90:cb3d968589d8 4571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
Kojto 90:cb3d968589d8 4572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
Kojto 90:cb3d968589d8 4573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
Kojto 90:cb3d968589d8 4574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
Kojto 90:cb3d968589d8 4575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
Kojto 90:cb3d968589d8 4576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
Kojto 90:cb3d968589d8 4577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
Kojto 90:cb3d968589d8 4578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
Kojto 90:cb3d968589d8 4579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
Kojto 90:cb3d968589d8 4580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
Kojto 90:cb3d968589d8 4581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
Kojto 90:cb3d968589d8 4582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
Kojto 90:cb3d968589d8 4583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
Kojto 90:cb3d968589d8 4584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
Kojto 90:cb3d968589d8 4585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
Kojto 90:cb3d968589d8 4586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
Kojto 90:cb3d968589d8 4587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
Kojto 90:cb3d968589d8 4588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
Kojto 90:cb3d968589d8 4589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
Kojto 90:cb3d968589d8 4590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
Kojto 90:cb3d968589d8 4591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
Kojto 90:cb3d968589d8 4592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
Kojto 90:cb3d968589d8 4593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
Kojto 90:cb3d968589d8 4594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
Kojto 90:cb3d968589d8 4595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
Kojto 90:cb3d968589d8 4596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
Kojto 90:cb3d968589d8 4597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
Kojto 90:cb3d968589d8 4598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
Kojto 90:cb3d968589d8 4599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
Kojto 90:cb3d968589d8 4600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
Kojto 90:cb3d968589d8 4601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
Kojto 90:cb3d968589d8 4602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
Kojto 90:cb3d968589d8 4603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
Kojto 90:cb3d968589d8 4604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
Kojto 90:cb3d968589d8 4605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
Kojto 90:cb3d968589d8 4606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
Kojto 90:cb3d968589d8 4607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
Kojto 90:cb3d968589d8 4608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
Kojto 90:cb3d968589d8 4609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
Kojto 90:cb3d968589d8 4610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
Kojto 90:cb3d968589d8 4611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
Kojto 90:cb3d968589d8 4612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
Kojto 90:cb3d968589d8 4613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
Kojto 90:cb3d968589d8 4614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
Kojto 90:cb3d968589d8 4615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
Kojto 90:cb3d968589d8 4616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
Kojto 90:cb3d968589d8 4617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
Kojto 90:cb3d968589d8 4618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
Kojto 90:cb3d968589d8 4619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
Kojto 90:cb3d968589d8 4620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
Kojto 90:cb3d968589d8 4621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
Kojto 90:cb3d968589d8 4622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
Kojto 90:cb3d968589d8 4623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
Kojto 90:cb3d968589d8 4624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
Kojto 90:cb3d968589d8 4625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
Kojto 90:cb3d968589d8 4626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
Kojto 90:cb3d968589d8 4627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
Kojto 90:cb3d968589d8 4628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
Kojto 90:cb3d968589d8 4629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
Kojto 90:cb3d968589d8 4630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
Kojto 90:cb3d968589d8 4631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
Kojto 90:cb3d968589d8 4632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
Kojto 90:cb3d968589d8 4633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
Kojto 90:cb3d968589d8 4634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
Kojto 90:cb3d968589d8 4635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
Kojto 90:cb3d968589d8 4636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
Kojto 90:cb3d968589d8 4637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
Kojto 90:cb3d968589d8 4638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
Kojto 90:cb3d968589d8 4639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
Kojto 90:cb3d968589d8 4640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
Kojto 90:cb3d968589d8 4641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
Kojto 90:cb3d968589d8 4642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
Kojto 90:cb3d968589d8 4643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
Kojto 90:cb3d968589d8 4644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
Kojto 90:cb3d968589d8 4645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
Kojto 90:cb3d968589d8 4646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
Kojto 90:cb3d968589d8 4647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
Kojto 90:cb3d968589d8 4648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
Kojto 90:cb3d968589d8 4649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
Kojto 90:cb3d968589d8 4650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
Kojto 90:cb3d968589d8 4651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
Kojto 90:cb3d968589d8 4652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
Kojto 90:cb3d968589d8 4653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
Kojto 90:cb3d968589d8 4654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
Kojto 90:cb3d968589d8 4655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
Kojto 90:cb3d968589d8 4656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
Kojto 90:cb3d968589d8 4657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
Kojto 90:cb3d968589d8 4658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
Kojto 90:cb3d968589d8 4659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
Kojto 90:cb3d968589d8 4660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
Kojto 90:cb3d968589d8 4661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
Kojto 90:cb3d968589d8 4662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
Kojto 90:cb3d968589d8 4663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
Kojto 90:cb3d968589d8 4664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
Kojto 90:cb3d968589d8 4665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
Kojto 90:cb3d968589d8 4666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
Kojto 90:cb3d968589d8 4667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
Kojto 90:cb3d968589d8 4668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
Kojto 90:cb3d968589d8 4669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
Kojto 90:cb3d968589d8 4670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
Kojto 90:cb3d968589d8 4671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
Kojto 90:cb3d968589d8 4672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
Kojto 90:cb3d968589d8 4673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
Kojto 90:cb3d968589d8 4674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
Kojto 90:cb3d968589d8 4675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
Kojto 90:cb3d968589d8 4676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
Kojto 90:cb3d968589d8 4677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
Kojto 90:cb3d968589d8 4678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
Kojto 90:cb3d968589d8 4679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
Kojto 90:cb3d968589d8 4680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
Kojto 90:cb3d968589d8 4681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
Kojto 90:cb3d968589d8 4682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
Kojto 90:cb3d968589d8 4683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
Kojto 90:cb3d968589d8 4684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
Kojto 90:cb3d968589d8 4685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
Kojto 90:cb3d968589d8 4686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
Kojto 90:cb3d968589d8 4687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
Kojto 90:cb3d968589d8 4688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
Kojto 90:cb3d968589d8 4689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
Kojto 90:cb3d968589d8 4690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
Kojto 90:cb3d968589d8 4691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
Kojto 90:cb3d968589d8 4692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
Kojto 90:cb3d968589d8 4693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
Kojto 90:cb3d968589d8 4694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
Kojto 90:cb3d968589d8 4695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
Kojto 90:cb3d968589d8 4696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
Kojto 90:cb3d968589d8 4697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
Kojto 90:cb3d968589d8 4698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
Kojto 90:cb3d968589d8 4699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
Kojto 90:cb3d968589d8 4700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
Kojto 90:cb3d968589d8 4701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
Kojto 90:cb3d968589d8 4702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
Kojto 90:cb3d968589d8 4703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
Kojto 90:cb3d968589d8 4704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
Kojto 90:cb3d968589d8 4705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
Kojto 90:cb3d968589d8 4706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
Kojto 90:cb3d968589d8 4707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
Kojto 90:cb3d968589d8 4708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
Kojto 90:cb3d968589d8 4709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
Kojto 90:cb3d968589d8 4710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
Kojto 90:cb3d968589d8 4711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
Kojto 90:cb3d968589d8 4712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
Kojto 90:cb3d968589d8 4713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
Kojto 90:cb3d968589d8 4714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
Kojto 90:cb3d968589d8 4715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
Kojto 90:cb3d968589d8 4716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
Kojto 90:cb3d968589d8 4717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
Kojto 90:cb3d968589d8 4718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
Kojto 90:cb3d968589d8 4719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
Kojto 90:cb3d968589d8 4720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
Kojto 90:cb3d968589d8 4721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
Kojto 90:cb3d968589d8 4722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
Kojto 90:cb3d968589d8 4723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
Kojto 90:cb3d968589d8 4724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
Kojto 90:cb3d968589d8 4725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
Kojto 90:cb3d968589d8 4726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
Kojto 90:cb3d968589d8 4727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
Kojto 90:cb3d968589d8 4728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
Kojto 90:cb3d968589d8 4729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
Kojto 90:cb3d968589d8 4730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
Kojto 90:cb3d968589d8 4731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
Kojto 90:cb3d968589d8 4732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
Kojto 90:cb3d968589d8 4733
Kojto 90:cb3d968589d8 4734 /* DMA - Register array accessors */
Kojto 90:cb3d968589d8 4735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
Kojto 90:cb3d968589d8 4736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
Kojto 90:cb3d968589d8 4737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
Kojto 90:cb3d968589d8 4738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
Kojto 90:cb3d968589d8 4739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
Kojto 90:cb3d968589d8 4740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
Kojto 90:cb3d968589d8 4741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
Kojto 90:cb3d968589d8 4742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
Kojto 90:cb3d968589d8 4743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
Kojto 90:cb3d968589d8 4744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
Kojto 90:cb3d968589d8 4745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
Kojto 90:cb3d968589d8 4746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
Kojto 90:cb3d968589d8 4747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
Kojto 90:cb3d968589d8 4748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
Kojto 90:cb3d968589d8 4749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
Kojto 90:cb3d968589d8 4750
Kojto 90:cb3d968589d8 4751 /*!
Kojto 90:cb3d968589d8 4752 * @}
Kojto 90:cb3d968589d8 4753 */ /* end of group DMA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4754
Kojto 90:cb3d968589d8 4755
Kojto 90:cb3d968589d8 4756 /*!
Kojto 90:cb3d968589d8 4757 * @}
Kojto 90:cb3d968589d8 4758 */ /* end of group DMA_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4759
Kojto 90:cb3d968589d8 4760
Kojto 90:cb3d968589d8 4761 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4762 -- DMAMUX Peripheral Access Layer
Kojto 90:cb3d968589d8 4763 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4764
Kojto 90:cb3d968589d8 4765 /*!
Kojto 90:cb3d968589d8 4766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Kojto 90:cb3d968589d8 4767 * @{
Kojto 90:cb3d968589d8 4768 */
Kojto 90:cb3d968589d8 4769
Kojto 90:cb3d968589d8 4770 /** DMAMUX - Register Layout Typedef */
Kojto 90:cb3d968589d8 4771 typedef struct {
Kojto 90:cb3d968589d8 4772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
Kojto 90:cb3d968589d8 4773 } DMAMUX_Type, *DMAMUX_MemMapPtr;
Kojto 90:cb3d968589d8 4774
Kojto 90:cb3d968589d8 4775 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4776 -- DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 4777 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4778
Kojto 90:cb3d968589d8 4779 /*!
Kojto 90:cb3d968589d8 4780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 4781 * @{
Kojto 90:cb3d968589d8 4782 */
Kojto 90:cb3d968589d8 4783
Kojto 90:cb3d968589d8 4784
Kojto 90:cb3d968589d8 4785 /* DMAMUX - Register accessors */
Kojto 90:cb3d968589d8 4786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
Kojto 90:cb3d968589d8 4787
Kojto 90:cb3d968589d8 4788 /*!
Kojto 90:cb3d968589d8 4789 * @}
Kojto 90:cb3d968589d8 4790 */ /* end of group DMAMUX_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4791
Kojto 90:cb3d968589d8 4792
Kojto 90:cb3d968589d8 4793 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4794 -- DMAMUX Register Masks
Kojto 90:cb3d968589d8 4795 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4796
Kojto 90:cb3d968589d8 4797 /*!
Kojto 90:cb3d968589d8 4798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Kojto 90:cb3d968589d8 4799 * @{
Kojto 90:cb3d968589d8 4800 */
Kojto 90:cb3d968589d8 4801
Kojto 90:cb3d968589d8 4802 /* CHCFG Bit Fields */
Kojto 90:cb3d968589d8 4803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
Kojto 90:cb3d968589d8 4804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
Kojto 90:cb3d968589d8 4805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
Kojto 90:cb3d968589d8 4806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
Kojto 90:cb3d968589d8 4807 #define DMAMUX_CHCFG_TRIG_SHIFT 6
Kojto 90:cb3d968589d8 4808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
Kojto 90:cb3d968589d8 4809 #define DMAMUX_CHCFG_ENBL_SHIFT 7
Kojto 90:cb3d968589d8 4810
Kojto 90:cb3d968589d8 4811 /*!
Kojto 90:cb3d968589d8 4812 * @}
Kojto 90:cb3d968589d8 4813 */ /* end of group DMAMUX_Register_Masks */
Kojto 90:cb3d968589d8 4814
Kojto 90:cb3d968589d8 4815
Kojto 90:cb3d968589d8 4816 /* DMAMUX - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4817 /** Peripheral DMAMUX base address */
Kojto 90:cb3d968589d8 4818 #define DMAMUX_BASE (0x40021000u)
Kojto 90:cb3d968589d8 4819 /** Peripheral DMAMUX base pointer */
Kojto 90:cb3d968589d8 4820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
Kojto 90:cb3d968589d8 4821 #define DMAMUX_BASE_PTR (DMAMUX)
Kojto 90:cb3d968589d8 4822 /** Array initializer of DMAMUX peripheral base addresses */
Kojto 90:cb3d968589d8 4823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
Kojto 90:cb3d968589d8 4824 /** Array initializer of DMAMUX peripheral base pointers */
Kojto 90:cb3d968589d8 4825 #define DMAMUX_BASE_PTRS { DMAMUX }
Kojto 90:cb3d968589d8 4826
Kojto 90:cb3d968589d8 4827 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4828 -- DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 4829 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4830
Kojto 90:cb3d968589d8 4831 /*!
Kojto 90:cb3d968589d8 4832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 4833 * @{
Kojto 90:cb3d968589d8 4834 */
Kojto 90:cb3d968589d8 4835
Kojto 90:cb3d968589d8 4836
Kojto 90:cb3d968589d8 4837 /* DMAMUX - Register instance definitions */
Kojto 90:cb3d968589d8 4838 /* DMAMUX */
Kojto 90:cb3d968589d8 4839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
Kojto 90:cb3d968589d8 4840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
Kojto 90:cb3d968589d8 4841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
Kojto 90:cb3d968589d8 4842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
Kojto 90:cb3d968589d8 4843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
Kojto 90:cb3d968589d8 4844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
Kojto 90:cb3d968589d8 4845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
Kojto 90:cb3d968589d8 4846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
Kojto 90:cb3d968589d8 4847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
Kojto 90:cb3d968589d8 4848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
Kojto 90:cb3d968589d8 4849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
Kojto 90:cb3d968589d8 4850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
Kojto 90:cb3d968589d8 4851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
Kojto 90:cb3d968589d8 4852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
Kojto 90:cb3d968589d8 4853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
Kojto 90:cb3d968589d8 4854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
Kojto 90:cb3d968589d8 4855
Kojto 90:cb3d968589d8 4856 /* DMAMUX - Register array accessors */
Kojto 90:cb3d968589d8 4857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
Kojto 90:cb3d968589d8 4858
Kojto 90:cb3d968589d8 4859 /*!
Kojto 90:cb3d968589d8 4860 * @}
Kojto 90:cb3d968589d8 4861 */ /* end of group DMAMUX_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4862
Kojto 90:cb3d968589d8 4863
Kojto 90:cb3d968589d8 4864 /*!
Kojto 90:cb3d968589d8 4865 * @}
Kojto 90:cb3d968589d8 4866 */ /* end of group DMAMUX_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4867
Kojto 90:cb3d968589d8 4868
Kojto 90:cb3d968589d8 4869 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4870 -- ENET Peripheral Access Layer
Kojto 90:cb3d968589d8 4871 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4872
Kojto 90:cb3d968589d8 4873 /*!
Kojto 90:cb3d968589d8 4874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
Kojto 90:cb3d968589d8 4875 * @{
Kojto 90:cb3d968589d8 4876 */
Kojto 90:cb3d968589d8 4877
Kojto 90:cb3d968589d8 4878 /** ENET - Register Layout Typedef */
Kojto 90:cb3d968589d8 4879 typedef struct {
Kojto 90:cb3d968589d8 4880 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 4881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
Kojto 90:cb3d968589d8 4882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
Kojto 90:cb3d968589d8 4883 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 4884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
Kojto 90:cb3d968589d8 4885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
Kojto 90:cb3d968589d8 4886 uint8_t RESERVED_2[12];
Kojto 90:cb3d968589d8 4887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
Kojto 90:cb3d968589d8 4888 uint8_t RESERVED_3[24];
Kojto 90:cb3d968589d8 4889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
Kojto 90:cb3d968589d8 4890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
Kojto 90:cb3d968589d8 4891 uint8_t RESERVED_4[28];
Kojto 90:cb3d968589d8 4892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
Kojto 90:cb3d968589d8 4893 uint8_t RESERVED_5[28];
Kojto 90:cb3d968589d8 4894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
Kojto 90:cb3d968589d8 4895 uint8_t RESERVED_6[60];
Kojto 90:cb3d968589d8 4896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
Kojto 90:cb3d968589d8 4897 uint8_t RESERVED_7[28];
Kojto 90:cb3d968589d8 4898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
Kojto 90:cb3d968589d8 4899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
Kojto 90:cb3d968589d8 4900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
Kojto 90:cb3d968589d8 4901 uint8_t RESERVED_8[40];
Kojto 90:cb3d968589d8 4902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
Kojto 90:cb3d968589d8 4903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
Kojto 90:cb3d968589d8 4904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
Kojto 90:cb3d968589d8 4905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
Kojto 90:cb3d968589d8 4906 uint8_t RESERVED_9[28];
Kojto 90:cb3d968589d8 4907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
Kojto 90:cb3d968589d8 4908 uint8_t RESERVED_10[56];
Kojto 90:cb3d968589d8 4909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
Kojto 90:cb3d968589d8 4910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
Kojto 90:cb3d968589d8 4911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
Kojto 90:cb3d968589d8 4912 uint8_t RESERVED_11[4];
Kojto 90:cb3d968589d8 4913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
Kojto 90:cb3d968589d8 4914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
Kojto 90:cb3d968589d8 4915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
Kojto 90:cb3d968589d8 4916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
Kojto 90:cb3d968589d8 4917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
Kojto 90:cb3d968589d8 4918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
Kojto 90:cb3d968589d8 4919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
Kojto 90:cb3d968589d8 4920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
Kojto 90:cb3d968589d8 4921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
Kojto 90:cb3d968589d8 4922 uint8_t RESERVED_12[12];
Kojto 90:cb3d968589d8 4923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
Kojto 90:cb3d968589d8 4924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
Kojto 90:cb3d968589d8 4925 uint8_t RESERVED_13[60];
Kojto 90:cb3d968589d8 4926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
Kojto 90:cb3d968589d8 4927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
Kojto 90:cb3d968589d8 4928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
Kojto 90:cb3d968589d8 4929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
Kojto 90:cb3d968589d8 4930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
Kojto 90:cb3d968589d8 4931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
Kojto 90:cb3d968589d8 4932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
Kojto 90:cb3d968589d8 4933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
Kojto 90:cb3d968589d8 4934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
Kojto 90:cb3d968589d8 4935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
Kojto 90:cb3d968589d8 4936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
Kojto 90:cb3d968589d8 4937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
Kojto 90:cb3d968589d8 4938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
Kojto 90:cb3d968589d8 4939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
Kojto 90:cb3d968589d8 4940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
Kojto 90:cb3d968589d8 4941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
Kojto 90:cb3d968589d8 4942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
Kojto 90:cb3d968589d8 4943 uint8_t RESERVED_14[4];
Kojto 90:cb3d968589d8 4944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
Kojto 90:cb3d968589d8 4945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
Kojto 90:cb3d968589d8 4946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
Kojto 90:cb3d968589d8 4947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
Kojto 90:cb3d968589d8 4948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
Kojto 90:cb3d968589d8 4949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
Kojto 90:cb3d968589d8 4950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
Kojto 90:cb3d968589d8 4951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
Kojto 90:cb3d968589d8 4952 uint8_t RESERVED_15[4];
Kojto 90:cb3d968589d8 4953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
Kojto 90:cb3d968589d8 4954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
Kojto 90:cb3d968589d8 4955 uint8_t RESERVED_16[12];
Kojto 90:cb3d968589d8 4956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
Kojto 90:cb3d968589d8 4957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
Kojto 90:cb3d968589d8 4958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
Kojto 90:cb3d968589d8 4959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
Kojto 90:cb3d968589d8 4960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
Kojto 90:cb3d968589d8 4961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
Kojto 90:cb3d968589d8 4962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
Kojto 90:cb3d968589d8 4963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
Kojto 90:cb3d968589d8 4964 uint8_t RESERVED_17[4];
Kojto 90:cb3d968589d8 4965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
Kojto 90:cb3d968589d8 4966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
Kojto 90:cb3d968589d8 4967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
Kojto 90:cb3d968589d8 4968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
Kojto 90:cb3d968589d8 4969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
Kojto 90:cb3d968589d8 4970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
Kojto 90:cb3d968589d8 4971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
Kojto 90:cb3d968589d8 4972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
Kojto 90:cb3d968589d8 4973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
Kojto 90:cb3d968589d8 4974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
Kojto 90:cb3d968589d8 4975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
Kojto 90:cb3d968589d8 4976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
Kojto 90:cb3d968589d8 4977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
Kojto 90:cb3d968589d8 4978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
Kojto 90:cb3d968589d8 4979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
Kojto 90:cb3d968589d8 4980 uint8_t RESERVED_18[284];
Kojto 90:cb3d968589d8 4981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
Kojto 90:cb3d968589d8 4982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
Kojto 90:cb3d968589d8 4983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
Kojto 90:cb3d968589d8 4984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
Kojto 90:cb3d968589d8 4985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
Kojto 90:cb3d968589d8 4986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
Kojto 90:cb3d968589d8 4987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
Kojto 90:cb3d968589d8 4988 uint8_t RESERVED_19[488];
Kojto 90:cb3d968589d8 4989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
Kojto 90:cb3d968589d8 4990 struct { /* offset: 0x608, array step: 0x8 */
Kojto 90:cb3d968589d8 4991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
Kojto 90:cb3d968589d8 4992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
Kojto 90:cb3d968589d8 4993 } CHANNEL[4];
Kojto 90:cb3d968589d8 4994 } ENET_Type, *ENET_MemMapPtr;
Kojto 90:cb3d968589d8 4995
Kojto 90:cb3d968589d8 4996 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4997 -- ENET - Register accessor macros
Kojto 90:cb3d968589d8 4998 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4999
Kojto 90:cb3d968589d8 5000 /*!
Kojto 90:cb3d968589d8 5001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
Kojto 90:cb3d968589d8 5002 * @{
Kojto 90:cb3d968589d8 5003 */
Kojto 90:cb3d968589d8 5004
Kojto 90:cb3d968589d8 5005
Kojto 90:cb3d968589d8 5006 /* ENET - Register accessors */
Kojto 90:cb3d968589d8 5007 #define ENET_EIR_REG(base) ((base)->EIR)
Kojto 90:cb3d968589d8 5008 #define ENET_EIMR_REG(base) ((base)->EIMR)
Kojto 90:cb3d968589d8 5009 #define ENET_RDAR_REG(base) ((base)->RDAR)
Kojto 90:cb3d968589d8 5010 #define ENET_TDAR_REG(base) ((base)->TDAR)
Kojto 90:cb3d968589d8 5011 #define ENET_ECR_REG(base) ((base)->ECR)
Kojto 90:cb3d968589d8 5012 #define ENET_MMFR_REG(base) ((base)->MMFR)
Kojto 90:cb3d968589d8 5013 #define ENET_MSCR_REG(base) ((base)->MSCR)
Kojto 90:cb3d968589d8 5014 #define ENET_MIBC_REG(base) ((base)->MIBC)
Kojto 90:cb3d968589d8 5015 #define ENET_RCR_REG(base) ((base)->RCR)
Kojto 90:cb3d968589d8 5016 #define ENET_TCR_REG(base) ((base)->TCR)
Kojto 90:cb3d968589d8 5017 #define ENET_PALR_REG(base) ((base)->PALR)
Kojto 90:cb3d968589d8 5018 #define ENET_PAUR_REG(base) ((base)->PAUR)
Kojto 90:cb3d968589d8 5019 #define ENET_OPD_REG(base) ((base)->OPD)
Kojto 90:cb3d968589d8 5020 #define ENET_IAUR_REG(base) ((base)->IAUR)
Kojto 90:cb3d968589d8 5021 #define ENET_IALR_REG(base) ((base)->IALR)
Kojto 90:cb3d968589d8 5022 #define ENET_GAUR_REG(base) ((base)->GAUR)
Kojto 90:cb3d968589d8 5023 #define ENET_GALR_REG(base) ((base)->GALR)
Kojto 90:cb3d968589d8 5024 #define ENET_TFWR_REG(base) ((base)->TFWR)
Kojto 90:cb3d968589d8 5025 #define ENET_RDSR_REG(base) ((base)->RDSR)
Kojto 90:cb3d968589d8 5026 #define ENET_TDSR_REG(base) ((base)->TDSR)
Kojto 90:cb3d968589d8 5027 #define ENET_MRBR_REG(base) ((base)->MRBR)
Kojto 90:cb3d968589d8 5028 #define ENET_RSFL_REG(base) ((base)->RSFL)
Kojto 90:cb3d968589d8 5029 #define ENET_RSEM_REG(base) ((base)->RSEM)
Kojto 90:cb3d968589d8 5030 #define ENET_RAEM_REG(base) ((base)->RAEM)
Kojto 90:cb3d968589d8 5031 #define ENET_RAFL_REG(base) ((base)->RAFL)
Kojto 90:cb3d968589d8 5032 #define ENET_TSEM_REG(base) ((base)->TSEM)
Kojto 90:cb3d968589d8 5033 #define ENET_TAEM_REG(base) ((base)->TAEM)
Kojto 90:cb3d968589d8 5034 #define ENET_TAFL_REG(base) ((base)->TAFL)
Kojto 90:cb3d968589d8 5035 #define ENET_TIPG_REG(base) ((base)->TIPG)
Kojto 90:cb3d968589d8 5036 #define ENET_FTRL_REG(base) ((base)->FTRL)
Kojto 90:cb3d968589d8 5037 #define ENET_TACC_REG(base) ((base)->TACC)
Kojto 90:cb3d968589d8 5038 #define ENET_RACC_REG(base) ((base)->RACC)
Kojto 90:cb3d968589d8 5039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
Kojto 90:cb3d968589d8 5040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
Kojto 90:cb3d968589d8 5041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
Kojto 90:cb3d968589d8 5042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
Kojto 90:cb3d968589d8 5043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
Kojto 90:cb3d968589d8 5044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
Kojto 90:cb3d968589d8 5045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
Kojto 90:cb3d968589d8 5046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
Kojto 90:cb3d968589d8 5047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
Kojto 90:cb3d968589d8 5048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
Kojto 90:cb3d968589d8 5049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
Kojto 90:cb3d968589d8 5050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
Kojto 90:cb3d968589d8 5051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
Kojto 90:cb3d968589d8 5052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
Kojto 90:cb3d968589d8 5053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
Kojto 90:cb3d968589d8 5054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
Kojto 90:cb3d968589d8 5055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
Kojto 90:cb3d968589d8 5056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
Kojto 90:cb3d968589d8 5057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
Kojto 90:cb3d968589d8 5058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
Kojto 90:cb3d968589d8 5059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
Kojto 90:cb3d968589d8 5060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
Kojto 90:cb3d968589d8 5061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
Kojto 90:cb3d968589d8 5062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
Kojto 90:cb3d968589d8 5063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
Kojto 90:cb3d968589d8 5064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
Kojto 90:cb3d968589d8 5065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
Kojto 90:cb3d968589d8 5066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
Kojto 90:cb3d968589d8 5067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
Kojto 90:cb3d968589d8 5068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
Kojto 90:cb3d968589d8 5069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
Kojto 90:cb3d968589d8 5070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
Kojto 90:cb3d968589d8 5071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
Kojto 90:cb3d968589d8 5072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
Kojto 90:cb3d968589d8 5073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
Kojto 90:cb3d968589d8 5074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
Kojto 90:cb3d968589d8 5075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
Kojto 90:cb3d968589d8 5076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
Kojto 90:cb3d968589d8 5077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
Kojto 90:cb3d968589d8 5078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
Kojto 90:cb3d968589d8 5079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
Kojto 90:cb3d968589d8 5080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
Kojto 90:cb3d968589d8 5081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
Kojto 90:cb3d968589d8 5082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
Kojto 90:cb3d968589d8 5083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
Kojto 90:cb3d968589d8 5084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
Kojto 90:cb3d968589d8 5085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
Kojto 90:cb3d968589d8 5086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
Kojto 90:cb3d968589d8 5087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
Kojto 90:cb3d968589d8 5088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
Kojto 90:cb3d968589d8 5089 #define ENET_ATCR_REG(base) ((base)->ATCR)
Kojto 90:cb3d968589d8 5090 #define ENET_ATVR_REG(base) ((base)->ATVR)
Kojto 90:cb3d968589d8 5091 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
Kojto 90:cb3d968589d8 5092 #define ENET_ATPER_REG(base) ((base)->ATPER)
Kojto 90:cb3d968589d8 5093 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
Kojto 90:cb3d968589d8 5094 #define ENET_ATINC_REG(base) ((base)->ATINC)
Kojto 90:cb3d968589d8 5095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
Kojto 90:cb3d968589d8 5096 #define ENET_TGSR_REG(base) ((base)->TGSR)
Kojto 90:cb3d968589d8 5097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
Kojto 90:cb3d968589d8 5098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
Kojto 90:cb3d968589d8 5099
Kojto 90:cb3d968589d8 5100 /*!
Kojto 90:cb3d968589d8 5101 * @}
Kojto 90:cb3d968589d8 5102 */ /* end of group ENET_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5103
Kojto 90:cb3d968589d8 5104
Kojto 90:cb3d968589d8 5105 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5106 -- ENET Register Masks
Kojto 90:cb3d968589d8 5107 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5108
Kojto 90:cb3d968589d8 5109 /*!
Kojto 90:cb3d968589d8 5110 * @addtogroup ENET_Register_Masks ENET Register Masks
Kojto 90:cb3d968589d8 5111 * @{
Kojto 90:cb3d968589d8 5112 */
Kojto 90:cb3d968589d8 5113
Kojto 90:cb3d968589d8 5114 /* EIR Bit Fields */
Kojto 90:cb3d968589d8 5115 #define ENET_EIR_TS_TIMER_MASK 0x8000u
Kojto 90:cb3d968589d8 5116 #define ENET_EIR_TS_TIMER_SHIFT 15
Kojto 90:cb3d968589d8 5117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
Kojto 90:cb3d968589d8 5118 #define ENET_EIR_TS_AVAIL_SHIFT 16
Kojto 90:cb3d968589d8 5119 #define ENET_EIR_WAKEUP_MASK 0x20000u
Kojto 90:cb3d968589d8 5120 #define ENET_EIR_WAKEUP_SHIFT 17
Kojto 90:cb3d968589d8 5121 #define ENET_EIR_PLR_MASK 0x40000u
Kojto 90:cb3d968589d8 5122 #define ENET_EIR_PLR_SHIFT 18
Kojto 90:cb3d968589d8 5123 #define ENET_EIR_UN_MASK 0x80000u
Kojto 90:cb3d968589d8 5124 #define ENET_EIR_UN_SHIFT 19
Kojto 90:cb3d968589d8 5125 #define ENET_EIR_RL_MASK 0x100000u
Kojto 90:cb3d968589d8 5126 #define ENET_EIR_RL_SHIFT 20
Kojto 90:cb3d968589d8 5127 #define ENET_EIR_LC_MASK 0x200000u
Kojto 90:cb3d968589d8 5128 #define ENET_EIR_LC_SHIFT 21
Kojto 90:cb3d968589d8 5129 #define ENET_EIR_EBERR_MASK 0x400000u
Kojto 90:cb3d968589d8 5130 #define ENET_EIR_EBERR_SHIFT 22
Kojto 90:cb3d968589d8 5131 #define ENET_EIR_MII_MASK 0x800000u
Kojto 90:cb3d968589d8 5132 #define ENET_EIR_MII_SHIFT 23
Kojto 90:cb3d968589d8 5133 #define ENET_EIR_RXB_MASK 0x1000000u
Kojto 90:cb3d968589d8 5134 #define ENET_EIR_RXB_SHIFT 24
Kojto 90:cb3d968589d8 5135 #define ENET_EIR_RXF_MASK 0x2000000u
Kojto 90:cb3d968589d8 5136 #define ENET_EIR_RXF_SHIFT 25
Kojto 90:cb3d968589d8 5137 #define ENET_EIR_TXB_MASK 0x4000000u
Kojto 90:cb3d968589d8 5138 #define ENET_EIR_TXB_SHIFT 26
Kojto 90:cb3d968589d8 5139 #define ENET_EIR_TXF_MASK 0x8000000u
Kojto 90:cb3d968589d8 5140 #define ENET_EIR_TXF_SHIFT 27
Kojto 90:cb3d968589d8 5141 #define ENET_EIR_GRA_MASK 0x10000000u
Kojto 90:cb3d968589d8 5142 #define ENET_EIR_GRA_SHIFT 28
Kojto 90:cb3d968589d8 5143 #define ENET_EIR_BABT_MASK 0x20000000u
Kojto 90:cb3d968589d8 5144 #define ENET_EIR_BABT_SHIFT 29
Kojto 90:cb3d968589d8 5145 #define ENET_EIR_BABR_MASK 0x40000000u
Kojto 90:cb3d968589d8 5146 #define ENET_EIR_BABR_SHIFT 30
Kojto 90:cb3d968589d8 5147 /* EIMR Bit Fields */
Kojto 90:cb3d968589d8 5148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
Kojto 90:cb3d968589d8 5149 #define ENET_EIMR_TS_TIMER_SHIFT 15
Kojto 90:cb3d968589d8 5150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
Kojto 90:cb3d968589d8 5151 #define ENET_EIMR_TS_AVAIL_SHIFT 16
Kojto 90:cb3d968589d8 5152 #define ENET_EIMR_WAKEUP_MASK 0x20000u
Kojto 90:cb3d968589d8 5153 #define ENET_EIMR_WAKEUP_SHIFT 17
Kojto 90:cb3d968589d8 5154 #define ENET_EIMR_PLR_MASK 0x40000u
Kojto 90:cb3d968589d8 5155 #define ENET_EIMR_PLR_SHIFT 18
Kojto 90:cb3d968589d8 5156 #define ENET_EIMR_UN_MASK 0x80000u
Kojto 90:cb3d968589d8 5157 #define ENET_EIMR_UN_SHIFT 19
Kojto 90:cb3d968589d8 5158 #define ENET_EIMR_RL_MASK 0x100000u
Kojto 90:cb3d968589d8 5159 #define ENET_EIMR_RL_SHIFT 20
Kojto 90:cb3d968589d8 5160 #define ENET_EIMR_LC_MASK 0x200000u
Kojto 90:cb3d968589d8 5161 #define ENET_EIMR_LC_SHIFT 21
Kojto 90:cb3d968589d8 5162 #define ENET_EIMR_EBERR_MASK 0x400000u
Kojto 90:cb3d968589d8 5163 #define ENET_EIMR_EBERR_SHIFT 22
Kojto 90:cb3d968589d8 5164 #define ENET_EIMR_MII_MASK 0x800000u
Kojto 90:cb3d968589d8 5165 #define ENET_EIMR_MII_SHIFT 23
Kojto 90:cb3d968589d8 5166 #define ENET_EIMR_RXB_MASK 0x1000000u
Kojto 90:cb3d968589d8 5167 #define ENET_EIMR_RXB_SHIFT 24
Kojto 90:cb3d968589d8 5168 #define ENET_EIMR_RXF_MASK 0x2000000u
Kojto 90:cb3d968589d8 5169 #define ENET_EIMR_RXF_SHIFT 25
Kojto 90:cb3d968589d8 5170 #define ENET_EIMR_TXB_MASK 0x4000000u
Kojto 90:cb3d968589d8 5171 #define ENET_EIMR_TXB_SHIFT 26
Kojto 90:cb3d968589d8 5172 #define ENET_EIMR_TXF_MASK 0x8000000u
Kojto 90:cb3d968589d8 5173 #define ENET_EIMR_TXF_SHIFT 27
Kojto 90:cb3d968589d8 5174 #define ENET_EIMR_GRA_MASK 0x10000000u
Kojto 90:cb3d968589d8 5175 #define ENET_EIMR_GRA_SHIFT 28
Kojto 90:cb3d968589d8 5176 #define ENET_EIMR_BABT_MASK 0x20000000u
Kojto 90:cb3d968589d8 5177 #define ENET_EIMR_BABT_SHIFT 29
Kojto 90:cb3d968589d8 5178 #define ENET_EIMR_BABR_MASK 0x40000000u
Kojto 90:cb3d968589d8 5179 #define ENET_EIMR_BABR_SHIFT 30
Kojto 90:cb3d968589d8 5180 /* RDAR Bit Fields */
Kojto 90:cb3d968589d8 5181 #define ENET_RDAR_RDAR_MASK 0x1000000u
Kojto 90:cb3d968589d8 5182 #define ENET_RDAR_RDAR_SHIFT 24
Kojto 90:cb3d968589d8 5183 /* TDAR Bit Fields */
Kojto 90:cb3d968589d8 5184 #define ENET_TDAR_TDAR_MASK 0x1000000u
Kojto 90:cb3d968589d8 5185 #define ENET_TDAR_TDAR_SHIFT 24
Kojto 90:cb3d968589d8 5186 /* ECR Bit Fields */
Kojto 90:cb3d968589d8 5187 #define ENET_ECR_RESET_MASK 0x1u
Kojto 90:cb3d968589d8 5188 #define ENET_ECR_RESET_SHIFT 0
Kojto 90:cb3d968589d8 5189 #define ENET_ECR_ETHEREN_MASK 0x2u
Kojto 90:cb3d968589d8 5190 #define ENET_ECR_ETHEREN_SHIFT 1
Kojto 90:cb3d968589d8 5191 #define ENET_ECR_MAGICEN_MASK 0x4u
Kojto 90:cb3d968589d8 5192 #define ENET_ECR_MAGICEN_SHIFT 2
Kojto 90:cb3d968589d8 5193 #define ENET_ECR_SLEEP_MASK 0x8u
Kojto 90:cb3d968589d8 5194 #define ENET_ECR_SLEEP_SHIFT 3
Kojto 90:cb3d968589d8 5195 #define ENET_ECR_EN1588_MASK 0x10u
Kojto 90:cb3d968589d8 5196 #define ENET_ECR_EN1588_SHIFT 4
Kojto 90:cb3d968589d8 5197 #define ENET_ECR_DBGEN_MASK 0x40u
Kojto 90:cb3d968589d8 5198 #define ENET_ECR_DBGEN_SHIFT 6
Kojto 90:cb3d968589d8 5199 #define ENET_ECR_STOPEN_MASK 0x80u
Kojto 90:cb3d968589d8 5200 #define ENET_ECR_STOPEN_SHIFT 7
Kojto 90:cb3d968589d8 5201 #define ENET_ECR_DBSWP_MASK 0x100u
Kojto 90:cb3d968589d8 5202 #define ENET_ECR_DBSWP_SHIFT 8
Kojto 90:cb3d968589d8 5203 /* MMFR Bit Fields */
Kojto 90:cb3d968589d8 5204 #define ENET_MMFR_DATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5205 #define ENET_MMFR_DATA_SHIFT 0
Kojto 90:cb3d968589d8 5206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
Kojto 90:cb3d968589d8 5207 #define ENET_MMFR_TA_MASK 0x30000u
Kojto 90:cb3d968589d8 5208 #define ENET_MMFR_TA_SHIFT 16
Kojto 90:cb3d968589d8 5209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
Kojto 90:cb3d968589d8 5210 #define ENET_MMFR_RA_MASK 0x7C0000u
Kojto 90:cb3d968589d8 5211 #define ENET_MMFR_RA_SHIFT 18
Kojto 90:cb3d968589d8 5212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
Kojto 90:cb3d968589d8 5213 #define ENET_MMFR_PA_MASK 0xF800000u
Kojto 90:cb3d968589d8 5214 #define ENET_MMFR_PA_SHIFT 23
Kojto 90:cb3d968589d8 5215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
Kojto 90:cb3d968589d8 5216 #define ENET_MMFR_OP_MASK 0x30000000u
Kojto 90:cb3d968589d8 5217 #define ENET_MMFR_OP_SHIFT 28
Kojto 90:cb3d968589d8 5218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
Kojto 90:cb3d968589d8 5219 #define ENET_MMFR_ST_MASK 0xC0000000u
Kojto 90:cb3d968589d8 5220 #define ENET_MMFR_ST_SHIFT 30
Kojto 90:cb3d968589d8 5221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
Kojto 90:cb3d968589d8 5222 /* MSCR Bit Fields */
Kojto 90:cb3d968589d8 5223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
Kojto 90:cb3d968589d8 5224 #define ENET_MSCR_MII_SPEED_SHIFT 1
Kojto 90:cb3d968589d8 5225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
Kojto 90:cb3d968589d8 5226 #define ENET_MSCR_DIS_PRE_MASK 0x80u
Kojto 90:cb3d968589d8 5227 #define ENET_MSCR_DIS_PRE_SHIFT 7
Kojto 90:cb3d968589d8 5228 #define ENET_MSCR_HOLDTIME_MASK 0x700u
Kojto 90:cb3d968589d8 5229 #define ENET_MSCR_HOLDTIME_SHIFT 8
Kojto 90:cb3d968589d8 5230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
Kojto 90:cb3d968589d8 5231 /* MIBC Bit Fields */
Kojto 90:cb3d968589d8 5232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
Kojto 90:cb3d968589d8 5233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
Kojto 90:cb3d968589d8 5234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
Kojto 90:cb3d968589d8 5235 #define ENET_MIBC_MIB_IDLE_SHIFT 30
Kojto 90:cb3d968589d8 5236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
Kojto 90:cb3d968589d8 5237 #define ENET_MIBC_MIB_DIS_SHIFT 31
Kojto 90:cb3d968589d8 5238 /* RCR Bit Fields */
Kojto 90:cb3d968589d8 5239 #define ENET_RCR_LOOP_MASK 0x1u
Kojto 90:cb3d968589d8 5240 #define ENET_RCR_LOOP_SHIFT 0
Kojto 90:cb3d968589d8 5241 #define ENET_RCR_DRT_MASK 0x2u
Kojto 90:cb3d968589d8 5242 #define ENET_RCR_DRT_SHIFT 1
Kojto 90:cb3d968589d8 5243 #define ENET_RCR_MII_MODE_MASK 0x4u
Kojto 90:cb3d968589d8 5244 #define ENET_RCR_MII_MODE_SHIFT 2
Kojto 90:cb3d968589d8 5245 #define ENET_RCR_PROM_MASK 0x8u
Kojto 90:cb3d968589d8 5246 #define ENET_RCR_PROM_SHIFT 3
Kojto 90:cb3d968589d8 5247 #define ENET_RCR_BC_REJ_MASK 0x10u
Kojto 90:cb3d968589d8 5248 #define ENET_RCR_BC_REJ_SHIFT 4
Kojto 90:cb3d968589d8 5249 #define ENET_RCR_FCE_MASK 0x20u
Kojto 90:cb3d968589d8 5250 #define ENET_RCR_FCE_SHIFT 5
Kojto 90:cb3d968589d8 5251 #define ENET_RCR_RMII_MODE_MASK 0x100u
Kojto 90:cb3d968589d8 5252 #define ENET_RCR_RMII_MODE_SHIFT 8
Kojto 90:cb3d968589d8 5253 #define ENET_RCR_RMII_10T_MASK 0x200u
Kojto 90:cb3d968589d8 5254 #define ENET_RCR_RMII_10T_SHIFT 9
Kojto 90:cb3d968589d8 5255 #define ENET_RCR_PADEN_MASK 0x1000u
Kojto 90:cb3d968589d8 5256 #define ENET_RCR_PADEN_SHIFT 12
Kojto 90:cb3d968589d8 5257 #define ENET_RCR_PAUFWD_MASK 0x2000u
Kojto 90:cb3d968589d8 5258 #define ENET_RCR_PAUFWD_SHIFT 13
Kojto 90:cb3d968589d8 5259 #define ENET_RCR_CRCFWD_MASK 0x4000u
Kojto 90:cb3d968589d8 5260 #define ENET_RCR_CRCFWD_SHIFT 14
Kojto 90:cb3d968589d8 5261 #define ENET_RCR_CFEN_MASK 0x8000u
Kojto 90:cb3d968589d8 5262 #define ENET_RCR_CFEN_SHIFT 15
Kojto 90:cb3d968589d8 5263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
Kojto 90:cb3d968589d8 5264 #define ENET_RCR_MAX_FL_SHIFT 16
Kojto 90:cb3d968589d8 5265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
Kojto 90:cb3d968589d8 5266 #define ENET_RCR_NLC_MASK 0x40000000u
Kojto 90:cb3d968589d8 5267 #define ENET_RCR_NLC_SHIFT 30
Kojto 90:cb3d968589d8 5268 #define ENET_RCR_GRS_MASK 0x80000000u
Kojto 90:cb3d968589d8 5269 #define ENET_RCR_GRS_SHIFT 31
Kojto 90:cb3d968589d8 5270 /* TCR Bit Fields */
Kojto 90:cb3d968589d8 5271 #define ENET_TCR_GTS_MASK 0x1u
Kojto 90:cb3d968589d8 5272 #define ENET_TCR_GTS_SHIFT 0
Kojto 90:cb3d968589d8 5273 #define ENET_TCR_FDEN_MASK 0x4u
Kojto 90:cb3d968589d8 5274 #define ENET_TCR_FDEN_SHIFT 2
Kojto 90:cb3d968589d8 5275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
Kojto 90:cb3d968589d8 5276 #define ENET_TCR_TFC_PAUSE_SHIFT 3
Kojto 90:cb3d968589d8 5277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
Kojto 90:cb3d968589d8 5278 #define ENET_TCR_RFC_PAUSE_SHIFT 4
Kojto 90:cb3d968589d8 5279 #define ENET_TCR_ADDSEL_MASK 0xE0u
Kojto 90:cb3d968589d8 5280 #define ENET_TCR_ADDSEL_SHIFT 5
Kojto 90:cb3d968589d8 5281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
Kojto 90:cb3d968589d8 5282 #define ENET_TCR_ADDINS_MASK 0x100u
Kojto 90:cb3d968589d8 5283 #define ENET_TCR_ADDINS_SHIFT 8
Kojto 90:cb3d968589d8 5284 #define ENET_TCR_CRCFWD_MASK 0x200u
Kojto 90:cb3d968589d8 5285 #define ENET_TCR_CRCFWD_SHIFT 9
Kojto 90:cb3d968589d8 5286 /* PALR Bit Fields */
Kojto 90:cb3d968589d8 5287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5288 #define ENET_PALR_PADDR1_SHIFT 0
Kojto 90:cb3d968589d8 5289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
Kojto 90:cb3d968589d8 5290 /* PAUR Bit Fields */
Kojto 90:cb3d968589d8 5291 #define ENET_PAUR_TYPE_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5292 #define ENET_PAUR_TYPE_SHIFT 0
Kojto 90:cb3d968589d8 5293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
Kojto 90:cb3d968589d8 5294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5295 #define ENET_PAUR_PADDR2_SHIFT 16
Kojto 90:cb3d968589d8 5296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
Kojto 90:cb3d968589d8 5297 /* OPD Bit Fields */
Kojto 90:cb3d968589d8 5298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5299 #define ENET_OPD_PAUSE_DUR_SHIFT 0
Kojto 90:cb3d968589d8 5300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
Kojto 90:cb3d968589d8 5301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5302 #define ENET_OPD_OPCODE_SHIFT 16
Kojto 90:cb3d968589d8 5303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
Kojto 90:cb3d968589d8 5304 /* IAUR Bit Fields */
Kojto 90:cb3d968589d8 5305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5306 #define ENET_IAUR_IADDR1_SHIFT 0
Kojto 90:cb3d968589d8 5307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
Kojto 90:cb3d968589d8 5308 /* IALR Bit Fields */
Kojto 90:cb3d968589d8 5309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5310 #define ENET_IALR_IADDR2_SHIFT 0
Kojto 90:cb3d968589d8 5311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
Kojto 90:cb3d968589d8 5312 /* GAUR Bit Fields */
Kojto 90:cb3d968589d8 5313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5314 #define ENET_GAUR_GADDR1_SHIFT 0
Kojto 90:cb3d968589d8 5315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
Kojto 90:cb3d968589d8 5316 /* GALR Bit Fields */
Kojto 90:cb3d968589d8 5317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5318 #define ENET_GALR_GADDR2_SHIFT 0
Kojto 90:cb3d968589d8 5319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
Kojto 90:cb3d968589d8 5320 /* TFWR Bit Fields */
Kojto 90:cb3d968589d8 5321 #define ENET_TFWR_TFWR_MASK 0x3Fu
Kojto 90:cb3d968589d8 5322 #define ENET_TFWR_TFWR_SHIFT 0
Kojto 90:cb3d968589d8 5323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
Kojto 90:cb3d968589d8 5324 #define ENET_TFWR_STRFWD_MASK 0x100u
Kojto 90:cb3d968589d8 5325 #define ENET_TFWR_STRFWD_SHIFT 8
Kojto 90:cb3d968589d8 5326 /* RDSR Bit Fields */
Kojto 90:cb3d968589d8 5327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
Kojto 90:cb3d968589d8 5328 #define ENET_RDSR_R_DES_START_SHIFT 3
Kojto 90:cb3d968589d8 5329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
Kojto 90:cb3d968589d8 5330 /* TDSR Bit Fields */
Kojto 90:cb3d968589d8 5331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
Kojto 90:cb3d968589d8 5332 #define ENET_TDSR_X_DES_START_SHIFT 3
Kojto 90:cb3d968589d8 5333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
Kojto 90:cb3d968589d8 5334 /* MRBR Bit Fields */
Kojto 90:cb3d968589d8 5335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
Kojto 90:cb3d968589d8 5336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
Kojto 90:cb3d968589d8 5337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
Kojto 90:cb3d968589d8 5338 /* RSFL Bit Fields */
Kojto 90:cb3d968589d8 5339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
Kojto 90:cb3d968589d8 5340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
Kojto 90:cb3d968589d8 5341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
Kojto 90:cb3d968589d8 5342 /* RSEM Bit Fields */
Kojto 90:cb3d968589d8 5343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
Kojto 90:cb3d968589d8 5344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
Kojto 90:cb3d968589d8 5345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
Kojto 90:cb3d968589d8 5346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
Kojto 90:cb3d968589d8 5347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
Kojto 90:cb3d968589d8 5348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
Kojto 90:cb3d968589d8 5349 /* RAEM Bit Fields */
Kojto 90:cb3d968589d8 5350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
Kojto 90:cb3d968589d8 5351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
Kojto 90:cb3d968589d8 5352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
Kojto 90:cb3d968589d8 5353 /* RAFL Bit Fields */
Kojto 90:cb3d968589d8 5354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
Kojto 90:cb3d968589d8 5355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
Kojto 90:cb3d968589d8 5356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
Kojto 90:cb3d968589d8 5357 /* TSEM Bit Fields */
Kojto 90:cb3d968589d8 5358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
Kojto 90:cb3d968589d8 5359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
Kojto 90:cb3d968589d8 5360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
Kojto 90:cb3d968589d8 5361 /* TAEM Bit Fields */
Kojto 90:cb3d968589d8 5362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
Kojto 90:cb3d968589d8 5363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
Kojto 90:cb3d968589d8 5364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
Kojto 90:cb3d968589d8 5365 /* TAFL Bit Fields */
Kojto 90:cb3d968589d8 5366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
Kojto 90:cb3d968589d8 5367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
Kojto 90:cb3d968589d8 5368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
Kojto 90:cb3d968589d8 5369 /* TIPG Bit Fields */
Kojto 90:cb3d968589d8 5370 #define ENET_TIPG_IPG_MASK 0x1Fu
Kojto 90:cb3d968589d8 5371 #define ENET_TIPG_IPG_SHIFT 0
Kojto 90:cb3d968589d8 5372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
Kojto 90:cb3d968589d8 5373 /* FTRL Bit Fields */
Kojto 90:cb3d968589d8 5374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
Kojto 90:cb3d968589d8 5375 #define ENET_FTRL_TRUNC_FL_SHIFT 0
Kojto 90:cb3d968589d8 5376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
Kojto 90:cb3d968589d8 5377 /* TACC Bit Fields */
Kojto 90:cb3d968589d8 5378 #define ENET_TACC_SHIFT16_MASK 0x1u
Kojto 90:cb3d968589d8 5379 #define ENET_TACC_SHIFT16_SHIFT 0
Kojto 90:cb3d968589d8 5380 #define ENET_TACC_IPCHK_MASK 0x8u
Kojto 90:cb3d968589d8 5381 #define ENET_TACC_IPCHK_SHIFT 3
Kojto 90:cb3d968589d8 5382 #define ENET_TACC_PROCHK_MASK 0x10u
Kojto 90:cb3d968589d8 5383 #define ENET_TACC_PROCHK_SHIFT 4
Kojto 90:cb3d968589d8 5384 /* RACC Bit Fields */
Kojto 90:cb3d968589d8 5385 #define ENET_RACC_PADREM_MASK 0x1u
Kojto 90:cb3d968589d8 5386 #define ENET_RACC_PADREM_SHIFT 0
Kojto 90:cb3d968589d8 5387 #define ENET_RACC_IPDIS_MASK 0x2u
Kojto 90:cb3d968589d8 5388 #define ENET_RACC_IPDIS_SHIFT 1
Kojto 90:cb3d968589d8 5389 #define ENET_RACC_PRODIS_MASK 0x4u
Kojto 90:cb3d968589d8 5390 #define ENET_RACC_PRODIS_SHIFT 2
Kojto 90:cb3d968589d8 5391 #define ENET_RACC_LINEDIS_MASK 0x40u
Kojto 90:cb3d968589d8 5392 #define ENET_RACC_LINEDIS_SHIFT 6
Kojto 90:cb3d968589d8 5393 #define ENET_RACC_SHIFT16_MASK 0x80u
Kojto 90:cb3d968589d8 5394 #define ENET_RACC_SHIFT16_SHIFT 7
Kojto 90:cb3d968589d8 5395 /* RMON_T_PACKETS Bit Fields */
Kojto 90:cb3d968589d8 5396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5399 /* RMON_T_BC_PKT Bit Fields */
Kojto 90:cb3d968589d8 5400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5403 /* RMON_T_MC_PKT Bit Fields */
Kojto 90:cb3d968589d8 5404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5407 /* RMON_T_CRC_ALIGN Bit Fields */
Kojto 90:cb3d968589d8 5408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5411 /* RMON_T_UNDERSIZE Bit Fields */
Kojto 90:cb3d968589d8 5412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5415 /* RMON_T_OVERSIZE Bit Fields */
Kojto 90:cb3d968589d8 5416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5419 /* RMON_T_FRAG Bit Fields */
Kojto 90:cb3d968589d8 5420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5423 /* RMON_T_JAB Bit Fields */
Kojto 90:cb3d968589d8 5424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5427 /* RMON_T_COL Bit Fields */
Kojto 90:cb3d968589d8 5428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5431 /* RMON_T_P64 Bit Fields */
Kojto 90:cb3d968589d8 5432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5435 /* RMON_T_P65TO127 Bit Fields */
Kojto 90:cb3d968589d8 5436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5439 /* RMON_T_P128TO255 Bit Fields */
Kojto 90:cb3d968589d8 5440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5443 /* RMON_T_P256TO511 Bit Fields */
Kojto 90:cb3d968589d8 5444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5447 /* RMON_T_P512TO1023 Bit Fields */
Kojto 90:cb3d968589d8 5448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5451 /* RMON_T_P1024TO2047 Bit Fields */
Kojto 90:cb3d968589d8 5452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5455 /* RMON_T_P_GTE2048 Bit Fields */
Kojto 90:cb3d968589d8 5456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
Kojto 90:cb3d968589d8 5458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
Kojto 90:cb3d968589d8 5459 /* RMON_T_OCTETS Bit Fields */
Kojto 90:cb3d968589d8 5460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
Kojto 90:cb3d968589d8 5462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
Kojto 90:cb3d968589d8 5463 /* IEEE_T_FRAME_OK Bit Fields */
Kojto 90:cb3d968589d8 5464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
Kojto 90:cb3d968589d8 5467 /* IEEE_T_1COL Bit Fields */
Kojto 90:cb3d968589d8 5468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
Kojto 90:cb3d968589d8 5471 /* IEEE_T_MCOL Bit Fields */
Kojto 90:cb3d968589d8 5472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
Kojto 90:cb3d968589d8 5475 /* IEEE_T_DEF Bit Fields */
Kojto 90:cb3d968589d8 5476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
Kojto 90:cb3d968589d8 5479 /* IEEE_T_LCOL Bit Fields */
Kojto 90:cb3d968589d8 5480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
Kojto 90:cb3d968589d8 5483 /* IEEE_T_EXCOL Bit Fields */
Kojto 90:cb3d968589d8 5484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
Kojto 90:cb3d968589d8 5487 /* IEEE_T_MACERR Bit Fields */
Kojto 90:cb3d968589d8 5488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
Kojto 90:cb3d968589d8 5491 /* IEEE_T_CSERR Bit Fields */
Kojto 90:cb3d968589d8 5492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
Kojto 90:cb3d968589d8 5495 /* IEEE_T_FDXFC Bit Fields */
Kojto 90:cb3d968589d8 5496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
Kojto 90:cb3d968589d8 5499 /* IEEE_T_OCTETS_OK Bit Fields */
Kojto 90:cb3d968589d8 5500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
Kojto 90:cb3d968589d8 5503 /* RMON_R_PACKETS Bit Fields */
Kojto 90:cb3d968589d8 5504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
Kojto 90:cb3d968589d8 5507 /* RMON_R_BC_PKT Bit Fields */
Kojto 90:cb3d968589d8 5508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
Kojto 90:cb3d968589d8 5511 /* RMON_R_MC_PKT Bit Fields */
Kojto 90:cb3d968589d8 5512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
Kojto 90:cb3d968589d8 5515 /* RMON_R_CRC_ALIGN Bit Fields */
Kojto 90:cb3d968589d8 5516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
Kojto 90:cb3d968589d8 5519 /* RMON_R_UNDERSIZE Bit Fields */
Kojto 90:cb3d968589d8 5520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
Kojto 90:cb3d968589d8 5523 /* RMON_R_OVERSIZE Bit Fields */
Kojto 90:cb3d968589d8 5524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
Kojto 90:cb3d968589d8 5527 /* RMON_R_FRAG Bit Fields */
Kojto 90:cb3d968589d8 5528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
Kojto 90:cb3d968589d8 5531 /* RMON_R_JAB Bit Fields */
Kojto 90:cb3d968589d8 5532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
Kojto 90:cb3d968589d8 5535 /* RMON_R_P64 Bit Fields */
Kojto 90:cb3d968589d8 5536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5537 #define ENET_RMON_R_P64_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
Kojto 90:cb3d968589d8 5539 /* RMON_R_P65TO127 Bit Fields */
Kojto 90:cb3d968589d8 5540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
Kojto 90:cb3d968589d8 5543 /* RMON_R_P128TO255 Bit Fields */
Kojto 90:cb3d968589d8 5544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
Kojto 90:cb3d968589d8 5547 /* RMON_R_P256TO511 Bit Fields */
Kojto 90:cb3d968589d8 5548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
Kojto 90:cb3d968589d8 5551 /* RMON_R_P512TO1023 Bit Fields */
Kojto 90:cb3d968589d8 5552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
Kojto 90:cb3d968589d8 5555 /* RMON_R_P1024TO2047 Bit Fields */
Kojto 90:cb3d968589d8 5556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
Kojto 90:cb3d968589d8 5559 /* RMON_R_P_GTE2048 Bit Fields */
Kojto 90:cb3d968589d8 5560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
Kojto 90:cb3d968589d8 5563 /* RMON_R_OCTETS Bit Fields */
Kojto 90:cb3d968589d8 5564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
Kojto 90:cb3d968589d8 5567 /* IEEE_R_DROP Bit Fields */
Kojto 90:cb3d968589d8 5568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
Kojto 90:cb3d968589d8 5571 /* IEEE_R_FRAME_OK Bit Fields */
Kojto 90:cb3d968589d8 5572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
Kojto 90:cb3d968589d8 5575 /* IEEE_R_CRC Bit Fields */
Kojto 90:cb3d968589d8 5576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
Kojto 90:cb3d968589d8 5579 /* IEEE_R_ALIGN Bit Fields */
Kojto 90:cb3d968589d8 5580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
Kojto 90:cb3d968589d8 5583 /* IEEE_R_MACERR Bit Fields */
Kojto 90:cb3d968589d8 5584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
Kojto 90:cb3d968589d8 5587 /* IEEE_R_FDXFC Bit Fields */
Kojto 90:cb3d968589d8 5588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
Kojto 90:cb3d968589d8 5591 /* IEEE_R_OCTETS_OK Bit Fields */
Kojto 90:cb3d968589d8 5592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 5594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
Kojto 90:cb3d968589d8 5595 /* ATCR Bit Fields */
Kojto 90:cb3d968589d8 5596 #define ENET_ATCR_EN_MASK 0x1u
Kojto 90:cb3d968589d8 5597 #define ENET_ATCR_EN_SHIFT 0
Kojto 90:cb3d968589d8 5598 #define ENET_ATCR_OFFEN_MASK 0x4u
Kojto 90:cb3d968589d8 5599 #define ENET_ATCR_OFFEN_SHIFT 2
Kojto 90:cb3d968589d8 5600 #define ENET_ATCR_OFFRST_MASK 0x8u
Kojto 90:cb3d968589d8 5601 #define ENET_ATCR_OFFRST_SHIFT 3
Kojto 90:cb3d968589d8 5602 #define ENET_ATCR_PEREN_MASK 0x10u
Kojto 90:cb3d968589d8 5603 #define ENET_ATCR_PEREN_SHIFT 4
Kojto 90:cb3d968589d8 5604 #define ENET_ATCR_PINPER_MASK 0x80u
Kojto 90:cb3d968589d8 5605 #define ENET_ATCR_PINPER_SHIFT 7
Kojto 90:cb3d968589d8 5606 #define ENET_ATCR_RESTART_MASK 0x200u
Kojto 90:cb3d968589d8 5607 #define ENET_ATCR_RESTART_SHIFT 9
Kojto 90:cb3d968589d8 5608 #define ENET_ATCR_CAPTURE_MASK 0x800u
Kojto 90:cb3d968589d8 5609 #define ENET_ATCR_CAPTURE_SHIFT 11
Kojto 90:cb3d968589d8 5610 #define ENET_ATCR_SLAVE_MASK 0x2000u
Kojto 90:cb3d968589d8 5611 #define ENET_ATCR_SLAVE_SHIFT 13
Kojto 90:cb3d968589d8 5612 /* ATVR Bit Fields */
Kojto 90:cb3d968589d8 5613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5614 #define ENET_ATVR_ATIME_SHIFT 0
Kojto 90:cb3d968589d8 5615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
Kojto 90:cb3d968589d8 5616 /* ATOFF Bit Fields */
Kojto 90:cb3d968589d8 5617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5618 #define ENET_ATOFF_OFFSET_SHIFT 0
Kojto 90:cb3d968589d8 5619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
Kojto 90:cb3d968589d8 5620 /* ATPER Bit Fields */
Kojto 90:cb3d968589d8 5621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5622 #define ENET_ATPER_PERIOD_SHIFT 0
Kojto 90:cb3d968589d8 5623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
Kojto 90:cb3d968589d8 5624 /* ATCOR Bit Fields */
Kojto 90:cb3d968589d8 5625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
Kojto 90:cb3d968589d8 5626 #define ENET_ATCOR_COR_SHIFT 0
Kojto 90:cb3d968589d8 5627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
Kojto 90:cb3d968589d8 5628 /* ATINC Bit Fields */
Kojto 90:cb3d968589d8 5629 #define ENET_ATINC_INC_MASK 0x7Fu
Kojto 90:cb3d968589d8 5630 #define ENET_ATINC_INC_SHIFT 0
Kojto 90:cb3d968589d8 5631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
Kojto 90:cb3d968589d8 5632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
Kojto 90:cb3d968589d8 5633 #define ENET_ATINC_INC_CORR_SHIFT 8
Kojto 90:cb3d968589d8 5634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
Kojto 90:cb3d968589d8 5635 /* ATSTMP Bit Fields */
Kojto 90:cb3d968589d8 5636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
Kojto 90:cb3d968589d8 5638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
Kojto 90:cb3d968589d8 5639 /* TGSR Bit Fields */
Kojto 90:cb3d968589d8 5640 #define ENET_TGSR_TF0_MASK 0x1u
Kojto 90:cb3d968589d8 5641 #define ENET_TGSR_TF0_SHIFT 0
Kojto 90:cb3d968589d8 5642 #define ENET_TGSR_TF1_MASK 0x2u
Kojto 90:cb3d968589d8 5643 #define ENET_TGSR_TF1_SHIFT 1
Kojto 90:cb3d968589d8 5644 #define ENET_TGSR_TF2_MASK 0x4u
Kojto 90:cb3d968589d8 5645 #define ENET_TGSR_TF2_SHIFT 2
Kojto 90:cb3d968589d8 5646 #define ENET_TGSR_TF3_MASK 0x8u
Kojto 90:cb3d968589d8 5647 #define ENET_TGSR_TF3_SHIFT 3
Kojto 90:cb3d968589d8 5648 /* TCSR Bit Fields */
Kojto 90:cb3d968589d8 5649 #define ENET_TCSR_TDRE_MASK 0x1u
Kojto 90:cb3d968589d8 5650 #define ENET_TCSR_TDRE_SHIFT 0
Kojto 90:cb3d968589d8 5651 #define ENET_TCSR_TMODE_MASK 0x3Cu
Kojto 90:cb3d968589d8 5652 #define ENET_TCSR_TMODE_SHIFT 2
Kojto 90:cb3d968589d8 5653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
Kojto 90:cb3d968589d8 5654 #define ENET_TCSR_TIE_MASK 0x40u
Kojto 90:cb3d968589d8 5655 #define ENET_TCSR_TIE_SHIFT 6
Kojto 90:cb3d968589d8 5656 #define ENET_TCSR_TF_MASK 0x80u
Kojto 90:cb3d968589d8 5657 #define ENET_TCSR_TF_SHIFT 7
Kojto 90:cb3d968589d8 5658 /* TCCR Bit Fields */
Kojto 90:cb3d968589d8 5659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5660 #define ENET_TCCR_TCC_SHIFT 0
Kojto 90:cb3d968589d8 5661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
Kojto 90:cb3d968589d8 5662
Kojto 90:cb3d968589d8 5663 /*!
Kojto 90:cb3d968589d8 5664 * @}
Kojto 90:cb3d968589d8 5665 */ /* end of group ENET_Register_Masks */
Kojto 90:cb3d968589d8 5666
Kojto 90:cb3d968589d8 5667
Kojto 90:cb3d968589d8 5668 /* ENET - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5669 /** Peripheral ENET base address */
Kojto 90:cb3d968589d8 5670 #define ENET_BASE (0x400C0000u)
Kojto 90:cb3d968589d8 5671 /** Peripheral ENET base pointer */
Kojto 90:cb3d968589d8 5672 #define ENET ((ENET_Type *)ENET_BASE)
Kojto 90:cb3d968589d8 5673 #define ENET_BASE_PTR (ENET)
Kojto 90:cb3d968589d8 5674 /** Array initializer of ENET peripheral base addresses */
Kojto 90:cb3d968589d8 5675 #define ENET_BASE_ADDRS { ENET_BASE }
Kojto 90:cb3d968589d8 5676 /** Array initializer of ENET peripheral base pointers */
Kojto 90:cb3d968589d8 5677 #define ENET_BASE_PTRS { ENET }
Kojto 90:cb3d968589d8 5678 /** Interrupt vectors for the ENET peripheral type */
Kojto 90:cb3d968589d8 5679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
Kojto 90:cb3d968589d8 5680 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
Kojto 90:cb3d968589d8 5681 #define ENET_Error_IRQS { ENET_Error_IRQn }
Kojto 90:cb3d968589d8 5682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
Kojto 90:cb3d968589d8 5683
Kojto 90:cb3d968589d8 5684 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5685 -- ENET - Register accessor macros
Kojto 90:cb3d968589d8 5686 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5687
Kojto 90:cb3d968589d8 5688 /*!
Kojto 90:cb3d968589d8 5689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
Kojto 90:cb3d968589d8 5690 * @{
Kojto 90:cb3d968589d8 5691 */
Kojto 90:cb3d968589d8 5692
Kojto 90:cb3d968589d8 5693
Kojto 90:cb3d968589d8 5694 /* ENET - Register instance definitions */
Kojto 90:cb3d968589d8 5695 /* ENET */
Kojto 90:cb3d968589d8 5696 #define ENET_EIR ENET_EIR_REG(ENET)
Kojto 90:cb3d968589d8 5697 #define ENET_EIMR ENET_EIMR_REG(ENET)
Kojto 90:cb3d968589d8 5698 #define ENET_RDAR ENET_RDAR_REG(ENET)
Kojto 90:cb3d968589d8 5699 #define ENET_TDAR ENET_TDAR_REG(ENET)
Kojto 90:cb3d968589d8 5700 #define ENET_ECR ENET_ECR_REG(ENET)
Kojto 90:cb3d968589d8 5701 #define ENET_MMFR ENET_MMFR_REG(ENET)
Kojto 90:cb3d968589d8 5702 #define ENET_MSCR ENET_MSCR_REG(ENET)
Kojto 90:cb3d968589d8 5703 #define ENET_MIBC ENET_MIBC_REG(ENET)
Kojto 90:cb3d968589d8 5704 #define ENET_RCR ENET_RCR_REG(ENET)
Kojto 90:cb3d968589d8 5705 #define ENET_TCR ENET_TCR_REG(ENET)
Kojto 90:cb3d968589d8 5706 #define ENET_PALR ENET_PALR_REG(ENET)
Kojto 90:cb3d968589d8 5707 #define ENET_PAUR ENET_PAUR_REG(ENET)
Kojto 90:cb3d968589d8 5708 #define ENET_OPD ENET_OPD_REG(ENET)
Kojto 90:cb3d968589d8 5709 #define ENET_IAUR ENET_IAUR_REG(ENET)
Kojto 90:cb3d968589d8 5710 #define ENET_IALR ENET_IALR_REG(ENET)
Kojto 90:cb3d968589d8 5711 #define ENET_GAUR ENET_GAUR_REG(ENET)
Kojto 90:cb3d968589d8 5712 #define ENET_GALR ENET_GALR_REG(ENET)
Kojto 90:cb3d968589d8 5713 #define ENET_TFWR ENET_TFWR_REG(ENET)
Kojto 90:cb3d968589d8 5714 #define ENET_RDSR ENET_RDSR_REG(ENET)
Kojto 90:cb3d968589d8 5715 #define ENET_TDSR ENET_TDSR_REG(ENET)
Kojto 90:cb3d968589d8 5716 #define ENET_MRBR ENET_MRBR_REG(ENET)
Kojto 90:cb3d968589d8 5717 #define ENET_RSFL ENET_RSFL_REG(ENET)
Kojto 90:cb3d968589d8 5718 #define ENET_RSEM ENET_RSEM_REG(ENET)
Kojto 90:cb3d968589d8 5719 #define ENET_RAEM ENET_RAEM_REG(ENET)
Kojto 90:cb3d968589d8 5720 #define ENET_RAFL ENET_RAFL_REG(ENET)
Kojto 90:cb3d968589d8 5721 #define ENET_TSEM ENET_TSEM_REG(ENET)
Kojto 90:cb3d968589d8 5722 #define ENET_TAEM ENET_TAEM_REG(ENET)
Kojto 90:cb3d968589d8 5723 #define ENET_TAFL ENET_TAFL_REG(ENET)
Kojto 90:cb3d968589d8 5724 #define ENET_TIPG ENET_TIPG_REG(ENET)
Kojto 90:cb3d968589d8 5725 #define ENET_FTRL ENET_FTRL_REG(ENET)
Kojto 90:cb3d968589d8 5726 #define ENET_TACC ENET_TACC_REG(ENET)
Kojto 90:cb3d968589d8 5727 #define ENET_RACC ENET_RACC_REG(ENET)
Kojto 90:cb3d968589d8 5728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
Kojto 90:cb3d968589d8 5729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
Kojto 90:cb3d968589d8 5730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
Kojto 90:cb3d968589d8 5731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
Kojto 90:cb3d968589d8 5732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
Kojto 90:cb3d968589d8 5733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
Kojto 90:cb3d968589d8 5734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
Kojto 90:cb3d968589d8 5735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
Kojto 90:cb3d968589d8 5736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
Kojto 90:cb3d968589d8 5737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
Kojto 90:cb3d968589d8 5738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
Kojto 90:cb3d968589d8 5739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
Kojto 90:cb3d968589d8 5740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
Kojto 90:cb3d968589d8 5741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
Kojto 90:cb3d968589d8 5742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
Kojto 90:cb3d968589d8 5743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
Kojto 90:cb3d968589d8 5744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
Kojto 90:cb3d968589d8 5745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
Kojto 90:cb3d968589d8 5746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
Kojto 90:cb3d968589d8 5747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
Kojto 90:cb3d968589d8 5748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
Kojto 90:cb3d968589d8 5749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
Kojto 90:cb3d968589d8 5750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
Kojto 90:cb3d968589d8 5751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
Kojto 90:cb3d968589d8 5752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
Kojto 90:cb3d968589d8 5753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
Kojto 90:cb3d968589d8 5754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
Kojto 90:cb3d968589d8 5755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
Kojto 90:cb3d968589d8 5756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
Kojto 90:cb3d968589d8 5757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
Kojto 90:cb3d968589d8 5758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
Kojto 90:cb3d968589d8 5759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
Kojto 90:cb3d968589d8 5760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
Kojto 90:cb3d968589d8 5761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
Kojto 90:cb3d968589d8 5762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
Kojto 90:cb3d968589d8 5763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
Kojto 90:cb3d968589d8 5764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
Kojto 90:cb3d968589d8 5765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
Kojto 90:cb3d968589d8 5766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
Kojto 90:cb3d968589d8 5767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
Kojto 90:cb3d968589d8 5768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
Kojto 90:cb3d968589d8 5769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
Kojto 90:cb3d968589d8 5770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
Kojto 90:cb3d968589d8 5771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
Kojto 90:cb3d968589d8 5772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
Kojto 90:cb3d968589d8 5773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
Kojto 90:cb3d968589d8 5774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
Kojto 90:cb3d968589d8 5775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
Kojto 90:cb3d968589d8 5776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
Kojto 90:cb3d968589d8 5777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
Kojto 90:cb3d968589d8 5778 #define ENET_ATCR ENET_ATCR_REG(ENET)
Kojto 90:cb3d968589d8 5779 #define ENET_ATVR ENET_ATVR_REG(ENET)
Kojto 90:cb3d968589d8 5780 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
Kojto 90:cb3d968589d8 5781 #define ENET_ATPER ENET_ATPER_REG(ENET)
Kojto 90:cb3d968589d8 5782 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
Kojto 90:cb3d968589d8 5783 #define ENET_ATINC ENET_ATINC_REG(ENET)
Kojto 90:cb3d968589d8 5784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
Kojto 90:cb3d968589d8 5785 #define ENET_TGSR ENET_TGSR_REG(ENET)
Kojto 90:cb3d968589d8 5786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
Kojto 90:cb3d968589d8 5787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
Kojto 90:cb3d968589d8 5788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
Kojto 90:cb3d968589d8 5789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
Kojto 90:cb3d968589d8 5790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
Kojto 90:cb3d968589d8 5791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
Kojto 90:cb3d968589d8 5792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
Kojto 90:cb3d968589d8 5793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
Kojto 90:cb3d968589d8 5794
Kojto 90:cb3d968589d8 5795 /* ENET - Register array accessors */
Kojto 90:cb3d968589d8 5796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
Kojto 90:cb3d968589d8 5797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
Kojto 90:cb3d968589d8 5798
Kojto 90:cb3d968589d8 5799 /*!
Kojto 90:cb3d968589d8 5800 * @}
Kojto 90:cb3d968589d8 5801 */ /* end of group ENET_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5802
Kojto 90:cb3d968589d8 5803
Kojto 90:cb3d968589d8 5804 /*!
Kojto 90:cb3d968589d8 5805 * @}
Kojto 90:cb3d968589d8 5806 */ /* end of group ENET_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5807
Kojto 90:cb3d968589d8 5808
Kojto 90:cb3d968589d8 5809 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5810 -- EWM Peripheral Access Layer
Kojto 90:cb3d968589d8 5811 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5812
Kojto 90:cb3d968589d8 5813 /*!
Kojto 90:cb3d968589d8 5814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
Kojto 90:cb3d968589d8 5815 * @{
Kojto 90:cb3d968589d8 5816 */
Kojto 90:cb3d968589d8 5817
Kojto 90:cb3d968589d8 5818 /** EWM - Register Layout Typedef */
Kojto 90:cb3d968589d8 5819 typedef struct {
Kojto 90:cb3d968589d8 5820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 5821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
Kojto 90:cb3d968589d8 5822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
Kojto 90:cb3d968589d8 5823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
Kojto 90:cb3d968589d8 5824 } EWM_Type, *EWM_MemMapPtr;
Kojto 90:cb3d968589d8 5825
Kojto 90:cb3d968589d8 5826 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5827 -- EWM - Register accessor macros
Kojto 90:cb3d968589d8 5828 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5829
Kojto 90:cb3d968589d8 5830 /*!
Kojto 90:cb3d968589d8 5831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
Kojto 90:cb3d968589d8 5832 * @{
Kojto 90:cb3d968589d8 5833 */
Kojto 90:cb3d968589d8 5834
Kojto 90:cb3d968589d8 5835
Kojto 90:cb3d968589d8 5836 /* EWM - Register accessors */
Kojto 90:cb3d968589d8 5837 #define EWM_CTRL_REG(base) ((base)->CTRL)
Kojto 90:cb3d968589d8 5838 #define EWM_SERV_REG(base) ((base)->SERV)
Kojto 90:cb3d968589d8 5839 #define EWM_CMPL_REG(base) ((base)->CMPL)
Kojto 90:cb3d968589d8 5840 #define EWM_CMPH_REG(base) ((base)->CMPH)
Kojto 90:cb3d968589d8 5841
Kojto 90:cb3d968589d8 5842 /*!
Kojto 90:cb3d968589d8 5843 * @}
Kojto 90:cb3d968589d8 5844 */ /* end of group EWM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5845
Kojto 90:cb3d968589d8 5846
Kojto 90:cb3d968589d8 5847 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5848 -- EWM Register Masks
Kojto 90:cb3d968589d8 5849 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5850
Kojto 90:cb3d968589d8 5851 /*!
Kojto 90:cb3d968589d8 5852 * @addtogroup EWM_Register_Masks EWM Register Masks
Kojto 90:cb3d968589d8 5853 * @{
Kojto 90:cb3d968589d8 5854 */
Kojto 90:cb3d968589d8 5855
Kojto 90:cb3d968589d8 5856 /* CTRL Bit Fields */
Kojto 90:cb3d968589d8 5857 #define EWM_CTRL_EWMEN_MASK 0x1u
Kojto 90:cb3d968589d8 5858 #define EWM_CTRL_EWMEN_SHIFT 0
Kojto 90:cb3d968589d8 5859 #define EWM_CTRL_ASSIN_MASK 0x2u
Kojto 90:cb3d968589d8 5860 #define EWM_CTRL_ASSIN_SHIFT 1
Kojto 90:cb3d968589d8 5861 #define EWM_CTRL_INEN_MASK 0x4u
Kojto 90:cb3d968589d8 5862 #define EWM_CTRL_INEN_SHIFT 2
Kojto 90:cb3d968589d8 5863 #define EWM_CTRL_INTEN_MASK 0x8u
Kojto 90:cb3d968589d8 5864 #define EWM_CTRL_INTEN_SHIFT 3
Kojto 90:cb3d968589d8 5865 /* SERV Bit Fields */
Kojto 90:cb3d968589d8 5866 #define EWM_SERV_SERVICE_MASK 0xFFu
Kojto 90:cb3d968589d8 5867 #define EWM_SERV_SERVICE_SHIFT 0
Kojto 90:cb3d968589d8 5868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
Kojto 90:cb3d968589d8 5869 /* CMPL Bit Fields */
Kojto 90:cb3d968589d8 5870 #define EWM_CMPL_COMPAREL_MASK 0xFFu
Kojto 90:cb3d968589d8 5871 #define EWM_CMPL_COMPAREL_SHIFT 0
Kojto 90:cb3d968589d8 5872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
Kojto 90:cb3d968589d8 5873 /* CMPH Bit Fields */
Kojto 90:cb3d968589d8 5874 #define EWM_CMPH_COMPAREH_MASK 0xFFu
Kojto 90:cb3d968589d8 5875 #define EWM_CMPH_COMPAREH_SHIFT 0
Kojto 90:cb3d968589d8 5876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
Kojto 90:cb3d968589d8 5877
Kojto 90:cb3d968589d8 5878 /*!
Kojto 90:cb3d968589d8 5879 * @}
Kojto 90:cb3d968589d8 5880 */ /* end of group EWM_Register_Masks */
Kojto 90:cb3d968589d8 5881
Kojto 90:cb3d968589d8 5882
Kojto 90:cb3d968589d8 5883 /* EWM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5884 /** Peripheral EWM base address */
Kojto 90:cb3d968589d8 5885 #define EWM_BASE (0x40061000u)
Kojto 90:cb3d968589d8 5886 /** Peripheral EWM base pointer */
Kojto 90:cb3d968589d8 5887 #define EWM ((EWM_Type *)EWM_BASE)
Kojto 90:cb3d968589d8 5888 #define EWM_BASE_PTR (EWM)
Kojto 90:cb3d968589d8 5889 /** Array initializer of EWM peripheral base addresses */
Kojto 90:cb3d968589d8 5890 #define EWM_BASE_ADDRS { EWM_BASE }
Kojto 90:cb3d968589d8 5891 /** Array initializer of EWM peripheral base pointers */
Kojto 90:cb3d968589d8 5892 #define EWM_BASE_PTRS { EWM }
Kojto 90:cb3d968589d8 5893 /** Interrupt vectors for the EWM peripheral type */
Kojto 90:cb3d968589d8 5894 #define EWM_IRQS { Watchdog_IRQn }
Kojto 90:cb3d968589d8 5895
Kojto 90:cb3d968589d8 5896 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5897 -- EWM - Register accessor macros
Kojto 90:cb3d968589d8 5898 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5899
Kojto 90:cb3d968589d8 5900 /*!
Kojto 90:cb3d968589d8 5901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
Kojto 90:cb3d968589d8 5902 * @{
Kojto 90:cb3d968589d8 5903 */
Kojto 90:cb3d968589d8 5904
Kojto 90:cb3d968589d8 5905
Kojto 90:cb3d968589d8 5906 /* EWM - Register instance definitions */
Kojto 90:cb3d968589d8 5907 /* EWM */
Kojto 90:cb3d968589d8 5908 #define EWM_CTRL EWM_CTRL_REG(EWM)
Kojto 90:cb3d968589d8 5909 #define EWM_SERV EWM_SERV_REG(EWM)
Kojto 90:cb3d968589d8 5910 #define EWM_CMPL EWM_CMPL_REG(EWM)
Kojto 90:cb3d968589d8 5911 #define EWM_CMPH EWM_CMPH_REG(EWM)
Kojto 90:cb3d968589d8 5912
Kojto 90:cb3d968589d8 5913 /*!
Kojto 90:cb3d968589d8 5914 * @}
Kojto 90:cb3d968589d8 5915 */ /* end of group EWM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5916
Kojto 90:cb3d968589d8 5917
Kojto 90:cb3d968589d8 5918 /*!
Kojto 90:cb3d968589d8 5919 * @}
Kojto 90:cb3d968589d8 5920 */ /* end of group EWM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5921
Kojto 90:cb3d968589d8 5922
Kojto 90:cb3d968589d8 5923 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5924 -- FB Peripheral Access Layer
Kojto 90:cb3d968589d8 5925 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5926
Kojto 90:cb3d968589d8 5927 /*!
Kojto 90:cb3d968589d8 5928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
Kojto 90:cb3d968589d8 5929 * @{
Kojto 90:cb3d968589d8 5930 */
Kojto 90:cb3d968589d8 5931
Kojto 90:cb3d968589d8 5932 /** FB - Register Layout Typedef */
Kojto 90:cb3d968589d8 5933 typedef struct {
Kojto 90:cb3d968589d8 5934 struct { /* offset: 0x0, array step: 0xC */
Kojto 90:cb3d968589d8 5935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
Kojto 90:cb3d968589d8 5936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
Kojto 90:cb3d968589d8 5937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
Kojto 90:cb3d968589d8 5938 } CS[6];
Kojto 90:cb3d968589d8 5939 uint8_t RESERVED_0[24];
Kojto 90:cb3d968589d8 5940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
Kojto 90:cb3d968589d8 5941 } FB_Type, *FB_MemMapPtr;
Kojto 90:cb3d968589d8 5942
Kojto 90:cb3d968589d8 5943 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5944 -- FB - Register accessor macros
Kojto 90:cb3d968589d8 5945 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5946
Kojto 90:cb3d968589d8 5947 /*!
Kojto 90:cb3d968589d8 5948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
Kojto 90:cb3d968589d8 5949 * @{
Kojto 90:cb3d968589d8 5950 */
Kojto 90:cb3d968589d8 5951
Kojto 90:cb3d968589d8 5952
Kojto 90:cb3d968589d8 5953 /* FB - Register accessors */
Kojto 90:cb3d968589d8 5954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
Kojto 90:cb3d968589d8 5955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
Kojto 90:cb3d968589d8 5956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
Kojto 90:cb3d968589d8 5957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
Kojto 90:cb3d968589d8 5958
Kojto 90:cb3d968589d8 5959 /*!
Kojto 90:cb3d968589d8 5960 * @}
Kojto 90:cb3d968589d8 5961 */ /* end of group FB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5962
Kojto 90:cb3d968589d8 5963
Kojto 90:cb3d968589d8 5964 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5965 -- FB Register Masks
Kojto 90:cb3d968589d8 5966 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5967
Kojto 90:cb3d968589d8 5968 /*!
Kojto 90:cb3d968589d8 5969 * @addtogroup FB_Register_Masks FB Register Masks
Kojto 90:cb3d968589d8 5970 * @{
Kojto 90:cb3d968589d8 5971 */
Kojto 90:cb3d968589d8 5972
Kojto 90:cb3d968589d8 5973 /* CSAR Bit Fields */
Kojto 90:cb3d968589d8 5974 #define FB_CSAR_BA_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5975 #define FB_CSAR_BA_SHIFT 16
Kojto 90:cb3d968589d8 5976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
Kojto 90:cb3d968589d8 5977 /* CSMR Bit Fields */
Kojto 90:cb3d968589d8 5978 #define FB_CSMR_V_MASK 0x1u
Kojto 90:cb3d968589d8 5979 #define FB_CSMR_V_SHIFT 0
Kojto 90:cb3d968589d8 5980 #define FB_CSMR_WP_MASK 0x100u
Kojto 90:cb3d968589d8 5981 #define FB_CSMR_WP_SHIFT 8
Kojto 90:cb3d968589d8 5982 #define FB_CSMR_BAM_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5983 #define FB_CSMR_BAM_SHIFT 16
Kojto 90:cb3d968589d8 5984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
Kojto 90:cb3d968589d8 5985 /* CSCR Bit Fields */
Kojto 90:cb3d968589d8 5986 #define FB_CSCR_BSTW_MASK 0x8u
Kojto 90:cb3d968589d8 5987 #define FB_CSCR_BSTW_SHIFT 3
Kojto 90:cb3d968589d8 5988 #define FB_CSCR_BSTR_MASK 0x10u
Kojto 90:cb3d968589d8 5989 #define FB_CSCR_BSTR_SHIFT 4
Kojto 90:cb3d968589d8 5990 #define FB_CSCR_BEM_MASK 0x20u
Kojto 90:cb3d968589d8 5991 #define FB_CSCR_BEM_SHIFT 5
Kojto 90:cb3d968589d8 5992 #define FB_CSCR_PS_MASK 0xC0u
Kojto 90:cb3d968589d8 5993 #define FB_CSCR_PS_SHIFT 6
Kojto 90:cb3d968589d8 5994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
Kojto 90:cb3d968589d8 5995 #define FB_CSCR_AA_MASK 0x100u
Kojto 90:cb3d968589d8 5996 #define FB_CSCR_AA_SHIFT 8
Kojto 90:cb3d968589d8 5997 #define FB_CSCR_BLS_MASK 0x200u
Kojto 90:cb3d968589d8 5998 #define FB_CSCR_BLS_SHIFT 9
Kojto 90:cb3d968589d8 5999 #define FB_CSCR_WS_MASK 0xFC00u
Kojto 90:cb3d968589d8 6000 #define FB_CSCR_WS_SHIFT 10
Kojto 90:cb3d968589d8 6001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
Kojto 90:cb3d968589d8 6002 #define FB_CSCR_WRAH_MASK 0x30000u
Kojto 90:cb3d968589d8 6003 #define FB_CSCR_WRAH_SHIFT 16
Kojto 90:cb3d968589d8 6004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
Kojto 90:cb3d968589d8 6005 #define FB_CSCR_RDAH_MASK 0xC0000u
Kojto 90:cb3d968589d8 6006 #define FB_CSCR_RDAH_SHIFT 18
Kojto 90:cb3d968589d8 6007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
Kojto 90:cb3d968589d8 6008 #define FB_CSCR_ASET_MASK 0x300000u
Kojto 90:cb3d968589d8 6009 #define FB_CSCR_ASET_SHIFT 20
Kojto 90:cb3d968589d8 6010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
Kojto 90:cb3d968589d8 6011 #define FB_CSCR_EXTS_MASK 0x400000u
Kojto 90:cb3d968589d8 6012 #define FB_CSCR_EXTS_SHIFT 22
Kojto 90:cb3d968589d8 6013 #define FB_CSCR_SWSEN_MASK 0x800000u
Kojto 90:cb3d968589d8 6014 #define FB_CSCR_SWSEN_SHIFT 23
Kojto 90:cb3d968589d8 6015 #define FB_CSCR_SWS_MASK 0xFC000000u
Kojto 90:cb3d968589d8 6016 #define FB_CSCR_SWS_SHIFT 26
Kojto 90:cb3d968589d8 6017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
Kojto 90:cb3d968589d8 6018 /* CSPMCR Bit Fields */
Kojto 90:cb3d968589d8 6019 #define FB_CSPMCR_GROUP5_MASK 0xF000u
Kojto 90:cb3d968589d8 6020 #define FB_CSPMCR_GROUP5_SHIFT 12
Kojto 90:cb3d968589d8 6021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
Kojto 90:cb3d968589d8 6022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
Kojto 90:cb3d968589d8 6023 #define FB_CSPMCR_GROUP4_SHIFT 16
Kojto 90:cb3d968589d8 6024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
Kojto 90:cb3d968589d8 6025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
Kojto 90:cb3d968589d8 6026 #define FB_CSPMCR_GROUP3_SHIFT 20
Kojto 90:cb3d968589d8 6027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
Kojto 90:cb3d968589d8 6028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
Kojto 90:cb3d968589d8 6029 #define FB_CSPMCR_GROUP2_SHIFT 24
Kojto 90:cb3d968589d8 6030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
Kojto 90:cb3d968589d8 6031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
Kojto 90:cb3d968589d8 6032 #define FB_CSPMCR_GROUP1_SHIFT 28
Kojto 90:cb3d968589d8 6033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
Kojto 90:cb3d968589d8 6034
Kojto 90:cb3d968589d8 6035 /*!
Kojto 90:cb3d968589d8 6036 * @}
Kojto 90:cb3d968589d8 6037 */ /* end of group FB_Register_Masks */
Kojto 90:cb3d968589d8 6038
Kojto 90:cb3d968589d8 6039
Kojto 90:cb3d968589d8 6040 /* FB - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6041 /** Peripheral FB base address */
Kojto 90:cb3d968589d8 6042 #define FB_BASE (0x4000C000u)
Kojto 90:cb3d968589d8 6043 /** Peripheral FB base pointer */
Kojto 90:cb3d968589d8 6044 #define FB ((FB_Type *)FB_BASE)
Kojto 90:cb3d968589d8 6045 #define FB_BASE_PTR (FB)
Kojto 90:cb3d968589d8 6046 /** Array initializer of FB peripheral base addresses */
Kojto 90:cb3d968589d8 6047 #define FB_BASE_ADDRS { FB_BASE }
Kojto 90:cb3d968589d8 6048 /** Array initializer of FB peripheral base pointers */
Kojto 90:cb3d968589d8 6049 #define FB_BASE_PTRS { FB }
Kojto 90:cb3d968589d8 6050
Kojto 90:cb3d968589d8 6051 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6052 -- FB - Register accessor macros
Kojto 90:cb3d968589d8 6053 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6054
Kojto 90:cb3d968589d8 6055 /*!
Kojto 90:cb3d968589d8 6056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
Kojto 90:cb3d968589d8 6057 * @{
Kojto 90:cb3d968589d8 6058 */
Kojto 90:cb3d968589d8 6059
Kojto 90:cb3d968589d8 6060
Kojto 90:cb3d968589d8 6061 /* FB - Register instance definitions */
Kojto 90:cb3d968589d8 6062 /* FB */
Kojto 90:cb3d968589d8 6063 #define FB_CSAR0 FB_CSAR_REG(FB,0)
Kojto 90:cb3d968589d8 6064 #define FB_CSMR0 FB_CSMR_REG(FB,0)
Kojto 90:cb3d968589d8 6065 #define FB_CSCR0 FB_CSCR_REG(FB,0)
Kojto 90:cb3d968589d8 6066 #define FB_CSAR1 FB_CSAR_REG(FB,1)
Kojto 90:cb3d968589d8 6067 #define FB_CSMR1 FB_CSMR_REG(FB,1)
Kojto 90:cb3d968589d8 6068 #define FB_CSCR1 FB_CSCR_REG(FB,1)
Kojto 90:cb3d968589d8 6069 #define FB_CSAR2 FB_CSAR_REG(FB,2)
Kojto 90:cb3d968589d8 6070 #define FB_CSMR2 FB_CSMR_REG(FB,2)
Kojto 90:cb3d968589d8 6071 #define FB_CSCR2 FB_CSCR_REG(FB,2)
Kojto 90:cb3d968589d8 6072 #define FB_CSAR3 FB_CSAR_REG(FB,3)
Kojto 90:cb3d968589d8 6073 #define FB_CSMR3 FB_CSMR_REG(FB,3)
Kojto 90:cb3d968589d8 6074 #define FB_CSCR3 FB_CSCR_REG(FB,3)
Kojto 90:cb3d968589d8 6075 #define FB_CSAR4 FB_CSAR_REG(FB,4)
Kojto 90:cb3d968589d8 6076 #define FB_CSMR4 FB_CSMR_REG(FB,4)
Kojto 90:cb3d968589d8 6077 #define FB_CSCR4 FB_CSCR_REG(FB,4)
Kojto 90:cb3d968589d8 6078 #define FB_CSAR5 FB_CSAR_REG(FB,5)
Kojto 90:cb3d968589d8 6079 #define FB_CSMR5 FB_CSMR_REG(FB,5)
Kojto 90:cb3d968589d8 6080 #define FB_CSCR5 FB_CSCR_REG(FB,5)
Kojto 90:cb3d968589d8 6081 #define FB_CSPMCR FB_CSPMCR_REG(FB)
Kojto 90:cb3d968589d8 6082
Kojto 90:cb3d968589d8 6083 /* FB - Register array accessors */
Kojto 90:cb3d968589d8 6084 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
Kojto 90:cb3d968589d8 6085 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
Kojto 90:cb3d968589d8 6086 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
Kojto 90:cb3d968589d8 6087
Kojto 90:cb3d968589d8 6088 /*!
Kojto 90:cb3d968589d8 6089 * @}
Kojto 90:cb3d968589d8 6090 */ /* end of group FB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6091
Kojto 90:cb3d968589d8 6092
Kojto 90:cb3d968589d8 6093 /*!
Kojto 90:cb3d968589d8 6094 * @}
Kojto 90:cb3d968589d8 6095 */ /* end of group FB_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6096
Kojto 90:cb3d968589d8 6097
Kojto 90:cb3d968589d8 6098 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6099 -- FMC Peripheral Access Layer
Kojto 90:cb3d968589d8 6100 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6101
Kojto 90:cb3d968589d8 6102 /*!
Kojto 90:cb3d968589d8 6103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
Kojto 90:cb3d968589d8 6104 * @{
Kojto 90:cb3d968589d8 6105 */
Kojto 90:cb3d968589d8 6106
Kojto 90:cb3d968589d8 6107 /** FMC - Register Layout Typedef */
Kojto 90:cb3d968589d8 6108 typedef struct {
Kojto 90:cb3d968589d8 6109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
Kojto 90:cb3d968589d8 6110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
Kojto 90:cb3d968589d8 6111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 6112 uint8_t RESERVED_0[244];
Kojto 90:cb3d968589d8 6113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
Kojto 90:cb3d968589d8 6114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
Kojto 90:cb3d968589d8 6115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
Kojto 90:cb3d968589d8 6116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
Kojto 90:cb3d968589d8 6117 uint8_t RESERVED_1[192];
Kojto 90:cb3d968589d8 6118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
Kojto 90:cb3d968589d8 6119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
Kojto 90:cb3d968589d8 6120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
Kojto 90:cb3d968589d8 6121 } SET[4][4];
Kojto 90:cb3d968589d8 6122 } FMC_Type, *FMC_MemMapPtr;
Kojto 90:cb3d968589d8 6123
Kojto 90:cb3d968589d8 6124 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6125 -- FMC - Register accessor macros
Kojto 90:cb3d968589d8 6126 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6127
Kojto 90:cb3d968589d8 6128 /*!
Kojto 90:cb3d968589d8 6129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
Kojto 90:cb3d968589d8 6130 * @{
Kojto 90:cb3d968589d8 6131 */
Kojto 90:cb3d968589d8 6132
Kojto 90:cb3d968589d8 6133
Kojto 90:cb3d968589d8 6134 /* FMC - Register accessors */
Kojto 90:cb3d968589d8 6135 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
Kojto 90:cb3d968589d8 6136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
Kojto 90:cb3d968589d8 6137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
Kojto 90:cb3d968589d8 6138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
Kojto 90:cb3d968589d8 6139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
Kojto 90:cb3d968589d8 6140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
Kojto 90:cb3d968589d8 6141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
Kojto 90:cb3d968589d8 6142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
Kojto 90:cb3d968589d8 6143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
Kojto 90:cb3d968589d8 6144
Kojto 90:cb3d968589d8 6145 /*!
Kojto 90:cb3d968589d8 6146 * @}
Kojto 90:cb3d968589d8 6147 */ /* end of group FMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6148
Kojto 90:cb3d968589d8 6149
Kojto 90:cb3d968589d8 6150 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6151 -- FMC Register Masks
Kojto 90:cb3d968589d8 6152 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6153
Kojto 90:cb3d968589d8 6154 /*!
Kojto 90:cb3d968589d8 6155 * @addtogroup FMC_Register_Masks FMC Register Masks
Kojto 90:cb3d968589d8 6156 * @{
Kojto 90:cb3d968589d8 6157 */
Kojto 90:cb3d968589d8 6158
Kojto 90:cb3d968589d8 6159 /* PFAPR Bit Fields */
Kojto 90:cb3d968589d8 6160 #define FMC_PFAPR_M0AP_MASK 0x3u
Kojto 90:cb3d968589d8 6161 #define FMC_PFAPR_M0AP_SHIFT 0
Kojto 90:cb3d968589d8 6162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
Kojto 90:cb3d968589d8 6163 #define FMC_PFAPR_M1AP_MASK 0xCu
Kojto 90:cb3d968589d8 6164 #define FMC_PFAPR_M1AP_SHIFT 2
Kojto 90:cb3d968589d8 6165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
Kojto 90:cb3d968589d8 6166 #define FMC_PFAPR_M2AP_MASK 0x30u
Kojto 90:cb3d968589d8 6167 #define FMC_PFAPR_M2AP_SHIFT 4
Kojto 90:cb3d968589d8 6168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
Kojto 90:cb3d968589d8 6169 #define FMC_PFAPR_M3AP_MASK 0xC0u
Kojto 90:cb3d968589d8 6170 #define FMC_PFAPR_M3AP_SHIFT 6
Kojto 90:cb3d968589d8 6171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
Kojto 90:cb3d968589d8 6172 #define FMC_PFAPR_M4AP_MASK 0x300u
Kojto 90:cb3d968589d8 6173 #define FMC_PFAPR_M4AP_SHIFT 8
Kojto 90:cb3d968589d8 6174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
Kojto 90:cb3d968589d8 6175 #define FMC_PFAPR_M5AP_MASK 0xC00u
Kojto 90:cb3d968589d8 6176 #define FMC_PFAPR_M5AP_SHIFT 10
Kojto 90:cb3d968589d8 6177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
Kojto 90:cb3d968589d8 6178 #define FMC_PFAPR_M6AP_MASK 0x3000u
Kojto 90:cb3d968589d8 6179 #define FMC_PFAPR_M6AP_SHIFT 12
Kojto 90:cb3d968589d8 6180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
Kojto 90:cb3d968589d8 6181 #define FMC_PFAPR_M7AP_MASK 0xC000u
Kojto 90:cb3d968589d8 6182 #define FMC_PFAPR_M7AP_SHIFT 14
Kojto 90:cb3d968589d8 6183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
Kojto 90:cb3d968589d8 6184 #define FMC_PFAPR_M0PFD_MASK 0x10000u
Kojto 90:cb3d968589d8 6185 #define FMC_PFAPR_M0PFD_SHIFT 16
Kojto 90:cb3d968589d8 6186 #define FMC_PFAPR_M1PFD_MASK 0x20000u
Kojto 90:cb3d968589d8 6187 #define FMC_PFAPR_M1PFD_SHIFT 17
Kojto 90:cb3d968589d8 6188 #define FMC_PFAPR_M2PFD_MASK 0x40000u
Kojto 90:cb3d968589d8 6189 #define FMC_PFAPR_M2PFD_SHIFT 18
Kojto 90:cb3d968589d8 6190 #define FMC_PFAPR_M3PFD_MASK 0x80000u
Kojto 90:cb3d968589d8 6191 #define FMC_PFAPR_M3PFD_SHIFT 19
Kojto 90:cb3d968589d8 6192 #define FMC_PFAPR_M4PFD_MASK 0x100000u
Kojto 90:cb3d968589d8 6193 #define FMC_PFAPR_M4PFD_SHIFT 20
Kojto 90:cb3d968589d8 6194 #define FMC_PFAPR_M5PFD_MASK 0x200000u
Kojto 90:cb3d968589d8 6195 #define FMC_PFAPR_M5PFD_SHIFT 21
Kojto 90:cb3d968589d8 6196 #define FMC_PFAPR_M6PFD_MASK 0x400000u
Kojto 90:cb3d968589d8 6197 #define FMC_PFAPR_M6PFD_SHIFT 22
Kojto 90:cb3d968589d8 6198 #define FMC_PFAPR_M7PFD_MASK 0x800000u
Kojto 90:cb3d968589d8 6199 #define FMC_PFAPR_M7PFD_SHIFT 23
Kojto 90:cb3d968589d8 6200 /* PFB0CR Bit Fields */
Kojto 90:cb3d968589d8 6201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
Kojto 90:cb3d968589d8 6202 #define FMC_PFB0CR_B0SEBE_SHIFT 0
Kojto 90:cb3d968589d8 6203 #define FMC_PFB0CR_B0IPE_MASK 0x2u
Kojto 90:cb3d968589d8 6204 #define FMC_PFB0CR_B0IPE_SHIFT 1
Kojto 90:cb3d968589d8 6205 #define FMC_PFB0CR_B0DPE_MASK 0x4u
Kojto 90:cb3d968589d8 6206 #define FMC_PFB0CR_B0DPE_SHIFT 2
Kojto 90:cb3d968589d8 6207 #define FMC_PFB0CR_B0ICE_MASK 0x8u
Kojto 90:cb3d968589d8 6208 #define FMC_PFB0CR_B0ICE_SHIFT 3
Kojto 90:cb3d968589d8 6209 #define FMC_PFB0CR_B0DCE_MASK 0x10u
Kojto 90:cb3d968589d8 6210 #define FMC_PFB0CR_B0DCE_SHIFT 4
Kojto 90:cb3d968589d8 6211 #define FMC_PFB0CR_CRC_MASK 0xE0u
Kojto 90:cb3d968589d8 6212 #define FMC_PFB0CR_CRC_SHIFT 5
Kojto 90:cb3d968589d8 6213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
Kojto 90:cb3d968589d8 6214 #define FMC_PFB0CR_B0MW_MASK 0x60000u
Kojto 90:cb3d968589d8 6215 #define FMC_PFB0CR_B0MW_SHIFT 17
Kojto 90:cb3d968589d8 6216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
Kojto 90:cb3d968589d8 6217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
Kojto 90:cb3d968589d8 6218 #define FMC_PFB0CR_S_B_INV_SHIFT 19
Kojto 90:cb3d968589d8 6219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
Kojto 90:cb3d968589d8 6220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
Kojto 90:cb3d968589d8 6221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
Kojto 90:cb3d968589d8 6222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
Kojto 90:cb3d968589d8 6223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
Kojto 90:cb3d968589d8 6224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
Kojto 90:cb3d968589d8 6225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
Kojto 90:cb3d968589d8 6226 #define FMC_PFB0CR_B0RWSC_SHIFT 28
Kojto 90:cb3d968589d8 6227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
Kojto 90:cb3d968589d8 6228 /* PFB1CR Bit Fields */
Kojto 90:cb3d968589d8 6229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
Kojto 90:cb3d968589d8 6230 #define FMC_PFB1CR_B1SEBE_SHIFT 0
Kojto 90:cb3d968589d8 6231 #define FMC_PFB1CR_B1IPE_MASK 0x2u
Kojto 90:cb3d968589d8 6232 #define FMC_PFB1CR_B1IPE_SHIFT 1
Kojto 90:cb3d968589d8 6233 #define FMC_PFB1CR_B1DPE_MASK 0x4u
Kojto 90:cb3d968589d8 6234 #define FMC_PFB1CR_B1DPE_SHIFT 2
Kojto 90:cb3d968589d8 6235 #define FMC_PFB1CR_B1ICE_MASK 0x8u
Kojto 90:cb3d968589d8 6236 #define FMC_PFB1CR_B1ICE_SHIFT 3
Kojto 90:cb3d968589d8 6237 #define FMC_PFB1CR_B1DCE_MASK 0x10u
Kojto 90:cb3d968589d8 6238 #define FMC_PFB1CR_B1DCE_SHIFT 4
Kojto 90:cb3d968589d8 6239 #define FMC_PFB1CR_B1MW_MASK 0x60000u
Kojto 90:cb3d968589d8 6240 #define FMC_PFB1CR_B1MW_SHIFT 17
Kojto 90:cb3d968589d8 6241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
Kojto 90:cb3d968589d8 6242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
Kojto 90:cb3d968589d8 6243 #define FMC_PFB1CR_B1RWSC_SHIFT 28
Kojto 90:cb3d968589d8 6244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
Kojto 90:cb3d968589d8 6245 /* TAGVDW0S Bit Fields */
Kojto 90:cb3d968589d8 6246 #define FMC_TAGVDW0S_valid_MASK 0x1u
Kojto 90:cb3d968589d8 6247 #define FMC_TAGVDW0S_valid_SHIFT 0
Kojto 90:cb3d968589d8 6248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
Kojto 90:cb3d968589d8 6249 #define FMC_TAGVDW0S_tag_SHIFT 5
Kojto 90:cb3d968589d8 6250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
Kojto 90:cb3d968589d8 6251 /* TAGVDW1S Bit Fields */
Kojto 90:cb3d968589d8 6252 #define FMC_TAGVDW1S_valid_MASK 0x1u
Kojto 90:cb3d968589d8 6253 #define FMC_TAGVDW1S_valid_SHIFT 0
Kojto 90:cb3d968589d8 6254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
Kojto 90:cb3d968589d8 6255 #define FMC_TAGVDW1S_tag_SHIFT 5
Kojto 90:cb3d968589d8 6256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
Kojto 90:cb3d968589d8 6257 /* TAGVDW2S Bit Fields */
Kojto 90:cb3d968589d8 6258 #define FMC_TAGVDW2S_valid_MASK 0x1u
Kojto 90:cb3d968589d8 6259 #define FMC_TAGVDW2S_valid_SHIFT 0
Kojto 90:cb3d968589d8 6260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
Kojto 90:cb3d968589d8 6261 #define FMC_TAGVDW2S_tag_SHIFT 5
Kojto 90:cb3d968589d8 6262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
Kojto 90:cb3d968589d8 6263 /* TAGVDW3S Bit Fields */
Kojto 90:cb3d968589d8 6264 #define FMC_TAGVDW3S_valid_MASK 0x1u
Kojto 90:cb3d968589d8 6265 #define FMC_TAGVDW3S_valid_SHIFT 0
Kojto 90:cb3d968589d8 6266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
Kojto 90:cb3d968589d8 6267 #define FMC_TAGVDW3S_tag_SHIFT 5
Kojto 90:cb3d968589d8 6268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
Kojto 90:cb3d968589d8 6269 /* DATA_U Bit Fields */
Kojto 90:cb3d968589d8 6270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6271 #define FMC_DATA_U_data_SHIFT 0
Kojto 90:cb3d968589d8 6272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
Kojto 90:cb3d968589d8 6273 /* DATA_L Bit Fields */
Kojto 90:cb3d968589d8 6274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6275 #define FMC_DATA_L_data_SHIFT 0
Kojto 90:cb3d968589d8 6276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
Kojto 90:cb3d968589d8 6277
Kojto 90:cb3d968589d8 6278 /*!
Kojto 90:cb3d968589d8 6279 * @}
Kojto 90:cb3d968589d8 6280 */ /* end of group FMC_Register_Masks */
Kojto 90:cb3d968589d8 6281
Kojto 90:cb3d968589d8 6282
Kojto 90:cb3d968589d8 6283 /* FMC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6284 /** Peripheral FMC base address */
Kojto 90:cb3d968589d8 6285 #define FMC_BASE (0x4001F000u)
Kojto 90:cb3d968589d8 6286 /** Peripheral FMC base pointer */
Kojto 90:cb3d968589d8 6287 #define FMC ((FMC_Type *)FMC_BASE)
Kojto 90:cb3d968589d8 6288 #define FMC_BASE_PTR (FMC)
Kojto 90:cb3d968589d8 6289 /** Array initializer of FMC peripheral base addresses */
Kojto 90:cb3d968589d8 6290 #define FMC_BASE_ADDRS { FMC_BASE }
Kojto 90:cb3d968589d8 6291 /** Array initializer of FMC peripheral base pointers */
Kojto 90:cb3d968589d8 6292 #define FMC_BASE_PTRS { FMC }
Kojto 90:cb3d968589d8 6293
Kojto 90:cb3d968589d8 6294 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6295 -- FMC - Register accessor macros
Kojto 90:cb3d968589d8 6296 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6297
Kojto 90:cb3d968589d8 6298 /*!
Kojto 90:cb3d968589d8 6299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
Kojto 90:cb3d968589d8 6300 * @{
Kojto 90:cb3d968589d8 6301 */
Kojto 90:cb3d968589d8 6302
Kojto 90:cb3d968589d8 6303
Kojto 90:cb3d968589d8 6304 /* FMC - Register instance definitions */
Kojto 90:cb3d968589d8 6305 /* FMC */
Kojto 90:cb3d968589d8 6306 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
Kojto 90:cb3d968589d8 6307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
Kojto 90:cb3d968589d8 6308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
Kojto 90:cb3d968589d8 6309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
Kojto 90:cb3d968589d8 6310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
Kojto 90:cb3d968589d8 6311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
Kojto 90:cb3d968589d8 6312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
Kojto 90:cb3d968589d8 6313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
Kojto 90:cb3d968589d8 6314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
Kojto 90:cb3d968589d8 6315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
Kojto 90:cb3d968589d8 6316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
Kojto 90:cb3d968589d8 6317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
Kojto 90:cb3d968589d8 6318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
Kojto 90:cb3d968589d8 6319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
Kojto 90:cb3d968589d8 6320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
Kojto 90:cb3d968589d8 6321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
Kojto 90:cb3d968589d8 6322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
Kojto 90:cb3d968589d8 6323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
Kojto 90:cb3d968589d8 6324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
Kojto 90:cb3d968589d8 6325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
Kojto 90:cb3d968589d8 6326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
Kojto 90:cb3d968589d8 6327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
Kojto 90:cb3d968589d8 6328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
Kojto 90:cb3d968589d8 6329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
Kojto 90:cb3d968589d8 6330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
Kojto 90:cb3d968589d8 6331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
Kojto 90:cb3d968589d8 6332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
Kojto 90:cb3d968589d8 6333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
Kojto 90:cb3d968589d8 6334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
Kojto 90:cb3d968589d8 6335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
Kojto 90:cb3d968589d8 6336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
Kojto 90:cb3d968589d8 6337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
Kojto 90:cb3d968589d8 6338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
Kojto 90:cb3d968589d8 6339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
Kojto 90:cb3d968589d8 6340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
Kojto 90:cb3d968589d8 6341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
Kojto 90:cb3d968589d8 6342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
Kojto 90:cb3d968589d8 6343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
Kojto 90:cb3d968589d8 6344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
Kojto 90:cb3d968589d8 6345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
Kojto 90:cb3d968589d8 6346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
Kojto 90:cb3d968589d8 6347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
Kojto 90:cb3d968589d8 6348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
Kojto 90:cb3d968589d8 6349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
Kojto 90:cb3d968589d8 6350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
Kojto 90:cb3d968589d8 6351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
Kojto 90:cb3d968589d8 6352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
Kojto 90:cb3d968589d8 6353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
Kojto 90:cb3d968589d8 6354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
Kojto 90:cb3d968589d8 6355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
Kojto 90:cb3d968589d8 6356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
Kojto 90:cb3d968589d8 6357
Kojto 90:cb3d968589d8 6358 /* FMC - Register array accessors */
Kojto 90:cb3d968589d8 6359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
Kojto 90:cb3d968589d8 6360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
Kojto 90:cb3d968589d8 6361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
Kojto 90:cb3d968589d8 6362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
Kojto 90:cb3d968589d8 6363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
Kojto 90:cb3d968589d8 6364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
Kojto 90:cb3d968589d8 6365
Kojto 90:cb3d968589d8 6366 /*!
Kojto 90:cb3d968589d8 6367 * @}
Kojto 90:cb3d968589d8 6368 */ /* end of group FMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6369
Kojto 90:cb3d968589d8 6370
Kojto 90:cb3d968589d8 6371 /*!
Kojto 90:cb3d968589d8 6372 * @}
Kojto 90:cb3d968589d8 6373 */ /* end of group FMC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6374
Kojto 90:cb3d968589d8 6375
Kojto 90:cb3d968589d8 6376 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6377 -- FTFE Peripheral Access Layer
Kojto 90:cb3d968589d8 6378 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6379
Kojto 90:cb3d968589d8 6380 /*!
Kojto 90:cb3d968589d8 6381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
Kojto 90:cb3d968589d8 6382 * @{
Kojto 90:cb3d968589d8 6383 */
Kojto 90:cb3d968589d8 6384
Kojto 90:cb3d968589d8 6385 /** FTFE - Register Layout Typedef */
Kojto 90:cb3d968589d8 6386 typedef struct {
Kojto 90:cb3d968589d8 6387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 6388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
Kojto 90:cb3d968589d8 6389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
Kojto 90:cb3d968589d8 6390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
Kojto 90:cb3d968589d8 6391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
Kojto 90:cb3d968589d8 6392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
Kojto 90:cb3d968589d8 6393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
Kojto 90:cb3d968589d8 6394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
Kojto 90:cb3d968589d8 6395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
Kojto 90:cb3d968589d8 6396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
Kojto 90:cb3d968589d8 6397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
Kojto 90:cb3d968589d8 6398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
Kojto 90:cb3d968589d8 6399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
Kojto 90:cb3d968589d8 6400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
Kojto 90:cb3d968589d8 6401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
Kojto 90:cb3d968589d8 6402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
Kojto 90:cb3d968589d8 6403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
Kojto 90:cb3d968589d8 6404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
Kojto 90:cb3d968589d8 6405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
Kojto 90:cb3d968589d8 6406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
Kojto 90:cb3d968589d8 6407 uint8_t RESERVED_0[2];
Kojto 90:cb3d968589d8 6408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
Kojto 90:cb3d968589d8 6409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
Kojto 90:cb3d968589d8 6410 } FTFE_Type, *FTFE_MemMapPtr;
Kojto 90:cb3d968589d8 6411
Kojto 90:cb3d968589d8 6412 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6413 -- FTFE - Register accessor macros
Kojto 90:cb3d968589d8 6414 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6415
Kojto 90:cb3d968589d8 6416 /*!
Kojto 90:cb3d968589d8 6417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
Kojto 90:cb3d968589d8 6418 * @{
Kojto 90:cb3d968589d8 6419 */
Kojto 90:cb3d968589d8 6420
Kojto 90:cb3d968589d8 6421
Kojto 90:cb3d968589d8 6422 /* FTFE - Register accessors */
Kojto 90:cb3d968589d8 6423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
Kojto 90:cb3d968589d8 6424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
Kojto 90:cb3d968589d8 6425 #define FTFE_FSEC_REG(base) ((base)->FSEC)
Kojto 90:cb3d968589d8 6426 #define FTFE_FOPT_REG(base) ((base)->FOPT)
Kojto 90:cb3d968589d8 6427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
Kojto 90:cb3d968589d8 6428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
Kojto 90:cb3d968589d8 6429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
Kojto 90:cb3d968589d8 6430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
Kojto 90:cb3d968589d8 6431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
Kojto 90:cb3d968589d8 6432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
Kojto 90:cb3d968589d8 6433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
Kojto 90:cb3d968589d8 6434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
Kojto 90:cb3d968589d8 6435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
Kojto 90:cb3d968589d8 6436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
Kojto 90:cb3d968589d8 6437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
Kojto 90:cb3d968589d8 6438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
Kojto 90:cb3d968589d8 6439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
Kojto 90:cb3d968589d8 6440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
Kojto 90:cb3d968589d8 6441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
Kojto 90:cb3d968589d8 6442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
Kojto 90:cb3d968589d8 6443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
Kojto 90:cb3d968589d8 6444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
Kojto 90:cb3d968589d8 6445
Kojto 90:cb3d968589d8 6446 /*!
Kojto 90:cb3d968589d8 6447 * @}
Kojto 90:cb3d968589d8 6448 */ /* end of group FTFE_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6449
Kojto 90:cb3d968589d8 6450
Kojto 90:cb3d968589d8 6451 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6452 -- FTFE Register Masks
Kojto 90:cb3d968589d8 6453 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6454
Kojto 90:cb3d968589d8 6455 /*!
Kojto 90:cb3d968589d8 6456 * @addtogroup FTFE_Register_Masks FTFE Register Masks
Kojto 90:cb3d968589d8 6457 * @{
Kojto 90:cb3d968589d8 6458 */
Kojto 90:cb3d968589d8 6459
Kojto 90:cb3d968589d8 6460 /* FSTAT Bit Fields */
Kojto 90:cb3d968589d8 6461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
Kojto 90:cb3d968589d8 6462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
Kojto 90:cb3d968589d8 6463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
Kojto 90:cb3d968589d8 6464 #define FTFE_FSTAT_FPVIOL_SHIFT 4
Kojto 90:cb3d968589d8 6465 #define FTFE_FSTAT_ACCERR_MASK 0x20u
Kojto 90:cb3d968589d8 6466 #define FTFE_FSTAT_ACCERR_SHIFT 5
Kojto 90:cb3d968589d8 6467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
Kojto 90:cb3d968589d8 6468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
Kojto 90:cb3d968589d8 6469 #define FTFE_FSTAT_CCIF_MASK 0x80u
Kojto 90:cb3d968589d8 6470 #define FTFE_FSTAT_CCIF_SHIFT 7
Kojto 90:cb3d968589d8 6471 /* FCNFG Bit Fields */
Kojto 90:cb3d968589d8 6472 #define FTFE_FCNFG_EEERDY_MASK 0x1u
Kojto 90:cb3d968589d8 6473 #define FTFE_FCNFG_EEERDY_SHIFT 0
Kojto 90:cb3d968589d8 6474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
Kojto 90:cb3d968589d8 6475 #define FTFE_FCNFG_RAMRDY_SHIFT 1
Kojto 90:cb3d968589d8 6476 #define FTFE_FCNFG_PFLSH_MASK 0x4u
Kojto 90:cb3d968589d8 6477 #define FTFE_FCNFG_PFLSH_SHIFT 2
Kojto 90:cb3d968589d8 6478 #define FTFE_FCNFG_SWAP_MASK 0x8u
Kojto 90:cb3d968589d8 6479 #define FTFE_FCNFG_SWAP_SHIFT 3
Kojto 90:cb3d968589d8 6480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
Kojto 90:cb3d968589d8 6481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
Kojto 90:cb3d968589d8 6482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
Kojto 90:cb3d968589d8 6483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
Kojto 90:cb3d968589d8 6484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
Kojto 90:cb3d968589d8 6485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
Kojto 90:cb3d968589d8 6486 #define FTFE_FCNFG_CCIE_MASK 0x80u
Kojto 90:cb3d968589d8 6487 #define FTFE_FCNFG_CCIE_SHIFT 7
Kojto 90:cb3d968589d8 6488 /* FSEC Bit Fields */
Kojto 90:cb3d968589d8 6489 #define FTFE_FSEC_SEC_MASK 0x3u
Kojto 90:cb3d968589d8 6490 #define FTFE_FSEC_SEC_SHIFT 0
Kojto 90:cb3d968589d8 6491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
Kojto 90:cb3d968589d8 6492 #define FTFE_FSEC_FSLACC_MASK 0xCu
Kojto 90:cb3d968589d8 6493 #define FTFE_FSEC_FSLACC_SHIFT 2
Kojto 90:cb3d968589d8 6494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
Kojto 90:cb3d968589d8 6495 #define FTFE_FSEC_MEEN_MASK 0x30u
Kojto 90:cb3d968589d8 6496 #define FTFE_FSEC_MEEN_SHIFT 4
Kojto 90:cb3d968589d8 6497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
Kojto 90:cb3d968589d8 6498 #define FTFE_FSEC_KEYEN_MASK 0xC0u
Kojto 90:cb3d968589d8 6499 #define FTFE_FSEC_KEYEN_SHIFT 6
Kojto 90:cb3d968589d8 6500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
Kojto 90:cb3d968589d8 6501 /* FOPT Bit Fields */
Kojto 90:cb3d968589d8 6502 #define FTFE_FOPT_OPT_MASK 0xFFu
Kojto 90:cb3d968589d8 6503 #define FTFE_FOPT_OPT_SHIFT 0
Kojto 90:cb3d968589d8 6504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
Kojto 90:cb3d968589d8 6505 /* FCCOB3 Bit Fields */
Kojto 90:cb3d968589d8 6506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6507 #define FTFE_FCCOB3_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
Kojto 90:cb3d968589d8 6509 /* FCCOB2 Bit Fields */
Kojto 90:cb3d968589d8 6510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6511 #define FTFE_FCCOB2_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
Kojto 90:cb3d968589d8 6513 /* FCCOB1 Bit Fields */
Kojto 90:cb3d968589d8 6514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6515 #define FTFE_FCCOB1_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
Kojto 90:cb3d968589d8 6517 /* FCCOB0 Bit Fields */
Kojto 90:cb3d968589d8 6518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6519 #define FTFE_FCCOB0_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
Kojto 90:cb3d968589d8 6521 /* FCCOB7 Bit Fields */
Kojto 90:cb3d968589d8 6522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6523 #define FTFE_FCCOB7_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
Kojto 90:cb3d968589d8 6525 /* FCCOB6 Bit Fields */
Kojto 90:cb3d968589d8 6526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6527 #define FTFE_FCCOB6_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
Kojto 90:cb3d968589d8 6529 /* FCCOB5 Bit Fields */
Kojto 90:cb3d968589d8 6530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6531 #define FTFE_FCCOB5_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
Kojto 90:cb3d968589d8 6533 /* FCCOB4 Bit Fields */
Kojto 90:cb3d968589d8 6534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6535 #define FTFE_FCCOB4_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
Kojto 90:cb3d968589d8 6537 /* FCCOBB Bit Fields */
Kojto 90:cb3d968589d8 6538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6539 #define FTFE_FCCOBB_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
Kojto 90:cb3d968589d8 6541 /* FCCOBA Bit Fields */
Kojto 90:cb3d968589d8 6542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6543 #define FTFE_FCCOBA_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
Kojto 90:cb3d968589d8 6545 /* FCCOB9 Bit Fields */
Kojto 90:cb3d968589d8 6546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6547 #define FTFE_FCCOB9_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
Kojto 90:cb3d968589d8 6549 /* FCCOB8 Bit Fields */
Kojto 90:cb3d968589d8 6550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 6551 #define FTFE_FCCOB8_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 6552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
Kojto 90:cb3d968589d8 6553 /* FPROT3 Bit Fields */
Kojto 90:cb3d968589d8 6554 #define FTFE_FPROT3_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6555 #define FTFE_FPROT3_PROT_SHIFT 0
Kojto 90:cb3d968589d8 6556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
Kojto 90:cb3d968589d8 6557 /* FPROT2 Bit Fields */
Kojto 90:cb3d968589d8 6558 #define FTFE_FPROT2_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6559 #define FTFE_FPROT2_PROT_SHIFT 0
Kojto 90:cb3d968589d8 6560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
Kojto 90:cb3d968589d8 6561 /* FPROT1 Bit Fields */
Kojto 90:cb3d968589d8 6562 #define FTFE_FPROT1_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6563 #define FTFE_FPROT1_PROT_SHIFT 0
Kojto 90:cb3d968589d8 6564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
Kojto 90:cb3d968589d8 6565 /* FPROT0 Bit Fields */
Kojto 90:cb3d968589d8 6566 #define FTFE_FPROT0_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6567 #define FTFE_FPROT0_PROT_SHIFT 0
Kojto 90:cb3d968589d8 6568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
Kojto 90:cb3d968589d8 6569 /* FEPROT Bit Fields */
Kojto 90:cb3d968589d8 6570 #define FTFE_FEPROT_EPROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6571 #define FTFE_FEPROT_EPROT_SHIFT 0
Kojto 90:cb3d968589d8 6572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
Kojto 90:cb3d968589d8 6573 /* FDPROT Bit Fields */
Kojto 90:cb3d968589d8 6574 #define FTFE_FDPROT_DPROT_MASK 0xFFu
Kojto 90:cb3d968589d8 6575 #define FTFE_FDPROT_DPROT_SHIFT 0
Kojto 90:cb3d968589d8 6576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
Kojto 90:cb3d968589d8 6577
Kojto 90:cb3d968589d8 6578 /*!
Kojto 90:cb3d968589d8 6579 * @}
Kojto 90:cb3d968589d8 6580 */ /* end of group FTFE_Register_Masks */
Kojto 90:cb3d968589d8 6581
Kojto 90:cb3d968589d8 6582
Kojto 90:cb3d968589d8 6583 /* FTFE - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6584 /** Peripheral FTFE base address */
Kojto 90:cb3d968589d8 6585 #define FTFE_BASE (0x40020000u)
Kojto 90:cb3d968589d8 6586 /** Peripheral FTFE base pointer */
Kojto 90:cb3d968589d8 6587 #define FTFE ((FTFE_Type *)FTFE_BASE)
Kojto 90:cb3d968589d8 6588 #define FTFE_BASE_PTR (FTFE)
Kojto 90:cb3d968589d8 6589 /** Array initializer of FTFE peripheral base addresses */
Kojto 90:cb3d968589d8 6590 #define FTFE_BASE_ADDRS { FTFE_BASE }
Kojto 90:cb3d968589d8 6591 /** Array initializer of FTFE peripheral base pointers */
Kojto 90:cb3d968589d8 6592 #define FTFE_BASE_PTRS { FTFE }
Kojto 90:cb3d968589d8 6593 /** Interrupt vectors for the FTFE peripheral type */
Kojto 90:cb3d968589d8 6594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
Kojto 90:cb3d968589d8 6595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
Kojto 90:cb3d968589d8 6596
Kojto 90:cb3d968589d8 6597 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6598 -- FTFE - Register accessor macros
Kojto 90:cb3d968589d8 6599 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6600
Kojto 90:cb3d968589d8 6601 /*!
Kojto 90:cb3d968589d8 6602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
Kojto 90:cb3d968589d8 6603 * @{
Kojto 90:cb3d968589d8 6604 */
Kojto 90:cb3d968589d8 6605
Kojto 90:cb3d968589d8 6606
Kojto 90:cb3d968589d8 6607 /* FTFE - Register instance definitions */
Kojto 90:cb3d968589d8 6608 /* FTFE */
Kojto 90:cb3d968589d8 6609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
Kojto 90:cb3d968589d8 6610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
Kojto 90:cb3d968589d8 6611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
Kojto 90:cb3d968589d8 6612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
Kojto 90:cb3d968589d8 6613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
Kojto 90:cb3d968589d8 6614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
Kojto 90:cb3d968589d8 6615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
Kojto 90:cb3d968589d8 6616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
Kojto 90:cb3d968589d8 6617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
Kojto 90:cb3d968589d8 6618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
Kojto 90:cb3d968589d8 6619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
Kojto 90:cb3d968589d8 6620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
Kojto 90:cb3d968589d8 6621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
Kojto 90:cb3d968589d8 6622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
Kojto 90:cb3d968589d8 6623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
Kojto 90:cb3d968589d8 6624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
Kojto 90:cb3d968589d8 6625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
Kojto 90:cb3d968589d8 6626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
Kojto 90:cb3d968589d8 6627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
Kojto 90:cb3d968589d8 6628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
Kojto 90:cb3d968589d8 6629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
Kojto 90:cb3d968589d8 6630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
Kojto 90:cb3d968589d8 6631
Kojto 90:cb3d968589d8 6632 /*!
Kojto 90:cb3d968589d8 6633 * @}
Kojto 90:cb3d968589d8 6634 */ /* end of group FTFE_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6635
Kojto 90:cb3d968589d8 6636
Kojto 90:cb3d968589d8 6637 /*!
Kojto 90:cb3d968589d8 6638 * @}
Kojto 90:cb3d968589d8 6639 */ /* end of group FTFE_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6640
Kojto 90:cb3d968589d8 6641
Kojto 90:cb3d968589d8 6642 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6643 -- FTM Peripheral Access Layer
Kojto 90:cb3d968589d8 6644 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6645
Kojto 90:cb3d968589d8 6646 /*!
Kojto 90:cb3d968589d8 6647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
Kojto 90:cb3d968589d8 6648 * @{
Kojto 90:cb3d968589d8 6649 */
Kojto 90:cb3d968589d8 6650
Kojto 90:cb3d968589d8 6651 /** FTM - Register Layout Typedef */
Kojto 90:cb3d968589d8 6652 typedef struct {
Kojto 90:cb3d968589d8 6653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
Kojto 90:cb3d968589d8 6654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
Kojto 90:cb3d968589d8 6655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
Kojto 90:cb3d968589d8 6656 struct { /* offset: 0xC, array step: 0x8 */
Kojto 90:cb3d968589d8 6657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
Kojto 90:cb3d968589d8 6658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
Kojto 90:cb3d968589d8 6659 } CONTROLS[8];
Kojto 90:cb3d968589d8 6660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
Kojto 90:cb3d968589d8 6661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
Kojto 90:cb3d968589d8 6662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
Kojto 90:cb3d968589d8 6663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
Kojto 90:cb3d968589d8 6664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
Kojto 90:cb3d968589d8 6665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
Kojto 90:cb3d968589d8 6666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
Kojto 90:cb3d968589d8 6667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
Kojto 90:cb3d968589d8 6668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
Kojto 90:cb3d968589d8 6669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
Kojto 90:cb3d968589d8 6670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
Kojto 90:cb3d968589d8 6671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
Kojto 90:cb3d968589d8 6672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
Kojto 90:cb3d968589d8 6673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
Kojto 90:cb3d968589d8 6674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
Kojto 90:cb3d968589d8 6675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
Kojto 90:cb3d968589d8 6676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
Kojto 90:cb3d968589d8 6677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
Kojto 90:cb3d968589d8 6678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
Kojto 90:cb3d968589d8 6679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
Kojto 90:cb3d968589d8 6680 } FTM_Type, *FTM_MemMapPtr;
Kojto 90:cb3d968589d8 6681
Kojto 90:cb3d968589d8 6682 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6683 -- FTM - Register accessor macros
Kojto 90:cb3d968589d8 6684 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6685
Kojto 90:cb3d968589d8 6686 /*!
Kojto 90:cb3d968589d8 6687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
Kojto 90:cb3d968589d8 6688 * @{
Kojto 90:cb3d968589d8 6689 */
Kojto 90:cb3d968589d8 6690
Kojto 90:cb3d968589d8 6691
Kojto 90:cb3d968589d8 6692 /* FTM - Register accessors */
Kojto 90:cb3d968589d8 6693 #define FTM_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 6694 #define FTM_CNT_REG(base) ((base)->CNT)
Kojto 90:cb3d968589d8 6695 #define FTM_MOD_REG(base) ((base)->MOD)
Kojto 90:cb3d968589d8 6696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
Kojto 90:cb3d968589d8 6697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
Kojto 90:cb3d968589d8 6698 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
Kojto 90:cb3d968589d8 6699 #define FTM_STATUS_REG(base) ((base)->STATUS)
Kojto 90:cb3d968589d8 6700 #define FTM_MODE_REG(base) ((base)->MODE)
Kojto 90:cb3d968589d8 6701 #define FTM_SYNC_REG(base) ((base)->SYNC)
Kojto 90:cb3d968589d8 6702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
Kojto 90:cb3d968589d8 6703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
Kojto 90:cb3d968589d8 6704 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
Kojto 90:cb3d968589d8 6705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
Kojto 90:cb3d968589d8 6706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
Kojto 90:cb3d968589d8 6707 #define FTM_POL_REG(base) ((base)->POL)
Kojto 90:cb3d968589d8 6708 #define FTM_FMS_REG(base) ((base)->FMS)
Kojto 90:cb3d968589d8 6709 #define FTM_FILTER_REG(base) ((base)->FILTER)
Kojto 90:cb3d968589d8 6710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
Kojto 90:cb3d968589d8 6711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
Kojto 90:cb3d968589d8 6712 #define FTM_CONF_REG(base) ((base)->CONF)
Kojto 90:cb3d968589d8 6713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
Kojto 90:cb3d968589d8 6714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
Kojto 90:cb3d968589d8 6715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
Kojto 90:cb3d968589d8 6716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
Kojto 90:cb3d968589d8 6717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
Kojto 90:cb3d968589d8 6718
Kojto 90:cb3d968589d8 6719 /*!
Kojto 90:cb3d968589d8 6720 * @}
Kojto 90:cb3d968589d8 6721 */ /* end of group FTM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6722
Kojto 90:cb3d968589d8 6723
Kojto 90:cb3d968589d8 6724 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6725 -- FTM Register Masks
Kojto 90:cb3d968589d8 6726 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6727
Kojto 90:cb3d968589d8 6728 /*!
Kojto 90:cb3d968589d8 6729 * @addtogroup FTM_Register_Masks FTM Register Masks
Kojto 90:cb3d968589d8 6730 * @{
Kojto 90:cb3d968589d8 6731 */
Kojto 90:cb3d968589d8 6732
Kojto 90:cb3d968589d8 6733 /* SC Bit Fields */
Kojto 90:cb3d968589d8 6734 #define FTM_SC_PS_MASK 0x7u
Kojto 90:cb3d968589d8 6735 #define FTM_SC_PS_SHIFT 0
Kojto 90:cb3d968589d8 6736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
Kojto 90:cb3d968589d8 6737 #define FTM_SC_CLKS_MASK 0x18u
Kojto 90:cb3d968589d8 6738 #define FTM_SC_CLKS_SHIFT 3
Kojto 90:cb3d968589d8 6739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
Kojto 90:cb3d968589d8 6740 #define FTM_SC_CPWMS_MASK 0x20u
Kojto 90:cb3d968589d8 6741 #define FTM_SC_CPWMS_SHIFT 5
Kojto 90:cb3d968589d8 6742 #define FTM_SC_TOIE_MASK 0x40u
Kojto 90:cb3d968589d8 6743 #define FTM_SC_TOIE_SHIFT 6
Kojto 90:cb3d968589d8 6744 #define FTM_SC_TOF_MASK 0x80u
Kojto 90:cb3d968589d8 6745 #define FTM_SC_TOF_SHIFT 7
Kojto 90:cb3d968589d8 6746 /* CNT Bit Fields */
Kojto 90:cb3d968589d8 6747 #define FTM_CNT_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 6748 #define FTM_CNT_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 6749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
Kojto 90:cb3d968589d8 6750 /* MOD Bit Fields */
Kojto 90:cb3d968589d8 6751 #define FTM_MOD_MOD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 6752 #define FTM_MOD_MOD_SHIFT 0
Kojto 90:cb3d968589d8 6753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
Kojto 90:cb3d968589d8 6754 /* CnSC Bit Fields */
Kojto 90:cb3d968589d8 6755 #define FTM_CnSC_DMA_MASK 0x1u
Kojto 90:cb3d968589d8 6756 #define FTM_CnSC_DMA_SHIFT 0
Kojto 90:cb3d968589d8 6757 #define FTM_CnSC_ELSA_MASK 0x4u
Kojto 90:cb3d968589d8 6758 #define FTM_CnSC_ELSA_SHIFT 2
Kojto 90:cb3d968589d8 6759 #define FTM_CnSC_ELSB_MASK 0x8u
Kojto 90:cb3d968589d8 6760 #define FTM_CnSC_ELSB_SHIFT 3
Kojto 90:cb3d968589d8 6761 #define FTM_CnSC_MSA_MASK 0x10u
Kojto 90:cb3d968589d8 6762 #define FTM_CnSC_MSA_SHIFT 4
Kojto 90:cb3d968589d8 6763 #define FTM_CnSC_MSB_MASK 0x20u
Kojto 90:cb3d968589d8 6764 #define FTM_CnSC_MSB_SHIFT 5
Kojto 90:cb3d968589d8 6765 #define FTM_CnSC_CHIE_MASK 0x40u
Kojto 90:cb3d968589d8 6766 #define FTM_CnSC_CHIE_SHIFT 6
Kojto 90:cb3d968589d8 6767 #define FTM_CnSC_CHF_MASK 0x80u
Kojto 90:cb3d968589d8 6768 #define FTM_CnSC_CHF_SHIFT 7
Kojto 90:cb3d968589d8 6769 /* CnV Bit Fields */
Kojto 90:cb3d968589d8 6770 #define FTM_CnV_VAL_MASK 0xFFFFu
Kojto 90:cb3d968589d8 6771 #define FTM_CnV_VAL_SHIFT 0
Kojto 90:cb3d968589d8 6772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
Kojto 90:cb3d968589d8 6773 /* CNTIN Bit Fields */
Kojto 90:cb3d968589d8 6774 #define FTM_CNTIN_INIT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 6775 #define FTM_CNTIN_INIT_SHIFT 0
Kojto 90:cb3d968589d8 6776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
Kojto 90:cb3d968589d8 6777 /* STATUS Bit Fields */
Kojto 90:cb3d968589d8 6778 #define FTM_STATUS_CH0F_MASK 0x1u
Kojto 90:cb3d968589d8 6779 #define FTM_STATUS_CH0F_SHIFT 0
Kojto 90:cb3d968589d8 6780 #define FTM_STATUS_CH1F_MASK 0x2u
Kojto 90:cb3d968589d8 6781 #define FTM_STATUS_CH1F_SHIFT 1
Kojto 90:cb3d968589d8 6782 #define FTM_STATUS_CH2F_MASK 0x4u
Kojto 90:cb3d968589d8 6783 #define FTM_STATUS_CH2F_SHIFT 2
Kojto 90:cb3d968589d8 6784 #define FTM_STATUS_CH3F_MASK 0x8u
Kojto 90:cb3d968589d8 6785 #define FTM_STATUS_CH3F_SHIFT 3
Kojto 90:cb3d968589d8 6786 #define FTM_STATUS_CH4F_MASK 0x10u
Kojto 90:cb3d968589d8 6787 #define FTM_STATUS_CH4F_SHIFT 4
Kojto 90:cb3d968589d8 6788 #define FTM_STATUS_CH5F_MASK 0x20u
Kojto 90:cb3d968589d8 6789 #define FTM_STATUS_CH5F_SHIFT 5
Kojto 90:cb3d968589d8 6790 #define FTM_STATUS_CH6F_MASK 0x40u
Kojto 90:cb3d968589d8 6791 #define FTM_STATUS_CH6F_SHIFT 6
Kojto 90:cb3d968589d8 6792 #define FTM_STATUS_CH7F_MASK 0x80u
Kojto 90:cb3d968589d8 6793 #define FTM_STATUS_CH7F_SHIFT 7
Kojto 90:cb3d968589d8 6794 /* MODE Bit Fields */
Kojto 90:cb3d968589d8 6795 #define FTM_MODE_FTMEN_MASK 0x1u
Kojto 90:cb3d968589d8 6796 #define FTM_MODE_FTMEN_SHIFT 0
Kojto 90:cb3d968589d8 6797 #define FTM_MODE_INIT_MASK 0x2u
Kojto 90:cb3d968589d8 6798 #define FTM_MODE_INIT_SHIFT 1
Kojto 90:cb3d968589d8 6799 #define FTM_MODE_WPDIS_MASK 0x4u
Kojto 90:cb3d968589d8 6800 #define FTM_MODE_WPDIS_SHIFT 2
Kojto 90:cb3d968589d8 6801 #define FTM_MODE_PWMSYNC_MASK 0x8u
Kojto 90:cb3d968589d8 6802 #define FTM_MODE_PWMSYNC_SHIFT 3
Kojto 90:cb3d968589d8 6803 #define FTM_MODE_CAPTEST_MASK 0x10u
Kojto 90:cb3d968589d8 6804 #define FTM_MODE_CAPTEST_SHIFT 4
Kojto 90:cb3d968589d8 6805 #define FTM_MODE_FAULTM_MASK 0x60u
Kojto 90:cb3d968589d8 6806 #define FTM_MODE_FAULTM_SHIFT 5
Kojto 90:cb3d968589d8 6807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
Kojto 90:cb3d968589d8 6808 #define FTM_MODE_FAULTIE_MASK 0x80u
Kojto 90:cb3d968589d8 6809 #define FTM_MODE_FAULTIE_SHIFT 7
Kojto 90:cb3d968589d8 6810 /* SYNC Bit Fields */
Kojto 90:cb3d968589d8 6811 #define FTM_SYNC_CNTMIN_MASK 0x1u
Kojto 90:cb3d968589d8 6812 #define FTM_SYNC_CNTMIN_SHIFT 0
Kojto 90:cb3d968589d8 6813 #define FTM_SYNC_CNTMAX_MASK 0x2u
Kojto 90:cb3d968589d8 6814 #define FTM_SYNC_CNTMAX_SHIFT 1
Kojto 90:cb3d968589d8 6815 #define FTM_SYNC_REINIT_MASK 0x4u
Kojto 90:cb3d968589d8 6816 #define FTM_SYNC_REINIT_SHIFT 2
Kojto 90:cb3d968589d8 6817 #define FTM_SYNC_SYNCHOM_MASK 0x8u
Kojto 90:cb3d968589d8 6818 #define FTM_SYNC_SYNCHOM_SHIFT 3
Kojto 90:cb3d968589d8 6819 #define FTM_SYNC_TRIG0_MASK 0x10u
Kojto 90:cb3d968589d8 6820 #define FTM_SYNC_TRIG0_SHIFT 4
Kojto 90:cb3d968589d8 6821 #define FTM_SYNC_TRIG1_MASK 0x20u
Kojto 90:cb3d968589d8 6822 #define FTM_SYNC_TRIG1_SHIFT 5
Kojto 90:cb3d968589d8 6823 #define FTM_SYNC_TRIG2_MASK 0x40u
Kojto 90:cb3d968589d8 6824 #define FTM_SYNC_TRIG2_SHIFT 6
Kojto 90:cb3d968589d8 6825 #define FTM_SYNC_SWSYNC_MASK 0x80u
Kojto 90:cb3d968589d8 6826 #define FTM_SYNC_SWSYNC_SHIFT 7
Kojto 90:cb3d968589d8 6827 /* OUTINIT Bit Fields */
Kojto 90:cb3d968589d8 6828 #define FTM_OUTINIT_CH0OI_MASK 0x1u
Kojto 90:cb3d968589d8 6829 #define FTM_OUTINIT_CH0OI_SHIFT 0
Kojto 90:cb3d968589d8 6830 #define FTM_OUTINIT_CH1OI_MASK 0x2u
Kojto 90:cb3d968589d8 6831 #define FTM_OUTINIT_CH1OI_SHIFT 1
Kojto 90:cb3d968589d8 6832 #define FTM_OUTINIT_CH2OI_MASK 0x4u
Kojto 90:cb3d968589d8 6833 #define FTM_OUTINIT_CH2OI_SHIFT 2
Kojto 90:cb3d968589d8 6834 #define FTM_OUTINIT_CH3OI_MASK 0x8u
Kojto 90:cb3d968589d8 6835 #define FTM_OUTINIT_CH3OI_SHIFT 3
Kojto 90:cb3d968589d8 6836 #define FTM_OUTINIT_CH4OI_MASK 0x10u
Kojto 90:cb3d968589d8 6837 #define FTM_OUTINIT_CH4OI_SHIFT 4
Kojto 90:cb3d968589d8 6838 #define FTM_OUTINIT_CH5OI_MASK 0x20u
Kojto 90:cb3d968589d8 6839 #define FTM_OUTINIT_CH5OI_SHIFT 5
Kojto 90:cb3d968589d8 6840 #define FTM_OUTINIT_CH6OI_MASK 0x40u
Kojto 90:cb3d968589d8 6841 #define FTM_OUTINIT_CH6OI_SHIFT 6
Kojto 90:cb3d968589d8 6842 #define FTM_OUTINIT_CH7OI_MASK 0x80u
Kojto 90:cb3d968589d8 6843 #define FTM_OUTINIT_CH7OI_SHIFT 7
Kojto 90:cb3d968589d8 6844 /* OUTMASK Bit Fields */
Kojto 90:cb3d968589d8 6845 #define FTM_OUTMASK_CH0OM_MASK 0x1u
Kojto 90:cb3d968589d8 6846 #define FTM_OUTMASK_CH0OM_SHIFT 0
Kojto 90:cb3d968589d8 6847 #define FTM_OUTMASK_CH1OM_MASK 0x2u
Kojto 90:cb3d968589d8 6848 #define FTM_OUTMASK_CH1OM_SHIFT 1
Kojto 90:cb3d968589d8 6849 #define FTM_OUTMASK_CH2OM_MASK 0x4u
Kojto 90:cb3d968589d8 6850 #define FTM_OUTMASK_CH2OM_SHIFT 2
Kojto 90:cb3d968589d8 6851 #define FTM_OUTMASK_CH3OM_MASK 0x8u
Kojto 90:cb3d968589d8 6852 #define FTM_OUTMASK_CH3OM_SHIFT 3
Kojto 90:cb3d968589d8 6853 #define FTM_OUTMASK_CH4OM_MASK 0x10u
Kojto 90:cb3d968589d8 6854 #define FTM_OUTMASK_CH4OM_SHIFT 4
Kojto 90:cb3d968589d8 6855 #define FTM_OUTMASK_CH5OM_MASK 0x20u
Kojto 90:cb3d968589d8 6856 #define FTM_OUTMASK_CH5OM_SHIFT 5
Kojto 90:cb3d968589d8 6857 #define FTM_OUTMASK_CH6OM_MASK 0x40u
Kojto 90:cb3d968589d8 6858 #define FTM_OUTMASK_CH6OM_SHIFT 6
Kojto 90:cb3d968589d8 6859 #define FTM_OUTMASK_CH7OM_MASK 0x80u
Kojto 90:cb3d968589d8 6860 #define FTM_OUTMASK_CH7OM_SHIFT 7
Kojto 90:cb3d968589d8 6861 /* COMBINE Bit Fields */
Kojto 90:cb3d968589d8 6862 #define FTM_COMBINE_COMBINE0_MASK 0x1u
Kojto 90:cb3d968589d8 6863 #define FTM_COMBINE_COMBINE0_SHIFT 0
Kojto 90:cb3d968589d8 6864 #define FTM_COMBINE_COMP0_MASK 0x2u
Kojto 90:cb3d968589d8 6865 #define FTM_COMBINE_COMP0_SHIFT 1
Kojto 90:cb3d968589d8 6866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
Kojto 90:cb3d968589d8 6867 #define FTM_COMBINE_DECAPEN0_SHIFT 2
Kojto 90:cb3d968589d8 6868 #define FTM_COMBINE_DECAP0_MASK 0x8u
Kojto 90:cb3d968589d8 6869 #define FTM_COMBINE_DECAP0_SHIFT 3
Kojto 90:cb3d968589d8 6870 #define FTM_COMBINE_DTEN0_MASK 0x10u
Kojto 90:cb3d968589d8 6871 #define FTM_COMBINE_DTEN0_SHIFT 4
Kojto 90:cb3d968589d8 6872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
Kojto 90:cb3d968589d8 6873 #define FTM_COMBINE_SYNCEN0_SHIFT 5
Kojto 90:cb3d968589d8 6874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
Kojto 90:cb3d968589d8 6875 #define FTM_COMBINE_FAULTEN0_SHIFT 6
Kojto 90:cb3d968589d8 6876 #define FTM_COMBINE_COMBINE1_MASK 0x100u
Kojto 90:cb3d968589d8 6877 #define FTM_COMBINE_COMBINE1_SHIFT 8
Kojto 90:cb3d968589d8 6878 #define FTM_COMBINE_COMP1_MASK 0x200u
Kojto 90:cb3d968589d8 6879 #define FTM_COMBINE_COMP1_SHIFT 9
Kojto 90:cb3d968589d8 6880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
Kojto 90:cb3d968589d8 6881 #define FTM_COMBINE_DECAPEN1_SHIFT 10
Kojto 90:cb3d968589d8 6882 #define FTM_COMBINE_DECAP1_MASK 0x800u
Kojto 90:cb3d968589d8 6883 #define FTM_COMBINE_DECAP1_SHIFT 11
Kojto 90:cb3d968589d8 6884 #define FTM_COMBINE_DTEN1_MASK 0x1000u
Kojto 90:cb3d968589d8 6885 #define FTM_COMBINE_DTEN1_SHIFT 12
Kojto 90:cb3d968589d8 6886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
Kojto 90:cb3d968589d8 6887 #define FTM_COMBINE_SYNCEN1_SHIFT 13
Kojto 90:cb3d968589d8 6888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
Kojto 90:cb3d968589d8 6889 #define FTM_COMBINE_FAULTEN1_SHIFT 14
Kojto 90:cb3d968589d8 6890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
Kojto 90:cb3d968589d8 6891 #define FTM_COMBINE_COMBINE2_SHIFT 16
Kojto 90:cb3d968589d8 6892 #define FTM_COMBINE_COMP2_MASK 0x20000u
Kojto 90:cb3d968589d8 6893 #define FTM_COMBINE_COMP2_SHIFT 17
Kojto 90:cb3d968589d8 6894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
Kojto 90:cb3d968589d8 6895 #define FTM_COMBINE_DECAPEN2_SHIFT 18
Kojto 90:cb3d968589d8 6896 #define FTM_COMBINE_DECAP2_MASK 0x80000u
Kojto 90:cb3d968589d8 6897 #define FTM_COMBINE_DECAP2_SHIFT 19
Kojto 90:cb3d968589d8 6898 #define FTM_COMBINE_DTEN2_MASK 0x100000u
Kojto 90:cb3d968589d8 6899 #define FTM_COMBINE_DTEN2_SHIFT 20
Kojto 90:cb3d968589d8 6900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
Kojto 90:cb3d968589d8 6901 #define FTM_COMBINE_SYNCEN2_SHIFT 21
Kojto 90:cb3d968589d8 6902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
Kojto 90:cb3d968589d8 6903 #define FTM_COMBINE_FAULTEN2_SHIFT 22
Kojto 90:cb3d968589d8 6904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
Kojto 90:cb3d968589d8 6905 #define FTM_COMBINE_COMBINE3_SHIFT 24
Kojto 90:cb3d968589d8 6906 #define FTM_COMBINE_COMP3_MASK 0x2000000u
Kojto 90:cb3d968589d8 6907 #define FTM_COMBINE_COMP3_SHIFT 25
Kojto 90:cb3d968589d8 6908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
Kojto 90:cb3d968589d8 6909 #define FTM_COMBINE_DECAPEN3_SHIFT 26
Kojto 90:cb3d968589d8 6910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
Kojto 90:cb3d968589d8 6911 #define FTM_COMBINE_DECAP3_SHIFT 27
Kojto 90:cb3d968589d8 6912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
Kojto 90:cb3d968589d8 6913 #define FTM_COMBINE_DTEN3_SHIFT 28
Kojto 90:cb3d968589d8 6914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
Kojto 90:cb3d968589d8 6915 #define FTM_COMBINE_SYNCEN3_SHIFT 29
Kojto 90:cb3d968589d8 6916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
Kojto 90:cb3d968589d8 6917 #define FTM_COMBINE_FAULTEN3_SHIFT 30
Kojto 90:cb3d968589d8 6918 /* DEADTIME Bit Fields */
Kojto 90:cb3d968589d8 6919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
Kojto 90:cb3d968589d8 6920 #define FTM_DEADTIME_DTVAL_SHIFT 0
Kojto 90:cb3d968589d8 6921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
Kojto 90:cb3d968589d8 6922 #define FTM_DEADTIME_DTPS_MASK 0xC0u
Kojto 90:cb3d968589d8 6923 #define FTM_DEADTIME_DTPS_SHIFT 6
Kojto 90:cb3d968589d8 6924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
Kojto 90:cb3d968589d8 6925 /* EXTTRIG Bit Fields */
Kojto 90:cb3d968589d8 6926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
Kojto 90:cb3d968589d8 6927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
Kojto 90:cb3d968589d8 6928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
Kojto 90:cb3d968589d8 6929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
Kojto 90:cb3d968589d8 6930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
Kojto 90:cb3d968589d8 6931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
Kojto 90:cb3d968589d8 6932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
Kojto 90:cb3d968589d8 6933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
Kojto 90:cb3d968589d8 6934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
Kojto 90:cb3d968589d8 6935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
Kojto 90:cb3d968589d8 6936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
Kojto 90:cb3d968589d8 6937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
Kojto 90:cb3d968589d8 6938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
Kojto 90:cb3d968589d8 6939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
Kojto 90:cb3d968589d8 6940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
Kojto 90:cb3d968589d8 6941 #define FTM_EXTTRIG_TRIGF_SHIFT 7
Kojto 90:cb3d968589d8 6942 /* POL Bit Fields */
Kojto 90:cb3d968589d8 6943 #define FTM_POL_POL0_MASK 0x1u
Kojto 90:cb3d968589d8 6944 #define FTM_POL_POL0_SHIFT 0
Kojto 90:cb3d968589d8 6945 #define FTM_POL_POL1_MASK 0x2u
Kojto 90:cb3d968589d8 6946 #define FTM_POL_POL1_SHIFT 1
Kojto 90:cb3d968589d8 6947 #define FTM_POL_POL2_MASK 0x4u
Kojto 90:cb3d968589d8 6948 #define FTM_POL_POL2_SHIFT 2
Kojto 90:cb3d968589d8 6949 #define FTM_POL_POL3_MASK 0x8u
Kojto 90:cb3d968589d8 6950 #define FTM_POL_POL3_SHIFT 3
Kojto 90:cb3d968589d8 6951 #define FTM_POL_POL4_MASK 0x10u
Kojto 90:cb3d968589d8 6952 #define FTM_POL_POL4_SHIFT 4
Kojto 90:cb3d968589d8 6953 #define FTM_POL_POL5_MASK 0x20u
Kojto 90:cb3d968589d8 6954 #define FTM_POL_POL5_SHIFT 5
Kojto 90:cb3d968589d8 6955 #define FTM_POL_POL6_MASK 0x40u
Kojto 90:cb3d968589d8 6956 #define FTM_POL_POL6_SHIFT 6
Kojto 90:cb3d968589d8 6957 #define FTM_POL_POL7_MASK 0x80u
Kojto 90:cb3d968589d8 6958 #define FTM_POL_POL7_SHIFT 7
Kojto 90:cb3d968589d8 6959 /* FMS Bit Fields */
Kojto 90:cb3d968589d8 6960 #define FTM_FMS_FAULTF0_MASK 0x1u
Kojto 90:cb3d968589d8 6961 #define FTM_FMS_FAULTF0_SHIFT 0
Kojto 90:cb3d968589d8 6962 #define FTM_FMS_FAULTF1_MASK 0x2u
Kojto 90:cb3d968589d8 6963 #define FTM_FMS_FAULTF1_SHIFT 1
Kojto 90:cb3d968589d8 6964 #define FTM_FMS_FAULTF2_MASK 0x4u
Kojto 90:cb3d968589d8 6965 #define FTM_FMS_FAULTF2_SHIFT 2
Kojto 90:cb3d968589d8 6966 #define FTM_FMS_FAULTF3_MASK 0x8u
Kojto 90:cb3d968589d8 6967 #define FTM_FMS_FAULTF3_SHIFT 3
Kojto 90:cb3d968589d8 6968 #define FTM_FMS_FAULTIN_MASK 0x20u
Kojto 90:cb3d968589d8 6969 #define FTM_FMS_FAULTIN_SHIFT 5
Kojto 90:cb3d968589d8 6970 #define FTM_FMS_WPEN_MASK 0x40u
Kojto 90:cb3d968589d8 6971 #define FTM_FMS_WPEN_SHIFT 6
Kojto 90:cb3d968589d8 6972 #define FTM_FMS_FAULTF_MASK 0x80u
Kojto 90:cb3d968589d8 6973 #define FTM_FMS_FAULTF_SHIFT 7
Kojto 90:cb3d968589d8 6974 /* FILTER Bit Fields */
Kojto 90:cb3d968589d8 6975 #define FTM_FILTER_CH0FVAL_MASK 0xFu
Kojto 90:cb3d968589d8 6976 #define FTM_FILTER_CH0FVAL_SHIFT 0
Kojto 90:cb3d968589d8 6977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
Kojto 90:cb3d968589d8 6978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
Kojto 90:cb3d968589d8 6979 #define FTM_FILTER_CH1FVAL_SHIFT 4
Kojto 90:cb3d968589d8 6980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
Kojto 90:cb3d968589d8 6981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
Kojto 90:cb3d968589d8 6982 #define FTM_FILTER_CH2FVAL_SHIFT 8
Kojto 90:cb3d968589d8 6983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
Kojto 90:cb3d968589d8 6984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
Kojto 90:cb3d968589d8 6985 #define FTM_FILTER_CH3FVAL_SHIFT 12
Kojto 90:cb3d968589d8 6986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
Kojto 90:cb3d968589d8 6987 /* FLTCTRL Bit Fields */
Kojto 90:cb3d968589d8 6988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
Kojto 90:cb3d968589d8 6989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
Kojto 90:cb3d968589d8 6990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
Kojto 90:cb3d968589d8 6991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
Kojto 90:cb3d968589d8 6992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
Kojto 90:cb3d968589d8 6993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
Kojto 90:cb3d968589d8 6994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
Kojto 90:cb3d968589d8 6995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
Kojto 90:cb3d968589d8 6996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
Kojto 90:cb3d968589d8 6997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
Kojto 90:cb3d968589d8 6998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
Kojto 90:cb3d968589d8 6999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
Kojto 90:cb3d968589d8 7000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
Kojto 90:cb3d968589d8 7001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
Kojto 90:cb3d968589d8 7002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
Kojto 90:cb3d968589d8 7003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
Kojto 90:cb3d968589d8 7004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
Kojto 90:cb3d968589d8 7005 #define FTM_FLTCTRL_FFVAL_SHIFT 8
Kojto 90:cb3d968589d8 7006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
Kojto 90:cb3d968589d8 7007 /* QDCTRL Bit Fields */
Kojto 90:cb3d968589d8 7008 #define FTM_QDCTRL_QUADEN_MASK 0x1u
Kojto 90:cb3d968589d8 7009 #define FTM_QDCTRL_QUADEN_SHIFT 0
Kojto 90:cb3d968589d8 7010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
Kojto 90:cb3d968589d8 7011 #define FTM_QDCTRL_TOFDIR_SHIFT 1
Kojto 90:cb3d968589d8 7012 #define FTM_QDCTRL_QUADIR_MASK 0x4u
Kojto 90:cb3d968589d8 7013 #define FTM_QDCTRL_QUADIR_SHIFT 2
Kojto 90:cb3d968589d8 7014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
Kojto 90:cb3d968589d8 7015 #define FTM_QDCTRL_QUADMODE_SHIFT 3
Kojto 90:cb3d968589d8 7016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
Kojto 90:cb3d968589d8 7017 #define FTM_QDCTRL_PHBPOL_SHIFT 4
Kojto 90:cb3d968589d8 7018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
Kojto 90:cb3d968589d8 7019 #define FTM_QDCTRL_PHAPOL_SHIFT 5
Kojto 90:cb3d968589d8 7020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
Kojto 90:cb3d968589d8 7021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
Kojto 90:cb3d968589d8 7022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
Kojto 90:cb3d968589d8 7023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
Kojto 90:cb3d968589d8 7024 /* CONF Bit Fields */
Kojto 90:cb3d968589d8 7025 #define FTM_CONF_NUMTOF_MASK 0x1Fu
Kojto 90:cb3d968589d8 7026 #define FTM_CONF_NUMTOF_SHIFT 0
Kojto 90:cb3d968589d8 7027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
Kojto 90:cb3d968589d8 7028 #define FTM_CONF_BDMMODE_MASK 0xC0u
Kojto 90:cb3d968589d8 7029 #define FTM_CONF_BDMMODE_SHIFT 6
Kojto 90:cb3d968589d8 7030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
Kojto 90:cb3d968589d8 7031 #define FTM_CONF_GTBEEN_MASK 0x200u
Kojto 90:cb3d968589d8 7032 #define FTM_CONF_GTBEEN_SHIFT 9
Kojto 90:cb3d968589d8 7033 #define FTM_CONF_GTBEOUT_MASK 0x400u
Kojto 90:cb3d968589d8 7034 #define FTM_CONF_GTBEOUT_SHIFT 10
Kojto 90:cb3d968589d8 7035 /* FLTPOL Bit Fields */
Kojto 90:cb3d968589d8 7036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
Kojto 90:cb3d968589d8 7037 #define FTM_FLTPOL_FLT0POL_SHIFT 0
Kojto 90:cb3d968589d8 7038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
Kojto 90:cb3d968589d8 7039 #define FTM_FLTPOL_FLT1POL_SHIFT 1
Kojto 90:cb3d968589d8 7040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
Kojto 90:cb3d968589d8 7041 #define FTM_FLTPOL_FLT2POL_SHIFT 2
Kojto 90:cb3d968589d8 7042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
Kojto 90:cb3d968589d8 7043 #define FTM_FLTPOL_FLT3POL_SHIFT 3
Kojto 90:cb3d968589d8 7044 /* SYNCONF Bit Fields */
Kojto 90:cb3d968589d8 7045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
Kojto 90:cb3d968589d8 7046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
Kojto 90:cb3d968589d8 7047 #define FTM_SYNCONF_CNTINC_MASK 0x4u
Kojto 90:cb3d968589d8 7048 #define FTM_SYNCONF_CNTINC_SHIFT 2
Kojto 90:cb3d968589d8 7049 #define FTM_SYNCONF_INVC_MASK 0x10u
Kojto 90:cb3d968589d8 7050 #define FTM_SYNCONF_INVC_SHIFT 4
Kojto 90:cb3d968589d8 7051 #define FTM_SYNCONF_SWOC_MASK 0x20u
Kojto 90:cb3d968589d8 7052 #define FTM_SYNCONF_SWOC_SHIFT 5
Kojto 90:cb3d968589d8 7053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
Kojto 90:cb3d968589d8 7054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
Kojto 90:cb3d968589d8 7055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
Kojto 90:cb3d968589d8 7056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
Kojto 90:cb3d968589d8 7057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
Kojto 90:cb3d968589d8 7058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
Kojto 90:cb3d968589d8 7059 #define FTM_SYNCONF_SWOM_MASK 0x400u
Kojto 90:cb3d968589d8 7060 #define FTM_SYNCONF_SWOM_SHIFT 10
Kojto 90:cb3d968589d8 7061 #define FTM_SYNCONF_SWINVC_MASK 0x800u
Kojto 90:cb3d968589d8 7062 #define FTM_SYNCONF_SWINVC_SHIFT 11
Kojto 90:cb3d968589d8 7063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
Kojto 90:cb3d968589d8 7064 #define FTM_SYNCONF_SWSOC_SHIFT 12
Kojto 90:cb3d968589d8 7065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
Kojto 90:cb3d968589d8 7066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
Kojto 90:cb3d968589d8 7067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
Kojto 90:cb3d968589d8 7068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
Kojto 90:cb3d968589d8 7069 #define FTM_SYNCONF_HWOM_MASK 0x40000u
Kojto 90:cb3d968589d8 7070 #define FTM_SYNCONF_HWOM_SHIFT 18
Kojto 90:cb3d968589d8 7071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
Kojto 90:cb3d968589d8 7072 #define FTM_SYNCONF_HWINVC_SHIFT 19
Kojto 90:cb3d968589d8 7073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
Kojto 90:cb3d968589d8 7074 #define FTM_SYNCONF_HWSOC_SHIFT 20
Kojto 90:cb3d968589d8 7075 /* INVCTRL Bit Fields */
Kojto 90:cb3d968589d8 7076 #define FTM_INVCTRL_INV0EN_MASK 0x1u
Kojto 90:cb3d968589d8 7077 #define FTM_INVCTRL_INV0EN_SHIFT 0
Kojto 90:cb3d968589d8 7078 #define FTM_INVCTRL_INV1EN_MASK 0x2u
Kojto 90:cb3d968589d8 7079 #define FTM_INVCTRL_INV1EN_SHIFT 1
Kojto 90:cb3d968589d8 7080 #define FTM_INVCTRL_INV2EN_MASK 0x4u
Kojto 90:cb3d968589d8 7081 #define FTM_INVCTRL_INV2EN_SHIFT 2
Kojto 90:cb3d968589d8 7082 #define FTM_INVCTRL_INV3EN_MASK 0x8u
Kojto 90:cb3d968589d8 7083 #define FTM_INVCTRL_INV3EN_SHIFT 3
Kojto 90:cb3d968589d8 7084 /* SWOCTRL Bit Fields */
Kojto 90:cb3d968589d8 7085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
Kojto 90:cb3d968589d8 7086 #define FTM_SWOCTRL_CH0OC_SHIFT 0
Kojto 90:cb3d968589d8 7087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
Kojto 90:cb3d968589d8 7088 #define FTM_SWOCTRL_CH1OC_SHIFT 1
Kojto 90:cb3d968589d8 7089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
Kojto 90:cb3d968589d8 7090 #define FTM_SWOCTRL_CH2OC_SHIFT 2
Kojto 90:cb3d968589d8 7091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
Kojto 90:cb3d968589d8 7092 #define FTM_SWOCTRL_CH3OC_SHIFT 3
Kojto 90:cb3d968589d8 7093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
Kojto 90:cb3d968589d8 7094 #define FTM_SWOCTRL_CH4OC_SHIFT 4
Kojto 90:cb3d968589d8 7095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
Kojto 90:cb3d968589d8 7096 #define FTM_SWOCTRL_CH5OC_SHIFT 5
Kojto 90:cb3d968589d8 7097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
Kojto 90:cb3d968589d8 7098 #define FTM_SWOCTRL_CH6OC_SHIFT 6
Kojto 90:cb3d968589d8 7099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
Kojto 90:cb3d968589d8 7100 #define FTM_SWOCTRL_CH7OC_SHIFT 7
Kojto 90:cb3d968589d8 7101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
Kojto 90:cb3d968589d8 7102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
Kojto 90:cb3d968589d8 7103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
Kojto 90:cb3d968589d8 7104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
Kojto 90:cb3d968589d8 7105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
Kojto 90:cb3d968589d8 7106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
Kojto 90:cb3d968589d8 7107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
Kojto 90:cb3d968589d8 7108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
Kojto 90:cb3d968589d8 7109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
Kojto 90:cb3d968589d8 7110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
Kojto 90:cb3d968589d8 7111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
Kojto 90:cb3d968589d8 7112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
Kojto 90:cb3d968589d8 7113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
Kojto 90:cb3d968589d8 7114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
Kojto 90:cb3d968589d8 7115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
Kojto 90:cb3d968589d8 7116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
Kojto 90:cb3d968589d8 7117 /* PWMLOAD Bit Fields */
Kojto 90:cb3d968589d8 7118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
Kojto 90:cb3d968589d8 7119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
Kojto 90:cb3d968589d8 7120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
Kojto 90:cb3d968589d8 7121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
Kojto 90:cb3d968589d8 7122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
Kojto 90:cb3d968589d8 7123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
Kojto 90:cb3d968589d8 7124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
Kojto 90:cb3d968589d8 7125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
Kojto 90:cb3d968589d8 7126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
Kojto 90:cb3d968589d8 7127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
Kojto 90:cb3d968589d8 7128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
Kojto 90:cb3d968589d8 7129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
Kojto 90:cb3d968589d8 7130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
Kojto 90:cb3d968589d8 7131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
Kojto 90:cb3d968589d8 7132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
Kojto 90:cb3d968589d8 7133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
Kojto 90:cb3d968589d8 7134 #define FTM_PWMLOAD_LDOK_MASK 0x200u
Kojto 90:cb3d968589d8 7135 #define FTM_PWMLOAD_LDOK_SHIFT 9
Kojto 90:cb3d968589d8 7136
Kojto 90:cb3d968589d8 7137 /*!
Kojto 90:cb3d968589d8 7138 * @}
Kojto 90:cb3d968589d8 7139 */ /* end of group FTM_Register_Masks */
Kojto 90:cb3d968589d8 7140
Kojto 90:cb3d968589d8 7141
Kojto 90:cb3d968589d8 7142 /* FTM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7143 /** Peripheral FTM0 base address */
Kojto 90:cb3d968589d8 7144 #define FTM0_BASE (0x40038000u)
Kojto 90:cb3d968589d8 7145 /** Peripheral FTM0 base pointer */
Kojto 90:cb3d968589d8 7146 #define FTM0 ((FTM_Type *)FTM0_BASE)
Kojto 90:cb3d968589d8 7147 #define FTM0_BASE_PTR (FTM0)
Kojto 90:cb3d968589d8 7148 /** Peripheral FTM1 base address */
Kojto 90:cb3d968589d8 7149 #define FTM1_BASE (0x40039000u)
Kojto 90:cb3d968589d8 7150 /** Peripheral FTM1 base pointer */
Kojto 90:cb3d968589d8 7151 #define FTM1 ((FTM_Type *)FTM1_BASE)
Kojto 90:cb3d968589d8 7152 #define FTM1_BASE_PTR (FTM1)
Kojto 90:cb3d968589d8 7153 /** Peripheral FTM2 base address */
Kojto 90:cb3d968589d8 7154 #define FTM2_BASE (0x4003A000u)
Kojto 90:cb3d968589d8 7155 /** Peripheral FTM2 base pointer */
Kojto 90:cb3d968589d8 7156 #define FTM2 ((FTM_Type *)FTM2_BASE)
Kojto 90:cb3d968589d8 7157 #define FTM2_BASE_PTR (FTM2)
Kojto 90:cb3d968589d8 7158 /** Peripheral FTM3 base address */
Kojto 90:cb3d968589d8 7159 #define FTM3_BASE (0x400B9000u)
Kojto 90:cb3d968589d8 7160 /** Peripheral FTM3 base pointer */
Kojto 90:cb3d968589d8 7161 #define FTM3 ((FTM_Type *)FTM3_BASE)
Kojto 90:cb3d968589d8 7162 #define FTM3_BASE_PTR (FTM3)
Kojto 90:cb3d968589d8 7163 /** Array initializer of FTM peripheral base addresses */
Kojto 90:cb3d968589d8 7164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
Kojto 90:cb3d968589d8 7165 /** Array initializer of FTM peripheral base pointers */
Kojto 90:cb3d968589d8 7166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
Kojto 90:cb3d968589d8 7167 /** Interrupt vectors for the FTM peripheral type */
Kojto 90:cb3d968589d8 7168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
Kojto 90:cb3d968589d8 7169
Kojto 90:cb3d968589d8 7170 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7171 -- FTM - Register accessor macros
Kojto 90:cb3d968589d8 7172 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7173
Kojto 90:cb3d968589d8 7174 /*!
Kojto 90:cb3d968589d8 7175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
Kojto 90:cb3d968589d8 7176 * @{
Kojto 90:cb3d968589d8 7177 */
Kojto 90:cb3d968589d8 7178
Kojto 90:cb3d968589d8 7179
Kojto 90:cb3d968589d8 7180 /* FTM - Register instance definitions */
Kojto 90:cb3d968589d8 7181 /* FTM0 */
Kojto 90:cb3d968589d8 7182 #define FTM0_SC FTM_SC_REG(FTM0)
Kojto 90:cb3d968589d8 7183 #define FTM0_CNT FTM_CNT_REG(FTM0)
Kojto 90:cb3d968589d8 7184 #define FTM0_MOD FTM_MOD_REG(FTM0)
Kojto 90:cb3d968589d8 7185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
Kojto 90:cb3d968589d8 7186 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
Kojto 90:cb3d968589d8 7187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
Kojto 90:cb3d968589d8 7188 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
Kojto 90:cb3d968589d8 7189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
Kojto 90:cb3d968589d8 7190 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
Kojto 90:cb3d968589d8 7191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
Kojto 90:cb3d968589d8 7192 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
Kojto 90:cb3d968589d8 7193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
Kojto 90:cb3d968589d8 7194 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
Kojto 90:cb3d968589d8 7195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
Kojto 90:cb3d968589d8 7196 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
Kojto 90:cb3d968589d8 7197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
Kojto 90:cb3d968589d8 7198 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
Kojto 90:cb3d968589d8 7199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
Kojto 90:cb3d968589d8 7200 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
Kojto 90:cb3d968589d8 7201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
Kojto 90:cb3d968589d8 7202 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
Kojto 90:cb3d968589d8 7203 #define FTM0_MODE FTM_MODE_REG(FTM0)
Kojto 90:cb3d968589d8 7204 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
Kojto 90:cb3d968589d8 7205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
Kojto 90:cb3d968589d8 7206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
Kojto 90:cb3d968589d8 7207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
Kojto 90:cb3d968589d8 7208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
Kojto 90:cb3d968589d8 7209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
Kojto 90:cb3d968589d8 7210 #define FTM0_POL FTM_POL_REG(FTM0)
Kojto 90:cb3d968589d8 7211 #define FTM0_FMS FTM_FMS_REG(FTM0)
Kojto 90:cb3d968589d8 7212 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
Kojto 90:cb3d968589d8 7213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
Kojto 90:cb3d968589d8 7214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
Kojto 90:cb3d968589d8 7215 #define FTM0_CONF FTM_CONF_REG(FTM0)
Kojto 90:cb3d968589d8 7216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
Kojto 90:cb3d968589d8 7217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
Kojto 90:cb3d968589d8 7218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
Kojto 90:cb3d968589d8 7219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
Kojto 90:cb3d968589d8 7220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
Kojto 90:cb3d968589d8 7221 /* FTM1 */
Kojto 90:cb3d968589d8 7222 #define FTM1_SC FTM_SC_REG(FTM1)
Kojto 90:cb3d968589d8 7223 #define FTM1_CNT FTM_CNT_REG(FTM1)
Kojto 90:cb3d968589d8 7224 #define FTM1_MOD FTM_MOD_REG(FTM1)
Kojto 90:cb3d968589d8 7225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
Kojto 90:cb3d968589d8 7226 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
Kojto 90:cb3d968589d8 7227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
Kojto 90:cb3d968589d8 7228 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
Kojto 90:cb3d968589d8 7229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
Kojto 90:cb3d968589d8 7230 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
Kojto 90:cb3d968589d8 7231 #define FTM1_MODE FTM_MODE_REG(FTM1)
Kojto 90:cb3d968589d8 7232 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
Kojto 90:cb3d968589d8 7233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
Kojto 90:cb3d968589d8 7234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
Kojto 90:cb3d968589d8 7235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
Kojto 90:cb3d968589d8 7236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
Kojto 90:cb3d968589d8 7237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
Kojto 90:cb3d968589d8 7238 #define FTM1_POL FTM_POL_REG(FTM1)
Kojto 90:cb3d968589d8 7239 #define FTM1_FMS FTM_FMS_REG(FTM1)
Kojto 90:cb3d968589d8 7240 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
Kojto 90:cb3d968589d8 7241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
Kojto 90:cb3d968589d8 7242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
Kojto 90:cb3d968589d8 7243 #define FTM1_CONF FTM_CONF_REG(FTM1)
Kojto 90:cb3d968589d8 7244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
Kojto 90:cb3d968589d8 7245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
Kojto 90:cb3d968589d8 7246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
Kojto 90:cb3d968589d8 7247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
Kojto 90:cb3d968589d8 7248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
Kojto 90:cb3d968589d8 7249 /* FTM2 */
Kojto 90:cb3d968589d8 7250 #define FTM2_SC FTM_SC_REG(FTM2)
Kojto 90:cb3d968589d8 7251 #define FTM2_CNT FTM_CNT_REG(FTM2)
Kojto 90:cb3d968589d8 7252 #define FTM2_MOD FTM_MOD_REG(FTM2)
Kojto 90:cb3d968589d8 7253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
Kojto 90:cb3d968589d8 7254 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
Kojto 90:cb3d968589d8 7255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
Kojto 90:cb3d968589d8 7256 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
Kojto 90:cb3d968589d8 7257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
Kojto 90:cb3d968589d8 7258 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
Kojto 90:cb3d968589d8 7259 #define FTM2_MODE FTM_MODE_REG(FTM2)
Kojto 90:cb3d968589d8 7260 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
Kojto 90:cb3d968589d8 7261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
Kojto 90:cb3d968589d8 7262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
Kojto 90:cb3d968589d8 7263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
Kojto 90:cb3d968589d8 7264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
Kojto 90:cb3d968589d8 7265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
Kojto 90:cb3d968589d8 7266 #define FTM2_POL FTM_POL_REG(FTM2)
Kojto 90:cb3d968589d8 7267 #define FTM2_FMS FTM_FMS_REG(FTM2)
Kojto 90:cb3d968589d8 7268 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
Kojto 90:cb3d968589d8 7269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
Kojto 90:cb3d968589d8 7270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
Kojto 90:cb3d968589d8 7271 #define FTM2_CONF FTM_CONF_REG(FTM2)
Kojto 90:cb3d968589d8 7272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
Kojto 90:cb3d968589d8 7273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
Kojto 90:cb3d968589d8 7274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
Kojto 90:cb3d968589d8 7275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
Kojto 90:cb3d968589d8 7276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
Kojto 90:cb3d968589d8 7277 /* FTM3 */
Kojto 90:cb3d968589d8 7278 #define FTM3_SC FTM_SC_REG(FTM3)
Kojto 90:cb3d968589d8 7279 #define FTM3_CNT FTM_CNT_REG(FTM3)
Kojto 90:cb3d968589d8 7280 #define FTM3_MOD FTM_MOD_REG(FTM3)
Kojto 90:cb3d968589d8 7281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
Kojto 90:cb3d968589d8 7282 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
Kojto 90:cb3d968589d8 7283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
Kojto 90:cb3d968589d8 7284 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
Kojto 90:cb3d968589d8 7285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
Kojto 90:cb3d968589d8 7286 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
Kojto 90:cb3d968589d8 7287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
Kojto 90:cb3d968589d8 7288 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
Kojto 90:cb3d968589d8 7289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
Kojto 90:cb3d968589d8 7290 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
Kojto 90:cb3d968589d8 7291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
Kojto 90:cb3d968589d8 7292 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
Kojto 90:cb3d968589d8 7293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
Kojto 90:cb3d968589d8 7294 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
Kojto 90:cb3d968589d8 7295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
Kojto 90:cb3d968589d8 7296 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
Kojto 90:cb3d968589d8 7297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
Kojto 90:cb3d968589d8 7298 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
Kojto 90:cb3d968589d8 7299 #define FTM3_MODE FTM_MODE_REG(FTM3)
Kojto 90:cb3d968589d8 7300 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
Kojto 90:cb3d968589d8 7301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
Kojto 90:cb3d968589d8 7302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
Kojto 90:cb3d968589d8 7303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
Kojto 90:cb3d968589d8 7304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
Kojto 90:cb3d968589d8 7305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
Kojto 90:cb3d968589d8 7306 #define FTM3_POL FTM_POL_REG(FTM3)
Kojto 90:cb3d968589d8 7307 #define FTM3_FMS FTM_FMS_REG(FTM3)
Kojto 90:cb3d968589d8 7308 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
Kojto 90:cb3d968589d8 7309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
Kojto 90:cb3d968589d8 7310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
Kojto 90:cb3d968589d8 7311 #define FTM3_CONF FTM_CONF_REG(FTM3)
Kojto 90:cb3d968589d8 7312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
Kojto 90:cb3d968589d8 7313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
Kojto 90:cb3d968589d8 7314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
Kojto 90:cb3d968589d8 7315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
Kojto 90:cb3d968589d8 7316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
Kojto 90:cb3d968589d8 7317
Kojto 90:cb3d968589d8 7318 /* FTM - Register array accessors */
Kojto 90:cb3d968589d8 7319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
Kojto 90:cb3d968589d8 7320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
Kojto 90:cb3d968589d8 7321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
Kojto 90:cb3d968589d8 7322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
Kojto 90:cb3d968589d8 7323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
Kojto 90:cb3d968589d8 7324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
Kojto 90:cb3d968589d8 7325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
Kojto 90:cb3d968589d8 7326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
Kojto 90:cb3d968589d8 7327
Kojto 90:cb3d968589d8 7328 /*!
Kojto 90:cb3d968589d8 7329 * @}
Kojto 90:cb3d968589d8 7330 */ /* end of group FTM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7331
Kojto 90:cb3d968589d8 7332
Kojto 90:cb3d968589d8 7333 /*!
Kojto 90:cb3d968589d8 7334 * @}
Kojto 90:cb3d968589d8 7335 */ /* end of group FTM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7336
Kojto 90:cb3d968589d8 7337
Kojto 90:cb3d968589d8 7338 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7339 -- GPIO Peripheral Access Layer
Kojto 90:cb3d968589d8 7340 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7341
Kojto 90:cb3d968589d8 7342 /*!
Kojto 90:cb3d968589d8 7343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Kojto 90:cb3d968589d8 7344 * @{
Kojto 90:cb3d968589d8 7345 */
Kojto 90:cb3d968589d8 7346
Kojto 90:cb3d968589d8 7347 /** GPIO - Register Layout Typedef */
Kojto 90:cb3d968589d8 7348 typedef struct {
Kojto 90:cb3d968589d8 7349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
Kojto 90:cb3d968589d8 7350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
Kojto 90:cb3d968589d8 7351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
Kojto 90:cb3d968589d8 7352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
Kojto 90:cb3d968589d8 7353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
Kojto 90:cb3d968589d8 7354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
Kojto 90:cb3d968589d8 7355 } GPIO_Type, *GPIO_MemMapPtr;
Kojto 90:cb3d968589d8 7356
Kojto 90:cb3d968589d8 7357 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7358 -- GPIO - Register accessor macros
Kojto 90:cb3d968589d8 7359 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7360
Kojto 90:cb3d968589d8 7361 /*!
Kojto 90:cb3d968589d8 7362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Kojto 90:cb3d968589d8 7363 * @{
Kojto 90:cb3d968589d8 7364 */
Kojto 90:cb3d968589d8 7365
Kojto 90:cb3d968589d8 7366
Kojto 90:cb3d968589d8 7367 /* GPIO - Register accessors */
Kojto 90:cb3d968589d8 7368 #define GPIO_PDOR_REG(base) ((base)->PDOR)
Kojto 90:cb3d968589d8 7369 #define GPIO_PSOR_REG(base) ((base)->PSOR)
Kojto 90:cb3d968589d8 7370 #define GPIO_PCOR_REG(base) ((base)->PCOR)
Kojto 90:cb3d968589d8 7371 #define GPIO_PTOR_REG(base) ((base)->PTOR)
Kojto 90:cb3d968589d8 7372 #define GPIO_PDIR_REG(base) ((base)->PDIR)
Kojto 90:cb3d968589d8 7373 #define GPIO_PDDR_REG(base) ((base)->PDDR)
Kojto 90:cb3d968589d8 7374
Kojto 90:cb3d968589d8 7375 /*!
Kojto 90:cb3d968589d8 7376 * @}
Kojto 90:cb3d968589d8 7377 */ /* end of group GPIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7378
Kojto 90:cb3d968589d8 7379
Kojto 90:cb3d968589d8 7380 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7381 -- GPIO Register Masks
Kojto 90:cb3d968589d8 7382 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7383
Kojto 90:cb3d968589d8 7384 /*!
Kojto 90:cb3d968589d8 7385 * @addtogroup GPIO_Register_Masks GPIO Register Masks
Kojto 90:cb3d968589d8 7386 * @{
Kojto 90:cb3d968589d8 7387 */
Kojto 90:cb3d968589d8 7388
Kojto 90:cb3d968589d8 7389 /* PDOR Bit Fields */
Kojto 90:cb3d968589d8 7390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7391 #define GPIO_PDOR_PDO_SHIFT 0
Kojto 90:cb3d968589d8 7392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
Kojto 90:cb3d968589d8 7393 /* PSOR Bit Fields */
Kojto 90:cb3d968589d8 7394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7395 #define GPIO_PSOR_PTSO_SHIFT 0
Kojto 90:cb3d968589d8 7396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
Kojto 90:cb3d968589d8 7397 /* PCOR Bit Fields */
Kojto 90:cb3d968589d8 7398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7399 #define GPIO_PCOR_PTCO_SHIFT 0
Kojto 90:cb3d968589d8 7400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
Kojto 90:cb3d968589d8 7401 /* PTOR Bit Fields */
Kojto 90:cb3d968589d8 7402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7403 #define GPIO_PTOR_PTTO_SHIFT 0
Kojto 90:cb3d968589d8 7404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
Kojto 90:cb3d968589d8 7405 /* PDIR Bit Fields */
Kojto 90:cb3d968589d8 7406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7407 #define GPIO_PDIR_PDI_SHIFT 0
Kojto 90:cb3d968589d8 7408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
Kojto 90:cb3d968589d8 7409 /* PDDR Bit Fields */
Kojto 90:cb3d968589d8 7410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7411 #define GPIO_PDDR_PDD_SHIFT 0
Kojto 90:cb3d968589d8 7412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
Kojto 90:cb3d968589d8 7413
Kojto 90:cb3d968589d8 7414 /*!
Kojto 90:cb3d968589d8 7415 * @}
Kojto 90:cb3d968589d8 7416 */ /* end of group GPIO_Register_Masks */
Kojto 90:cb3d968589d8 7417
Kojto 90:cb3d968589d8 7418
Kojto 90:cb3d968589d8 7419 /* GPIO - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7420 /** Peripheral PTA base address */
Kojto 90:cb3d968589d8 7421 #define PTA_BASE (0x400FF000u)
Kojto 90:cb3d968589d8 7422 /** Peripheral PTA base pointer */
Kojto 90:cb3d968589d8 7423 #define PTA ((GPIO_Type *)PTA_BASE)
Kojto 90:cb3d968589d8 7424 #define PTA_BASE_PTR (PTA)
Kojto 90:cb3d968589d8 7425 /** Peripheral PTB base address */
Kojto 90:cb3d968589d8 7426 #define PTB_BASE (0x400FF040u)
Kojto 90:cb3d968589d8 7427 /** Peripheral PTB base pointer */
Kojto 90:cb3d968589d8 7428 #define PTB ((GPIO_Type *)PTB_BASE)
Kojto 90:cb3d968589d8 7429 #define PTB_BASE_PTR (PTB)
Kojto 90:cb3d968589d8 7430 /** Peripheral PTC base address */
Kojto 90:cb3d968589d8 7431 #define PTC_BASE (0x400FF080u)
Kojto 90:cb3d968589d8 7432 /** Peripheral PTC base pointer */
Kojto 90:cb3d968589d8 7433 #define PTC ((GPIO_Type *)PTC_BASE)
Kojto 90:cb3d968589d8 7434 #define PTC_BASE_PTR (PTC)
Kojto 90:cb3d968589d8 7435 /** Peripheral PTD base address */
Kojto 90:cb3d968589d8 7436 #define PTD_BASE (0x400FF0C0u)
Kojto 90:cb3d968589d8 7437 /** Peripheral PTD base pointer */
Kojto 90:cb3d968589d8 7438 #define PTD ((GPIO_Type *)PTD_BASE)
Kojto 90:cb3d968589d8 7439 #define PTD_BASE_PTR (PTD)
Kojto 90:cb3d968589d8 7440 /** Peripheral PTE base address */
Kojto 90:cb3d968589d8 7441 #define PTE_BASE (0x400FF100u)
Kojto 90:cb3d968589d8 7442 /** Peripheral PTE base pointer */
Kojto 90:cb3d968589d8 7443 #define PTE ((GPIO_Type *)PTE_BASE)
Kojto 90:cb3d968589d8 7444 #define PTE_BASE_PTR (PTE)
Kojto 90:cb3d968589d8 7445 /** Array initializer of GPIO peripheral base addresses */
Kojto 90:cb3d968589d8 7446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
Kojto 90:cb3d968589d8 7447 /** Array initializer of GPIO peripheral base pointers */
Kojto 90:cb3d968589d8 7448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
Kojto 90:cb3d968589d8 7449
Kojto 90:cb3d968589d8 7450 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7451 -- GPIO - Register accessor macros
Kojto 90:cb3d968589d8 7452 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7453
Kojto 90:cb3d968589d8 7454 /*!
Kojto 90:cb3d968589d8 7455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Kojto 90:cb3d968589d8 7456 * @{
Kojto 90:cb3d968589d8 7457 */
Kojto 90:cb3d968589d8 7458
Kojto 90:cb3d968589d8 7459
Kojto 90:cb3d968589d8 7460 /* GPIO - Register instance definitions */
Kojto 90:cb3d968589d8 7461 /* PTA */
Kojto 90:cb3d968589d8 7462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
Kojto 90:cb3d968589d8 7463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
Kojto 90:cb3d968589d8 7464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
Kojto 90:cb3d968589d8 7465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
Kojto 90:cb3d968589d8 7466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
Kojto 90:cb3d968589d8 7467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
Kojto 90:cb3d968589d8 7468 /* PTB */
Kojto 90:cb3d968589d8 7469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
Kojto 90:cb3d968589d8 7470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
Kojto 90:cb3d968589d8 7471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
Kojto 90:cb3d968589d8 7472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
Kojto 90:cb3d968589d8 7473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
Kojto 90:cb3d968589d8 7474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
Kojto 90:cb3d968589d8 7475 /* PTC */
Kojto 90:cb3d968589d8 7476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
Kojto 90:cb3d968589d8 7477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
Kojto 90:cb3d968589d8 7478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
Kojto 90:cb3d968589d8 7479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
Kojto 90:cb3d968589d8 7480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
Kojto 90:cb3d968589d8 7481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
Kojto 90:cb3d968589d8 7482 /* PTD */
Kojto 90:cb3d968589d8 7483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
Kojto 90:cb3d968589d8 7484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
Kojto 90:cb3d968589d8 7485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
Kojto 90:cb3d968589d8 7486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
Kojto 90:cb3d968589d8 7487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
Kojto 90:cb3d968589d8 7488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
Kojto 90:cb3d968589d8 7489 /* PTE */
Kojto 90:cb3d968589d8 7490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
Kojto 90:cb3d968589d8 7491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
Kojto 90:cb3d968589d8 7492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
Kojto 90:cb3d968589d8 7493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
Kojto 90:cb3d968589d8 7494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
Kojto 90:cb3d968589d8 7495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
Kojto 90:cb3d968589d8 7496
Kojto 90:cb3d968589d8 7497 /*!
Kojto 90:cb3d968589d8 7498 * @}
Kojto 90:cb3d968589d8 7499 */ /* end of group GPIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7500
Kojto 90:cb3d968589d8 7501
Kojto 90:cb3d968589d8 7502 /*!
Kojto 90:cb3d968589d8 7503 * @}
Kojto 90:cb3d968589d8 7504 */ /* end of group GPIO_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7505
Kojto 90:cb3d968589d8 7506
Kojto 90:cb3d968589d8 7507 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7508 -- I2C Peripheral Access Layer
Kojto 90:cb3d968589d8 7509 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7510
Kojto 90:cb3d968589d8 7511 /*!
Kojto 90:cb3d968589d8 7512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Kojto 90:cb3d968589d8 7513 * @{
Kojto 90:cb3d968589d8 7514 */
Kojto 90:cb3d968589d8 7515
Kojto 90:cb3d968589d8 7516 /** I2C - Register Layout Typedef */
Kojto 90:cb3d968589d8 7517 typedef struct {
Kojto 90:cb3d968589d8 7518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 7519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
Kojto 90:cb3d968589d8 7520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
Kojto 90:cb3d968589d8 7521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
Kojto 90:cb3d968589d8 7522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
Kojto 90:cb3d968589d8 7523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
Kojto 90:cb3d968589d8 7524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
Kojto 90:cb3d968589d8 7525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
Kojto 90:cb3d968589d8 7526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
Kojto 90:cb3d968589d8 7527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
Kojto 90:cb3d968589d8 7528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
Kojto 90:cb3d968589d8 7529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
Kojto 90:cb3d968589d8 7530 } I2C_Type, *I2C_MemMapPtr;
Kojto 90:cb3d968589d8 7531
Kojto 90:cb3d968589d8 7532 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7533 -- I2C - Register accessor macros
Kojto 90:cb3d968589d8 7534 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7535
Kojto 90:cb3d968589d8 7536 /*!
Kojto 90:cb3d968589d8 7537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Kojto 90:cb3d968589d8 7538 * @{
Kojto 90:cb3d968589d8 7539 */
Kojto 90:cb3d968589d8 7540
Kojto 90:cb3d968589d8 7541
Kojto 90:cb3d968589d8 7542 /* I2C - Register accessors */
Kojto 90:cb3d968589d8 7543 #define I2C_A1_REG(base) ((base)->A1)
Kojto 90:cb3d968589d8 7544 #define I2C_F_REG(base) ((base)->F)
Kojto 90:cb3d968589d8 7545 #define I2C_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 7546 #define I2C_S_REG(base) ((base)->S)
Kojto 90:cb3d968589d8 7547 #define I2C_D_REG(base) ((base)->D)
Kojto 90:cb3d968589d8 7548 #define I2C_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 7549 #define I2C_FLT_REG(base) ((base)->FLT)
Kojto 90:cb3d968589d8 7550 #define I2C_RA_REG(base) ((base)->RA)
Kojto 90:cb3d968589d8 7551 #define I2C_SMB_REG(base) ((base)->SMB)
Kojto 90:cb3d968589d8 7552 #define I2C_A2_REG(base) ((base)->A2)
Kojto 90:cb3d968589d8 7553 #define I2C_SLTH_REG(base) ((base)->SLTH)
Kojto 90:cb3d968589d8 7554 #define I2C_SLTL_REG(base) ((base)->SLTL)
Kojto 90:cb3d968589d8 7555
Kojto 90:cb3d968589d8 7556 /*!
Kojto 90:cb3d968589d8 7557 * @}
Kojto 90:cb3d968589d8 7558 */ /* end of group I2C_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7559
Kojto 90:cb3d968589d8 7560
Kojto 90:cb3d968589d8 7561 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7562 -- I2C Register Masks
Kojto 90:cb3d968589d8 7563 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7564
Kojto 90:cb3d968589d8 7565 /*!
Kojto 90:cb3d968589d8 7566 * @addtogroup I2C_Register_Masks I2C Register Masks
Kojto 90:cb3d968589d8 7567 * @{
Kojto 90:cb3d968589d8 7568 */
Kojto 90:cb3d968589d8 7569
Kojto 90:cb3d968589d8 7570 /* A1 Bit Fields */
Kojto 90:cb3d968589d8 7571 #define I2C_A1_AD_MASK 0xFEu
Kojto 90:cb3d968589d8 7572 #define I2C_A1_AD_SHIFT 1
Kojto 90:cb3d968589d8 7573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
Kojto 90:cb3d968589d8 7574 /* F Bit Fields */
Kojto 90:cb3d968589d8 7575 #define I2C_F_ICR_MASK 0x3Fu
Kojto 90:cb3d968589d8 7576 #define I2C_F_ICR_SHIFT 0
Kojto 90:cb3d968589d8 7577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
Kojto 90:cb3d968589d8 7578 #define I2C_F_MULT_MASK 0xC0u
Kojto 90:cb3d968589d8 7579 #define I2C_F_MULT_SHIFT 6
Kojto 90:cb3d968589d8 7580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
Kojto 90:cb3d968589d8 7581 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 7582 #define I2C_C1_DMAEN_MASK 0x1u
Kojto 90:cb3d968589d8 7583 #define I2C_C1_DMAEN_SHIFT 0
Kojto 90:cb3d968589d8 7584 #define I2C_C1_WUEN_MASK 0x2u
Kojto 90:cb3d968589d8 7585 #define I2C_C1_WUEN_SHIFT 1
Kojto 90:cb3d968589d8 7586 #define I2C_C1_RSTA_MASK 0x4u
Kojto 90:cb3d968589d8 7587 #define I2C_C1_RSTA_SHIFT 2
Kojto 90:cb3d968589d8 7588 #define I2C_C1_TXAK_MASK 0x8u
Kojto 90:cb3d968589d8 7589 #define I2C_C1_TXAK_SHIFT 3
Kojto 90:cb3d968589d8 7590 #define I2C_C1_TX_MASK 0x10u
Kojto 90:cb3d968589d8 7591 #define I2C_C1_TX_SHIFT 4
Kojto 90:cb3d968589d8 7592 #define I2C_C1_MST_MASK 0x20u
Kojto 90:cb3d968589d8 7593 #define I2C_C1_MST_SHIFT 5
Kojto 90:cb3d968589d8 7594 #define I2C_C1_IICIE_MASK 0x40u
Kojto 90:cb3d968589d8 7595 #define I2C_C1_IICIE_SHIFT 6
Kojto 90:cb3d968589d8 7596 #define I2C_C1_IICEN_MASK 0x80u
Kojto 90:cb3d968589d8 7597 #define I2C_C1_IICEN_SHIFT 7
Kojto 90:cb3d968589d8 7598 /* S Bit Fields */
Kojto 90:cb3d968589d8 7599 #define I2C_S_RXAK_MASK 0x1u
Kojto 90:cb3d968589d8 7600 #define I2C_S_RXAK_SHIFT 0
Kojto 90:cb3d968589d8 7601 #define I2C_S_IICIF_MASK 0x2u
Kojto 90:cb3d968589d8 7602 #define I2C_S_IICIF_SHIFT 1
Kojto 90:cb3d968589d8 7603 #define I2C_S_SRW_MASK 0x4u
Kojto 90:cb3d968589d8 7604 #define I2C_S_SRW_SHIFT 2
Kojto 90:cb3d968589d8 7605 #define I2C_S_RAM_MASK 0x8u
Kojto 90:cb3d968589d8 7606 #define I2C_S_RAM_SHIFT 3
Kojto 90:cb3d968589d8 7607 #define I2C_S_ARBL_MASK 0x10u
Kojto 90:cb3d968589d8 7608 #define I2C_S_ARBL_SHIFT 4
Kojto 90:cb3d968589d8 7609 #define I2C_S_BUSY_MASK 0x20u
Kojto 90:cb3d968589d8 7610 #define I2C_S_BUSY_SHIFT 5
Kojto 90:cb3d968589d8 7611 #define I2C_S_IAAS_MASK 0x40u
Kojto 90:cb3d968589d8 7612 #define I2C_S_IAAS_SHIFT 6
Kojto 90:cb3d968589d8 7613 #define I2C_S_TCF_MASK 0x80u
Kojto 90:cb3d968589d8 7614 #define I2C_S_TCF_SHIFT 7
Kojto 90:cb3d968589d8 7615 /* D Bit Fields */
Kojto 90:cb3d968589d8 7616 #define I2C_D_DATA_MASK 0xFFu
Kojto 90:cb3d968589d8 7617 #define I2C_D_DATA_SHIFT 0
Kojto 90:cb3d968589d8 7618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
Kojto 90:cb3d968589d8 7619 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 7620 #define I2C_C2_AD_MASK 0x7u
Kojto 90:cb3d968589d8 7621 #define I2C_C2_AD_SHIFT 0
Kojto 90:cb3d968589d8 7622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
Kojto 90:cb3d968589d8 7623 #define I2C_C2_RMEN_MASK 0x8u
Kojto 90:cb3d968589d8 7624 #define I2C_C2_RMEN_SHIFT 3
Kojto 90:cb3d968589d8 7625 #define I2C_C2_SBRC_MASK 0x10u
Kojto 90:cb3d968589d8 7626 #define I2C_C2_SBRC_SHIFT 4
Kojto 90:cb3d968589d8 7627 #define I2C_C2_HDRS_MASK 0x20u
Kojto 90:cb3d968589d8 7628 #define I2C_C2_HDRS_SHIFT 5
Kojto 90:cb3d968589d8 7629 #define I2C_C2_ADEXT_MASK 0x40u
Kojto 90:cb3d968589d8 7630 #define I2C_C2_ADEXT_SHIFT 6
Kojto 90:cb3d968589d8 7631 #define I2C_C2_GCAEN_MASK 0x80u
Kojto 90:cb3d968589d8 7632 #define I2C_C2_GCAEN_SHIFT 7
Kojto 90:cb3d968589d8 7633 /* FLT Bit Fields */
Kojto 90:cb3d968589d8 7634 #define I2C_FLT_FLT_MASK 0xFu
Kojto 90:cb3d968589d8 7635 #define I2C_FLT_FLT_SHIFT 0
Kojto 90:cb3d968589d8 7636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
Kojto 90:cb3d968589d8 7637 #define I2C_FLT_STARTF_MASK 0x10u
Kojto 90:cb3d968589d8 7638 #define I2C_FLT_STARTF_SHIFT 4
Kojto 90:cb3d968589d8 7639 #define I2C_FLT_SSIE_MASK 0x20u
Kojto 90:cb3d968589d8 7640 #define I2C_FLT_SSIE_SHIFT 5
Kojto 90:cb3d968589d8 7641 #define I2C_FLT_STOPF_MASK 0x40u
Kojto 90:cb3d968589d8 7642 #define I2C_FLT_STOPF_SHIFT 6
Kojto 90:cb3d968589d8 7643 #define I2C_FLT_SHEN_MASK 0x80u
Kojto 90:cb3d968589d8 7644 #define I2C_FLT_SHEN_SHIFT 7
Kojto 90:cb3d968589d8 7645 /* RA Bit Fields */
Kojto 90:cb3d968589d8 7646 #define I2C_RA_RAD_MASK 0xFEu
Kojto 90:cb3d968589d8 7647 #define I2C_RA_RAD_SHIFT 1
Kojto 90:cb3d968589d8 7648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
Kojto 90:cb3d968589d8 7649 /* SMB Bit Fields */
Kojto 90:cb3d968589d8 7650 #define I2C_SMB_SHTF2IE_MASK 0x1u
Kojto 90:cb3d968589d8 7651 #define I2C_SMB_SHTF2IE_SHIFT 0
Kojto 90:cb3d968589d8 7652 #define I2C_SMB_SHTF2_MASK 0x2u
Kojto 90:cb3d968589d8 7653 #define I2C_SMB_SHTF2_SHIFT 1
Kojto 90:cb3d968589d8 7654 #define I2C_SMB_SHTF1_MASK 0x4u
Kojto 90:cb3d968589d8 7655 #define I2C_SMB_SHTF1_SHIFT 2
Kojto 90:cb3d968589d8 7656 #define I2C_SMB_SLTF_MASK 0x8u
Kojto 90:cb3d968589d8 7657 #define I2C_SMB_SLTF_SHIFT 3
Kojto 90:cb3d968589d8 7658 #define I2C_SMB_TCKSEL_MASK 0x10u
Kojto 90:cb3d968589d8 7659 #define I2C_SMB_TCKSEL_SHIFT 4
Kojto 90:cb3d968589d8 7660 #define I2C_SMB_SIICAEN_MASK 0x20u
Kojto 90:cb3d968589d8 7661 #define I2C_SMB_SIICAEN_SHIFT 5
Kojto 90:cb3d968589d8 7662 #define I2C_SMB_ALERTEN_MASK 0x40u
Kojto 90:cb3d968589d8 7663 #define I2C_SMB_ALERTEN_SHIFT 6
Kojto 90:cb3d968589d8 7664 #define I2C_SMB_FACK_MASK 0x80u
Kojto 90:cb3d968589d8 7665 #define I2C_SMB_FACK_SHIFT 7
Kojto 90:cb3d968589d8 7666 /* A2 Bit Fields */
Kojto 90:cb3d968589d8 7667 #define I2C_A2_SAD_MASK 0xFEu
Kojto 90:cb3d968589d8 7668 #define I2C_A2_SAD_SHIFT 1
Kojto 90:cb3d968589d8 7669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
Kojto 90:cb3d968589d8 7670 /* SLTH Bit Fields */
Kojto 90:cb3d968589d8 7671 #define I2C_SLTH_SSLT_MASK 0xFFu
Kojto 90:cb3d968589d8 7672 #define I2C_SLTH_SSLT_SHIFT 0
Kojto 90:cb3d968589d8 7673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
Kojto 90:cb3d968589d8 7674 /* SLTL Bit Fields */
Kojto 90:cb3d968589d8 7675 #define I2C_SLTL_SSLT_MASK 0xFFu
Kojto 90:cb3d968589d8 7676 #define I2C_SLTL_SSLT_SHIFT 0
Kojto 90:cb3d968589d8 7677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
Kojto 90:cb3d968589d8 7678
Kojto 90:cb3d968589d8 7679 /*!
Kojto 90:cb3d968589d8 7680 * @}
Kojto 90:cb3d968589d8 7681 */ /* end of group I2C_Register_Masks */
Kojto 90:cb3d968589d8 7682
Kojto 90:cb3d968589d8 7683
Kojto 90:cb3d968589d8 7684 /* I2C - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7685 /** Peripheral I2C0 base address */
Kojto 90:cb3d968589d8 7686 #define I2C0_BASE (0x40066000u)
Kojto 90:cb3d968589d8 7687 /** Peripheral I2C0 base pointer */
Kojto 90:cb3d968589d8 7688 #define I2C0 ((I2C_Type *)I2C0_BASE)
Kojto 90:cb3d968589d8 7689 #define I2C0_BASE_PTR (I2C0)
Kojto 90:cb3d968589d8 7690 /** Peripheral I2C1 base address */
Kojto 90:cb3d968589d8 7691 #define I2C1_BASE (0x40067000u)
Kojto 90:cb3d968589d8 7692 /** Peripheral I2C1 base pointer */
Kojto 90:cb3d968589d8 7693 #define I2C1 ((I2C_Type *)I2C1_BASE)
Kojto 90:cb3d968589d8 7694 #define I2C1_BASE_PTR (I2C1)
Kojto 90:cb3d968589d8 7695 /** Peripheral I2C2 base address */
Kojto 90:cb3d968589d8 7696 #define I2C2_BASE (0x400E6000u)
Kojto 90:cb3d968589d8 7697 /** Peripheral I2C2 base pointer */
Kojto 90:cb3d968589d8 7698 #define I2C2 ((I2C_Type *)I2C2_BASE)
Kojto 90:cb3d968589d8 7699 #define I2C2_BASE_PTR (I2C2)
Kojto 90:cb3d968589d8 7700 /** Array initializer of I2C peripheral base addresses */
Kojto 90:cb3d968589d8 7701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
Kojto 90:cb3d968589d8 7702 /** Array initializer of I2C peripheral base pointers */
Kojto 90:cb3d968589d8 7703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
Kojto 90:cb3d968589d8 7704 /** Interrupt vectors for the I2C peripheral type */
Kojto 90:cb3d968589d8 7705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
Kojto 90:cb3d968589d8 7706
Kojto 90:cb3d968589d8 7707 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7708 -- I2C - Register accessor macros
Kojto 90:cb3d968589d8 7709 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7710
Kojto 90:cb3d968589d8 7711 /*!
Kojto 90:cb3d968589d8 7712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Kojto 90:cb3d968589d8 7713 * @{
Kojto 90:cb3d968589d8 7714 */
Kojto 90:cb3d968589d8 7715
Kojto 90:cb3d968589d8 7716
Kojto 90:cb3d968589d8 7717 /* I2C - Register instance definitions */
Kojto 90:cb3d968589d8 7718 /* I2C0 */
Kojto 90:cb3d968589d8 7719 #define I2C0_A1 I2C_A1_REG(I2C0)
Kojto 90:cb3d968589d8 7720 #define I2C0_F I2C_F_REG(I2C0)
Kojto 90:cb3d968589d8 7721 #define I2C0_C1 I2C_C1_REG(I2C0)
Kojto 90:cb3d968589d8 7722 #define I2C0_S I2C_S_REG(I2C0)
Kojto 90:cb3d968589d8 7723 #define I2C0_D I2C_D_REG(I2C0)
Kojto 90:cb3d968589d8 7724 #define I2C0_C2 I2C_C2_REG(I2C0)
Kojto 90:cb3d968589d8 7725 #define I2C0_FLT I2C_FLT_REG(I2C0)
Kojto 90:cb3d968589d8 7726 #define I2C0_RA I2C_RA_REG(I2C0)
Kojto 90:cb3d968589d8 7727 #define I2C0_SMB I2C_SMB_REG(I2C0)
Kojto 90:cb3d968589d8 7728 #define I2C0_A2 I2C_A2_REG(I2C0)
Kojto 90:cb3d968589d8 7729 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
Kojto 90:cb3d968589d8 7730 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
Kojto 90:cb3d968589d8 7731 /* I2C1 */
Kojto 90:cb3d968589d8 7732 #define I2C1_A1 I2C_A1_REG(I2C1)
Kojto 90:cb3d968589d8 7733 #define I2C1_F I2C_F_REG(I2C1)
Kojto 90:cb3d968589d8 7734 #define I2C1_C1 I2C_C1_REG(I2C1)
Kojto 90:cb3d968589d8 7735 #define I2C1_S I2C_S_REG(I2C1)
Kojto 90:cb3d968589d8 7736 #define I2C1_D I2C_D_REG(I2C1)
Kojto 90:cb3d968589d8 7737 #define I2C1_C2 I2C_C2_REG(I2C1)
Kojto 90:cb3d968589d8 7738 #define I2C1_FLT I2C_FLT_REG(I2C1)
Kojto 90:cb3d968589d8 7739 #define I2C1_RA I2C_RA_REG(I2C1)
Kojto 90:cb3d968589d8 7740 #define I2C1_SMB I2C_SMB_REG(I2C1)
Kojto 90:cb3d968589d8 7741 #define I2C1_A2 I2C_A2_REG(I2C1)
Kojto 90:cb3d968589d8 7742 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
Kojto 90:cb3d968589d8 7743 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
Kojto 90:cb3d968589d8 7744 /* I2C2 */
Kojto 90:cb3d968589d8 7745 #define I2C2_A1 I2C_A1_REG(I2C2)
Kojto 90:cb3d968589d8 7746 #define I2C2_F I2C_F_REG(I2C2)
Kojto 90:cb3d968589d8 7747 #define I2C2_C1 I2C_C1_REG(I2C2)
Kojto 90:cb3d968589d8 7748 #define I2C2_S I2C_S_REG(I2C2)
Kojto 90:cb3d968589d8 7749 #define I2C2_D I2C_D_REG(I2C2)
Kojto 90:cb3d968589d8 7750 #define I2C2_C2 I2C_C2_REG(I2C2)
Kojto 90:cb3d968589d8 7751 #define I2C2_FLT I2C_FLT_REG(I2C2)
Kojto 90:cb3d968589d8 7752 #define I2C2_RA I2C_RA_REG(I2C2)
Kojto 90:cb3d968589d8 7753 #define I2C2_SMB I2C_SMB_REG(I2C2)
Kojto 90:cb3d968589d8 7754 #define I2C2_A2 I2C_A2_REG(I2C2)
Kojto 90:cb3d968589d8 7755 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
Kojto 90:cb3d968589d8 7756 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
Kojto 90:cb3d968589d8 7757
Kojto 90:cb3d968589d8 7758 /*!
Kojto 90:cb3d968589d8 7759 * @}
Kojto 90:cb3d968589d8 7760 */ /* end of group I2C_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7761
Kojto 90:cb3d968589d8 7762
Kojto 90:cb3d968589d8 7763 /*!
Kojto 90:cb3d968589d8 7764 * @}
Kojto 90:cb3d968589d8 7765 */ /* end of group I2C_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7766
Kojto 90:cb3d968589d8 7767
Kojto 90:cb3d968589d8 7768 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7769 -- I2S Peripheral Access Layer
Kojto 90:cb3d968589d8 7770 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7771
Kojto 90:cb3d968589d8 7772 /*!
Kojto 90:cb3d968589d8 7773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Kojto 90:cb3d968589d8 7774 * @{
Kojto 90:cb3d968589d8 7775 */
Kojto 90:cb3d968589d8 7776
Kojto 90:cb3d968589d8 7777 /** I2S - Register Layout Typedef */
Kojto 90:cb3d968589d8 7778 typedef struct {
Kojto 90:cb3d968589d8 7779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 7780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
Kojto 90:cb3d968589d8 7781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
Kojto 90:cb3d968589d8 7782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
Kojto 90:cb3d968589d8 7783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
Kojto 90:cb3d968589d8 7784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
Kojto 90:cb3d968589d8 7785 uint8_t RESERVED_0[8];
Kojto 90:cb3d968589d8 7786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
Kojto 90:cb3d968589d8 7787 uint8_t RESERVED_1[24];
Kojto 90:cb3d968589d8 7788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
Kojto 90:cb3d968589d8 7789 uint8_t RESERVED_2[24];
Kojto 90:cb3d968589d8 7790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
Kojto 90:cb3d968589d8 7791 uint8_t RESERVED_3[28];
Kojto 90:cb3d968589d8 7792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
Kojto 90:cb3d968589d8 7793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
Kojto 90:cb3d968589d8 7794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
Kojto 90:cb3d968589d8 7795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
Kojto 90:cb3d968589d8 7796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
Kojto 90:cb3d968589d8 7797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
Kojto 90:cb3d968589d8 7798 uint8_t RESERVED_4[8];
Kojto 90:cb3d968589d8 7799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
Kojto 90:cb3d968589d8 7800 uint8_t RESERVED_5[24];
Kojto 90:cb3d968589d8 7801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
Kojto 90:cb3d968589d8 7802 uint8_t RESERVED_6[24];
Kojto 90:cb3d968589d8 7803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
Kojto 90:cb3d968589d8 7804 uint8_t RESERVED_7[28];
Kojto 90:cb3d968589d8 7805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
Kojto 90:cb3d968589d8 7806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
Kojto 90:cb3d968589d8 7807 } I2S_Type, *I2S_MemMapPtr;
Kojto 90:cb3d968589d8 7808
Kojto 90:cb3d968589d8 7809 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7810 -- I2S - Register accessor macros
Kojto 90:cb3d968589d8 7811 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7812
Kojto 90:cb3d968589d8 7813 /*!
Kojto 90:cb3d968589d8 7814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Kojto 90:cb3d968589d8 7815 * @{
Kojto 90:cb3d968589d8 7816 */
Kojto 90:cb3d968589d8 7817
Kojto 90:cb3d968589d8 7818
Kojto 90:cb3d968589d8 7819 /* I2S - Register accessors */
Kojto 90:cb3d968589d8 7820 #define I2S_TCSR_REG(base) ((base)->TCSR)
Kojto 90:cb3d968589d8 7821 #define I2S_TCR1_REG(base) ((base)->TCR1)
Kojto 90:cb3d968589d8 7822 #define I2S_TCR2_REG(base) ((base)->TCR2)
Kojto 90:cb3d968589d8 7823 #define I2S_TCR3_REG(base) ((base)->TCR3)
Kojto 90:cb3d968589d8 7824 #define I2S_TCR4_REG(base) ((base)->TCR4)
Kojto 90:cb3d968589d8 7825 #define I2S_TCR5_REG(base) ((base)->TCR5)
Kojto 90:cb3d968589d8 7826 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
Kojto 90:cb3d968589d8 7827 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
Kojto 90:cb3d968589d8 7828 #define I2S_TMR_REG(base) ((base)->TMR)
Kojto 90:cb3d968589d8 7829 #define I2S_RCSR_REG(base) ((base)->RCSR)
Kojto 90:cb3d968589d8 7830 #define I2S_RCR1_REG(base) ((base)->RCR1)
Kojto 90:cb3d968589d8 7831 #define I2S_RCR2_REG(base) ((base)->RCR2)
Kojto 90:cb3d968589d8 7832 #define I2S_RCR3_REG(base) ((base)->RCR3)
Kojto 90:cb3d968589d8 7833 #define I2S_RCR4_REG(base) ((base)->RCR4)
Kojto 90:cb3d968589d8 7834 #define I2S_RCR5_REG(base) ((base)->RCR5)
Kojto 90:cb3d968589d8 7835 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
Kojto 90:cb3d968589d8 7836 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
Kojto 90:cb3d968589d8 7837 #define I2S_RMR_REG(base) ((base)->RMR)
Kojto 90:cb3d968589d8 7838 #define I2S_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 7839 #define I2S_MDR_REG(base) ((base)->MDR)
Kojto 90:cb3d968589d8 7840
Kojto 90:cb3d968589d8 7841 /*!
Kojto 90:cb3d968589d8 7842 * @}
Kojto 90:cb3d968589d8 7843 */ /* end of group I2S_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7844
Kojto 90:cb3d968589d8 7845
Kojto 90:cb3d968589d8 7846 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7847 -- I2S Register Masks
Kojto 90:cb3d968589d8 7848 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7849
Kojto 90:cb3d968589d8 7850 /*!
Kojto 90:cb3d968589d8 7851 * @addtogroup I2S_Register_Masks I2S Register Masks
Kojto 90:cb3d968589d8 7852 * @{
Kojto 90:cb3d968589d8 7853 */
Kojto 90:cb3d968589d8 7854
Kojto 90:cb3d968589d8 7855 /* TCSR Bit Fields */
Kojto 90:cb3d968589d8 7856 #define I2S_TCSR_FRDE_MASK 0x1u
Kojto 90:cb3d968589d8 7857 #define I2S_TCSR_FRDE_SHIFT 0
Kojto 90:cb3d968589d8 7858 #define I2S_TCSR_FWDE_MASK 0x2u
Kojto 90:cb3d968589d8 7859 #define I2S_TCSR_FWDE_SHIFT 1
Kojto 90:cb3d968589d8 7860 #define I2S_TCSR_FRIE_MASK 0x100u
Kojto 90:cb3d968589d8 7861 #define I2S_TCSR_FRIE_SHIFT 8
Kojto 90:cb3d968589d8 7862 #define I2S_TCSR_FWIE_MASK 0x200u
Kojto 90:cb3d968589d8 7863 #define I2S_TCSR_FWIE_SHIFT 9
Kojto 90:cb3d968589d8 7864 #define I2S_TCSR_FEIE_MASK 0x400u
Kojto 90:cb3d968589d8 7865 #define I2S_TCSR_FEIE_SHIFT 10
Kojto 90:cb3d968589d8 7866 #define I2S_TCSR_SEIE_MASK 0x800u
Kojto 90:cb3d968589d8 7867 #define I2S_TCSR_SEIE_SHIFT 11
Kojto 90:cb3d968589d8 7868 #define I2S_TCSR_WSIE_MASK 0x1000u
Kojto 90:cb3d968589d8 7869 #define I2S_TCSR_WSIE_SHIFT 12
Kojto 90:cb3d968589d8 7870 #define I2S_TCSR_FRF_MASK 0x10000u
Kojto 90:cb3d968589d8 7871 #define I2S_TCSR_FRF_SHIFT 16
Kojto 90:cb3d968589d8 7872 #define I2S_TCSR_FWF_MASK 0x20000u
Kojto 90:cb3d968589d8 7873 #define I2S_TCSR_FWF_SHIFT 17
Kojto 90:cb3d968589d8 7874 #define I2S_TCSR_FEF_MASK 0x40000u
Kojto 90:cb3d968589d8 7875 #define I2S_TCSR_FEF_SHIFT 18
Kojto 90:cb3d968589d8 7876 #define I2S_TCSR_SEF_MASK 0x80000u
Kojto 90:cb3d968589d8 7877 #define I2S_TCSR_SEF_SHIFT 19
Kojto 90:cb3d968589d8 7878 #define I2S_TCSR_WSF_MASK 0x100000u
Kojto 90:cb3d968589d8 7879 #define I2S_TCSR_WSF_SHIFT 20
Kojto 90:cb3d968589d8 7880 #define I2S_TCSR_SR_MASK 0x1000000u
Kojto 90:cb3d968589d8 7881 #define I2S_TCSR_SR_SHIFT 24
Kojto 90:cb3d968589d8 7882 #define I2S_TCSR_FR_MASK 0x2000000u
Kojto 90:cb3d968589d8 7883 #define I2S_TCSR_FR_SHIFT 25
Kojto 90:cb3d968589d8 7884 #define I2S_TCSR_BCE_MASK 0x10000000u
Kojto 90:cb3d968589d8 7885 #define I2S_TCSR_BCE_SHIFT 28
Kojto 90:cb3d968589d8 7886 #define I2S_TCSR_DBGE_MASK 0x20000000u
Kojto 90:cb3d968589d8 7887 #define I2S_TCSR_DBGE_SHIFT 29
Kojto 90:cb3d968589d8 7888 #define I2S_TCSR_STOPE_MASK 0x40000000u
Kojto 90:cb3d968589d8 7889 #define I2S_TCSR_STOPE_SHIFT 30
Kojto 90:cb3d968589d8 7890 #define I2S_TCSR_TE_MASK 0x80000000u
Kojto 90:cb3d968589d8 7891 #define I2S_TCSR_TE_SHIFT 31
Kojto 90:cb3d968589d8 7892 /* TCR1 Bit Fields */
Kojto 90:cb3d968589d8 7893 #define I2S_TCR1_TFW_MASK 0x7u
Kojto 90:cb3d968589d8 7894 #define I2S_TCR1_TFW_SHIFT 0
Kojto 90:cb3d968589d8 7895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
Kojto 90:cb3d968589d8 7896 /* TCR2 Bit Fields */
Kojto 90:cb3d968589d8 7897 #define I2S_TCR2_DIV_MASK 0xFFu
Kojto 90:cb3d968589d8 7898 #define I2S_TCR2_DIV_SHIFT 0
Kojto 90:cb3d968589d8 7899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
Kojto 90:cb3d968589d8 7900 #define I2S_TCR2_BCD_MASK 0x1000000u
Kojto 90:cb3d968589d8 7901 #define I2S_TCR2_BCD_SHIFT 24
Kojto 90:cb3d968589d8 7902 #define I2S_TCR2_BCP_MASK 0x2000000u
Kojto 90:cb3d968589d8 7903 #define I2S_TCR2_BCP_SHIFT 25
Kojto 90:cb3d968589d8 7904 #define I2S_TCR2_MSEL_MASK 0xC000000u
Kojto 90:cb3d968589d8 7905 #define I2S_TCR2_MSEL_SHIFT 26
Kojto 90:cb3d968589d8 7906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
Kojto 90:cb3d968589d8 7907 #define I2S_TCR2_BCI_MASK 0x10000000u
Kojto 90:cb3d968589d8 7908 #define I2S_TCR2_BCI_SHIFT 28
Kojto 90:cb3d968589d8 7909 #define I2S_TCR2_BCS_MASK 0x20000000u
Kojto 90:cb3d968589d8 7910 #define I2S_TCR2_BCS_SHIFT 29
Kojto 90:cb3d968589d8 7911 #define I2S_TCR2_SYNC_MASK 0xC0000000u
Kojto 90:cb3d968589d8 7912 #define I2S_TCR2_SYNC_SHIFT 30
Kojto 90:cb3d968589d8 7913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
Kojto 90:cb3d968589d8 7914 /* TCR3 Bit Fields */
Kojto 90:cb3d968589d8 7915 #define I2S_TCR3_WDFL_MASK 0x1Fu
Kojto 90:cb3d968589d8 7916 #define I2S_TCR3_WDFL_SHIFT 0
Kojto 90:cb3d968589d8 7917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
Kojto 90:cb3d968589d8 7918 #define I2S_TCR3_TCE_MASK 0x30000u
Kojto 90:cb3d968589d8 7919 #define I2S_TCR3_TCE_SHIFT 16
Kojto 90:cb3d968589d8 7920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
Kojto 90:cb3d968589d8 7921 /* TCR4 Bit Fields */
Kojto 90:cb3d968589d8 7922 #define I2S_TCR4_FSD_MASK 0x1u
Kojto 90:cb3d968589d8 7923 #define I2S_TCR4_FSD_SHIFT 0
Kojto 90:cb3d968589d8 7924 #define I2S_TCR4_FSP_MASK 0x2u
Kojto 90:cb3d968589d8 7925 #define I2S_TCR4_FSP_SHIFT 1
Kojto 90:cb3d968589d8 7926 #define I2S_TCR4_FSE_MASK 0x8u
Kojto 90:cb3d968589d8 7927 #define I2S_TCR4_FSE_SHIFT 3
Kojto 90:cb3d968589d8 7928 #define I2S_TCR4_MF_MASK 0x10u
Kojto 90:cb3d968589d8 7929 #define I2S_TCR4_MF_SHIFT 4
Kojto 90:cb3d968589d8 7930 #define I2S_TCR4_SYWD_MASK 0x1F00u
Kojto 90:cb3d968589d8 7931 #define I2S_TCR4_SYWD_SHIFT 8
Kojto 90:cb3d968589d8 7932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
Kojto 90:cb3d968589d8 7933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
Kojto 90:cb3d968589d8 7934 #define I2S_TCR4_FRSZ_SHIFT 16
Kojto 90:cb3d968589d8 7935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
Kojto 90:cb3d968589d8 7936 /* TCR5 Bit Fields */
Kojto 90:cb3d968589d8 7937 #define I2S_TCR5_FBT_MASK 0x1F00u
Kojto 90:cb3d968589d8 7938 #define I2S_TCR5_FBT_SHIFT 8
Kojto 90:cb3d968589d8 7939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
Kojto 90:cb3d968589d8 7940 #define I2S_TCR5_W0W_MASK 0x1F0000u
Kojto 90:cb3d968589d8 7941 #define I2S_TCR5_W0W_SHIFT 16
Kojto 90:cb3d968589d8 7942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
Kojto 90:cb3d968589d8 7943 #define I2S_TCR5_WNW_MASK 0x1F000000u
Kojto 90:cb3d968589d8 7944 #define I2S_TCR5_WNW_SHIFT 24
Kojto 90:cb3d968589d8 7945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
Kojto 90:cb3d968589d8 7946 /* TDR Bit Fields */
Kojto 90:cb3d968589d8 7947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7948 #define I2S_TDR_TDR_SHIFT 0
Kojto 90:cb3d968589d8 7949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
Kojto 90:cb3d968589d8 7950 /* TFR Bit Fields */
Kojto 90:cb3d968589d8 7951 #define I2S_TFR_RFP_MASK 0xFu
Kojto 90:cb3d968589d8 7952 #define I2S_TFR_RFP_SHIFT 0
Kojto 90:cb3d968589d8 7953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
Kojto 90:cb3d968589d8 7954 #define I2S_TFR_WFP_MASK 0xF0000u
Kojto 90:cb3d968589d8 7955 #define I2S_TFR_WFP_SHIFT 16
Kojto 90:cb3d968589d8 7956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
Kojto 90:cb3d968589d8 7957 /* TMR Bit Fields */
Kojto 90:cb3d968589d8 7958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7959 #define I2S_TMR_TWM_SHIFT 0
Kojto 90:cb3d968589d8 7960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
Kojto 90:cb3d968589d8 7961 /* RCSR Bit Fields */
Kojto 90:cb3d968589d8 7962 #define I2S_RCSR_FRDE_MASK 0x1u
Kojto 90:cb3d968589d8 7963 #define I2S_RCSR_FRDE_SHIFT 0
Kojto 90:cb3d968589d8 7964 #define I2S_RCSR_FWDE_MASK 0x2u
Kojto 90:cb3d968589d8 7965 #define I2S_RCSR_FWDE_SHIFT 1
Kojto 90:cb3d968589d8 7966 #define I2S_RCSR_FRIE_MASK 0x100u
Kojto 90:cb3d968589d8 7967 #define I2S_RCSR_FRIE_SHIFT 8
Kojto 90:cb3d968589d8 7968 #define I2S_RCSR_FWIE_MASK 0x200u
Kojto 90:cb3d968589d8 7969 #define I2S_RCSR_FWIE_SHIFT 9
Kojto 90:cb3d968589d8 7970 #define I2S_RCSR_FEIE_MASK 0x400u
Kojto 90:cb3d968589d8 7971 #define I2S_RCSR_FEIE_SHIFT 10
Kojto 90:cb3d968589d8 7972 #define I2S_RCSR_SEIE_MASK 0x800u
Kojto 90:cb3d968589d8 7973 #define I2S_RCSR_SEIE_SHIFT 11
Kojto 90:cb3d968589d8 7974 #define I2S_RCSR_WSIE_MASK 0x1000u
Kojto 90:cb3d968589d8 7975 #define I2S_RCSR_WSIE_SHIFT 12
Kojto 90:cb3d968589d8 7976 #define I2S_RCSR_FRF_MASK 0x10000u
Kojto 90:cb3d968589d8 7977 #define I2S_RCSR_FRF_SHIFT 16
Kojto 90:cb3d968589d8 7978 #define I2S_RCSR_FWF_MASK 0x20000u
Kojto 90:cb3d968589d8 7979 #define I2S_RCSR_FWF_SHIFT 17
Kojto 90:cb3d968589d8 7980 #define I2S_RCSR_FEF_MASK 0x40000u
Kojto 90:cb3d968589d8 7981 #define I2S_RCSR_FEF_SHIFT 18
Kojto 90:cb3d968589d8 7982 #define I2S_RCSR_SEF_MASK 0x80000u
Kojto 90:cb3d968589d8 7983 #define I2S_RCSR_SEF_SHIFT 19
Kojto 90:cb3d968589d8 7984 #define I2S_RCSR_WSF_MASK 0x100000u
Kojto 90:cb3d968589d8 7985 #define I2S_RCSR_WSF_SHIFT 20
Kojto 90:cb3d968589d8 7986 #define I2S_RCSR_SR_MASK 0x1000000u
Kojto 90:cb3d968589d8 7987 #define I2S_RCSR_SR_SHIFT 24
Kojto 90:cb3d968589d8 7988 #define I2S_RCSR_FR_MASK 0x2000000u
Kojto 90:cb3d968589d8 7989 #define I2S_RCSR_FR_SHIFT 25
Kojto 90:cb3d968589d8 7990 #define I2S_RCSR_BCE_MASK 0x10000000u
Kojto 90:cb3d968589d8 7991 #define I2S_RCSR_BCE_SHIFT 28
Kojto 90:cb3d968589d8 7992 #define I2S_RCSR_DBGE_MASK 0x20000000u
Kojto 90:cb3d968589d8 7993 #define I2S_RCSR_DBGE_SHIFT 29
Kojto 90:cb3d968589d8 7994 #define I2S_RCSR_STOPE_MASK 0x40000000u
Kojto 90:cb3d968589d8 7995 #define I2S_RCSR_STOPE_SHIFT 30
Kojto 90:cb3d968589d8 7996 #define I2S_RCSR_RE_MASK 0x80000000u
Kojto 90:cb3d968589d8 7997 #define I2S_RCSR_RE_SHIFT 31
Kojto 90:cb3d968589d8 7998 /* RCR1 Bit Fields */
Kojto 90:cb3d968589d8 7999 #define I2S_RCR1_RFW_MASK 0x7u
Kojto 90:cb3d968589d8 8000 #define I2S_RCR1_RFW_SHIFT 0
Kojto 90:cb3d968589d8 8001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
Kojto 90:cb3d968589d8 8002 /* RCR2 Bit Fields */
Kojto 90:cb3d968589d8 8003 #define I2S_RCR2_DIV_MASK 0xFFu
Kojto 90:cb3d968589d8 8004 #define I2S_RCR2_DIV_SHIFT 0
Kojto 90:cb3d968589d8 8005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
Kojto 90:cb3d968589d8 8006 #define I2S_RCR2_BCD_MASK 0x1000000u
Kojto 90:cb3d968589d8 8007 #define I2S_RCR2_BCD_SHIFT 24
Kojto 90:cb3d968589d8 8008 #define I2S_RCR2_BCP_MASK 0x2000000u
Kojto 90:cb3d968589d8 8009 #define I2S_RCR2_BCP_SHIFT 25
Kojto 90:cb3d968589d8 8010 #define I2S_RCR2_MSEL_MASK 0xC000000u
Kojto 90:cb3d968589d8 8011 #define I2S_RCR2_MSEL_SHIFT 26
Kojto 90:cb3d968589d8 8012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
Kojto 90:cb3d968589d8 8013 #define I2S_RCR2_BCI_MASK 0x10000000u
Kojto 90:cb3d968589d8 8014 #define I2S_RCR2_BCI_SHIFT 28
Kojto 90:cb3d968589d8 8015 #define I2S_RCR2_BCS_MASK 0x20000000u
Kojto 90:cb3d968589d8 8016 #define I2S_RCR2_BCS_SHIFT 29
Kojto 90:cb3d968589d8 8017 #define I2S_RCR2_SYNC_MASK 0xC0000000u
Kojto 90:cb3d968589d8 8018 #define I2S_RCR2_SYNC_SHIFT 30
Kojto 90:cb3d968589d8 8019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
Kojto 90:cb3d968589d8 8020 /* RCR3 Bit Fields */
Kojto 90:cb3d968589d8 8021 #define I2S_RCR3_WDFL_MASK 0x1Fu
Kojto 90:cb3d968589d8 8022 #define I2S_RCR3_WDFL_SHIFT 0
Kojto 90:cb3d968589d8 8023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
Kojto 90:cb3d968589d8 8024 #define I2S_RCR3_RCE_MASK 0x30000u
Kojto 90:cb3d968589d8 8025 #define I2S_RCR3_RCE_SHIFT 16
Kojto 90:cb3d968589d8 8026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
Kojto 90:cb3d968589d8 8027 /* RCR4 Bit Fields */
Kojto 90:cb3d968589d8 8028 #define I2S_RCR4_FSD_MASK 0x1u
Kojto 90:cb3d968589d8 8029 #define I2S_RCR4_FSD_SHIFT 0
Kojto 90:cb3d968589d8 8030 #define I2S_RCR4_FSP_MASK 0x2u
Kojto 90:cb3d968589d8 8031 #define I2S_RCR4_FSP_SHIFT 1
Kojto 90:cb3d968589d8 8032 #define I2S_RCR4_FSE_MASK 0x8u
Kojto 90:cb3d968589d8 8033 #define I2S_RCR4_FSE_SHIFT 3
Kojto 90:cb3d968589d8 8034 #define I2S_RCR4_MF_MASK 0x10u
Kojto 90:cb3d968589d8 8035 #define I2S_RCR4_MF_SHIFT 4
Kojto 90:cb3d968589d8 8036 #define I2S_RCR4_SYWD_MASK 0x1F00u
Kojto 90:cb3d968589d8 8037 #define I2S_RCR4_SYWD_SHIFT 8
Kojto 90:cb3d968589d8 8038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
Kojto 90:cb3d968589d8 8039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
Kojto 90:cb3d968589d8 8040 #define I2S_RCR4_FRSZ_SHIFT 16
Kojto 90:cb3d968589d8 8041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
Kojto 90:cb3d968589d8 8042 /* RCR5 Bit Fields */
Kojto 90:cb3d968589d8 8043 #define I2S_RCR5_FBT_MASK 0x1F00u
Kojto 90:cb3d968589d8 8044 #define I2S_RCR5_FBT_SHIFT 8
Kojto 90:cb3d968589d8 8045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
Kojto 90:cb3d968589d8 8046 #define I2S_RCR5_W0W_MASK 0x1F0000u
Kojto 90:cb3d968589d8 8047 #define I2S_RCR5_W0W_SHIFT 16
Kojto 90:cb3d968589d8 8048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
Kojto 90:cb3d968589d8 8049 #define I2S_RCR5_WNW_MASK 0x1F000000u
Kojto 90:cb3d968589d8 8050 #define I2S_RCR5_WNW_SHIFT 24
Kojto 90:cb3d968589d8 8051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
Kojto 90:cb3d968589d8 8052 /* RDR Bit Fields */
Kojto 90:cb3d968589d8 8053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 8054 #define I2S_RDR_RDR_SHIFT 0
Kojto 90:cb3d968589d8 8055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
Kojto 90:cb3d968589d8 8056 /* RFR Bit Fields */
Kojto 90:cb3d968589d8 8057 #define I2S_RFR_RFP_MASK 0xFu
Kojto 90:cb3d968589d8 8058 #define I2S_RFR_RFP_SHIFT 0
Kojto 90:cb3d968589d8 8059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
Kojto 90:cb3d968589d8 8060 #define I2S_RFR_WFP_MASK 0xF0000u
Kojto 90:cb3d968589d8 8061 #define I2S_RFR_WFP_SHIFT 16
Kojto 90:cb3d968589d8 8062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
Kojto 90:cb3d968589d8 8063 /* RMR Bit Fields */
Kojto 90:cb3d968589d8 8064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 8065 #define I2S_RMR_RWM_SHIFT 0
Kojto 90:cb3d968589d8 8066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
Kojto 90:cb3d968589d8 8067 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 8068 #define I2S_MCR_MICS_MASK 0x3000000u
Kojto 90:cb3d968589d8 8069 #define I2S_MCR_MICS_SHIFT 24
Kojto 90:cb3d968589d8 8070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
Kojto 90:cb3d968589d8 8071 #define I2S_MCR_MOE_MASK 0x40000000u
Kojto 90:cb3d968589d8 8072 #define I2S_MCR_MOE_SHIFT 30
Kojto 90:cb3d968589d8 8073 #define I2S_MCR_DUF_MASK 0x80000000u
Kojto 90:cb3d968589d8 8074 #define I2S_MCR_DUF_SHIFT 31
Kojto 90:cb3d968589d8 8075 /* MDR Bit Fields */
Kojto 90:cb3d968589d8 8076 #define I2S_MDR_DIVIDE_MASK 0xFFFu
Kojto 90:cb3d968589d8 8077 #define I2S_MDR_DIVIDE_SHIFT 0
Kojto 90:cb3d968589d8 8078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
Kojto 90:cb3d968589d8 8079 #define I2S_MDR_FRACT_MASK 0xFF000u
Kojto 90:cb3d968589d8 8080 #define I2S_MDR_FRACT_SHIFT 12
Kojto 90:cb3d968589d8 8081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
Kojto 90:cb3d968589d8 8082
Kojto 90:cb3d968589d8 8083 /*!
Kojto 90:cb3d968589d8 8084 * @}
Kojto 90:cb3d968589d8 8085 */ /* end of group I2S_Register_Masks */
Kojto 90:cb3d968589d8 8086
Kojto 90:cb3d968589d8 8087
Kojto 90:cb3d968589d8 8088 /* I2S - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8089 /** Peripheral I2S0 base address */
Kojto 90:cb3d968589d8 8090 #define I2S0_BASE (0x4002F000u)
Kojto 90:cb3d968589d8 8091 /** Peripheral I2S0 base pointer */
Kojto 90:cb3d968589d8 8092 #define I2S0 ((I2S_Type *)I2S0_BASE)
Kojto 90:cb3d968589d8 8093 #define I2S0_BASE_PTR (I2S0)
Kojto 90:cb3d968589d8 8094 /** Array initializer of I2S peripheral base addresses */
Kojto 90:cb3d968589d8 8095 #define I2S_BASE_ADDRS { I2S0_BASE }
Kojto 90:cb3d968589d8 8096 /** Array initializer of I2S peripheral base pointers */
Kojto 90:cb3d968589d8 8097 #define I2S_BASE_PTRS { I2S0 }
Kojto 90:cb3d968589d8 8098 /** Interrupt vectors for the I2S peripheral type */
Kojto 90:cb3d968589d8 8099 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
Kojto 90:cb3d968589d8 8100 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
Kojto 90:cb3d968589d8 8101
Kojto 90:cb3d968589d8 8102 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8103 -- I2S - Register accessor macros
Kojto 90:cb3d968589d8 8104 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8105
Kojto 90:cb3d968589d8 8106 /*!
Kojto 90:cb3d968589d8 8107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Kojto 90:cb3d968589d8 8108 * @{
Kojto 90:cb3d968589d8 8109 */
Kojto 90:cb3d968589d8 8110
Kojto 90:cb3d968589d8 8111
Kojto 90:cb3d968589d8 8112 /* I2S - Register instance definitions */
Kojto 90:cb3d968589d8 8113 /* I2S0 */
Kojto 90:cb3d968589d8 8114 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
Kojto 90:cb3d968589d8 8115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
Kojto 90:cb3d968589d8 8116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
Kojto 90:cb3d968589d8 8117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
Kojto 90:cb3d968589d8 8118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
Kojto 90:cb3d968589d8 8119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
Kojto 90:cb3d968589d8 8120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
Kojto 90:cb3d968589d8 8121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
Kojto 90:cb3d968589d8 8122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
Kojto 90:cb3d968589d8 8123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
Kojto 90:cb3d968589d8 8124 #define I2S0_TMR I2S_TMR_REG(I2S0)
Kojto 90:cb3d968589d8 8125 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
Kojto 90:cb3d968589d8 8126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
Kojto 90:cb3d968589d8 8127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
Kojto 90:cb3d968589d8 8128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
Kojto 90:cb3d968589d8 8129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
Kojto 90:cb3d968589d8 8130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
Kojto 90:cb3d968589d8 8131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
Kojto 90:cb3d968589d8 8132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
Kojto 90:cb3d968589d8 8133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
Kojto 90:cb3d968589d8 8134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
Kojto 90:cb3d968589d8 8135 #define I2S0_RMR I2S_RMR_REG(I2S0)
Kojto 90:cb3d968589d8 8136 #define I2S0_MCR I2S_MCR_REG(I2S0)
Kojto 90:cb3d968589d8 8137 #define I2S0_MDR I2S_MDR_REG(I2S0)
Kojto 90:cb3d968589d8 8138
Kojto 90:cb3d968589d8 8139 /* I2S - Register array accessors */
Kojto 90:cb3d968589d8 8140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
Kojto 90:cb3d968589d8 8141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
Kojto 90:cb3d968589d8 8142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
Kojto 90:cb3d968589d8 8143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
Kojto 90:cb3d968589d8 8144
Kojto 90:cb3d968589d8 8145 /*!
Kojto 90:cb3d968589d8 8146 * @}
Kojto 90:cb3d968589d8 8147 */ /* end of group I2S_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8148
Kojto 90:cb3d968589d8 8149
Kojto 90:cb3d968589d8 8150 /*!
Kojto 90:cb3d968589d8 8151 * @}
Kojto 90:cb3d968589d8 8152 */ /* end of group I2S_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8153
Kojto 90:cb3d968589d8 8154
Kojto 90:cb3d968589d8 8155 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8156 -- LLWU Peripheral Access Layer
Kojto 90:cb3d968589d8 8157 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8158
Kojto 90:cb3d968589d8 8159 /*!
Kojto 90:cb3d968589d8 8160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Kojto 90:cb3d968589d8 8161 * @{
Kojto 90:cb3d968589d8 8162 */
Kojto 90:cb3d968589d8 8163
Kojto 90:cb3d968589d8 8164 /** LLWU - Register Layout Typedef */
Kojto 90:cb3d968589d8 8165 typedef struct {
Kojto 90:cb3d968589d8 8166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
Kojto 90:cb3d968589d8 8167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
Kojto 90:cb3d968589d8 8168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
Kojto 90:cb3d968589d8 8169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
Kojto 90:cb3d968589d8 8170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
Kojto 90:cb3d968589d8 8171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
Kojto 90:cb3d968589d8 8172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
Kojto 90:cb3d968589d8 8173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
Kojto 90:cb3d968589d8 8174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
Kojto 90:cb3d968589d8 8175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
Kojto 90:cb3d968589d8 8176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
Kojto 90:cb3d968589d8 8177 } LLWU_Type, *LLWU_MemMapPtr;
Kojto 90:cb3d968589d8 8178
Kojto 90:cb3d968589d8 8179 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8180 -- LLWU - Register accessor macros
Kojto 90:cb3d968589d8 8181 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8182
Kojto 90:cb3d968589d8 8183 /*!
Kojto 90:cb3d968589d8 8184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Kojto 90:cb3d968589d8 8185 * @{
Kojto 90:cb3d968589d8 8186 */
Kojto 90:cb3d968589d8 8187
Kojto 90:cb3d968589d8 8188
Kojto 90:cb3d968589d8 8189 /* LLWU - Register accessors */
Kojto 90:cb3d968589d8 8190 #define LLWU_PE1_REG(base) ((base)->PE1)
Kojto 90:cb3d968589d8 8191 #define LLWU_PE2_REG(base) ((base)->PE2)
Kojto 90:cb3d968589d8 8192 #define LLWU_PE3_REG(base) ((base)->PE3)
Kojto 90:cb3d968589d8 8193 #define LLWU_PE4_REG(base) ((base)->PE4)
Kojto 90:cb3d968589d8 8194 #define LLWU_ME_REG(base) ((base)->ME)
Kojto 90:cb3d968589d8 8195 #define LLWU_F1_REG(base) ((base)->F1)
Kojto 90:cb3d968589d8 8196 #define LLWU_F2_REG(base) ((base)->F2)
Kojto 90:cb3d968589d8 8197 #define LLWU_F3_REG(base) ((base)->F3)
Kojto 90:cb3d968589d8 8198 #define LLWU_FILT1_REG(base) ((base)->FILT1)
Kojto 90:cb3d968589d8 8199 #define LLWU_FILT2_REG(base) ((base)->FILT2)
Kojto 90:cb3d968589d8 8200 #define LLWU_RST_REG(base) ((base)->RST)
Kojto 90:cb3d968589d8 8201
Kojto 90:cb3d968589d8 8202 /*!
Kojto 90:cb3d968589d8 8203 * @}
Kojto 90:cb3d968589d8 8204 */ /* end of group LLWU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8205
Kojto 90:cb3d968589d8 8206
Kojto 90:cb3d968589d8 8207 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8208 -- LLWU Register Masks
Kojto 90:cb3d968589d8 8209 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8210
Kojto 90:cb3d968589d8 8211 /*!
Kojto 90:cb3d968589d8 8212 * @addtogroup LLWU_Register_Masks LLWU Register Masks
Kojto 90:cb3d968589d8 8213 * @{
Kojto 90:cb3d968589d8 8214 */
Kojto 90:cb3d968589d8 8215
Kojto 90:cb3d968589d8 8216 /* PE1 Bit Fields */
Kojto 90:cb3d968589d8 8217 #define LLWU_PE1_WUPE0_MASK 0x3u
Kojto 90:cb3d968589d8 8218 #define LLWU_PE1_WUPE0_SHIFT 0
Kojto 90:cb3d968589d8 8219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
Kojto 90:cb3d968589d8 8220 #define LLWU_PE1_WUPE1_MASK 0xCu
Kojto 90:cb3d968589d8 8221 #define LLWU_PE1_WUPE1_SHIFT 2
Kojto 90:cb3d968589d8 8222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
Kojto 90:cb3d968589d8 8223 #define LLWU_PE1_WUPE2_MASK 0x30u
Kojto 90:cb3d968589d8 8224 #define LLWU_PE1_WUPE2_SHIFT 4
Kojto 90:cb3d968589d8 8225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
Kojto 90:cb3d968589d8 8226 #define LLWU_PE1_WUPE3_MASK 0xC0u
Kojto 90:cb3d968589d8 8227 #define LLWU_PE1_WUPE3_SHIFT 6
Kojto 90:cb3d968589d8 8228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
Kojto 90:cb3d968589d8 8229 /* PE2 Bit Fields */
Kojto 90:cb3d968589d8 8230 #define LLWU_PE2_WUPE4_MASK 0x3u
Kojto 90:cb3d968589d8 8231 #define LLWU_PE2_WUPE4_SHIFT 0
Kojto 90:cb3d968589d8 8232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
Kojto 90:cb3d968589d8 8233 #define LLWU_PE2_WUPE5_MASK 0xCu
Kojto 90:cb3d968589d8 8234 #define LLWU_PE2_WUPE5_SHIFT 2
Kojto 90:cb3d968589d8 8235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
Kojto 90:cb3d968589d8 8236 #define LLWU_PE2_WUPE6_MASK 0x30u
Kojto 90:cb3d968589d8 8237 #define LLWU_PE2_WUPE6_SHIFT 4
Kojto 90:cb3d968589d8 8238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
Kojto 90:cb3d968589d8 8239 #define LLWU_PE2_WUPE7_MASK 0xC0u
Kojto 90:cb3d968589d8 8240 #define LLWU_PE2_WUPE7_SHIFT 6
Kojto 90:cb3d968589d8 8241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
Kojto 90:cb3d968589d8 8242 /* PE3 Bit Fields */
Kojto 90:cb3d968589d8 8243 #define LLWU_PE3_WUPE8_MASK 0x3u
Kojto 90:cb3d968589d8 8244 #define LLWU_PE3_WUPE8_SHIFT 0
Kojto 90:cb3d968589d8 8245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
Kojto 90:cb3d968589d8 8246 #define LLWU_PE3_WUPE9_MASK 0xCu
Kojto 90:cb3d968589d8 8247 #define LLWU_PE3_WUPE9_SHIFT 2
Kojto 90:cb3d968589d8 8248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
Kojto 90:cb3d968589d8 8249 #define LLWU_PE3_WUPE10_MASK 0x30u
Kojto 90:cb3d968589d8 8250 #define LLWU_PE3_WUPE10_SHIFT 4
Kojto 90:cb3d968589d8 8251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
Kojto 90:cb3d968589d8 8252 #define LLWU_PE3_WUPE11_MASK 0xC0u
Kojto 90:cb3d968589d8 8253 #define LLWU_PE3_WUPE11_SHIFT 6
Kojto 90:cb3d968589d8 8254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
Kojto 90:cb3d968589d8 8255 /* PE4 Bit Fields */
Kojto 90:cb3d968589d8 8256 #define LLWU_PE4_WUPE12_MASK 0x3u
Kojto 90:cb3d968589d8 8257 #define LLWU_PE4_WUPE12_SHIFT 0
Kojto 90:cb3d968589d8 8258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
Kojto 90:cb3d968589d8 8259 #define LLWU_PE4_WUPE13_MASK 0xCu
Kojto 90:cb3d968589d8 8260 #define LLWU_PE4_WUPE13_SHIFT 2
Kojto 90:cb3d968589d8 8261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
Kojto 90:cb3d968589d8 8262 #define LLWU_PE4_WUPE14_MASK 0x30u
Kojto 90:cb3d968589d8 8263 #define LLWU_PE4_WUPE14_SHIFT 4
Kojto 90:cb3d968589d8 8264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
Kojto 90:cb3d968589d8 8265 #define LLWU_PE4_WUPE15_MASK 0xC0u
Kojto 90:cb3d968589d8 8266 #define LLWU_PE4_WUPE15_SHIFT 6
Kojto 90:cb3d968589d8 8267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
Kojto 90:cb3d968589d8 8268 /* ME Bit Fields */
Kojto 90:cb3d968589d8 8269 #define LLWU_ME_WUME0_MASK 0x1u
Kojto 90:cb3d968589d8 8270 #define LLWU_ME_WUME0_SHIFT 0
Kojto 90:cb3d968589d8 8271 #define LLWU_ME_WUME1_MASK 0x2u
Kojto 90:cb3d968589d8 8272 #define LLWU_ME_WUME1_SHIFT 1
Kojto 90:cb3d968589d8 8273 #define LLWU_ME_WUME2_MASK 0x4u
Kojto 90:cb3d968589d8 8274 #define LLWU_ME_WUME2_SHIFT 2
Kojto 90:cb3d968589d8 8275 #define LLWU_ME_WUME3_MASK 0x8u
Kojto 90:cb3d968589d8 8276 #define LLWU_ME_WUME3_SHIFT 3
Kojto 90:cb3d968589d8 8277 #define LLWU_ME_WUME4_MASK 0x10u
Kojto 90:cb3d968589d8 8278 #define LLWU_ME_WUME4_SHIFT 4
Kojto 90:cb3d968589d8 8279 #define LLWU_ME_WUME5_MASK 0x20u
Kojto 90:cb3d968589d8 8280 #define LLWU_ME_WUME5_SHIFT 5
Kojto 90:cb3d968589d8 8281 #define LLWU_ME_WUME6_MASK 0x40u
Kojto 90:cb3d968589d8 8282 #define LLWU_ME_WUME6_SHIFT 6
Kojto 90:cb3d968589d8 8283 #define LLWU_ME_WUME7_MASK 0x80u
Kojto 90:cb3d968589d8 8284 #define LLWU_ME_WUME7_SHIFT 7
Kojto 90:cb3d968589d8 8285 /* F1 Bit Fields */
Kojto 90:cb3d968589d8 8286 #define LLWU_F1_WUF0_MASK 0x1u
Kojto 90:cb3d968589d8 8287 #define LLWU_F1_WUF0_SHIFT 0
Kojto 90:cb3d968589d8 8288 #define LLWU_F1_WUF1_MASK 0x2u
Kojto 90:cb3d968589d8 8289 #define LLWU_F1_WUF1_SHIFT 1
Kojto 90:cb3d968589d8 8290 #define LLWU_F1_WUF2_MASK 0x4u
Kojto 90:cb3d968589d8 8291 #define LLWU_F1_WUF2_SHIFT 2
Kojto 90:cb3d968589d8 8292 #define LLWU_F1_WUF3_MASK 0x8u
Kojto 90:cb3d968589d8 8293 #define LLWU_F1_WUF3_SHIFT 3
Kojto 90:cb3d968589d8 8294 #define LLWU_F1_WUF4_MASK 0x10u
Kojto 90:cb3d968589d8 8295 #define LLWU_F1_WUF4_SHIFT 4
Kojto 90:cb3d968589d8 8296 #define LLWU_F1_WUF5_MASK 0x20u
Kojto 90:cb3d968589d8 8297 #define LLWU_F1_WUF5_SHIFT 5
Kojto 90:cb3d968589d8 8298 #define LLWU_F1_WUF6_MASK 0x40u
Kojto 90:cb3d968589d8 8299 #define LLWU_F1_WUF6_SHIFT 6
Kojto 90:cb3d968589d8 8300 #define LLWU_F1_WUF7_MASK 0x80u
Kojto 90:cb3d968589d8 8301 #define LLWU_F1_WUF7_SHIFT 7
Kojto 90:cb3d968589d8 8302 /* F2 Bit Fields */
Kojto 90:cb3d968589d8 8303 #define LLWU_F2_WUF8_MASK 0x1u
Kojto 90:cb3d968589d8 8304 #define LLWU_F2_WUF8_SHIFT 0
Kojto 90:cb3d968589d8 8305 #define LLWU_F2_WUF9_MASK 0x2u
Kojto 90:cb3d968589d8 8306 #define LLWU_F2_WUF9_SHIFT 1
Kojto 90:cb3d968589d8 8307 #define LLWU_F2_WUF10_MASK 0x4u
Kojto 90:cb3d968589d8 8308 #define LLWU_F2_WUF10_SHIFT 2
Kojto 90:cb3d968589d8 8309 #define LLWU_F2_WUF11_MASK 0x8u
Kojto 90:cb3d968589d8 8310 #define LLWU_F2_WUF11_SHIFT 3
Kojto 90:cb3d968589d8 8311 #define LLWU_F2_WUF12_MASK 0x10u
Kojto 90:cb3d968589d8 8312 #define LLWU_F2_WUF12_SHIFT 4
Kojto 90:cb3d968589d8 8313 #define LLWU_F2_WUF13_MASK 0x20u
Kojto 90:cb3d968589d8 8314 #define LLWU_F2_WUF13_SHIFT 5
Kojto 90:cb3d968589d8 8315 #define LLWU_F2_WUF14_MASK 0x40u
Kojto 90:cb3d968589d8 8316 #define LLWU_F2_WUF14_SHIFT 6
Kojto 90:cb3d968589d8 8317 #define LLWU_F2_WUF15_MASK 0x80u
Kojto 90:cb3d968589d8 8318 #define LLWU_F2_WUF15_SHIFT 7
Kojto 90:cb3d968589d8 8319 /* F3 Bit Fields */
Kojto 90:cb3d968589d8 8320 #define LLWU_F3_MWUF0_MASK 0x1u
Kojto 90:cb3d968589d8 8321 #define LLWU_F3_MWUF0_SHIFT 0
Kojto 90:cb3d968589d8 8322 #define LLWU_F3_MWUF1_MASK 0x2u
Kojto 90:cb3d968589d8 8323 #define LLWU_F3_MWUF1_SHIFT 1
Kojto 90:cb3d968589d8 8324 #define LLWU_F3_MWUF2_MASK 0x4u
Kojto 90:cb3d968589d8 8325 #define LLWU_F3_MWUF2_SHIFT 2
Kojto 90:cb3d968589d8 8326 #define LLWU_F3_MWUF3_MASK 0x8u
Kojto 90:cb3d968589d8 8327 #define LLWU_F3_MWUF3_SHIFT 3
Kojto 90:cb3d968589d8 8328 #define LLWU_F3_MWUF4_MASK 0x10u
Kojto 90:cb3d968589d8 8329 #define LLWU_F3_MWUF4_SHIFT 4
Kojto 90:cb3d968589d8 8330 #define LLWU_F3_MWUF5_MASK 0x20u
Kojto 90:cb3d968589d8 8331 #define LLWU_F3_MWUF5_SHIFT 5
Kojto 90:cb3d968589d8 8332 #define LLWU_F3_MWUF6_MASK 0x40u
Kojto 90:cb3d968589d8 8333 #define LLWU_F3_MWUF6_SHIFT 6
Kojto 90:cb3d968589d8 8334 #define LLWU_F3_MWUF7_MASK 0x80u
Kojto 90:cb3d968589d8 8335 #define LLWU_F3_MWUF7_SHIFT 7
Kojto 90:cb3d968589d8 8336 /* FILT1 Bit Fields */
Kojto 90:cb3d968589d8 8337 #define LLWU_FILT1_FILTSEL_MASK 0xFu
Kojto 90:cb3d968589d8 8338 #define LLWU_FILT1_FILTSEL_SHIFT 0
Kojto 90:cb3d968589d8 8339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
Kojto 90:cb3d968589d8 8340 #define LLWU_FILT1_FILTE_MASK 0x60u
Kojto 90:cb3d968589d8 8341 #define LLWU_FILT1_FILTE_SHIFT 5
Kojto 90:cb3d968589d8 8342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
Kojto 90:cb3d968589d8 8343 #define LLWU_FILT1_FILTF_MASK 0x80u
Kojto 90:cb3d968589d8 8344 #define LLWU_FILT1_FILTF_SHIFT 7
Kojto 90:cb3d968589d8 8345 /* FILT2 Bit Fields */
Kojto 90:cb3d968589d8 8346 #define LLWU_FILT2_FILTSEL_MASK 0xFu
Kojto 90:cb3d968589d8 8347 #define LLWU_FILT2_FILTSEL_SHIFT 0
Kojto 90:cb3d968589d8 8348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
Kojto 90:cb3d968589d8 8349 #define LLWU_FILT2_FILTE_MASK 0x60u
Kojto 90:cb3d968589d8 8350 #define LLWU_FILT2_FILTE_SHIFT 5
Kojto 90:cb3d968589d8 8351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
Kojto 90:cb3d968589d8 8352 #define LLWU_FILT2_FILTF_MASK 0x80u
Kojto 90:cb3d968589d8 8353 #define LLWU_FILT2_FILTF_SHIFT 7
Kojto 90:cb3d968589d8 8354 /* RST Bit Fields */
Kojto 90:cb3d968589d8 8355 #define LLWU_RST_RSTFILT_MASK 0x1u
Kojto 90:cb3d968589d8 8356 #define LLWU_RST_RSTFILT_SHIFT 0
Kojto 90:cb3d968589d8 8357 #define LLWU_RST_LLRSTE_MASK 0x2u
Kojto 90:cb3d968589d8 8358 #define LLWU_RST_LLRSTE_SHIFT 1
Kojto 90:cb3d968589d8 8359
Kojto 90:cb3d968589d8 8360 /*!
Kojto 90:cb3d968589d8 8361 * @}
Kojto 90:cb3d968589d8 8362 */ /* end of group LLWU_Register_Masks */
Kojto 90:cb3d968589d8 8363
Kojto 90:cb3d968589d8 8364
Kojto 90:cb3d968589d8 8365 /* LLWU - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8366 /** Peripheral LLWU base address */
Kojto 90:cb3d968589d8 8367 #define LLWU_BASE (0x4007C000u)
Kojto 90:cb3d968589d8 8368 /** Peripheral LLWU base pointer */
Kojto 90:cb3d968589d8 8369 #define LLWU ((LLWU_Type *)LLWU_BASE)
Kojto 90:cb3d968589d8 8370 #define LLWU_BASE_PTR (LLWU)
Kojto 90:cb3d968589d8 8371 /** Array initializer of LLWU peripheral base addresses */
Kojto 90:cb3d968589d8 8372 #define LLWU_BASE_ADDRS { LLWU_BASE }
Kojto 90:cb3d968589d8 8373 /** Array initializer of LLWU peripheral base pointers */
Kojto 90:cb3d968589d8 8374 #define LLWU_BASE_PTRS { LLWU }
Kojto 90:cb3d968589d8 8375 /** Interrupt vectors for the LLWU peripheral type */
Kojto 90:cb3d968589d8 8376 #define LLWU_IRQS { LLW_IRQn }
Kojto 90:cb3d968589d8 8377
Kojto 90:cb3d968589d8 8378 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8379 -- LLWU - Register accessor macros
Kojto 90:cb3d968589d8 8380 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8381
Kojto 90:cb3d968589d8 8382 /*!
Kojto 90:cb3d968589d8 8383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Kojto 90:cb3d968589d8 8384 * @{
Kojto 90:cb3d968589d8 8385 */
Kojto 90:cb3d968589d8 8386
Kojto 90:cb3d968589d8 8387
Kojto 90:cb3d968589d8 8388 /* LLWU - Register instance definitions */
Kojto 90:cb3d968589d8 8389 /* LLWU */
Kojto 90:cb3d968589d8 8390 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
Kojto 90:cb3d968589d8 8391 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
Kojto 90:cb3d968589d8 8392 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
Kojto 90:cb3d968589d8 8393 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
Kojto 90:cb3d968589d8 8394 #define LLWU_ME LLWU_ME_REG(LLWU)
Kojto 90:cb3d968589d8 8395 #define LLWU_F1 LLWU_F1_REG(LLWU)
Kojto 90:cb3d968589d8 8396 #define LLWU_F2 LLWU_F2_REG(LLWU)
Kojto 90:cb3d968589d8 8397 #define LLWU_F3 LLWU_F3_REG(LLWU)
Kojto 90:cb3d968589d8 8398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
Kojto 90:cb3d968589d8 8399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
Kojto 90:cb3d968589d8 8400 #define LLWU_RST LLWU_RST_REG(LLWU)
Kojto 90:cb3d968589d8 8401
Kojto 90:cb3d968589d8 8402 /*!
Kojto 90:cb3d968589d8 8403 * @}
Kojto 90:cb3d968589d8 8404 */ /* end of group LLWU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8405
Kojto 90:cb3d968589d8 8406
Kojto 90:cb3d968589d8 8407 /*!
Kojto 90:cb3d968589d8 8408 * @}
Kojto 90:cb3d968589d8 8409 */ /* end of group LLWU_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8410
Kojto 90:cb3d968589d8 8411
Kojto 90:cb3d968589d8 8412 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8413 -- LPTMR Peripheral Access Layer
Kojto 90:cb3d968589d8 8414 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8415
Kojto 90:cb3d968589d8 8416 /*!
Kojto 90:cb3d968589d8 8417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Kojto 90:cb3d968589d8 8418 * @{
Kojto 90:cb3d968589d8 8419 */
Kojto 90:cb3d968589d8 8420
Kojto 90:cb3d968589d8 8421 /** LPTMR - Register Layout Typedef */
Kojto 90:cb3d968589d8 8422 typedef struct {
Kojto 90:cb3d968589d8 8423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 8424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
Kojto 90:cb3d968589d8 8425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
Kojto 90:cb3d968589d8 8426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
Kojto 90:cb3d968589d8 8427 } LPTMR_Type, *LPTMR_MemMapPtr;
Kojto 90:cb3d968589d8 8428
Kojto 90:cb3d968589d8 8429 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8430 -- LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 8431 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8432
Kojto 90:cb3d968589d8 8433 /*!
Kojto 90:cb3d968589d8 8434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 8435 * @{
Kojto 90:cb3d968589d8 8436 */
Kojto 90:cb3d968589d8 8437
Kojto 90:cb3d968589d8 8438
Kojto 90:cb3d968589d8 8439 /* LPTMR - Register accessors */
Kojto 90:cb3d968589d8 8440 #define LPTMR_CSR_REG(base) ((base)->CSR)
Kojto 90:cb3d968589d8 8441 #define LPTMR_PSR_REG(base) ((base)->PSR)
Kojto 90:cb3d968589d8 8442 #define LPTMR_CMR_REG(base) ((base)->CMR)
Kojto 90:cb3d968589d8 8443 #define LPTMR_CNR_REG(base) ((base)->CNR)
Kojto 90:cb3d968589d8 8444
Kojto 90:cb3d968589d8 8445 /*!
Kojto 90:cb3d968589d8 8446 * @}
Kojto 90:cb3d968589d8 8447 */ /* end of group LPTMR_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8448
Kojto 90:cb3d968589d8 8449
Kojto 90:cb3d968589d8 8450 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8451 -- LPTMR Register Masks
Kojto 90:cb3d968589d8 8452 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8453
Kojto 90:cb3d968589d8 8454 /*!
Kojto 90:cb3d968589d8 8455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Kojto 90:cb3d968589d8 8456 * @{
Kojto 90:cb3d968589d8 8457 */
Kojto 90:cb3d968589d8 8458
Kojto 90:cb3d968589d8 8459 /* CSR Bit Fields */
Kojto 90:cb3d968589d8 8460 #define LPTMR_CSR_TEN_MASK 0x1u
Kojto 90:cb3d968589d8 8461 #define LPTMR_CSR_TEN_SHIFT 0
Kojto 90:cb3d968589d8 8462 #define LPTMR_CSR_TMS_MASK 0x2u
Kojto 90:cb3d968589d8 8463 #define LPTMR_CSR_TMS_SHIFT 1
Kojto 90:cb3d968589d8 8464 #define LPTMR_CSR_TFC_MASK 0x4u
Kojto 90:cb3d968589d8 8465 #define LPTMR_CSR_TFC_SHIFT 2
Kojto 90:cb3d968589d8 8466 #define LPTMR_CSR_TPP_MASK 0x8u
Kojto 90:cb3d968589d8 8467 #define LPTMR_CSR_TPP_SHIFT 3
Kojto 90:cb3d968589d8 8468 #define LPTMR_CSR_TPS_MASK 0x30u
Kojto 90:cb3d968589d8 8469 #define LPTMR_CSR_TPS_SHIFT 4
Kojto 90:cb3d968589d8 8470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
Kojto 90:cb3d968589d8 8471 #define LPTMR_CSR_TIE_MASK 0x40u
Kojto 90:cb3d968589d8 8472 #define LPTMR_CSR_TIE_SHIFT 6
Kojto 90:cb3d968589d8 8473 #define LPTMR_CSR_TCF_MASK 0x80u
Kojto 90:cb3d968589d8 8474 #define LPTMR_CSR_TCF_SHIFT 7
Kojto 90:cb3d968589d8 8475 /* PSR Bit Fields */
Kojto 90:cb3d968589d8 8476 #define LPTMR_PSR_PCS_MASK 0x3u
Kojto 90:cb3d968589d8 8477 #define LPTMR_PSR_PCS_SHIFT 0
Kojto 90:cb3d968589d8 8478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
Kojto 90:cb3d968589d8 8479 #define LPTMR_PSR_PBYP_MASK 0x4u
Kojto 90:cb3d968589d8 8480 #define LPTMR_PSR_PBYP_SHIFT 2
Kojto 90:cb3d968589d8 8481 #define LPTMR_PSR_PRESCALE_MASK 0x78u
Kojto 90:cb3d968589d8 8482 #define LPTMR_PSR_PRESCALE_SHIFT 3
Kojto 90:cb3d968589d8 8483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
Kojto 90:cb3d968589d8 8484 /* CMR Bit Fields */
Kojto 90:cb3d968589d8 8485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
Kojto 90:cb3d968589d8 8486 #define LPTMR_CMR_COMPARE_SHIFT 0
Kojto 90:cb3d968589d8 8487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
Kojto 90:cb3d968589d8 8488 /* CNR Bit Fields */
Kojto 90:cb3d968589d8 8489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
Kojto 90:cb3d968589d8 8490 #define LPTMR_CNR_COUNTER_SHIFT 0
Kojto 90:cb3d968589d8 8491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
Kojto 90:cb3d968589d8 8492
Kojto 90:cb3d968589d8 8493 /*!
Kojto 90:cb3d968589d8 8494 * @}
Kojto 90:cb3d968589d8 8495 */ /* end of group LPTMR_Register_Masks */
Kojto 90:cb3d968589d8 8496
Kojto 90:cb3d968589d8 8497
Kojto 90:cb3d968589d8 8498 /* LPTMR - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8499 /** Peripheral LPTMR0 base address */
Kojto 90:cb3d968589d8 8500 #define LPTMR0_BASE (0x40040000u)
Kojto 90:cb3d968589d8 8501 /** Peripheral LPTMR0 base pointer */
Kojto 90:cb3d968589d8 8502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Kojto 90:cb3d968589d8 8503 #define LPTMR0_BASE_PTR (LPTMR0)
Kojto 90:cb3d968589d8 8504 /** Array initializer of LPTMR peripheral base addresses */
Kojto 90:cb3d968589d8 8505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
Kojto 90:cb3d968589d8 8506 /** Array initializer of LPTMR peripheral base pointers */
Kojto 90:cb3d968589d8 8507 #define LPTMR_BASE_PTRS { LPTMR0 }
Kojto 90:cb3d968589d8 8508 /** Interrupt vectors for the LPTMR peripheral type */
Kojto 90:cb3d968589d8 8509 #define LPTMR_IRQS { LPTimer_IRQn }
Kojto 90:cb3d968589d8 8510
Kojto 90:cb3d968589d8 8511 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8512 -- LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 8513 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8514
Kojto 90:cb3d968589d8 8515 /*!
Kojto 90:cb3d968589d8 8516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 8517 * @{
Kojto 90:cb3d968589d8 8518 */
Kojto 90:cb3d968589d8 8519
Kojto 90:cb3d968589d8 8520
Kojto 90:cb3d968589d8 8521 /* LPTMR - Register instance definitions */
Kojto 90:cb3d968589d8 8522 /* LPTMR0 */
Kojto 90:cb3d968589d8 8523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
Kojto 90:cb3d968589d8 8524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
Kojto 90:cb3d968589d8 8525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
Kojto 90:cb3d968589d8 8526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
Kojto 90:cb3d968589d8 8527
Kojto 90:cb3d968589d8 8528 /*!
Kojto 90:cb3d968589d8 8529 * @}
Kojto 90:cb3d968589d8 8530 */ /* end of group LPTMR_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8531
Kojto 90:cb3d968589d8 8532
Kojto 90:cb3d968589d8 8533 /*!
Kojto 90:cb3d968589d8 8534 * @}
Kojto 90:cb3d968589d8 8535 */ /* end of group LPTMR_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8536
Kojto 90:cb3d968589d8 8537
Kojto 90:cb3d968589d8 8538 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8539 -- MCG Peripheral Access Layer
Kojto 90:cb3d968589d8 8540 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8541
Kojto 90:cb3d968589d8 8542 /*!
Kojto 90:cb3d968589d8 8543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Kojto 90:cb3d968589d8 8544 * @{
Kojto 90:cb3d968589d8 8545 */
Kojto 90:cb3d968589d8 8546
Kojto 90:cb3d968589d8 8547 /** MCG - Register Layout Typedef */
Kojto 90:cb3d968589d8 8548 typedef struct {
Kojto 90:cb3d968589d8 8549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
Kojto 90:cb3d968589d8 8550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
Kojto 90:cb3d968589d8 8551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
Kojto 90:cb3d968589d8 8552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
Kojto 90:cb3d968589d8 8553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
Kojto 90:cb3d968589d8 8554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
Kojto 90:cb3d968589d8 8555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
Kojto 90:cb3d968589d8 8556 uint8_t RESERVED_0[1];
Kojto 90:cb3d968589d8 8557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 8558 uint8_t RESERVED_1[1];
Kojto 90:cb3d968589d8 8559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
Kojto 90:cb3d968589d8 8560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
Kojto 90:cb3d968589d8 8561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
Kojto 90:cb3d968589d8 8562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
Kojto 90:cb3d968589d8 8563 } MCG_Type, *MCG_MemMapPtr;
Kojto 90:cb3d968589d8 8564
Kojto 90:cb3d968589d8 8565 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8566 -- MCG - Register accessor macros
Kojto 90:cb3d968589d8 8567 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8568
Kojto 90:cb3d968589d8 8569 /*!
Kojto 90:cb3d968589d8 8570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Kojto 90:cb3d968589d8 8571 * @{
Kojto 90:cb3d968589d8 8572 */
Kojto 90:cb3d968589d8 8573
Kojto 90:cb3d968589d8 8574
Kojto 90:cb3d968589d8 8575 /* MCG - Register accessors */
Kojto 90:cb3d968589d8 8576 #define MCG_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 8577 #define MCG_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 8578 #define MCG_C3_REG(base) ((base)->C3)
Kojto 90:cb3d968589d8 8579 #define MCG_C4_REG(base) ((base)->C4)
Kojto 90:cb3d968589d8 8580 #define MCG_C5_REG(base) ((base)->C5)
Kojto 90:cb3d968589d8 8581 #define MCG_C6_REG(base) ((base)->C6)
Kojto 90:cb3d968589d8 8582 #define MCG_S_REG(base) ((base)->S)
Kojto 90:cb3d968589d8 8583 #define MCG_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 8584 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
Kojto 90:cb3d968589d8 8585 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
Kojto 90:cb3d968589d8 8586 #define MCG_C7_REG(base) ((base)->C7)
Kojto 90:cb3d968589d8 8587 #define MCG_C8_REG(base) ((base)->C8)
Kojto 90:cb3d968589d8 8588
Kojto 90:cb3d968589d8 8589 /*!
Kojto 90:cb3d968589d8 8590 * @}
Kojto 90:cb3d968589d8 8591 */ /* end of group MCG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8592
Kojto 90:cb3d968589d8 8593
Kojto 90:cb3d968589d8 8594 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8595 -- MCG Register Masks
Kojto 90:cb3d968589d8 8596 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8597
Kojto 90:cb3d968589d8 8598 /*!
Kojto 90:cb3d968589d8 8599 * @addtogroup MCG_Register_Masks MCG Register Masks
Kojto 90:cb3d968589d8 8600 * @{
Kojto 90:cb3d968589d8 8601 */
Kojto 90:cb3d968589d8 8602
Kojto 90:cb3d968589d8 8603 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 8604 #define MCG_C1_IREFSTEN_MASK 0x1u
Kojto 90:cb3d968589d8 8605 #define MCG_C1_IREFSTEN_SHIFT 0
Kojto 90:cb3d968589d8 8606 #define MCG_C1_IRCLKEN_MASK 0x2u
Kojto 90:cb3d968589d8 8607 #define MCG_C1_IRCLKEN_SHIFT 1
Kojto 90:cb3d968589d8 8608 #define MCG_C1_IREFS_MASK 0x4u
Kojto 90:cb3d968589d8 8609 #define MCG_C1_IREFS_SHIFT 2
Kojto 90:cb3d968589d8 8610 #define MCG_C1_FRDIV_MASK 0x38u
Kojto 90:cb3d968589d8 8611 #define MCG_C1_FRDIV_SHIFT 3
Kojto 90:cb3d968589d8 8612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
Kojto 90:cb3d968589d8 8613 #define MCG_C1_CLKS_MASK 0xC0u
Kojto 90:cb3d968589d8 8614 #define MCG_C1_CLKS_SHIFT 6
Kojto 90:cb3d968589d8 8615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
Kojto 90:cb3d968589d8 8616 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 8617 #define MCG_C2_IRCS_MASK 0x1u
Kojto 90:cb3d968589d8 8618 #define MCG_C2_IRCS_SHIFT 0
Kojto 90:cb3d968589d8 8619 #define MCG_C2_LP_MASK 0x2u
Kojto 90:cb3d968589d8 8620 #define MCG_C2_LP_SHIFT 1
Kojto 90:cb3d968589d8 8621 #define MCG_C2_EREFS_MASK 0x4u
Kojto 90:cb3d968589d8 8622 #define MCG_C2_EREFS_SHIFT 2
Kojto 90:cb3d968589d8 8623 #define MCG_C2_HGO_MASK 0x8u
Kojto 90:cb3d968589d8 8624 #define MCG_C2_HGO_SHIFT 3
Kojto 90:cb3d968589d8 8625 #define MCG_C2_RANGE_MASK 0x30u
Kojto 90:cb3d968589d8 8626 #define MCG_C2_RANGE_SHIFT 4
Kojto 90:cb3d968589d8 8627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
Kojto 90:cb3d968589d8 8628 #define MCG_C2_FCFTRIM_MASK 0x40u
Kojto 90:cb3d968589d8 8629 #define MCG_C2_FCFTRIM_SHIFT 6
Kojto 90:cb3d968589d8 8630 #define MCG_C2_LOCRE0_MASK 0x80u
Kojto 90:cb3d968589d8 8631 #define MCG_C2_LOCRE0_SHIFT 7
Kojto 90:cb3d968589d8 8632 /* C3 Bit Fields */
Kojto 90:cb3d968589d8 8633 #define MCG_C3_SCTRIM_MASK 0xFFu
Kojto 90:cb3d968589d8 8634 #define MCG_C3_SCTRIM_SHIFT 0
Kojto 90:cb3d968589d8 8635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
Kojto 90:cb3d968589d8 8636 /* C4 Bit Fields */
Kojto 90:cb3d968589d8 8637 #define MCG_C4_SCFTRIM_MASK 0x1u
Kojto 90:cb3d968589d8 8638 #define MCG_C4_SCFTRIM_SHIFT 0
Kojto 90:cb3d968589d8 8639 #define MCG_C4_FCTRIM_MASK 0x1Eu
Kojto 90:cb3d968589d8 8640 #define MCG_C4_FCTRIM_SHIFT 1
Kojto 90:cb3d968589d8 8641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
Kojto 90:cb3d968589d8 8642 #define MCG_C4_DRST_DRS_MASK 0x60u
Kojto 90:cb3d968589d8 8643 #define MCG_C4_DRST_DRS_SHIFT 5
Kojto 90:cb3d968589d8 8644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
Kojto 90:cb3d968589d8 8645 #define MCG_C4_DMX32_MASK 0x80u
Kojto 90:cb3d968589d8 8646 #define MCG_C4_DMX32_SHIFT 7
Kojto 90:cb3d968589d8 8647 /* C5 Bit Fields */
Kojto 90:cb3d968589d8 8648 #define MCG_C5_PRDIV0_MASK 0x1Fu
Kojto 90:cb3d968589d8 8649 #define MCG_C5_PRDIV0_SHIFT 0
Kojto 90:cb3d968589d8 8650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
Kojto 90:cb3d968589d8 8651 #define MCG_C5_PLLSTEN0_MASK 0x20u
Kojto 90:cb3d968589d8 8652 #define MCG_C5_PLLSTEN0_SHIFT 5
Kojto 90:cb3d968589d8 8653 #define MCG_C5_PLLCLKEN0_MASK 0x40u
Kojto 90:cb3d968589d8 8654 #define MCG_C5_PLLCLKEN0_SHIFT 6
Kojto 90:cb3d968589d8 8655 /* C6 Bit Fields */
Kojto 90:cb3d968589d8 8656 #define MCG_C6_VDIV0_MASK 0x1Fu
Kojto 90:cb3d968589d8 8657 #define MCG_C6_VDIV0_SHIFT 0
Kojto 90:cb3d968589d8 8658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
Kojto 90:cb3d968589d8 8659 #define MCG_C6_CME0_MASK 0x20u
Kojto 90:cb3d968589d8 8660 #define MCG_C6_CME0_SHIFT 5
Kojto 90:cb3d968589d8 8661 #define MCG_C6_PLLS_MASK 0x40u
Kojto 90:cb3d968589d8 8662 #define MCG_C6_PLLS_SHIFT 6
Kojto 90:cb3d968589d8 8663 #define MCG_C6_LOLIE0_MASK 0x80u
Kojto 90:cb3d968589d8 8664 #define MCG_C6_LOLIE0_SHIFT 7
Kojto 90:cb3d968589d8 8665 /* S Bit Fields */
Kojto 90:cb3d968589d8 8666 #define MCG_S_IRCST_MASK 0x1u
Kojto 90:cb3d968589d8 8667 #define MCG_S_IRCST_SHIFT 0
Kojto 90:cb3d968589d8 8668 #define MCG_S_OSCINIT0_MASK 0x2u
Kojto 90:cb3d968589d8 8669 #define MCG_S_OSCINIT0_SHIFT 1
Kojto 90:cb3d968589d8 8670 #define MCG_S_CLKST_MASK 0xCu
Kojto 90:cb3d968589d8 8671 #define MCG_S_CLKST_SHIFT 2
Kojto 90:cb3d968589d8 8672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
Kojto 90:cb3d968589d8 8673 #define MCG_S_IREFST_MASK 0x10u
Kojto 90:cb3d968589d8 8674 #define MCG_S_IREFST_SHIFT 4
Kojto 90:cb3d968589d8 8675 #define MCG_S_PLLST_MASK 0x20u
Kojto 90:cb3d968589d8 8676 #define MCG_S_PLLST_SHIFT 5
Kojto 90:cb3d968589d8 8677 #define MCG_S_LOCK0_MASK 0x40u
Kojto 90:cb3d968589d8 8678 #define MCG_S_LOCK0_SHIFT 6
Kojto 90:cb3d968589d8 8679 #define MCG_S_LOLS0_MASK 0x80u
Kojto 90:cb3d968589d8 8680 #define MCG_S_LOLS0_SHIFT 7
Kojto 90:cb3d968589d8 8681 /* SC Bit Fields */
Kojto 90:cb3d968589d8 8682 #define MCG_SC_LOCS0_MASK 0x1u
Kojto 90:cb3d968589d8 8683 #define MCG_SC_LOCS0_SHIFT 0
Kojto 90:cb3d968589d8 8684 #define MCG_SC_FCRDIV_MASK 0xEu
Kojto 90:cb3d968589d8 8685 #define MCG_SC_FCRDIV_SHIFT 1
Kojto 90:cb3d968589d8 8686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
Kojto 90:cb3d968589d8 8687 #define MCG_SC_FLTPRSRV_MASK 0x10u
Kojto 90:cb3d968589d8 8688 #define MCG_SC_FLTPRSRV_SHIFT 4
Kojto 90:cb3d968589d8 8689 #define MCG_SC_ATMF_MASK 0x20u
Kojto 90:cb3d968589d8 8690 #define MCG_SC_ATMF_SHIFT 5
Kojto 90:cb3d968589d8 8691 #define MCG_SC_ATMS_MASK 0x40u
Kojto 90:cb3d968589d8 8692 #define MCG_SC_ATMS_SHIFT 6
Kojto 90:cb3d968589d8 8693 #define MCG_SC_ATME_MASK 0x80u
Kojto 90:cb3d968589d8 8694 #define MCG_SC_ATME_SHIFT 7
Kojto 90:cb3d968589d8 8695 /* ATCVH Bit Fields */
Kojto 90:cb3d968589d8 8696 #define MCG_ATCVH_ATCVH_MASK 0xFFu
Kojto 90:cb3d968589d8 8697 #define MCG_ATCVH_ATCVH_SHIFT 0
Kojto 90:cb3d968589d8 8698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
Kojto 90:cb3d968589d8 8699 /* ATCVL Bit Fields */
Kojto 90:cb3d968589d8 8700 #define MCG_ATCVL_ATCVL_MASK 0xFFu
Kojto 90:cb3d968589d8 8701 #define MCG_ATCVL_ATCVL_SHIFT 0
Kojto 90:cb3d968589d8 8702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
Kojto 90:cb3d968589d8 8703 /* C7 Bit Fields */
Kojto 90:cb3d968589d8 8704 #define MCG_C7_OSCSEL_MASK 0x3u
Kojto 90:cb3d968589d8 8705 #define MCG_C7_OSCSEL_SHIFT 0
Kojto 90:cb3d968589d8 8706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
Kojto 90:cb3d968589d8 8707 /* C8 Bit Fields */
Kojto 90:cb3d968589d8 8708 #define MCG_C8_LOCS1_MASK 0x1u
Kojto 90:cb3d968589d8 8709 #define MCG_C8_LOCS1_SHIFT 0
Kojto 90:cb3d968589d8 8710 #define MCG_C8_CME1_MASK 0x20u
Kojto 90:cb3d968589d8 8711 #define MCG_C8_CME1_SHIFT 5
Kojto 90:cb3d968589d8 8712 #define MCG_C8_LOLRE_MASK 0x40u
Kojto 90:cb3d968589d8 8713 #define MCG_C8_LOLRE_SHIFT 6
Kojto 90:cb3d968589d8 8714 #define MCG_C8_LOCRE1_MASK 0x80u
Kojto 90:cb3d968589d8 8715 #define MCG_C8_LOCRE1_SHIFT 7
Kojto 90:cb3d968589d8 8716
Kojto 90:cb3d968589d8 8717 /*!
Kojto 90:cb3d968589d8 8718 * @}
Kojto 90:cb3d968589d8 8719 */ /* end of group MCG_Register_Masks */
Kojto 90:cb3d968589d8 8720
Kojto 90:cb3d968589d8 8721
Kojto 90:cb3d968589d8 8722 /* MCG - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8723 /** Peripheral MCG base address */
Kojto 90:cb3d968589d8 8724 #define MCG_BASE (0x40064000u)
Kojto 90:cb3d968589d8 8725 /** Peripheral MCG base pointer */
Kojto 90:cb3d968589d8 8726 #define MCG ((MCG_Type *)MCG_BASE)
Kojto 90:cb3d968589d8 8727 #define MCG_BASE_PTR (MCG)
Kojto 90:cb3d968589d8 8728 /** Array initializer of MCG peripheral base addresses */
Kojto 90:cb3d968589d8 8729 #define MCG_BASE_ADDRS { MCG_BASE }
Kojto 90:cb3d968589d8 8730 /** Array initializer of MCG peripheral base pointers */
Kojto 90:cb3d968589d8 8731 #define MCG_BASE_PTRS { MCG }
Kojto 90:cb3d968589d8 8732
Kojto 90:cb3d968589d8 8733 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8734 -- MCG - Register accessor macros
Kojto 90:cb3d968589d8 8735 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8736
Kojto 90:cb3d968589d8 8737 /*!
Kojto 90:cb3d968589d8 8738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Kojto 90:cb3d968589d8 8739 * @{
Kojto 90:cb3d968589d8 8740 */
Kojto 90:cb3d968589d8 8741
Kojto 90:cb3d968589d8 8742
Kojto 90:cb3d968589d8 8743 /* MCG - Register instance definitions */
Kojto 90:cb3d968589d8 8744 /* MCG */
Kojto 90:cb3d968589d8 8745 #define MCG_C1 MCG_C1_REG(MCG)
Kojto 90:cb3d968589d8 8746 #define MCG_C2 MCG_C2_REG(MCG)
Kojto 90:cb3d968589d8 8747 #define MCG_C3 MCG_C3_REG(MCG)
Kojto 90:cb3d968589d8 8748 #define MCG_C4 MCG_C4_REG(MCG)
Kojto 90:cb3d968589d8 8749 #define MCG_C5 MCG_C5_REG(MCG)
Kojto 90:cb3d968589d8 8750 #define MCG_C6 MCG_C6_REG(MCG)
Kojto 90:cb3d968589d8 8751 #define MCG_S MCG_S_REG(MCG)
Kojto 90:cb3d968589d8 8752 #define MCG_SC MCG_SC_REG(MCG)
Kojto 90:cb3d968589d8 8753 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
Kojto 90:cb3d968589d8 8754 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
Kojto 90:cb3d968589d8 8755 #define MCG_C7 MCG_C7_REG(MCG)
Kojto 90:cb3d968589d8 8756 #define MCG_C8 MCG_C8_REG(MCG)
Kojto 90:cb3d968589d8 8757
Kojto 90:cb3d968589d8 8758 /*!
Kojto 90:cb3d968589d8 8759 * @}
Kojto 90:cb3d968589d8 8760 */ /* end of group MCG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8761
Kojto 90:cb3d968589d8 8762
Kojto 90:cb3d968589d8 8763 /*!
Kojto 90:cb3d968589d8 8764 * @}
Kojto 90:cb3d968589d8 8765 */ /* end of group MCG_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8766
Kojto 90:cb3d968589d8 8767
Kojto 90:cb3d968589d8 8768 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8769 -- MCM Peripheral Access Layer
Kojto 90:cb3d968589d8 8770 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8771
Kojto 90:cb3d968589d8 8772 /*!
Kojto 90:cb3d968589d8 8773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
Kojto 90:cb3d968589d8 8774 * @{
Kojto 90:cb3d968589d8 8775 */
Kojto 90:cb3d968589d8 8776
Kojto 90:cb3d968589d8 8777 /** MCM - Register Layout Typedef */
Kojto 90:cb3d968589d8 8778 typedef struct {
Kojto 90:cb3d968589d8 8779 uint8_t RESERVED_0[8];
Kojto 90:cb3d968589d8 8780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
Kojto 90:cb3d968589d8 8781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
Kojto 90:cb3d968589d8 8782 __IO uint32_t CR; /**< Control Register, offset: 0xC */
Kojto 90:cb3d968589d8 8783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
Kojto 90:cb3d968589d8 8784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
Kojto 90:cb3d968589d8 8785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
Kojto 90:cb3d968589d8 8786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
Kojto 90:cb3d968589d8 8787 uint8_t RESERVED_1[16];
Kojto 90:cb3d968589d8 8788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
Kojto 90:cb3d968589d8 8789 } MCM_Type, *MCM_MemMapPtr;
Kojto 90:cb3d968589d8 8790
Kojto 90:cb3d968589d8 8791 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8792 -- MCM - Register accessor macros
Kojto 90:cb3d968589d8 8793 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8794
Kojto 90:cb3d968589d8 8795 /*!
Kojto 90:cb3d968589d8 8796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Kojto 90:cb3d968589d8 8797 * @{
Kojto 90:cb3d968589d8 8798 */
Kojto 90:cb3d968589d8 8799
Kojto 90:cb3d968589d8 8800
Kojto 90:cb3d968589d8 8801 /* MCM - Register accessors */
Kojto 90:cb3d968589d8 8802 #define MCM_PLASC_REG(base) ((base)->PLASC)
Kojto 90:cb3d968589d8 8803 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
Kojto 90:cb3d968589d8 8804 #define MCM_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 8805 #define MCM_ISCR_REG(base) ((base)->ISCR)
Kojto 90:cb3d968589d8 8806 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
Kojto 90:cb3d968589d8 8807 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
Kojto 90:cb3d968589d8 8808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
Kojto 90:cb3d968589d8 8809 #define MCM_PID_REG(base) ((base)->PID)
Kojto 90:cb3d968589d8 8810
Kojto 90:cb3d968589d8 8811 /*!
Kojto 90:cb3d968589d8 8812 * @}
Kojto 90:cb3d968589d8 8813 */ /* end of group MCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8814
Kojto 90:cb3d968589d8 8815
Kojto 90:cb3d968589d8 8816 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8817 -- MCM Register Masks
Kojto 90:cb3d968589d8 8818 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8819
Kojto 90:cb3d968589d8 8820 /*!
Kojto 90:cb3d968589d8 8821 * @addtogroup MCM_Register_Masks MCM Register Masks
Kojto 90:cb3d968589d8 8822 * @{
Kojto 90:cb3d968589d8 8823 */
Kojto 90:cb3d968589d8 8824
Kojto 90:cb3d968589d8 8825 /* PLASC Bit Fields */
Kojto 90:cb3d968589d8 8826 #define MCM_PLASC_ASC_MASK 0xFFu
Kojto 90:cb3d968589d8 8827 #define MCM_PLASC_ASC_SHIFT 0
Kojto 90:cb3d968589d8 8828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
Kojto 90:cb3d968589d8 8829 /* PLAMC Bit Fields */
Kojto 90:cb3d968589d8 8830 #define MCM_PLAMC_AMC_MASK 0xFFu
Kojto 90:cb3d968589d8 8831 #define MCM_PLAMC_AMC_SHIFT 0
Kojto 90:cb3d968589d8 8832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
Kojto 90:cb3d968589d8 8833 /* CR Bit Fields */
Kojto 90:cb3d968589d8 8834 #define MCM_CR_SRAMUAP_MASK 0x3000000u
Kojto 90:cb3d968589d8 8835 #define MCM_CR_SRAMUAP_SHIFT 24
Kojto 90:cb3d968589d8 8836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
Kojto 90:cb3d968589d8 8837 #define MCM_CR_SRAMUWP_MASK 0x4000000u
Kojto 90:cb3d968589d8 8838 #define MCM_CR_SRAMUWP_SHIFT 26
Kojto 90:cb3d968589d8 8839 #define MCM_CR_SRAMLAP_MASK 0x30000000u
Kojto 90:cb3d968589d8 8840 #define MCM_CR_SRAMLAP_SHIFT 28
Kojto 90:cb3d968589d8 8841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
Kojto 90:cb3d968589d8 8842 #define MCM_CR_SRAMLWP_MASK 0x40000000u
Kojto 90:cb3d968589d8 8843 #define MCM_CR_SRAMLWP_SHIFT 30
Kojto 90:cb3d968589d8 8844 /* ISCR Bit Fields */
Kojto 90:cb3d968589d8 8845 #define MCM_ISCR_IRQ_MASK 0x2u
Kojto 90:cb3d968589d8 8846 #define MCM_ISCR_IRQ_SHIFT 1
Kojto 90:cb3d968589d8 8847 #define MCM_ISCR_NMI_MASK 0x4u
Kojto 90:cb3d968589d8 8848 #define MCM_ISCR_NMI_SHIFT 2
Kojto 90:cb3d968589d8 8849 #define MCM_ISCR_DHREQ_MASK 0x8u
Kojto 90:cb3d968589d8 8850 #define MCM_ISCR_DHREQ_SHIFT 3
Kojto 90:cb3d968589d8 8851 #define MCM_ISCR_FIOC_MASK 0x100u
Kojto 90:cb3d968589d8 8852 #define MCM_ISCR_FIOC_SHIFT 8
Kojto 90:cb3d968589d8 8853 #define MCM_ISCR_FDZC_MASK 0x200u
Kojto 90:cb3d968589d8 8854 #define MCM_ISCR_FDZC_SHIFT 9
Kojto 90:cb3d968589d8 8855 #define MCM_ISCR_FOFC_MASK 0x400u
Kojto 90:cb3d968589d8 8856 #define MCM_ISCR_FOFC_SHIFT 10
Kojto 90:cb3d968589d8 8857 #define MCM_ISCR_FUFC_MASK 0x800u
Kojto 90:cb3d968589d8 8858 #define MCM_ISCR_FUFC_SHIFT 11
Kojto 90:cb3d968589d8 8859 #define MCM_ISCR_FIXC_MASK 0x1000u
Kojto 90:cb3d968589d8 8860 #define MCM_ISCR_FIXC_SHIFT 12
Kojto 90:cb3d968589d8 8861 #define MCM_ISCR_FIDC_MASK 0x8000u
Kojto 90:cb3d968589d8 8862 #define MCM_ISCR_FIDC_SHIFT 15
Kojto 90:cb3d968589d8 8863 #define MCM_ISCR_FIOCE_MASK 0x1000000u
Kojto 90:cb3d968589d8 8864 #define MCM_ISCR_FIOCE_SHIFT 24
Kojto 90:cb3d968589d8 8865 #define MCM_ISCR_FDZCE_MASK 0x2000000u
Kojto 90:cb3d968589d8 8866 #define MCM_ISCR_FDZCE_SHIFT 25
Kojto 90:cb3d968589d8 8867 #define MCM_ISCR_FOFCE_MASK 0x4000000u
Kojto 90:cb3d968589d8 8868 #define MCM_ISCR_FOFCE_SHIFT 26
Kojto 90:cb3d968589d8 8869 #define MCM_ISCR_FUFCE_MASK 0x8000000u
Kojto 90:cb3d968589d8 8870 #define MCM_ISCR_FUFCE_SHIFT 27
Kojto 90:cb3d968589d8 8871 #define MCM_ISCR_FIXCE_MASK 0x10000000u
Kojto 90:cb3d968589d8 8872 #define MCM_ISCR_FIXCE_SHIFT 28
Kojto 90:cb3d968589d8 8873 #define MCM_ISCR_FIDCE_MASK 0x80000000u
Kojto 90:cb3d968589d8 8874 #define MCM_ISCR_FIDCE_SHIFT 31
Kojto 90:cb3d968589d8 8875 /* ETBCC Bit Fields */
Kojto 90:cb3d968589d8 8876 #define MCM_ETBCC_CNTEN_MASK 0x1u
Kojto 90:cb3d968589d8 8877 #define MCM_ETBCC_CNTEN_SHIFT 0
Kojto 90:cb3d968589d8 8878 #define MCM_ETBCC_RSPT_MASK 0x6u
Kojto 90:cb3d968589d8 8879 #define MCM_ETBCC_RSPT_SHIFT 1
Kojto 90:cb3d968589d8 8880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
Kojto 90:cb3d968589d8 8881 #define MCM_ETBCC_RLRQ_MASK 0x8u
Kojto 90:cb3d968589d8 8882 #define MCM_ETBCC_RLRQ_SHIFT 3
Kojto 90:cb3d968589d8 8883 #define MCM_ETBCC_ETDIS_MASK 0x10u
Kojto 90:cb3d968589d8 8884 #define MCM_ETBCC_ETDIS_SHIFT 4
Kojto 90:cb3d968589d8 8885 #define MCM_ETBCC_ITDIS_MASK 0x20u
Kojto 90:cb3d968589d8 8886 #define MCM_ETBCC_ITDIS_SHIFT 5
Kojto 90:cb3d968589d8 8887 /* ETBRL Bit Fields */
Kojto 90:cb3d968589d8 8888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
Kojto 90:cb3d968589d8 8889 #define MCM_ETBRL_RELOAD_SHIFT 0
Kojto 90:cb3d968589d8 8890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
Kojto 90:cb3d968589d8 8891 /* ETBCNT Bit Fields */
Kojto 90:cb3d968589d8 8892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
Kojto 90:cb3d968589d8 8893 #define MCM_ETBCNT_COUNTER_SHIFT 0
Kojto 90:cb3d968589d8 8894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
Kojto 90:cb3d968589d8 8895 /* PID Bit Fields */
Kojto 90:cb3d968589d8 8896 #define MCM_PID_PID_MASK 0xFFu
Kojto 90:cb3d968589d8 8897 #define MCM_PID_PID_SHIFT 0
Kojto 90:cb3d968589d8 8898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
Kojto 90:cb3d968589d8 8899
Kojto 90:cb3d968589d8 8900 /*!
Kojto 90:cb3d968589d8 8901 * @}
Kojto 90:cb3d968589d8 8902 */ /* end of group MCM_Register_Masks */
Kojto 90:cb3d968589d8 8903
Kojto 90:cb3d968589d8 8904
Kojto 90:cb3d968589d8 8905 /* MCM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8906 /** Peripheral MCM base address */
Kojto 90:cb3d968589d8 8907 #define MCM_BASE (0xE0080000u)
Kojto 90:cb3d968589d8 8908 /** Peripheral MCM base pointer */
Kojto 90:cb3d968589d8 8909 #define MCM ((MCM_Type *)MCM_BASE)
Kojto 90:cb3d968589d8 8910 #define MCM_BASE_PTR (MCM)
Kojto 90:cb3d968589d8 8911 /** Array initializer of MCM peripheral base addresses */
Kojto 90:cb3d968589d8 8912 #define MCM_BASE_ADDRS { MCM_BASE }
Kojto 90:cb3d968589d8 8913 /** Array initializer of MCM peripheral base pointers */
Kojto 90:cb3d968589d8 8914 #define MCM_BASE_PTRS { MCM }
Kojto 90:cb3d968589d8 8915
Kojto 90:cb3d968589d8 8916 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8917 -- MCM - Register accessor macros
Kojto 90:cb3d968589d8 8918 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8919
Kojto 90:cb3d968589d8 8920 /*!
Kojto 90:cb3d968589d8 8921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Kojto 90:cb3d968589d8 8922 * @{
Kojto 90:cb3d968589d8 8923 */
Kojto 90:cb3d968589d8 8924
Kojto 90:cb3d968589d8 8925
Kojto 90:cb3d968589d8 8926 /* MCM - Register instance definitions */
Kojto 90:cb3d968589d8 8927 /* MCM */
Kojto 90:cb3d968589d8 8928 #define MCM_PLASC MCM_PLASC_REG(MCM)
Kojto 90:cb3d968589d8 8929 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
Kojto 90:cb3d968589d8 8930 #define MCM_CR MCM_CR_REG(MCM)
Kojto 90:cb3d968589d8 8931 #define MCM_ISCR MCM_ISCR_REG(MCM)
Kojto 90:cb3d968589d8 8932 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
Kojto 90:cb3d968589d8 8933 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
Kojto 90:cb3d968589d8 8934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
Kojto 90:cb3d968589d8 8935 #define MCM_PID MCM_PID_REG(MCM)
Kojto 90:cb3d968589d8 8936
Kojto 90:cb3d968589d8 8937 /*!
Kojto 90:cb3d968589d8 8938 * @}
Kojto 90:cb3d968589d8 8939 */ /* end of group MCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8940
Kojto 90:cb3d968589d8 8941
Kojto 90:cb3d968589d8 8942 /*!
Kojto 90:cb3d968589d8 8943 * @}
Kojto 90:cb3d968589d8 8944 */ /* end of group MCM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8945
Kojto 90:cb3d968589d8 8946
Kojto 90:cb3d968589d8 8947 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8948 -- MPU Peripheral Access Layer
Kojto 90:cb3d968589d8 8949 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8950
Kojto 90:cb3d968589d8 8951 /*!
Kojto 90:cb3d968589d8 8952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
Kojto 90:cb3d968589d8 8953 * @{
Kojto 90:cb3d968589d8 8954 */
Kojto 90:cb3d968589d8 8955
Kojto 90:cb3d968589d8 8956 /** MPU - Register Layout Typedef */
Kojto 90:cb3d968589d8 8957 typedef struct {
Kojto 90:cb3d968589d8 8958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 8959 uint8_t RESERVED_0[12];
Kojto 90:cb3d968589d8 8960 struct { /* offset: 0x10, array step: 0x8 */
Kojto 90:cb3d968589d8 8961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
Kojto 90:cb3d968589d8 8962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
Kojto 90:cb3d968589d8 8963 } SP[5];
Kojto 90:cb3d968589d8 8964 uint8_t RESERVED_1[968];
Kojto 90:cb3d968589d8 8965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
Kojto 90:cb3d968589d8 8966 uint8_t RESERVED_2[832];
Kojto 90:cb3d968589d8 8967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
Kojto 90:cb3d968589d8 8968 } MPU_Type, *MPU_MemMapPtr;
Kojto 90:cb3d968589d8 8969
Kojto 90:cb3d968589d8 8970 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8971 -- MPU - Register accessor macros
Kojto 90:cb3d968589d8 8972 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8973
Kojto 90:cb3d968589d8 8974 /*!
Kojto 90:cb3d968589d8 8975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
Kojto 90:cb3d968589d8 8976 * @{
Kojto 90:cb3d968589d8 8977 */
Kojto 90:cb3d968589d8 8978
Kojto 90:cb3d968589d8 8979
Kojto 90:cb3d968589d8 8980 /* MPU - Register accessors */
Kojto 90:cb3d968589d8 8981 #define MPU_CESR_REG(base) ((base)->CESR)
Kojto 90:cb3d968589d8 8982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
Kojto 90:cb3d968589d8 8983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
Kojto 90:cb3d968589d8 8984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
Kojto 90:cb3d968589d8 8985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
Kojto 90:cb3d968589d8 8986
Kojto 90:cb3d968589d8 8987 /*!
Kojto 90:cb3d968589d8 8988 * @}
Kojto 90:cb3d968589d8 8989 */ /* end of group MPU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8990
Kojto 90:cb3d968589d8 8991
Kojto 90:cb3d968589d8 8992 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8993 -- MPU Register Masks
Kojto 90:cb3d968589d8 8994 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8995
Kojto 90:cb3d968589d8 8996 /*!
Kojto 90:cb3d968589d8 8997 * @addtogroup MPU_Register_Masks MPU Register Masks
Kojto 90:cb3d968589d8 8998 * @{
Kojto 90:cb3d968589d8 8999 */
Kojto 90:cb3d968589d8 9000
Kojto 90:cb3d968589d8 9001 /* CESR Bit Fields */
Kojto 90:cb3d968589d8 9002 #define MPU_CESR_VLD_MASK 0x1u
Kojto 90:cb3d968589d8 9003 #define MPU_CESR_VLD_SHIFT 0
Kojto 90:cb3d968589d8 9004 #define MPU_CESR_NRGD_MASK 0xF00u
Kojto 90:cb3d968589d8 9005 #define MPU_CESR_NRGD_SHIFT 8
Kojto 90:cb3d968589d8 9006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
Kojto 90:cb3d968589d8 9007 #define MPU_CESR_NSP_MASK 0xF000u
Kojto 90:cb3d968589d8 9008 #define MPU_CESR_NSP_SHIFT 12
Kojto 90:cb3d968589d8 9009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
Kojto 90:cb3d968589d8 9010 #define MPU_CESR_HRL_MASK 0xF0000u
Kojto 90:cb3d968589d8 9011 #define MPU_CESR_HRL_SHIFT 16
Kojto 90:cb3d968589d8 9012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
Kojto 90:cb3d968589d8 9013 #define MPU_CESR_SPERR_MASK 0xF8000000u
Kojto 90:cb3d968589d8 9014 #define MPU_CESR_SPERR_SHIFT 27
Kojto 90:cb3d968589d8 9015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
Kojto 90:cb3d968589d8 9016 /* EAR Bit Fields */
Kojto 90:cb3d968589d8 9017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 9018 #define MPU_EAR_EADDR_SHIFT 0
Kojto 90:cb3d968589d8 9019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
Kojto 90:cb3d968589d8 9020 /* EDR Bit Fields */
Kojto 90:cb3d968589d8 9021 #define MPU_EDR_ERW_MASK 0x1u
Kojto 90:cb3d968589d8 9022 #define MPU_EDR_ERW_SHIFT 0
Kojto 90:cb3d968589d8 9023 #define MPU_EDR_EATTR_MASK 0xEu
Kojto 90:cb3d968589d8 9024 #define MPU_EDR_EATTR_SHIFT 1
Kojto 90:cb3d968589d8 9025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
Kojto 90:cb3d968589d8 9026 #define MPU_EDR_EMN_MASK 0xF0u
Kojto 90:cb3d968589d8 9027 #define MPU_EDR_EMN_SHIFT 4
Kojto 90:cb3d968589d8 9028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
Kojto 90:cb3d968589d8 9029 #define MPU_EDR_EPID_MASK 0xFF00u
Kojto 90:cb3d968589d8 9030 #define MPU_EDR_EPID_SHIFT 8
Kojto 90:cb3d968589d8 9031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
Kojto 90:cb3d968589d8 9032 #define MPU_EDR_EACD_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 9033 #define MPU_EDR_EACD_SHIFT 16
Kojto 90:cb3d968589d8 9034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
Kojto 90:cb3d968589d8 9035 /* WORD Bit Fields */
Kojto 90:cb3d968589d8 9036 #define MPU_WORD_VLD_MASK 0x1u
Kojto 90:cb3d968589d8 9037 #define MPU_WORD_VLD_SHIFT 0
Kojto 90:cb3d968589d8 9038 #define MPU_WORD_M0UM_MASK 0x7u
Kojto 90:cb3d968589d8 9039 #define MPU_WORD_M0UM_SHIFT 0
Kojto 90:cb3d968589d8 9040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
Kojto 90:cb3d968589d8 9041 #define MPU_WORD_M0SM_MASK 0x18u
Kojto 90:cb3d968589d8 9042 #define MPU_WORD_M0SM_SHIFT 3
Kojto 90:cb3d968589d8 9043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
Kojto 90:cb3d968589d8 9044 #define MPU_WORD_M0PE_MASK 0x20u
Kojto 90:cb3d968589d8 9045 #define MPU_WORD_M0PE_SHIFT 5
Kojto 90:cb3d968589d8 9046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
Kojto 90:cb3d968589d8 9047 #define MPU_WORD_ENDADDR_SHIFT 5
Kojto 90:cb3d968589d8 9048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
Kojto 90:cb3d968589d8 9049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
Kojto 90:cb3d968589d8 9050 #define MPU_WORD_SRTADDR_SHIFT 5
Kojto 90:cb3d968589d8 9051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
Kojto 90:cb3d968589d8 9052 #define MPU_WORD_M1UM_MASK 0x1C0u
Kojto 90:cb3d968589d8 9053 #define MPU_WORD_M1UM_SHIFT 6
Kojto 90:cb3d968589d8 9054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
Kojto 90:cb3d968589d8 9055 #define MPU_WORD_M1SM_MASK 0x600u
Kojto 90:cb3d968589d8 9056 #define MPU_WORD_M1SM_SHIFT 9
Kojto 90:cb3d968589d8 9057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
Kojto 90:cb3d968589d8 9058 #define MPU_WORD_M1PE_MASK 0x800u
Kojto 90:cb3d968589d8 9059 #define MPU_WORD_M1PE_SHIFT 11
Kojto 90:cb3d968589d8 9060 #define MPU_WORD_M2UM_MASK 0x7000u
Kojto 90:cb3d968589d8 9061 #define MPU_WORD_M2UM_SHIFT 12
Kojto 90:cb3d968589d8 9062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
Kojto 90:cb3d968589d8 9063 #define MPU_WORD_M2SM_MASK 0x18000u
Kojto 90:cb3d968589d8 9064 #define MPU_WORD_M2SM_SHIFT 15
Kojto 90:cb3d968589d8 9065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
Kojto 90:cb3d968589d8 9066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
Kojto 90:cb3d968589d8 9067 #define MPU_WORD_PIDMASK_SHIFT 16
Kojto 90:cb3d968589d8 9068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
Kojto 90:cb3d968589d8 9069 #define MPU_WORD_M2PE_MASK 0x20000u
Kojto 90:cb3d968589d8 9070 #define MPU_WORD_M2PE_SHIFT 17
Kojto 90:cb3d968589d8 9071 #define MPU_WORD_M3UM_MASK 0x1C0000u
Kojto 90:cb3d968589d8 9072 #define MPU_WORD_M3UM_SHIFT 18
Kojto 90:cb3d968589d8 9073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
Kojto 90:cb3d968589d8 9074 #define MPU_WORD_M3SM_MASK 0x600000u
Kojto 90:cb3d968589d8 9075 #define MPU_WORD_M3SM_SHIFT 21
Kojto 90:cb3d968589d8 9076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
Kojto 90:cb3d968589d8 9077 #define MPU_WORD_M3PE_MASK 0x800000u
Kojto 90:cb3d968589d8 9078 #define MPU_WORD_M3PE_SHIFT 23
Kojto 90:cb3d968589d8 9079 #define MPU_WORD_PID_MASK 0xFF000000u
Kojto 90:cb3d968589d8 9080 #define MPU_WORD_PID_SHIFT 24
Kojto 90:cb3d968589d8 9081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
Kojto 90:cb3d968589d8 9082 #define MPU_WORD_M4WE_MASK 0x1000000u
Kojto 90:cb3d968589d8 9083 #define MPU_WORD_M4WE_SHIFT 24
Kojto 90:cb3d968589d8 9084 #define MPU_WORD_M4RE_MASK 0x2000000u
Kojto 90:cb3d968589d8 9085 #define MPU_WORD_M4RE_SHIFT 25
Kojto 90:cb3d968589d8 9086 #define MPU_WORD_M5WE_MASK 0x4000000u
Kojto 90:cb3d968589d8 9087 #define MPU_WORD_M5WE_SHIFT 26
Kojto 90:cb3d968589d8 9088 #define MPU_WORD_M5RE_MASK 0x8000000u
Kojto 90:cb3d968589d8 9089 #define MPU_WORD_M5RE_SHIFT 27
Kojto 90:cb3d968589d8 9090 #define MPU_WORD_M6WE_MASK 0x10000000u
Kojto 90:cb3d968589d8 9091 #define MPU_WORD_M6WE_SHIFT 28
Kojto 90:cb3d968589d8 9092 #define MPU_WORD_M6RE_MASK 0x20000000u
Kojto 90:cb3d968589d8 9093 #define MPU_WORD_M6RE_SHIFT 29
Kojto 90:cb3d968589d8 9094 #define MPU_WORD_M7WE_MASK 0x40000000u
Kojto 90:cb3d968589d8 9095 #define MPU_WORD_M7WE_SHIFT 30
Kojto 90:cb3d968589d8 9096 #define MPU_WORD_M7RE_MASK 0x80000000u
Kojto 90:cb3d968589d8 9097 #define MPU_WORD_M7RE_SHIFT 31
Kojto 90:cb3d968589d8 9098 /* RGDAAC Bit Fields */
Kojto 90:cb3d968589d8 9099 #define MPU_RGDAAC_M0UM_MASK 0x7u
Kojto 90:cb3d968589d8 9100 #define MPU_RGDAAC_M0UM_SHIFT 0
Kojto 90:cb3d968589d8 9101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
Kojto 90:cb3d968589d8 9102 #define MPU_RGDAAC_M0SM_MASK 0x18u
Kojto 90:cb3d968589d8 9103 #define MPU_RGDAAC_M0SM_SHIFT 3
Kojto 90:cb3d968589d8 9104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
Kojto 90:cb3d968589d8 9105 #define MPU_RGDAAC_M0PE_MASK 0x20u
Kojto 90:cb3d968589d8 9106 #define MPU_RGDAAC_M0PE_SHIFT 5
Kojto 90:cb3d968589d8 9107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
Kojto 90:cb3d968589d8 9108 #define MPU_RGDAAC_M1UM_SHIFT 6
Kojto 90:cb3d968589d8 9109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
Kojto 90:cb3d968589d8 9110 #define MPU_RGDAAC_M1SM_MASK 0x600u
Kojto 90:cb3d968589d8 9111 #define MPU_RGDAAC_M1SM_SHIFT 9
Kojto 90:cb3d968589d8 9112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
Kojto 90:cb3d968589d8 9113 #define MPU_RGDAAC_M1PE_MASK 0x800u
Kojto 90:cb3d968589d8 9114 #define MPU_RGDAAC_M1PE_SHIFT 11
Kojto 90:cb3d968589d8 9115 #define MPU_RGDAAC_M2UM_MASK 0x7000u
Kojto 90:cb3d968589d8 9116 #define MPU_RGDAAC_M2UM_SHIFT 12
Kojto 90:cb3d968589d8 9117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
Kojto 90:cb3d968589d8 9118 #define MPU_RGDAAC_M2SM_MASK 0x18000u
Kojto 90:cb3d968589d8 9119 #define MPU_RGDAAC_M2SM_SHIFT 15
Kojto 90:cb3d968589d8 9120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
Kojto 90:cb3d968589d8 9121 #define MPU_RGDAAC_M2PE_MASK 0x20000u
Kojto 90:cb3d968589d8 9122 #define MPU_RGDAAC_M2PE_SHIFT 17
Kojto 90:cb3d968589d8 9123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
Kojto 90:cb3d968589d8 9124 #define MPU_RGDAAC_M3UM_SHIFT 18
Kojto 90:cb3d968589d8 9125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
Kojto 90:cb3d968589d8 9126 #define MPU_RGDAAC_M3SM_MASK 0x600000u
Kojto 90:cb3d968589d8 9127 #define MPU_RGDAAC_M3SM_SHIFT 21
Kojto 90:cb3d968589d8 9128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
Kojto 90:cb3d968589d8 9129 #define MPU_RGDAAC_M3PE_MASK 0x800000u
Kojto 90:cb3d968589d8 9130 #define MPU_RGDAAC_M3PE_SHIFT 23
Kojto 90:cb3d968589d8 9131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
Kojto 90:cb3d968589d8 9132 #define MPU_RGDAAC_M4WE_SHIFT 24
Kojto 90:cb3d968589d8 9133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
Kojto 90:cb3d968589d8 9134 #define MPU_RGDAAC_M4RE_SHIFT 25
Kojto 90:cb3d968589d8 9135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
Kojto 90:cb3d968589d8 9136 #define MPU_RGDAAC_M5WE_SHIFT 26
Kojto 90:cb3d968589d8 9137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
Kojto 90:cb3d968589d8 9138 #define MPU_RGDAAC_M5RE_SHIFT 27
Kojto 90:cb3d968589d8 9139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
Kojto 90:cb3d968589d8 9140 #define MPU_RGDAAC_M6WE_SHIFT 28
Kojto 90:cb3d968589d8 9141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
Kojto 90:cb3d968589d8 9142 #define MPU_RGDAAC_M6RE_SHIFT 29
Kojto 90:cb3d968589d8 9143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
Kojto 90:cb3d968589d8 9144 #define MPU_RGDAAC_M7WE_SHIFT 30
Kojto 90:cb3d968589d8 9145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
Kojto 90:cb3d968589d8 9146 #define MPU_RGDAAC_M7RE_SHIFT 31
Kojto 90:cb3d968589d8 9147
Kojto 90:cb3d968589d8 9148 /*!
Kojto 90:cb3d968589d8 9149 * @}
Kojto 90:cb3d968589d8 9150 */ /* end of group MPU_Register_Masks */
Kojto 90:cb3d968589d8 9151
Kojto 90:cb3d968589d8 9152
Kojto 90:cb3d968589d8 9153 /* MPU - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 9154 /** Peripheral MPU base address */
Kojto 90:cb3d968589d8 9155 #define MPU_BASE (0x4000D000u)
Kojto 90:cb3d968589d8 9156 /** Peripheral MPU base pointer */
Kojto 90:cb3d968589d8 9157 #define MPU ((MPU_Type *)MPU_BASE)
Kojto 90:cb3d968589d8 9158 #define MPU_BASE_PTR (MPU)
Kojto 90:cb3d968589d8 9159 /** Array initializer of MPU peripheral base addresses */
Kojto 90:cb3d968589d8 9160 #define MPU_BASE_ADDRS { MPU_BASE }
Kojto 90:cb3d968589d8 9161 /** Array initializer of MPU peripheral base pointers */
Kojto 90:cb3d968589d8 9162 #define MPU_BASE_PTRS { MPU }
Kojto 90:cb3d968589d8 9163
Kojto 90:cb3d968589d8 9164 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9165 -- MPU - Register accessor macros
Kojto 90:cb3d968589d8 9166 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9167
Kojto 90:cb3d968589d8 9168 /*!
Kojto 90:cb3d968589d8 9169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
Kojto 90:cb3d968589d8 9170 * @{
Kojto 90:cb3d968589d8 9171 */
Kojto 90:cb3d968589d8 9172
Kojto 90:cb3d968589d8 9173
Kojto 90:cb3d968589d8 9174 /* MPU - Register instance definitions */
Kojto 90:cb3d968589d8 9175 /* MPU */
Kojto 90:cb3d968589d8 9176 #define MPU_CESR MPU_CESR_REG(MPU)
Kojto 90:cb3d968589d8 9177 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
Kojto 90:cb3d968589d8 9178 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
Kojto 90:cb3d968589d8 9179 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
Kojto 90:cb3d968589d8 9180 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
Kojto 90:cb3d968589d8 9181 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
Kojto 90:cb3d968589d8 9182 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
Kojto 90:cb3d968589d8 9183 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
Kojto 90:cb3d968589d8 9184 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
Kojto 90:cb3d968589d8 9185 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
Kojto 90:cb3d968589d8 9186 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
Kojto 90:cb3d968589d8 9187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
Kojto 90:cb3d968589d8 9188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
Kojto 90:cb3d968589d8 9189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
Kojto 90:cb3d968589d8 9190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
Kojto 90:cb3d968589d8 9191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
Kojto 90:cb3d968589d8 9192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
Kojto 90:cb3d968589d8 9193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
Kojto 90:cb3d968589d8 9194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
Kojto 90:cb3d968589d8 9195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
Kojto 90:cb3d968589d8 9196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
Kojto 90:cb3d968589d8 9197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
Kojto 90:cb3d968589d8 9198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
Kojto 90:cb3d968589d8 9199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
Kojto 90:cb3d968589d8 9200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
Kojto 90:cb3d968589d8 9201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
Kojto 90:cb3d968589d8 9202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
Kojto 90:cb3d968589d8 9203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
Kojto 90:cb3d968589d8 9204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
Kojto 90:cb3d968589d8 9205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
Kojto 90:cb3d968589d8 9206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
Kojto 90:cb3d968589d8 9207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
Kojto 90:cb3d968589d8 9208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
Kojto 90:cb3d968589d8 9209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
Kojto 90:cb3d968589d8 9210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
Kojto 90:cb3d968589d8 9211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
Kojto 90:cb3d968589d8 9212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
Kojto 90:cb3d968589d8 9213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
Kojto 90:cb3d968589d8 9214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
Kojto 90:cb3d968589d8 9215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
Kojto 90:cb3d968589d8 9216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
Kojto 90:cb3d968589d8 9217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
Kojto 90:cb3d968589d8 9218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
Kojto 90:cb3d968589d8 9219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
Kojto 90:cb3d968589d8 9220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
Kojto 90:cb3d968589d8 9221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
Kojto 90:cb3d968589d8 9222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
Kojto 90:cb3d968589d8 9223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
Kojto 90:cb3d968589d8 9224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
Kojto 90:cb3d968589d8 9225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
Kojto 90:cb3d968589d8 9226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
Kojto 90:cb3d968589d8 9227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
Kojto 90:cb3d968589d8 9228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
Kojto 90:cb3d968589d8 9229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
Kojto 90:cb3d968589d8 9230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
Kojto 90:cb3d968589d8 9231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
Kojto 90:cb3d968589d8 9232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
Kojto 90:cb3d968589d8 9233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
Kojto 90:cb3d968589d8 9234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
Kojto 90:cb3d968589d8 9235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
Kojto 90:cb3d968589d8 9236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
Kojto 90:cb3d968589d8 9237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
Kojto 90:cb3d968589d8 9238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
Kojto 90:cb3d968589d8 9239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
Kojto 90:cb3d968589d8 9240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
Kojto 90:cb3d968589d8 9241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
Kojto 90:cb3d968589d8 9242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
Kojto 90:cb3d968589d8 9243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
Kojto 90:cb3d968589d8 9244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
Kojto 90:cb3d968589d8 9245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
Kojto 90:cb3d968589d8 9246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
Kojto 90:cb3d968589d8 9247
Kojto 90:cb3d968589d8 9248 /* MPU - Register array accessors */
Kojto 90:cb3d968589d8 9249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
Kojto 90:cb3d968589d8 9250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
Kojto 90:cb3d968589d8 9251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
Kojto 90:cb3d968589d8 9252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
Kojto 90:cb3d968589d8 9253
Kojto 90:cb3d968589d8 9254 /*!
Kojto 90:cb3d968589d8 9255 * @}
Kojto 90:cb3d968589d8 9256 */ /* end of group MPU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9257
Kojto 90:cb3d968589d8 9258
Kojto 90:cb3d968589d8 9259 /*!
Kojto 90:cb3d968589d8 9260 * @}
Kojto 90:cb3d968589d8 9261 */ /* end of group MPU_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 9262
Kojto 90:cb3d968589d8 9263
Kojto 90:cb3d968589d8 9264 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9265 -- NV Peripheral Access Layer
Kojto 90:cb3d968589d8 9266 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9267
Kojto 90:cb3d968589d8 9268 /*!
Kojto 90:cb3d968589d8 9269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Kojto 90:cb3d968589d8 9270 * @{
Kojto 90:cb3d968589d8 9271 */
Kojto 90:cb3d968589d8 9272
Kojto 90:cb3d968589d8 9273 /** NV - Register Layout Typedef */
Kojto 90:cb3d968589d8 9274 typedef struct {
Kojto 90:cb3d968589d8 9275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
Kojto 90:cb3d968589d8 9276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
Kojto 90:cb3d968589d8 9277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
Kojto 90:cb3d968589d8 9278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
Kojto 90:cb3d968589d8 9279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
Kojto 90:cb3d968589d8 9280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
Kojto 90:cb3d968589d8 9281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
Kojto 90:cb3d968589d8 9282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
Kojto 90:cb3d968589d8 9283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
Kojto 90:cb3d968589d8 9284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
Kojto 90:cb3d968589d8 9285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
Kojto 90:cb3d968589d8 9286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
Kojto 90:cb3d968589d8 9287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
Kojto 90:cb3d968589d8 9288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
Kojto 90:cb3d968589d8 9289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
Kojto 90:cb3d968589d8 9290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
Kojto 90:cb3d968589d8 9291 } NV_Type, *NV_MemMapPtr;
Kojto 90:cb3d968589d8 9292
Kojto 90:cb3d968589d8 9293 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9294 -- NV - Register accessor macros
Kojto 90:cb3d968589d8 9295 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9296
Kojto 90:cb3d968589d8 9297 /*!
Kojto 90:cb3d968589d8 9298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Kojto 90:cb3d968589d8 9299 * @{
Kojto 90:cb3d968589d8 9300 */
Kojto 90:cb3d968589d8 9301
Kojto 90:cb3d968589d8 9302
Kojto 90:cb3d968589d8 9303 /* NV - Register accessors */
Kojto 90:cb3d968589d8 9304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
Kojto 90:cb3d968589d8 9305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
Kojto 90:cb3d968589d8 9306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
Kojto 90:cb3d968589d8 9307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
Kojto 90:cb3d968589d8 9308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
Kojto 90:cb3d968589d8 9309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
Kojto 90:cb3d968589d8 9310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
Kojto 90:cb3d968589d8 9311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
Kojto 90:cb3d968589d8 9312 #define NV_FPROT3_REG(base) ((base)->FPROT3)
Kojto 90:cb3d968589d8 9313 #define NV_FPROT2_REG(base) ((base)->FPROT2)
Kojto 90:cb3d968589d8 9314 #define NV_FPROT1_REG(base) ((base)->FPROT1)
Kojto 90:cb3d968589d8 9315 #define NV_FPROT0_REG(base) ((base)->FPROT0)
Kojto 90:cb3d968589d8 9316 #define NV_FSEC_REG(base) ((base)->FSEC)
Kojto 90:cb3d968589d8 9317 #define NV_FOPT_REG(base) ((base)->FOPT)
Kojto 90:cb3d968589d8 9318 #define NV_FEPROT_REG(base) ((base)->FEPROT)
Kojto 90:cb3d968589d8 9319 #define NV_FDPROT_REG(base) ((base)->FDPROT)
Kojto 90:cb3d968589d8 9320
Kojto 90:cb3d968589d8 9321 /*!
Kojto 90:cb3d968589d8 9322 * @}
Kojto 90:cb3d968589d8 9323 */ /* end of group NV_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9324
Kojto 90:cb3d968589d8 9325
Kojto 90:cb3d968589d8 9326 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9327 -- NV Register Masks
Kojto 90:cb3d968589d8 9328 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9329
Kojto 90:cb3d968589d8 9330 /*!
Kojto 90:cb3d968589d8 9331 * @addtogroup NV_Register_Masks NV Register Masks
Kojto 90:cb3d968589d8 9332 * @{
Kojto 90:cb3d968589d8 9333 */
Kojto 90:cb3d968589d8 9334
Kojto 90:cb3d968589d8 9335 /* BACKKEY3 Bit Fields */
Kojto 90:cb3d968589d8 9336 #define NV_BACKKEY3_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9337 #define NV_BACKKEY3_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
Kojto 90:cb3d968589d8 9339 /* BACKKEY2 Bit Fields */
Kojto 90:cb3d968589d8 9340 #define NV_BACKKEY2_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9341 #define NV_BACKKEY2_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
Kojto 90:cb3d968589d8 9343 /* BACKKEY1 Bit Fields */
Kojto 90:cb3d968589d8 9344 #define NV_BACKKEY1_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9345 #define NV_BACKKEY1_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
Kojto 90:cb3d968589d8 9347 /* BACKKEY0 Bit Fields */
Kojto 90:cb3d968589d8 9348 #define NV_BACKKEY0_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9349 #define NV_BACKKEY0_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
Kojto 90:cb3d968589d8 9351 /* BACKKEY7 Bit Fields */
Kojto 90:cb3d968589d8 9352 #define NV_BACKKEY7_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9353 #define NV_BACKKEY7_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
Kojto 90:cb3d968589d8 9355 /* BACKKEY6 Bit Fields */
Kojto 90:cb3d968589d8 9356 #define NV_BACKKEY6_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9357 #define NV_BACKKEY6_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
Kojto 90:cb3d968589d8 9359 /* BACKKEY5 Bit Fields */
Kojto 90:cb3d968589d8 9360 #define NV_BACKKEY5_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9361 #define NV_BACKKEY5_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
Kojto 90:cb3d968589d8 9363 /* BACKKEY4 Bit Fields */
Kojto 90:cb3d968589d8 9364 #define NV_BACKKEY4_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 9365 #define NV_BACKKEY4_KEY_SHIFT 0
Kojto 90:cb3d968589d8 9366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
Kojto 90:cb3d968589d8 9367 /* FPROT3 Bit Fields */
Kojto 90:cb3d968589d8 9368 #define NV_FPROT3_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9369 #define NV_FPROT3_PROT_SHIFT 0
Kojto 90:cb3d968589d8 9370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
Kojto 90:cb3d968589d8 9371 /* FPROT2 Bit Fields */
Kojto 90:cb3d968589d8 9372 #define NV_FPROT2_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9373 #define NV_FPROT2_PROT_SHIFT 0
Kojto 90:cb3d968589d8 9374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
Kojto 90:cb3d968589d8 9375 /* FPROT1 Bit Fields */
Kojto 90:cb3d968589d8 9376 #define NV_FPROT1_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9377 #define NV_FPROT1_PROT_SHIFT 0
Kojto 90:cb3d968589d8 9378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
Kojto 90:cb3d968589d8 9379 /* FPROT0 Bit Fields */
Kojto 90:cb3d968589d8 9380 #define NV_FPROT0_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9381 #define NV_FPROT0_PROT_SHIFT 0
Kojto 90:cb3d968589d8 9382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
Kojto 90:cb3d968589d8 9383 /* FSEC Bit Fields */
Kojto 90:cb3d968589d8 9384 #define NV_FSEC_SEC_MASK 0x3u
Kojto 90:cb3d968589d8 9385 #define NV_FSEC_SEC_SHIFT 0
Kojto 90:cb3d968589d8 9386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
Kojto 90:cb3d968589d8 9387 #define NV_FSEC_FSLACC_MASK 0xCu
Kojto 90:cb3d968589d8 9388 #define NV_FSEC_FSLACC_SHIFT 2
Kojto 90:cb3d968589d8 9389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
Kojto 90:cb3d968589d8 9390 #define NV_FSEC_MEEN_MASK 0x30u
Kojto 90:cb3d968589d8 9391 #define NV_FSEC_MEEN_SHIFT 4
Kojto 90:cb3d968589d8 9392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
Kojto 90:cb3d968589d8 9393 #define NV_FSEC_KEYEN_MASK 0xC0u
Kojto 90:cb3d968589d8 9394 #define NV_FSEC_KEYEN_SHIFT 6
Kojto 90:cb3d968589d8 9395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
Kojto 90:cb3d968589d8 9396 /* FOPT Bit Fields */
Kojto 90:cb3d968589d8 9397 #define NV_FOPT_LPBOOT_MASK 0x1u
Kojto 90:cb3d968589d8 9398 #define NV_FOPT_LPBOOT_SHIFT 0
Kojto 90:cb3d968589d8 9399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
Kojto 90:cb3d968589d8 9400 #define NV_FOPT_EZPORT_DIS_SHIFT 1
Kojto 90:cb3d968589d8 9401 /* FEPROT Bit Fields */
Kojto 90:cb3d968589d8 9402 #define NV_FEPROT_EPROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9403 #define NV_FEPROT_EPROT_SHIFT 0
Kojto 90:cb3d968589d8 9404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
Kojto 90:cb3d968589d8 9405 /* FDPROT Bit Fields */
Kojto 90:cb3d968589d8 9406 #define NV_FDPROT_DPROT_MASK 0xFFu
Kojto 90:cb3d968589d8 9407 #define NV_FDPROT_DPROT_SHIFT 0
Kojto 90:cb3d968589d8 9408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
Kojto 90:cb3d968589d8 9409
Kojto 90:cb3d968589d8 9410 /*!
Kojto 90:cb3d968589d8 9411 * @}
Kojto 90:cb3d968589d8 9412 */ /* end of group NV_Register_Masks */
Kojto 90:cb3d968589d8 9413
Kojto 90:cb3d968589d8 9414
Kojto 90:cb3d968589d8 9415 /* NV - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 9416 /** Peripheral FTFE_FlashConfig base address */
Kojto 90:cb3d968589d8 9417 #define FTFE_FlashConfig_BASE (0x400u)
Kojto 90:cb3d968589d8 9418 /** Peripheral FTFE_FlashConfig base pointer */
Kojto 90:cb3d968589d8 9419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
Kojto 90:cb3d968589d8 9420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9421 /** Array initializer of NV peripheral base addresses */
Kojto 90:cb3d968589d8 9422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
Kojto 90:cb3d968589d8 9423 /** Array initializer of NV peripheral base pointers */
Kojto 90:cb3d968589d8 9424 #define NV_BASE_PTRS { FTFE_FlashConfig }
Kojto 90:cb3d968589d8 9425
Kojto 90:cb3d968589d8 9426 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9427 -- NV - Register accessor macros
Kojto 90:cb3d968589d8 9428 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9429
Kojto 90:cb3d968589d8 9430 /*!
Kojto 90:cb3d968589d8 9431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Kojto 90:cb3d968589d8 9432 * @{
Kojto 90:cb3d968589d8 9433 */
Kojto 90:cb3d968589d8 9434
Kojto 90:cb3d968589d8 9435
Kojto 90:cb3d968589d8 9436 /* NV - Register instance definitions */
Kojto 90:cb3d968589d8 9437 /* FTFE_FlashConfig */
Kojto 90:cb3d968589d8 9438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
Kojto 90:cb3d968589d8 9454
Kojto 90:cb3d968589d8 9455 /*!
Kojto 90:cb3d968589d8 9456 * @}
Kojto 90:cb3d968589d8 9457 */ /* end of group NV_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9458
Kojto 90:cb3d968589d8 9459
Kojto 90:cb3d968589d8 9460 /*!
Kojto 90:cb3d968589d8 9461 * @}
Kojto 90:cb3d968589d8 9462 */ /* end of group NV_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 9463
Kojto 90:cb3d968589d8 9464
Kojto 90:cb3d968589d8 9465 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9466 -- OSC Peripheral Access Layer
Kojto 90:cb3d968589d8 9467 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9468
Kojto 90:cb3d968589d8 9469 /*!
Kojto 90:cb3d968589d8 9470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Kojto 90:cb3d968589d8 9471 * @{
Kojto 90:cb3d968589d8 9472 */
Kojto 90:cb3d968589d8 9473
Kojto 90:cb3d968589d8 9474 /** OSC - Register Layout Typedef */
Kojto 90:cb3d968589d8 9475 typedef struct {
Kojto 90:cb3d968589d8 9476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 9477 } OSC_Type, *OSC_MemMapPtr;
Kojto 90:cb3d968589d8 9478
Kojto 90:cb3d968589d8 9479 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9480 -- OSC - Register accessor macros
Kojto 90:cb3d968589d8 9481 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9482
Kojto 90:cb3d968589d8 9483 /*!
Kojto 90:cb3d968589d8 9484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Kojto 90:cb3d968589d8 9485 * @{
Kojto 90:cb3d968589d8 9486 */
Kojto 90:cb3d968589d8 9487
Kojto 90:cb3d968589d8 9488
Kojto 90:cb3d968589d8 9489 /* OSC - Register accessors */
Kojto 90:cb3d968589d8 9490 #define OSC_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 9491
Kojto 90:cb3d968589d8 9492 /*!
Kojto 90:cb3d968589d8 9493 * @}
Kojto 90:cb3d968589d8 9494 */ /* end of group OSC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9495
Kojto 90:cb3d968589d8 9496
Kojto 90:cb3d968589d8 9497 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9498 -- OSC Register Masks
Kojto 90:cb3d968589d8 9499 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9500
Kojto 90:cb3d968589d8 9501 /*!
Kojto 90:cb3d968589d8 9502 * @addtogroup OSC_Register_Masks OSC Register Masks
Kojto 90:cb3d968589d8 9503 * @{
Kojto 90:cb3d968589d8 9504 */
Kojto 90:cb3d968589d8 9505
Kojto 90:cb3d968589d8 9506 /* CR Bit Fields */
Kojto 90:cb3d968589d8 9507 #define OSC_CR_SC16P_MASK 0x1u
Kojto 90:cb3d968589d8 9508 #define OSC_CR_SC16P_SHIFT 0
Kojto 90:cb3d968589d8 9509 #define OSC_CR_SC8P_MASK 0x2u
Kojto 90:cb3d968589d8 9510 #define OSC_CR_SC8P_SHIFT 1
Kojto 90:cb3d968589d8 9511 #define OSC_CR_SC4P_MASK 0x4u
Kojto 90:cb3d968589d8 9512 #define OSC_CR_SC4P_SHIFT 2
Kojto 90:cb3d968589d8 9513 #define OSC_CR_SC2P_MASK 0x8u
Kojto 90:cb3d968589d8 9514 #define OSC_CR_SC2P_SHIFT 3
Kojto 90:cb3d968589d8 9515 #define OSC_CR_EREFSTEN_MASK 0x20u
Kojto 90:cb3d968589d8 9516 #define OSC_CR_EREFSTEN_SHIFT 5
Kojto 90:cb3d968589d8 9517 #define OSC_CR_ERCLKEN_MASK 0x80u
Kojto 90:cb3d968589d8 9518 #define OSC_CR_ERCLKEN_SHIFT 7
Kojto 90:cb3d968589d8 9519
Kojto 90:cb3d968589d8 9520 /*!
Kojto 90:cb3d968589d8 9521 * @}
Kojto 90:cb3d968589d8 9522 */ /* end of group OSC_Register_Masks */
Kojto 90:cb3d968589d8 9523
Kojto 90:cb3d968589d8 9524
Kojto 90:cb3d968589d8 9525 /* OSC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 9526 /** Peripheral OSC base address */
Kojto 90:cb3d968589d8 9527 #define OSC_BASE (0x40065000u)
Kojto 90:cb3d968589d8 9528 /** Peripheral OSC base pointer */
Kojto 90:cb3d968589d8 9529 #define OSC ((OSC_Type *)OSC_BASE)
Kojto 90:cb3d968589d8 9530 #define OSC_BASE_PTR (OSC)
Kojto 90:cb3d968589d8 9531 /** Array initializer of OSC peripheral base addresses */
Kojto 90:cb3d968589d8 9532 #define OSC_BASE_ADDRS { OSC_BASE }
Kojto 90:cb3d968589d8 9533 /** Array initializer of OSC peripheral base pointers */
Kojto 90:cb3d968589d8 9534 #define OSC_BASE_PTRS { OSC }
Kojto 90:cb3d968589d8 9535
Kojto 90:cb3d968589d8 9536 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9537 -- OSC - Register accessor macros
Kojto 90:cb3d968589d8 9538 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9539
Kojto 90:cb3d968589d8 9540 /*!
Kojto 90:cb3d968589d8 9541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Kojto 90:cb3d968589d8 9542 * @{
Kojto 90:cb3d968589d8 9543 */
Kojto 90:cb3d968589d8 9544
Kojto 90:cb3d968589d8 9545
Kojto 90:cb3d968589d8 9546 /* OSC - Register instance definitions */
Kojto 90:cb3d968589d8 9547 /* OSC */
Kojto 90:cb3d968589d8 9548 #define OSC_CR OSC_CR_REG(OSC)
Kojto 90:cb3d968589d8 9549
Kojto 90:cb3d968589d8 9550 /*!
Kojto 90:cb3d968589d8 9551 * @}
Kojto 90:cb3d968589d8 9552 */ /* end of group OSC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9553
Kojto 90:cb3d968589d8 9554
Kojto 90:cb3d968589d8 9555 /*!
Kojto 90:cb3d968589d8 9556 * @}
Kojto 90:cb3d968589d8 9557 */ /* end of group OSC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 9558
Kojto 90:cb3d968589d8 9559
Kojto 90:cb3d968589d8 9560 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9561 -- PDB Peripheral Access Layer
Kojto 90:cb3d968589d8 9562 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9563
Kojto 90:cb3d968589d8 9564 /*!
Kojto 90:cb3d968589d8 9565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
Kojto 90:cb3d968589d8 9566 * @{
Kojto 90:cb3d968589d8 9567 */
Kojto 90:cb3d968589d8 9568
Kojto 90:cb3d968589d8 9569 /** PDB - Register Layout Typedef */
Kojto 90:cb3d968589d8 9570 typedef struct {
Kojto 90:cb3d968589d8 9571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
Kojto 90:cb3d968589d8 9572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
Kojto 90:cb3d968589d8 9573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
Kojto 90:cb3d968589d8 9574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
Kojto 90:cb3d968589d8 9575 struct { /* offset: 0x10, array step: 0x28 */
Kojto 90:cb3d968589d8 9576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
Kojto 90:cb3d968589d8 9577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
Kojto 90:cb3d968589d8 9578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
Kojto 90:cb3d968589d8 9579 uint8_t RESERVED_0[24];
Kojto 90:cb3d968589d8 9580 } CH[2];
Kojto 90:cb3d968589d8 9581 uint8_t RESERVED_0[240];
Kojto 90:cb3d968589d8 9582 struct { /* offset: 0x150, array step: 0x8 */
Kojto 90:cb3d968589d8 9583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
Kojto 90:cb3d968589d8 9584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
Kojto 90:cb3d968589d8 9585 } DAC[2];
Kojto 90:cb3d968589d8 9586 uint8_t RESERVED_1[48];
Kojto 90:cb3d968589d8 9587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
Kojto 90:cb3d968589d8 9588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
Kojto 90:cb3d968589d8 9589 } PDB_Type, *PDB_MemMapPtr;
Kojto 90:cb3d968589d8 9590
Kojto 90:cb3d968589d8 9591 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9592 -- PDB - Register accessor macros
Kojto 90:cb3d968589d8 9593 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9594
Kojto 90:cb3d968589d8 9595 /*!
Kojto 90:cb3d968589d8 9596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
Kojto 90:cb3d968589d8 9597 * @{
Kojto 90:cb3d968589d8 9598 */
Kojto 90:cb3d968589d8 9599
Kojto 90:cb3d968589d8 9600
Kojto 90:cb3d968589d8 9601 /* PDB - Register accessors */
Kojto 90:cb3d968589d8 9602 #define PDB_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 9603 #define PDB_MOD_REG(base) ((base)->MOD)
Kojto 90:cb3d968589d8 9604 #define PDB_CNT_REG(base) ((base)->CNT)
Kojto 90:cb3d968589d8 9605 #define PDB_IDLY_REG(base) ((base)->IDLY)
Kojto 90:cb3d968589d8 9606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
Kojto 90:cb3d968589d8 9607 #define PDB_S_REG(base,index) ((base)->CH[index].S)
Kojto 90:cb3d968589d8 9608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
Kojto 90:cb3d968589d8 9609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
Kojto 90:cb3d968589d8 9610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
Kojto 90:cb3d968589d8 9611 #define PDB_POEN_REG(base) ((base)->POEN)
Kojto 90:cb3d968589d8 9612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
Kojto 90:cb3d968589d8 9613
Kojto 90:cb3d968589d8 9614 /*!
Kojto 90:cb3d968589d8 9615 * @}
Kojto 90:cb3d968589d8 9616 */ /* end of group PDB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9617
Kojto 90:cb3d968589d8 9618
Kojto 90:cb3d968589d8 9619 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9620 -- PDB Register Masks
Kojto 90:cb3d968589d8 9621 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9622
Kojto 90:cb3d968589d8 9623 /*!
Kojto 90:cb3d968589d8 9624 * @addtogroup PDB_Register_Masks PDB Register Masks
Kojto 90:cb3d968589d8 9625 * @{
Kojto 90:cb3d968589d8 9626 */
Kojto 90:cb3d968589d8 9627
Kojto 90:cb3d968589d8 9628 /* SC Bit Fields */
Kojto 90:cb3d968589d8 9629 #define PDB_SC_LDOK_MASK 0x1u
Kojto 90:cb3d968589d8 9630 #define PDB_SC_LDOK_SHIFT 0
Kojto 90:cb3d968589d8 9631 #define PDB_SC_CONT_MASK 0x2u
Kojto 90:cb3d968589d8 9632 #define PDB_SC_CONT_SHIFT 1
Kojto 90:cb3d968589d8 9633 #define PDB_SC_MULT_MASK 0xCu
Kojto 90:cb3d968589d8 9634 #define PDB_SC_MULT_SHIFT 2
Kojto 90:cb3d968589d8 9635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
Kojto 90:cb3d968589d8 9636 #define PDB_SC_PDBIE_MASK 0x20u
Kojto 90:cb3d968589d8 9637 #define PDB_SC_PDBIE_SHIFT 5
Kojto 90:cb3d968589d8 9638 #define PDB_SC_PDBIF_MASK 0x40u
Kojto 90:cb3d968589d8 9639 #define PDB_SC_PDBIF_SHIFT 6
Kojto 90:cb3d968589d8 9640 #define PDB_SC_PDBEN_MASK 0x80u
Kojto 90:cb3d968589d8 9641 #define PDB_SC_PDBEN_SHIFT 7
Kojto 90:cb3d968589d8 9642 #define PDB_SC_TRGSEL_MASK 0xF00u
Kojto 90:cb3d968589d8 9643 #define PDB_SC_TRGSEL_SHIFT 8
Kojto 90:cb3d968589d8 9644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
Kojto 90:cb3d968589d8 9645 #define PDB_SC_PRESCALER_MASK 0x7000u
Kojto 90:cb3d968589d8 9646 #define PDB_SC_PRESCALER_SHIFT 12
Kojto 90:cb3d968589d8 9647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
Kojto 90:cb3d968589d8 9648 #define PDB_SC_DMAEN_MASK 0x8000u
Kojto 90:cb3d968589d8 9649 #define PDB_SC_DMAEN_SHIFT 15
Kojto 90:cb3d968589d8 9650 #define PDB_SC_SWTRIG_MASK 0x10000u
Kojto 90:cb3d968589d8 9651 #define PDB_SC_SWTRIG_SHIFT 16
Kojto 90:cb3d968589d8 9652 #define PDB_SC_PDBEIE_MASK 0x20000u
Kojto 90:cb3d968589d8 9653 #define PDB_SC_PDBEIE_SHIFT 17
Kojto 90:cb3d968589d8 9654 #define PDB_SC_LDMOD_MASK 0xC0000u
Kojto 90:cb3d968589d8 9655 #define PDB_SC_LDMOD_SHIFT 18
Kojto 90:cb3d968589d8 9656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
Kojto 90:cb3d968589d8 9657 /* MOD Bit Fields */
Kojto 90:cb3d968589d8 9658 #define PDB_MOD_MOD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9659 #define PDB_MOD_MOD_SHIFT 0
Kojto 90:cb3d968589d8 9660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
Kojto 90:cb3d968589d8 9661 /* CNT Bit Fields */
Kojto 90:cb3d968589d8 9662 #define PDB_CNT_CNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9663 #define PDB_CNT_CNT_SHIFT 0
Kojto 90:cb3d968589d8 9664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
Kojto 90:cb3d968589d8 9665 /* IDLY Bit Fields */
Kojto 90:cb3d968589d8 9666 #define PDB_IDLY_IDLY_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9667 #define PDB_IDLY_IDLY_SHIFT 0
Kojto 90:cb3d968589d8 9668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
Kojto 90:cb3d968589d8 9669 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 9670 #define PDB_C1_EN_MASK 0xFFu
Kojto 90:cb3d968589d8 9671 #define PDB_C1_EN_SHIFT 0
Kojto 90:cb3d968589d8 9672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
Kojto 90:cb3d968589d8 9673 #define PDB_C1_TOS_MASK 0xFF00u
Kojto 90:cb3d968589d8 9674 #define PDB_C1_TOS_SHIFT 8
Kojto 90:cb3d968589d8 9675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
Kojto 90:cb3d968589d8 9676 #define PDB_C1_BB_MASK 0xFF0000u
Kojto 90:cb3d968589d8 9677 #define PDB_C1_BB_SHIFT 16
Kojto 90:cb3d968589d8 9678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
Kojto 90:cb3d968589d8 9679 /* S Bit Fields */
Kojto 90:cb3d968589d8 9680 #define PDB_S_ERR_MASK 0xFFu
Kojto 90:cb3d968589d8 9681 #define PDB_S_ERR_SHIFT 0
Kojto 90:cb3d968589d8 9682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
Kojto 90:cb3d968589d8 9683 #define PDB_S_CF_MASK 0xFF0000u
Kojto 90:cb3d968589d8 9684 #define PDB_S_CF_SHIFT 16
Kojto 90:cb3d968589d8 9685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
Kojto 90:cb3d968589d8 9686 /* DLY Bit Fields */
Kojto 90:cb3d968589d8 9687 #define PDB_DLY_DLY_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9688 #define PDB_DLY_DLY_SHIFT 0
Kojto 90:cb3d968589d8 9689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
Kojto 90:cb3d968589d8 9690 /* INTC Bit Fields */
Kojto 90:cb3d968589d8 9691 #define PDB_INTC_TOE_MASK 0x1u
Kojto 90:cb3d968589d8 9692 #define PDB_INTC_TOE_SHIFT 0
Kojto 90:cb3d968589d8 9693 #define PDB_INTC_EXT_MASK 0x2u
Kojto 90:cb3d968589d8 9694 #define PDB_INTC_EXT_SHIFT 1
Kojto 90:cb3d968589d8 9695 /* INT Bit Fields */
Kojto 90:cb3d968589d8 9696 #define PDB_INT_INT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9697 #define PDB_INT_INT_SHIFT 0
Kojto 90:cb3d968589d8 9698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
Kojto 90:cb3d968589d8 9699 /* POEN Bit Fields */
Kojto 90:cb3d968589d8 9700 #define PDB_POEN_POEN_MASK 0xFFu
Kojto 90:cb3d968589d8 9701 #define PDB_POEN_POEN_SHIFT 0
Kojto 90:cb3d968589d8 9702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
Kojto 90:cb3d968589d8 9703 /* PODLY Bit Fields */
Kojto 90:cb3d968589d8 9704 #define PDB_PODLY_DLY2_MASK 0xFFFFu
Kojto 90:cb3d968589d8 9705 #define PDB_PODLY_DLY2_SHIFT 0
Kojto 90:cb3d968589d8 9706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
Kojto 90:cb3d968589d8 9707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 9708 #define PDB_PODLY_DLY1_SHIFT 16
Kojto 90:cb3d968589d8 9709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
Kojto 90:cb3d968589d8 9710
Kojto 90:cb3d968589d8 9711 /*!
Kojto 90:cb3d968589d8 9712 * @}
Kojto 90:cb3d968589d8 9713 */ /* end of group PDB_Register_Masks */
Kojto 90:cb3d968589d8 9714
Kojto 90:cb3d968589d8 9715
Kojto 90:cb3d968589d8 9716 /* PDB - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 9717 /** Peripheral PDB0 base address */
Kojto 90:cb3d968589d8 9718 #define PDB0_BASE (0x40036000u)
Kojto 90:cb3d968589d8 9719 /** Peripheral PDB0 base pointer */
Kojto 90:cb3d968589d8 9720 #define PDB0 ((PDB_Type *)PDB0_BASE)
Kojto 90:cb3d968589d8 9721 #define PDB0_BASE_PTR (PDB0)
Kojto 90:cb3d968589d8 9722 /** Array initializer of PDB peripheral base addresses */
Kojto 90:cb3d968589d8 9723 #define PDB_BASE_ADDRS { PDB0_BASE }
Kojto 90:cb3d968589d8 9724 /** Array initializer of PDB peripheral base pointers */
Kojto 90:cb3d968589d8 9725 #define PDB_BASE_PTRS { PDB0 }
Kojto 90:cb3d968589d8 9726 /** Interrupt vectors for the PDB peripheral type */
Kojto 90:cb3d968589d8 9727 #define PDB_IRQS { PDB0_IRQn }
Kojto 90:cb3d968589d8 9728
Kojto 90:cb3d968589d8 9729 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9730 -- PDB - Register accessor macros
Kojto 90:cb3d968589d8 9731 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9732
Kojto 90:cb3d968589d8 9733 /*!
Kojto 90:cb3d968589d8 9734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
Kojto 90:cb3d968589d8 9735 * @{
Kojto 90:cb3d968589d8 9736 */
Kojto 90:cb3d968589d8 9737
Kojto 90:cb3d968589d8 9738
Kojto 90:cb3d968589d8 9739 /* PDB - Register instance definitions */
Kojto 90:cb3d968589d8 9740 /* PDB0 */
Kojto 90:cb3d968589d8 9741 #define PDB0_SC PDB_SC_REG(PDB0)
Kojto 90:cb3d968589d8 9742 #define PDB0_MOD PDB_MOD_REG(PDB0)
Kojto 90:cb3d968589d8 9743 #define PDB0_CNT PDB_CNT_REG(PDB0)
Kojto 90:cb3d968589d8 9744 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
Kojto 90:cb3d968589d8 9745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
Kojto 90:cb3d968589d8 9746 #define PDB0_CH0S PDB_S_REG(PDB0,0)
Kojto 90:cb3d968589d8 9747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
Kojto 90:cb3d968589d8 9748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
Kojto 90:cb3d968589d8 9749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
Kojto 90:cb3d968589d8 9750 #define PDB0_CH1S PDB_S_REG(PDB0,1)
Kojto 90:cb3d968589d8 9751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
Kojto 90:cb3d968589d8 9752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
Kojto 90:cb3d968589d8 9753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
Kojto 90:cb3d968589d8 9754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
Kojto 90:cb3d968589d8 9755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
Kojto 90:cb3d968589d8 9756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
Kojto 90:cb3d968589d8 9757 #define PDB0_POEN PDB_POEN_REG(PDB0)
Kojto 90:cb3d968589d8 9758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
Kojto 90:cb3d968589d8 9759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
Kojto 90:cb3d968589d8 9760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
Kojto 90:cb3d968589d8 9761
Kojto 90:cb3d968589d8 9762 /* PDB - Register array accessors */
Kojto 90:cb3d968589d8 9763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
Kojto 90:cb3d968589d8 9764 #define PDB0_S(index) PDB_S_REG(PDB0,index)
Kojto 90:cb3d968589d8 9765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
Kojto 90:cb3d968589d8 9766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
Kojto 90:cb3d968589d8 9767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
Kojto 90:cb3d968589d8 9768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
Kojto 90:cb3d968589d8 9769
Kojto 90:cb3d968589d8 9770 /*!
Kojto 90:cb3d968589d8 9771 * @}
Kojto 90:cb3d968589d8 9772 */ /* end of group PDB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9773
Kojto 90:cb3d968589d8 9774
Kojto 90:cb3d968589d8 9775 /*!
Kojto 90:cb3d968589d8 9776 * @}
Kojto 90:cb3d968589d8 9777 */ /* end of group PDB_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 9778
Kojto 90:cb3d968589d8 9779
Kojto 90:cb3d968589d8 9780 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9781 -- PIT Peripheral Access Layer
Kojto 90:cb3d968589d8 9782 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9783
Kojto 90:cb3d968589d8 9784 /*!
Kojto 90:cb3d968589d8 9785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Kojto 90:cb3d968589d8 9786 * @{
Kojto 90:cb3d968589d8 9787 */
Kojto 90:cb3d968589d8 9788
Kojto 90:cb3d968589d8 9789 /** PIT - Register Layout Typedef */
Kojto 90:cb3d968589d8 9790 typedef struct {
Kojto 90:cb3d968589d8 9791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 9792 uint8_t RESERVED_0[252];
Kojto 90:cb3d968589d8 9793 struct { /* offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 9794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 9795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
Kojto 90:cb3d968589d8 9796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
Kojto 90:cb3d968589d8 9797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
Kojto 90:cb3d968589d8 9798 } CHANNEL[4];
Kojto 90:cb3d968589d8 9799 } PIT_Type, *PIT_MemMapPtr;
Kojto 90:cb3d968589d8 9800
Kojto 90:cb3d968589d8 9801 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9802 -- PIT - Register accessor macros
Kojto 90:cb3d968589d8 9803 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9804
Kojto 90:cb3d968589d8 9805 /*!
Kojto 90:cb3d968589d8 9806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Kojto 90:cb3d968589d8 9807 * @{
Kojto 90:cb3d968589d8 9808 */
Kojto 90:cb3d968589d8 9809
Kojto 90:cb3d968589d8 9810
Kojto 90:cb3d968589d8 9811 /* PIT - Register accessors */
Kojto 90:cb3d968589d8 9812 #define PIT_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 9813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
Kojto 90:cb3d968589d8 9814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
Kojto 90:cb3d968589d8 9815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
Kojto 90:cb3d968589d8 9816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
Kojto 90:cb3d968589d8 9817
Kojto 90:cb3d968589d8 9818 /*!
Kojto 90:cb3d968589d8 9819 * @}
Kojto 90:cb3d968589d8 9820 */ /* end of group PIT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9821
Kojto 90:cb3d968589d8 9822
Kojto 90:cb3d968589d8 9823 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9824 -- PIT Register Masks
Kojto 90:cb3d968589d8 9825 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9826
Kojto 90:cb3d968589d8 9827 /*!
Kojto 90:cb3d968589d8 9828 * @addtogroup PIT_Register_Masks PIT Register Masks
Kojto 90:cb3d968589d8 9829 * @{
Kojto 90:cb3d968589d8 9830 */
Kojto 90:cb3d968589d8 9831
Kojto 90:cb3d968589d8 9832 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 9833 #define PIT_MCR_FRZ_MASK 0x1u
Kojto 90:cb3d968589d8 9834 #define PIT_MCR_FRZ_SHIFT 0
Kojto 90:cb3d968589d8 9835 #define PIT_MCR_MDIS_MASK 0x2u
Kojto 90:cb3d968589d8 9836 #define PIT_MCR_MDIS_SHIFT 1
Kojto 90:cb3d968589d8 9837 /* LDVAL Bit Fields */
Kojto 90:cb3d968589d8 9838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 9839 #define PIT_LDVAL_TSV_SHIFT 0
Kojto 90:cb3d968589d8 9840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
Kojto 90:cb3d968589d8 9841 /* CVAL Bit Fields */
Kojto 90:cb3d968589d8 9842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 9843 #define PIT_CVAL_TVL_SHIFT 0
Kojto 90:cb3d968589d8 9844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
Kojto 90:cb3d968589d8 9845 /* TCTRL Bit Fields */
Kojto 90:cb3d968589d8 9846 #define PIT_TCTRL_TEN_MASK 0x1u
Kojto 90:cb3d968589d8 9847 #define PIT_TCTRL_TEN_SHIFT 0
Kojto 90:cb3d968589d8 9848 #define PIT_TCTRL_TIE_MASK 0x2u
Kojto 90:cb3d968589d8 9849 #define PIT_TCTRL_TIE_SHIFT 1
Kojto 90:cb3d968589d8 9850 #define PIT_TCTRL_CHN_MASK 0x4u
Kojto 90:cb3d968589d8 9851 #define PIT_TCTRL_CHN_SHIFT 2
Kojto 90:cb3d968589d8 9852 /* TFLG Bit Fields */
Kojto 90:cb3d968589d8 9853 #define PIT_TFLG_TIF_MASK 0x1u
Kojto 90:cb3d968589d8 9854 #define PIT_TFLG_TIF_SHIFT 0
Kojto 90:cb3d968589d8 9855
Kojto 90:cb3d968589d8 9856 /*!
Kojto 90:cb3d968589d8 9857 * @}
Kojto 90:cb3d968589d8 9858 */ /* end of group PIT_Register_Masks */
Kojto 90:cb3d968589d8 9859
Kojto 90:cb3d968589d8 9860
Kojto 90:cb3d968589d8 9861 /* PIT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 9862 /** Peripheral PIT base address */
Kojto 90:cb3d968589d8 9863 #define PIT_BASE (0x40037000u)
Kojto 90:cb3d968589d8 9864 /** Peripheral PIT base pointer */
Kojto 90:cb3d968589d8 9865 #define PIT ((PIT_Type *)PIT_BASE)
Kojto 90:cb3d968589d8 9866 #define PIT_BASE_PTR (PIT)
Kojto 90:cb3d968589d8 9867 /** Array initializer of PIT peripheral base addresses */
Kojto 90:cb3d968589d8 9868 #define PIT_BASE_ADDRS { PIT_BASE }
Kojto 90:cb3d968589d8 9869 /** Array initializer of PIT peripheral base pointers */
Kojto 90:cb3d968589d8 9870 #define PIT_BASE_PTRS { PIT }
Kojto 90:cb3d968589d8 9871 /** Interrupt vectors for the PIT peripheral type */
Kojto 90:cb3d968589d8 9872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
Kojto 90:cb3d968589d8 9873
Kojto 90:cb3d968589d8 9874 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9875 -- PIT - Register accessor macros
Kojto 90:cb3d968589d8 9876 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9877
Kojto 90:cb3d968589d8 9878 /*!
Kojto 90:cb3d968589d8 9879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Kojto 90:cb3d968589d8 9880 * @{
Kojto 90:cb3d968589d8 9881 */
Kojto 90:cb3d968589d8 9882
Kojto 90:cb3d968589d8 9883
Kojto 90:cb3d968589d8 9884 /* PIT - Register instance definitions */
Kojto 90:cb3d968589d8 9885 /* PIT */
Kojto 90:cb3d968589d8 9886 #define PIT_MCR PIT_MCR_REG(PIT)
Kojto 90:cb3d968589d8 9887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
Kojto 90:cb3d968589d8 9888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
Kojto 90:cb3d968589d8 9889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
Kojto 90:cb3d968589d8 9890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
Kojto 90:cb3d968589d8 9891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
Kojto 90:cb3d968589d8 9892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
Kojto 90:cb3d968589d8 9893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
Kojto 90:cb3d968589d8 9894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
Kojto 90:cb3d968589d8 9895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
Kojto 90:cb3d968589d8 9896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
Kojto 90:cb3d968589d8 9897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
Kojto 90:cb3d968589d8 9898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
Kojto 90:cb3d968589d8 9899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
Kojto 90:cb3d968589d8 9900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
Kojto 90:cb3d968589d8 9901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
Kojto 90:cb3d968589d8 9902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
Kojto 90:cb3d968589d8 9903
Kojto 90:cb3d968589d8 9904 /* PIT - Register array accessors */
Kojto 90:cb3d968589d8 9905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
Kojto 90:cb3d968589d8 9906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
Kojto 90:cb3d968589d8 9907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
Kojto 90:cb3d968589d8 9908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
Kojto 90:cb3d968589d8 9909
Kojto 90:cb3d968589d8 9910 /*!
Kojto 90:cb3d968589d8 9911 * @}
Kojto 90:cb3d968589d8 9912 */ /* end of group PIT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9913
Kojto 90:cb3d968589d8 9914
Kojto 90:cb3d968589d8 9915 /*!
Kojto 90:cb3d968589d8 9916 * @}
Kojto 90:cb3d968589d8 9917 */ /* end of group PIT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 9918
Kojto 90:cb3d968589d8 9919
Kojto 90:cb3d968589d8 9920 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9921 -- PMC Peripheral Access Layer
Kojto 90:cb3d968589d8 9922 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9923
Kojto 90:cb3d968589d8 9924 /*!
Kojto 90:cb3d968589d8 9925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Kojto 90:cb3d968589d8 9926 * @{
Kojto 90:cb3d968589d8 9927 */
Kojto 90:cb3d968589d8 9928
Kojto 90:cb3d968589d8 9929 /** PMC - Register Layout Typedef */
Kojto 90:cb3d968589d8 9930 typedef struct {
Kojto 90:cb3d968589d8 9931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
Kojto 90:cb3d968589d8 9932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
Kojto 90:cb3d968589d8 9933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
Kojto 90:cb3d968589d8 9934 } PMC_Type, *PMC_MemMapPtr;
Kojto 90:cb3d968589d8 9935
Kojto 90:cb3d968589d8 9936 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9937 -- PMC - Register accessor macros
Kojto 90:cb3d968589d8 9938 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9939
Kojto 90:cb3d968589d8 9940 /*!
Kojto 90:cb3d968589d8 9941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Kojto 90:cb3d968589d8 9942 * @{
Kojto 90:cb3d968589d8 9943 */
Kojto 90:cb3d968589d8 9944
Kojto 90:cb3d968589d8 9945
Kojto 90:cb3d968589d8 9946 /* PMC - Register accessors */
Kojto 90:cb3d968589d8 9947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
Kojto 90:cb3d968589d8 9948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
Kojto 90:cb3d968589d8 9949 #define PMC_REGSC_REG(base) ((base)->REGSC)
Kojto 90:cb3d968589d8 9950
Kojto 90:cb3d968589d8 9951 /*!
Kojto 90:cb3d968589d8 9952 * @}
Kojto 90:cb3d968589d8 9953 */ /* end of group PMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 9954
Kojto 90:cb3d968589d8 9955
Kojto 90:cb3d968589d8 9956 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 9957 -- PMC Register Masks
Kojto 90:cb3d968589d8 9958 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 9959
Kojto 90:cb3d968589d8 9960 /*!
Kojto 90:cb3d968589d8 9961 * @addtogroup PMC_Register_Masks PMC Register Masks
Kojto 90:cb3d968589d8 9962 * @{
Kojto 90:cb3d968589d8 9963 */
Kojto 90:cb3d968589d8 9964
Kojto 90:cb3d968589d8 9965 /* LVDSC1 Bit Fields */
Kojto 90:cb3d968589d8 9966 #define PMC_LVDSC1_LVDV_MASK 0x3u
Kojto 90:cb3d968589d8 9967 #define PMC_LVDSC1_LVDV_SHIFT 0
Kojto 90:cb3d968589d8 9968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
Kojto 90:cb3d968589d8 9969 #define PMC_LVDSC1_LVDRE_MASK 0x10u
Kojto 90:cb3d968589d8 9970 #define PMC_LVDSC1_LVDRE_SHIFT 4
Kojto 90:cb3d968589d8 9971 #define PMC_LVDSC1_LVDIE_MASK 0x20u
Kojto 90:cb3d968589d8 9972 #define PMC_LVDSC1_LVDIE_SHIFT 5
Kojto 90:cb3d968589d8 9973 #define PMC_LVDSC1_LVDACK_MASK 0x40u
Kojto 90:cb3d968589d8 9974 #define PMC_LVDSC1_LVDACK_SHIFT 6
Kojto 90:cb3d968589d8 9975 #define PMC_LVDSC1_LVDF_MASK 0x80u
Kojto 90:cb3d968589d8 9976 #define PMC_LVDSC1_LVDF_SHIFT 7
Kojto 90:cb3d968589d8 9977 /* LVDSC2 Bit Fields */
Kojto 90:cb3d968589d8 9978 #define PMC_LVDSC2_LVWV_MASK 0x3u
Kojto 90:cb3d968589d8 9979 #define PMC_LVDSC2_LVWV_SHIFT 0
Kojto 90:cb3d968589d8 9980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
Kojto 90:cb3d968589d8 9981 #define PMC_LVDSC2_LVWIE_MASK 0x20u
Kojto 90:cb3d968589d8 9982 #define PMC_LVDSC2_LVWIE_SHIFT 5
Kojto 90:cb3d968589d8 9983 #define PMC_LVDSC2_LVWACK_MASK 0x40u
Kojto 90:cb3d968589d8 9984 #define PMC_LVDSC2_LVWACK_SHIFT 6
Kojto 90:cb3d968589d8 9985 #define PMC_LVDSC2_LVWF_MASK 0x80u
Kojto 90:cb3d968589d8 9986 #define PMC_LVDSC2_LVWF_SHIFT 7
Kojto 90:cb3d968589d8 9987 /* REGSC Bit Fields */
Kojto 90:cb3d968589d8 9988 #define PMC_REGSC_BGBE_MASK 0x1u
Kojto 90:cb3d968589d8 9989 #define PMC_REGSC_BGBE_SHIFT 0
Kojto 90:cb3d968589d8 9990 #define PMC_REGSC_REGONS_MASK 0x4u
Kojto 90:cb3d968589d8 9991 #define PMC_REGSC_REGONS_SHIFT 2
Kojto 90:cb3d968589d8 9992 #define PMC_REGSC_ACKISO_MASK 0x8u
Kojto 90:cb3d968589d8 9993 #define PMC_REGSC_ACKISO_SHIFT 3
Kojto 90:cb3d968589d8 9994 #define PMC_REGSC_BGEN_MASK 0x10u
Kojto 90:cb3d968589d8 9995 #define PMC_REGSC_BGEN_SHIFT 4
Kojto 90:cb3d968589d8 9996
Kojto 90:cb3d968589d8 9997 /*!
Kojto 90:cb3d968589d8 9998 * @}
Kojto 90:cb3d968589d8 9999 */ /* end of group PMC_Register_Masks */
Kojto 90:cb3d968589d8 10000
Kojto 90:cb3d968589d8 10001
Kojto 90:cb3d968589d8 10002 /* PMC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10003 /** Peripheral PMC base address */
Kojto 90:cb3d968589d8 10004 #define PMC_BASE (0x4007D000u)
Kojto 90:cb3d968589d8 10005 /** Peripheral PMC base pointer */
Kojto 90:cb3d968589d8 10006 #define PMC ((PMC_Type *)PMC_BASE)
Kojto 90:cb3d968589d8 10007 #define PMC_BASE_PTR (PMC)
Kojto 90:cb3d968589d8 10008 /** Array initializer of PMC peripheral base addresses */
Kojto 90:cb3d968589d8 10009 #define PMC_BASE_ADDRS { PMC_BASE }
Kojto 90:cb3d968589d8 10010 /** Array initializer of PMC peripheral base pointers */
Kojto 90:cb3d968589d8 10011 #define PMC_BASE_PTRS { PMC }
Kojto 90:cb3d968589d8 10012 /** Interrupt vectors for the PMC peripheral type */
Kojto 90:cb3d968589d8 10013 #define PMC_IRQS { LVD_LVW_IRQn }
Kojto 90:cb3d968589d8 10014
Kojto 90:cb3d968589d8 10015 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10016 -- PMC - Register accessor macros
Kojto 90:cb3d968589d8 10017 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10018
Kojto 90:cb3d968589d8 10019 /*!
Kojto 90:cb3d968589d8 10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Kojto 90:cb3d968589d8 10021 * @{
Kojto 90:cb3d968589d8 10022 */
Kojto 90:cb3d968589d8 10023
Kojto 90:cb3d968589d8 10024
Kojto 90:cb3d968589d8 10025 /* PMC - Register instance definitions */
Kojto 90:cb3d968589d8 10026 /* PMC */
Kojto 90:cb3d968589d8 10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
Kojto 90:cb3d968589d8 10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
Kojto 90:cb3d968589d8 10029 #define PMC_REGSC PMC_REGSC_REG(PMC)
Kojto 90:cb3d968589d8 10030
Kojto 90:cb3d968589d8 10031 /*!
Kojto 90:cb3d968589d8 10032 * @}
Kojto 90:cb3d968589d8 10033 */ /* end of group PMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10034
Kojto 90:cb3d968589d8 10035
Kojto 90:cb3d968589d8 10036 /*!
Kojto 90:cb3d968589d8 10037 * @}
Kojto 90:cb3d968589d8 10038 */ /* end of group PMC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10039
Kojto 90:cb3d968589d8 10040
Kojto 90:cb3d968589d8 10041 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10042 -- PORT Peripheral Access Layer
Kojto 90:cb3d968589d8 10043 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10044
Kojto 90:cb3d968589d8 10045 /*!
Kojto 90:cb3d968589d8 10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Kojto 90:cb3d968589d8 10047 * @{
Kojto 90:cb3d968589d8 10048 */
Kojto 90:cb3d968589d8 10049
Kojto 90:cb3d968589d8 10050 /** PORT - Register Layout Typedef */
Kojto 90:cb3d968589d8 10051 typedef struct {
Kojto 90:cb3d968589d8 10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
Kojto 90:cb3d968589d8 10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
Kojto 90:cb3d968589d8 10055 uint8_t RESERVED_0[24];
Kojto 90:cb3d968589d8 10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
Kojto 90:cb3d968589d8 10057 uint8_t RESERVED_1[28];
Kojto 90:cb3d968589d8 10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
Kojto 90:cb3d968589d8 10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
Kojto 90:cb3d968589d8 10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
Kojto 90:cb3d968589d8 10061 } PORT_Type, *PORT_MemMapPtr;
Kojto 90:cb3d968589d8 10062
Kojto 90:cb3d968589d8 10063 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10064 -- PORT - Register accessor macros
Kojto 90:cb3d968589d8 10065 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10066
Kojto 90:cb3d968589d8 10067 /*!
Kojto 90:cb3d968589d8 10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Kojto 90:cb3d968589d8 10069 * @{
Kojto 90:cb3d968589d8 10070 */
Kojto 90:cb3d968589d8 10071
Kojto 90:cb3d968589d8 10072
Kojto 90:cb3d968589d8 10073 /* PORT - Register accessors */
Kojto 90:cb3d968589d8 10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
Kojto 90:cb3d968589d8 10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
Kojto 90:cb3d968589d8 10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
Kojto 90:cb3d968589d8 10077 #define PORT_ISFR_REG(base) ((base)->ISFR)
Kojto 90:cb3d968589d8 10078 #define PORT_DFER_REG(base) ((base)->DFER)
Kojto 90:cb3d968589d8 10079 #define PORT_DFCR_REG(base) ((base)->DFCR)
Kojto 90:cb3d968589d8 10080 #define PORT_DFWR_REG(base) ((base)->DFWR)
Kojto 90:cb3d968589d8 10081
Kojto 90:cb3d968589d8 10082 /*!
Kojto 90:cb3d968589d8 10083 * @}
Kojto 90:cb3d968589d8 10084 */ /* end of group PORT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10085
Kojto 90:cb3d968589d8 10086
Kojto 90:cb3d968589d8 10087 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10088 -- PORT Register Masks
Kojto 90:cb3d968589d8 10089 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10090
Kojto 90:cb3d968589d8 10091 /*!
Kojto 90:cb3d968589d8 10092 * @addtogroup PORT_Register_Masks PORT Register Masks
Kojto 90:cb3d968589d8 10093 * @{
Kojto 90:cb3d968589d8 10094 */
Kojto 90:cb3d968589d8 10095
Kojto 90:cb3d968589d8 10096 /* PCR Bit Fields */
Kojto 90:cb3d968589d8 10097 #define PORT_PCR_PS_MASK 0x1u
Kojto 90:cb3d968589d8 10098 #define PORT_PCR_PS_SHIFT 0
Kojto 90:cb3d968589d8 10099 #define PORT_PCR_PE_MASK 0x2u
Kojto 90:cb3d968589d8 10100 #define PORT_PCR_PE_SHIFT 1
Kojto 90:cb3d968589d8 10101 #define PORT_PCR_SRE_MASK 0x4u
Kojto 90:cb3d968589d8 10102 #define PORT_PCR_SRE_SHIFT 2
Kojto 90:cb3d968589d8 10103 #define PORT_PCR_PFE_MASK 0x10u
Kojto 90:cb3d968589d8 10104 #define PORT_PCR_PFE_SHIFT 4
Kojto 90:cb3d968589d8 10105 #define PORT_PCR_ODE_MASK 0x20u
Kojto 90:cb3d968589d8 10106 #define PORT_PCR_ODE_SHIFT 5
Kojto 90:cb3d968589d8 10107 #define PORT_PCR_DSE_MASK 0x40u
Kojto 90:cb3d968589d8 10108 #define PORT_PCR_DSE_SHIFT 6
Kojto 90:cb3d968589d8 10109 #define PORT_PCR_MUX_MASK 0x700u
Kojto 90:cb3d968589d8 10110 #define PORT_PCR_MUX_SHIFT 8
Kojto 90:cb3d968589d8 10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
Kojto 90:cb3d968589d8 10112 #define PORT_PCR_LK_MASK 0x8000u
Kojto 90:cb3d968589d8 10113 #define PORT_PCR_LK_SHIFT 15
Kojto 90:cb3d968589d8 10114 #define PORT_PCR_IRQC_MASK 0xF0000u
Kojto 90:cb3d968589d8 10115 #define PORT_PCR_IRQC_SHIFT 16
Kojto 90:cb3d968589d8 10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
Kojto 90:cb3d968589d8 10117 #define PORT_PCR_ISF_MASK 0x1000000u
Kojto 90:cb3d968589d8 10118 #define PORT_PCR_ISF_SHIFT 24
Kojto 90:cb3d968589d8 10119 /* GPCLR Bit Fields */
Kojto 90:cb3d968589d8 10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 10121 #define PORT_GPCLR_GPWD_SHIFT 0
Kojto 90:cb3d968589d8 10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
Kojto 90:cb3d968589d8 10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 10124 #define PORT_GPCLR_GPWE_SHIFT 16
Kojto 90:cb3d968589d8 10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
Kojto 90:cb3d968589d8 10126 /* GPCHR Bit Fields */
Kojto 90:cb3d968589d8 10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 10128 #define PORT_GPCHR_GPWD_SHIFT 0
Kojto 90:cb3d968589d8 10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
Kojto 90:cb3d968589d8 10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 10131 #define PORT_GPCHR_GPWE_SHIFT 16
Kojto 90:cb3d968589d8 10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
Kojto 90:cb3d968589d8 10133 /* ISFR Bit Fields */
Kojto 90:cb3d968589d8 10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10135 #define PORT_ISFR_ISF_SHIFT 0
Kojto 90:cb3d968589d8 10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
Kojto 90:cb3d968589d8 10137 /* DFER Bit Fields */
Kojto 90:cb3d968589d8 10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10139 #define PORT_DFER_DFE_SHIFT 0
Kojto 90:cb3d968589d8 10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
Kojto 90:cb3d968589d8 10141 /* DFCR Bit Fields */
Kojto 90:cb3d968589d8 10142 #define PORT_DFCR_CS_MASK 0x1u
Kojto 90:cb3d968589d8 10143 #define PORT_DFCR_CS_SHIFT 0
Kojto 90:cb3d968589d8 10144 /* DFWR Bit Fields */
Kojto 90:cb3d968589d8 10145 #define PORT_DFWR_FILT_MASK 0x1Fu
Kojto 90:cb3d968589d8 10146 #define PORT_DFWR_FILT_SHIFT 0
Kojto 90:cb3d968589d8 10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
Kojto 90:cb3d968589d8 10148
Kojto 90:cb3d968589d8 10149 /*!
Kojto 90:cb3d968589d8 10150 * @}
Kojto 90:cb3d968589d8 10151 */ /* end of group PORT_Register_Masks */
Kojto 90:cb3d968589d8 10152
Kojto 90:cb3d968589d8 10153
Kojto 90:cb3d968589d8 10154 /* PORT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10155 /** Peripheral PORTA base address */
Kojto 90:cb3d968589d8 10156 #define PORTA_BASE (0x40049000u)
Kojto 90:cb3d968589d8 10157 /** Peripheral PORTA base pointer */
Kojto 90:cb3d968589d8 10158 #define PORTA ((PORT_Type *)PORTA_BASE)
Kojto 90:cb3d968589d8 10159 #define PORTA_BASE_PTR (PORTA)
Kojto 90:cb3d968589d8 10160 /** Peripheral PORTB base address */
Kojto 90:cb3d968589d8 10161 #define PORTB_BASE (0x4004A000u)
Kojto 90:cb3d968589d8 10162 /** Peripheral PORTB base pointer */
Kojto 90:cb3d968589d8 10163 #define PORTB ((PORT_Type *)PORTB_BASE)
Kojto 90:cb3d968589d8 10164 #define PORTB_BASE_PTR (PORTB)
Kojto 90:cb3d968589d8 10165 /** Peripheral PORTC base address */
Kojto 90:cb3d968589d8 10166 #define PORTC_BASE (0x4004B000u)
Kojto 90:cb3d968589d8 10167 /** Peripheral PORTC base pointer */
Kojto 90:cb3d968589d8 10168 #define PORTC ((PORT_Type *)PORTC_BASE)
Kojto 90:cb3d968589d8 10169 #define PORTC_BASE_PTR (PORTC)
Kojto 90:cb3d968589d8 10170 /** Peripheral PORTD base address */
Kojto 90:cb3d968589d8 10171 #define PORTD_BASE (0x4004C000u)
Kojto 90:cb3d968589d8 10172 /** Peripheral PORTD base pointer */
Kojto 90:cb3d968589d8 10173 #define PORTD ((PORT_Type *)PORTD_BASE)
Kojto 90:cb3d968589d8 10174 #define PORTD_BASE_PTR (PORTD)
Kojto 90:cb3d968589d8 10175 /** Peripheral PORTE base address */
Kojto 90:cb3d968589d8 10176 #define PORTE_BASE (0x4004D000u)
Kojto 90:cb3d968589d8 10177 /** Peripheral PORTE base pointer */
Kojto 90:cb3d968589d8 10178 #define PORTE ((PORT_Type *)PORTE_BASE)
Kojto 90:cb3d968589d8 10179 #define PORTE_BASE_PTR (PORTE)
Kojto 90:cb3d968589d8 10180 /** Array initializer of PORT peripheral base addresses */
Kojto 90:cb3d968589d8 10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
Kojto 90:cb3d968589d8 10182 /** Array initializer of PORT peripheral base pointers */
Kojto 90:cb3d968589d8 10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
Kojto 90:cb3d968589d8 10184 /** Interrupt vectors for the PORT peripheral type */
Kojto 90:cb3d968589d8 10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
Kojto 90:cb3d968589d8 10186
Kojto 90:cb3d968589d8 10187 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10188 -- PORT - Register accessor macros
Kojto 90:cb3d968589d8 10189 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10190
Kojto 90:cb3d968589d8 10191 /*!
Kojto 90:cb3d968589d8 10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Kojto 90:cb3d968589d8 10193 * @{
Kojto 90:cb3d968589d8 10194 */
Kojto 90:cb3d968589d8 10195
Kojto 90:cb3d968589d8 10196
Kojto 90:cb3d968589d8 10197 /* PORT - Register instance definitions */
Kojto 90:cb3d968589d8 10198 /* PORTA */
Kojto 90:cb3d968589d8 10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
Kojto 90:cb3d968589d8 10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
Kojto 90:cb3d968589d8 10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
Kojto 90:cb3d968589d8 10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
Kojto 90:cb3d968589d8 10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
Kojto 90:cb3d968589d8 10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
Kojto 90:cb3d968589d8 10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
Kojto 90:cb3d968589d8 10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
Kojto 90:cb3d968589d8 10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
Kojto 90:cb3d968589d8 10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
Kojto 90:cb3d968589d8 10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
Kojto 90:cb3d968589d8 10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
Kojto 90:cb3d968589d8 10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
Kojto 90:cb3d968589d8 10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
Kojto 90:cb3d968589d8 10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
Kojto 90:cb3d968589d8 10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
Kojto 90:cb3d968589d8 10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
Kojto 90:cb3d968589d8 10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
Kojto 90:cb3d968589d8 10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
Kojto 90:cb3d968589d8 10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
Kojto 90:cb3d968589d8 10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
Kojto 90:cb3d968589d8 10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
Kojto 90:cb3d968589d8 10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
Kojto 90:cb3d968589d8 10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
Kojto 90:cb3d968589d8 10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
Kojto 90:cb3d968589d8 10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
Kojto 90:cb3d968589d8 10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
Kojto 90:cb3d968589d8 10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
Kojto 90:cb3d968589d8 10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
Kojto 90:cb3d968589d8 10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
Kojto 90:cb3d968589d8 10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
Kojto 90:cb3d968589d8 10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
Kojto 90:cb3d968589d8 10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
Kojto 90:cb3d968589d8 10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
Kojto 90:cb3d968589d8 10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
Kojto 90:cb3d968589d8 10234 /* PORTB */
Kojto 90:cb3d968589d8 10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
Kojto 90:cb3d968589d8 10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
Kojto 90:cb3d968589d8 10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
Kojto 90:cb3d968589d8 10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
Kojto 90:cb3d968589d8 10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
Kojto 90:cb3d968589d8 10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
Kojto 90:cb3d968589d8 10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
Kojto 90:cb3d968589d8 10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
Kojto 90:cb3d968589d8 10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
Kojto 90:cb3d968589d8 10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
Kojto 90:cb3d968589d8 10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
Kojto 90:cb3d968589d8 10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
Kojto 90:cb3d968589d8 10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
Kojto 90:cb3d968589d8 10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
Kojto 90:cb3d968589d8 10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
Kojto 90:cb3d968589d8 10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
Kojto 90:cb3d968589d8 10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
Kojto 90:cb3d968589d8 10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
Kojto 90:cb3d968589d8 10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
Kojto 90:cb3d968589d8 10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
Kojto 90:cb3d968589d8 10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
Kojto 90:cb3d968589d8 10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
Kojto 90:cb3d968589d8 10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
Kojto 90:cb3d968589d8 10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
Kojto 90:cb3d968589d8 10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
Kojto 90:cb3d968589d8 10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
Kojto 90:cb3d968589d8 10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
Kojto 90:cb3d968589d8 10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
Kojto 90:cb3d968589d8 10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
Kojto 90:cb3d968589d8 10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
Kojto 90:cb3d968589d8 10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
Kojto 90:cb3d968589d8 10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
Kojto 90:cb3d968589d8 10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
Kojto 90:cb3d968589d8 10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
Kojto 90:cb3d968589d8 10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
Kojto 90:cb3d968589d8 10270 /* PORTC */
Kojto 90:cb3d968589d8 10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
Kojto 90:cb3d968589d8 10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
Kojto 90:cb3d968589d8 10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
Kojto 90:cb3d968589d8 10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
Kojto 90:cb3d968589d8 10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
Kojto 90:cb3d968589d8 10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
Kojto 90:cb3d968589d8 10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
Kojto 90:cb3d968589d8 10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
Kojto 90:cb3d968589d8 10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
Kojto 90:cb3d968589d8 10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
Kojto 90:cb3d968589d8 10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
Kojto 90:cb3d968589d8 10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
Kojto 90:cb3d968589d8 10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
Kojto 90:cb3d968589d8 10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
Kojto 90:cb3d968589d8 10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
Kojto 90:cb3d968589d8 10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
Kojto 90:cb3d968589d8 10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
Kojto 90:cb3d968589d8 10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
Kojto 90:cb3d968589d8 10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
Kojto 90:cb3d968589d8 10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
Kojto 90:cb3d968589d8 10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
Kojto 90:cb3d968589d8 10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
Kojto 90:cb3d968589d8 10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
Kojto 90:cb3d968589d8 10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
Kojto 90:cb3d968589d8 10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
Kojto 90:cb3d968589d8 10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
Kojto 90:cb3d968589d8 10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
Kojto 90:cb3d968589d8 10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
Kojto 90:cb3d968589d8 10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
Kojto 90:cb3d968589d8 10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
Kojto 90:cb3d968589d8 10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
Kojto 90:cb3d968589d8 10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
Kojto 90:cb3d968589d8 10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
Kojto 90:cb3d968589d8 10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
Kojto 90:cb3d968589d8 10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
Kojto 90:cb3d968589d8 10306 /* PORTD */
Kojto 90:cb3d968589d8 10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
Kojto 90:cb3d968589d8 10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
Kojto 90:cb3d968589d8 10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
Kojto 90:cb3d968589d8 10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
Kojto 90:cb3d968589d8 10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
Kojto 90:cb3d968589d8 10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
Kojto 90:cb3d968589d8 10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
Kojto 90:cb3d968589d8 10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
Kojto 90:cb3d968589d8 10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
Kojto 90:cb3d968589d8 10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
Kojto 90:cb3d968589d8 10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
Kojto 90:cb3d968589d8 10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
Kojto 90:cb3d968589d8 10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
Kojto 90:cb3d968589d8 10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
Kojto 90:cb3d968589d8 10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
Kojto 90:cb3d968589d8 10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
Kojto 90:cb3d968589d8 10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
Kojto 90:cb3d968589d8 10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
Kojto 90:cb3d968589d8 10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
Kojto 90:cb3d968589d8 10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
Kojto 90:cb3d968589d8 10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
Kojto 90:cb3d968589d8 10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
Kojto 90:cb3d968589d8 10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
Kojto 90:cb3d968589d8 10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
Kojto 90:cb3d968589d8 10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
Kojto 90:cb3d968589d8 10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
Kojto 90:cb3d968589d8 10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
Kojto 90:cb3d968589d8 10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
Kojto 90:cb3d968589d8 10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
Kojto 90:cb3d968589d8 10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
Kojto 90:cb3d968589d8 10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
Kojto 90:cb3d968589d8 10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
Kojto 90:cb3d968589d8 10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
Kojto 90:cb3d968589d8 10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
Kojto 90:cb3d968589d8 10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
Kojto 90:cb3d968589d8 10342 #define PORTD_DFER PORT_DFER_REG(PORTD)
Kojto 90:cb3d968589d8 10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
Kojto 90:cb3d968589d8 10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
Kojto 90:cb3d968589d8 10345 /* PORTE */
Kojto 90:cb3d968589d8 10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
Kojto 90:cb3d968589d8 10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
Kojto 90:cb3d968589d8 10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
Kojto 90:cb3d968589d8 10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
Kojto 90:cb3d968589d8 10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
Kojto 90:cb3d968589d8 10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
Kojto 90:cb3d968589d8 10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
Kojto 90:cb3d968589d8 10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
Kojto 90:cb3d968589d8 10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
Kojto 90:cb3d968589d8 10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
Kojto 90:cb3d968589d8 10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
Kojto 90:cb3d968589d8 10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
Kojto 90:cb3d968589d8 10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
Kojto 90:cb3d968589d8 10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
Kojto 90:cb3d968589d8 10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
Kojto 90:cb3d968589d8 10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
Kojto 90:cb3d968589d8 10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
Kojto 90:cb3d968589d8 10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
Kojto 90:cb3d968589d8 10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
Kojto 90:cb3d968589d8 10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
Kojto 90:cb3d968589d8 10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
Kojto 90:cb3d968589d8 10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
Kojto 90:cb3d968589d8 10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
Kojto 90:cb3d968589d8 10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
Kojto 90:cb3d968589d8 10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
Kojto 90:cb3d968589d8 10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
Kojto 90:cb3d968589d8 10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
Kojto 90:cb3d968589d8 10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
Kojto 90:cb3d968589d8 10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
Kojto 90:cb3d968589d8 10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
Kojto 90:cb3d968589d8 10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
Kojto 90:cb3d968589d8 10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
Kojto 90:cb3d968589d8 10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
Kojto 90:cb3d968589d8 10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
Kojto 90:cb3d968589d8 10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
Kojto 90:cb3d968589d8 10381
Kojto 90:cb3d968589d8 10382 /* PORT - Register array accessors */
Kojto 90:cb3d968589d8 10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
Kojto 90:cb3d968589d8 10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
Kojto 90:cb3d968589d8 10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
Kojto 90:cb3d968589d8 10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
Kojto 90:cb3d968589d8 10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
Kojto 90:cb3d968589d8 10388
Kojto 90:cb3d968589d8 10389 /*!
Kojto 90:cb3d968589d8 10390 * @}
Kojto 90:cb3d968589d8 10391 */ /* end of group PORT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10392
Kojto 90:cb3d968589d8 10393
Kojto 90:cb3d968589d8 10394 /*!
Kojto 90:cb3d968589d8 10395 * @}
Kojto 90:cb3d968589d8 10396 */ /* end of group PORT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10397
Kojto 90:cb3d968589d8 10398
Kojto 90:cb3d968589d8 10399 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10400 -- RCM Peripheral Access Layer
Kojto 90:cb3d968589d8 10401 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10402
Kojto 90:cb3d968589d8 10403 /*!
Kojto 90:cb3d968589d8 10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Kojto 90:cb3d968589d8 10405 * @{
Kojto 90:cb3d968589d8 10406 */
Kojto 90:cb3d968589d8 10407
Kojto 90:cb3d968589d8 10408 /** RCM - Register Layout Typedef */
Kojto 90:cb3d968589d8 10409 typedef struct {
Kojto 90:cb3d968589d8 10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
Kojto 90:cb3d968589d8 10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
Kojto 90:cb3d968589d8 10412 uint8_t RESERVED_0[2];
Kojto 90:cb3d968589d8 10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
Kojto 90:cb3d968589d8 10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
Kojto 90:cb3d968589d8 10415 uint8_t RESERVED_1[1];
Kojto 90:cb3d968589d8 10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
Kojto 90:cb3d968589d8 10417 } RCM_Type, *RCM_MemMapPtr;
Kojto 90:cb3d968589d8 10418
Kojto 90:cb3d968589d8 10419 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10420 -- RCM - Register accessor macros
Kojto 90:cb3d968589d8 10421 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10422
Kojto 90:cb3d968589d8 10423 /*!
Kojto 90:cb3d968589d8 10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Kojto 90:cb3d968589d8 10425 * @{
Kojto 90:cb3d968589d8 10426 */
Kojto 90:cb3d968589d8 10427
Kojto 90:cb3d968589d8 10428
Kojto 90:cb3d968589d8 10429 /* RCM - Register accessors */
Kojto 90:cb3d968589d8 10430 #define RCM_SRS0_REG(base) ((base)->SRS0)
Kojto 90:cb3d968589d8 10431 #define RCM_SRS1_REG(base) ((base)->SRS1)
Kojto 90:cb3d968589d8 10432 #define RCM_RPFC_REG(base) ((base)->RPFC)
Kojto 90:cb3d968589d8 10433 #define RCM_RPFW_REG(base) ((base)->RPFW)
Kojto 90:cb3d968589d8 10434 #define RCM_MR_REG(base) ((base)->MR)
Kojto 90:cb3d968589d8 10435
Kojto 90:cb3d968589d8 10436 /*!
Kojto 90:cb3d968589d8 10437 * @}
Kojto 90:cb3d968589d8 10438 */ /* end of group RCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10439
Kojto 90:cb3d968589d8 10440
Kojto 90:cb3d968589d8 10441 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10442 -- RCM Register Masks
Kojto 90:cb3d968589d8 10443 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10444
Kojto 90:cb3d968589d8 10445 /*!
Kojto 90:cb3d968589d8 10446 * @addtogroup RCM_Register_Masks RCM Register Masks
Kojto 90:cb3d968589d8 10447 * @{
Kojto 90:cb3d968589d8 10448 */
Kojto 90:cb3d968589d8 10449
Kojto 90:cb3d968589d8 10450 /* SRS0 Bit Fields */
Kojto 90:cb3d968589d8 10451 #define RCM_SRS0_WAKEUP_MASK 0x1u
Kojto 90:cb3d968589d8 10452 #define RCM_SRS0_WAKEUP_SHIFT 0
Kojto 90:cb3d968589d8 10453 #define RCM_SRS0_LVD_MASK 0x2u
Kojto 90:cb3d968589d8 10454 #define RCM_SRS0_LVD_SHIFT 1
Kojto 90:cb3d968589d8 10455 #define RCM_SRS0_LOC_MASK 0x4u
Kojto 90:cb3d968589d8 10456 #define RCM_SRS0_LOC_SHIFT 2
Kojto 90:cb3d968589d8 10457 #define RCM_SRS0_LOL_MASK 0x8u
Kojto 90:cb3d968589d8 10458 #define RCM_SRS0_LOL_SHIFT 3
Kojto 90:cb3d968589d8 10459 #define RCM_SRS0_WDOG_MASK 0x20u
Kojto 90:cb3d968589d8 10460 #define RCM_SRS0_WDOG_SHIFT 5
Kojto 90:cb3d968589d8 10461 #define RCM_SRS0_PIN_MASK 0x40u
Kojto 90:cb3d968589d8 10462 #define RCM_SRS0_PIN_SHIFT 6
Kojto 90:cb3d968589d8 10463 #define RCM_SRS0_POR_MASK 0x80u
Kojto 90:cb3d968589d8 10464 #define RCM_SRS0_POR_SHIFT 7
Kojto 90:cb3d968589d8 10465 /* SRS1 Bit Fields */
Kojto 90:cb3d968589d8 10466 #define RCM_SRS1_JTAG_MASK 0x1u
Kojto 90:cb3d968589d8 10467 #define RCM_SRS1_JTAG_SHIFT 0
Kojto 90:cb3d968589d8 10468 #define RCM_SRS1_LOCKUP_MASK 0x2u
Kojto 90:cb3d968589d8 10469 #define RCM_SRS1_LOCKUP_SHIFT 1
Kojto 90:cb3d968589d8 10470 #define RCM_SRS1_SW_MASK 0x4u
Kojto 90:cb3d968589d8 10471 #define RCM_SRS1_SW_SHIFT 2
Kojto 90:cb3d968589d8 10472 #define RCM_SRS1_MDM_AP_MASK 0x8u
Kojto 90:cb3d968589d8 10473 #define RCM_SRS1_MDM_AP_SHIFT 3
Kojto 90:cb3d968589d8 10474 #define RCM_SRS1_EZPT_MASK 0x10u
Kojto 90:cb3d968589d8 10475 #define RCM_SRS1_EZPT_SHIFT 4
Kojto 90:cb3d968589d8 10476 #define RCM_SRS1_SACKERR_MASK 0x20u
Kojto 90:cb3d968589d8 10477 #define RCM_SRS1_SACKERR_SHIFT 5
Kojto 90:cb3d968589d8 10478 /* RPFC Bit Fields */
Kojto 90:cb3d968589d8 10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
Kojto 90:cb3d968589d8 10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
Kojto 90:cb3d968589d8 10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
Kojto 90:cb3d968589d8 10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
Kojto 90:cb3d968589d8 10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2
Kojto 90:cb3d968589d8 10484 /* RPFW Bit Fields */
Kojto 90:cb3d968589d8 10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
Kojto 90:cb3d968589d8 10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
Kojto 90:cb3d968589d8 10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
Kojto 90:cb3d968589d8 10488 /* MR Bit Fields */
Kojto 90:cb3d968589d8 10489 #define RCM_MR_EZP_MS_MASK 0x2u
Kojto 90:cb3d968589d8 10490 #define RCM_MR_EZP_MS_SHIFT 1
Kojto 90:cb3d968589d8 10491
Kojto 90:cb3d968589d8 10492 /*!
Kojto 90:cb3d968589d8 10493 * @}
Kojto 90:cb3d968589d8 10494 */ /* end of group RCM_Register_Masks */
Kojto 90:cb3d968589d8 10495
Kojto 90:cb3d968589d8 10496
Kojto 90:cb3d968589d8 10497 /* RCM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10498 /** Peripheral RCM base address */
Kojto 90:cb3d968589d8 10499 #define RCM_BASE (0x4007F000u)
Kojto 90:cb3d968589d8 10500 /** Peripheral RCM base pointer */
Kojto 90:cb3d968589d8 10501 #define RCM ((RCM_Type *)RCM_BASE)
Kojto 90:cb3d968589d8 10502 #define RCM_BASE_PTR (RCM)
Kojto 90:cb3d968589d8 10503 /** Array initializer of RCM peripheral base addresses */
Kojto 90:cb3d968589d8 10504 #define RCM_BASE_ADDRS { RCM_BASE }
Kojto 90:cb3d968589d8 10505 /** Array initializer of RCM peripheral base pointers */
Kojto 90:cb3d968589d8 10506 #define RCM_BASE_PTRS { RCM }
Kojto 90:cb3d968589d8 10507
Kojto 90:cb3d968589d8 10508 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10509 -- RCM - Register accessor macros
Kojto 90:cb3d968589d8 10510 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10511
Kojto 90:cb3d968589d8 10512 /*!
Kojto 90:cb3d968589d8 10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Kojto 90:cb3d968589d8 10514 * @{
Kojto 90:cb3d968589d8 10515 */
Kojto 90:cb3d968589d8 10516
Kojto 90:cb3d968589d8 10517
Kojto 90:cb3d968589d8 10518 /* RCM - Register instance definitions */
Kojto 90:cb3d968589d8 10519 /* RCM */
Kojto 90:cb3d968589d8 10520 #define RCM_SRS0 RCM_SRS0_REG(RCM)
Kojto 90:cb3d968589d8 10521 #define RCM_SRS1 RCM_SRS1_REG(RCM)
Kojto 90:cb3d968589d8 10522 #define RCM_RPFC RCM_RPFC_REG(RCM)
Kojto 90:cb3d968589d8 10523 #define RCM_RPFW RCM_RPFW_REG(RCM)
Kojto 90:cb3d968589d8 10524 #define RCM_MR RCM_MR_REG(RCM)
Kojto 90:cb3d968589d8 10525
Kojto 90:cb3d968589d8 10526 /*!
Kojto 90:cb3d968589d8 10527 * @}
Kojto 90:cb3d968589d8 10528 */ /* end of group RCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10529
Kojto 90:cb3d968589d8 10530
Kojto 90:cb3d968589d8 10531 /*!
Kojto 90:cb3d968589d8 10532 * @}
Kojto 90:cb3d968589d8 10533 */ /* end of group RCM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10534
Kojto 90:cb3d968589d8 10535
Kojto 90:cb3d968589d8 10536 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10537 -- RFSYS Peripheral Access Layer
Kojto 90:cb3d968589d8 10538 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10539
Kojto 90:cb3d968589d8 10540 /*!
Kojto 90:cb3d968589d8 10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
Kojto 90:cb3d968589d8 10542 * @{
Kojto 90:cb3d968589d8 10543 */
Kojto 90:cb3d968589d8 10544
Kojto 90:cb3d968589d8 10545 /** RFSYS - Register Layout Typedef */
Kojto 90:cb3d968589d8 10546 typedef struct {
Kojto 90:cb3d968589d8 10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 10548 } RFSYS_Type, *RFSYS_MemMapPtr;
Kojto 90:cb3d968589d8 10549
Kojto 90:cb3d968589d8 10550 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10551 -- RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 10552 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10553
Kojto 90:cb3d968589d8 10554 /*!
Kojto 90:cb3d968589d8 10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 10556 * @{
Kojto 90:cb3d968589d8 10557 */
Kojto 90:cb3d968589d8 10558
Kojto 90:cb3d968589d8 10559
Kojto 90:cb3d968589d8 10560 /* RFSYS - Register accessors */
Kojto 90:cb3d968589d8 10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
Kojto 90:cb3d968589d8 10562
Kojto 90:cb3d968589d8 10563 /*!
Kojto 90:cb3d968589d8 10564 * @}
Kojto 90:cb3d968589d8 10565 */ /* end of group RFSYS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10566
Kojto 90:cb3d968589d8 10567
Kojto 90:cb3d968589d8 10568 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10569 -- RFSYS Register Masks
Kojto 90:cb3d968589d8 10570 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10571
Kojto 90:cb3d968589d8 10572 /*!
Kojto 90:cb3d968589d8 10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
Kojto 90:cb3d968589d8 10574 * @{
Kojto 90:cb3d968589d8 10575 */
Kojto 90:cb3d968589d8 10576
Kojto 90:cb3d968589d8 10577 /* REG Bit Fields */
Kojto 90:cb3d968589d8 10578 #define RFSYS_REG_LL_MASK 0xFFu
Kojto 90:cb3d968589d8 10579 #define RFSYS_REG_LL_SHIFT 0
Kojto 90:cb3d968589d8 10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
Kojto 90:cb3d968589d8 10581 #define RFSYS_REG_LH_MASK 0xFF00u
Kojto 90:cb3d968589d8 10582 #define RFSYS_REG_LH_SHIFT 8
Kojto 90:cb3d968589d8 10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
Kojto 90:cb3d968589d8 10584 #define RFSYS_REG_HL_MASK 0xFF0000u
Kojto 90:cb3d968589d8 10585 #define RFSYS_REG_HL_SHIFT 16
Kojto 90:cb3d968589d8 10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
Kojto 90:cb3d968589d8 10587 #define RFSYS_REG_HH_MASK 0xFF000000u
Kojto 90:cb3d968589d8 10588 #define RFSYS_REG_HH_SHIFT 24
Kojto 90:cb3d968589d8 10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
Kojto 90:cb3d968589d8 10590
Kojto 90:cb3d968589d8 10591 /*!
Kojto 90:cb3d968589d8 10592 * @}
Kojto 90:cb3d968589d8 10593 */ /* end of group RFSYS_Register_Masks */
Kojto 90:cb3d968589d8 10594
Kojto 90:cb3d968589d8 10595
Kojto 90:cb3d968589d8 10596 /* RFSYS - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10597 /** Peripheral RFSYS base address */
Kojto 90:cb3d968589d8 10598 #define RFSYS_BASE (0x40041000u)
Kojto 90:cb3d968589d8 10599 /** Peripheral RFSYS base pointer */
Kojto 90:cb3d968589d8 10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
Kojto 90:cb3d968589d8 10601 #define RFSYS_BASE_PTR (RFSYS)
Kojto 90:cb3d968589d8 10602 /** Array initializer of RFSYS peripheral base addresses */
Kojto 90:cb3d968589d8 10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
Kojto 90:cb3d968589d8 10604 /** Array initializer of RFSYS peripheral base pointers */
Kojto 90:cb3d968589d8 10605 #define RFSYS_BASE_PTRS { RFSYS }
Kojto 90:cb3d968589d8 10606
Kojto 90:cb3d968589d8 10607 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10608 -- RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 10609 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10610
Kojto 90:cb3d968589d8 10611 /*!
Kojto 90:cb3d968589d8 10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 10613 * @{
Kojto 90:cb3d968589d8 10614 */
Kojto 90:cb3d968589d8 10615
Kojto 90:cb3d968589d8 10616
Kojto 90:cb3d968589d8 10617 /* RFSYS - Register instance definitions */
Kojto 90:cb3d968589d8 10618 /* RFSYS */
Kojto 90:cb3d968589d8 10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
Kojto 90:cb3d968589d8 10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
Kojto 90:cb3d968589d8 10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
Kojto 90:cb3d968589d8 10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
Kojto 90:cb3d968589d8 10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
Kojto 90:cb3d968589d8 10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
Kojto 90:cb3d968589d8 10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
Kojto 90:cb3d968589d8 10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
Kojto 90:cb3d968589d8 10627
Kojto 90:cb3d968589d8 10628 /* RFSYS - Register array accessors */
Kojto 90:cb3d968589d8 10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
Kojto 90:cb3d968589d8 10630
Kojto 90:cb3d968589d8 10631 /*!
Kojto 90:cb3d968589d8 10632 * @}
Kojto 90:cb3d968589d8 10633 */ /* end of group RFSYS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10634
Kojto 90:cb3d968589d8 10635
Kojto 90:cb3d968589d8 10636 /*!
Kojto 90:cb3d968589d8 10637 * @}
Kojto 90:cb3d968589d8 10638 */ /* end of group RFSYS_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10639
Kojto 90:cb3d968589d8 10640
Kojto 90:cb3d968589d8 10641 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10642 -- RFVBAT Peripheral Access Layer
Kojto 90:cb3d968589d8 10643 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10644
Kojto 90:cb3d968589d8 10645 /*!
Kojto 90:cb3d968589d8 10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
Kojto 90:cb3d968589d8 10647 * @{
Kojto 90:cb3d968589d8 10648 */
Kojto 90:cb3d968589d8 10649
Kojto 90:cb3d968589d8 10650 /** RFVBAT - Register Layout Typedef */
Kojto 90:cb3d968589d8 10651 typedef struct {
Kojto 90:cb3d968589d8 10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 10653 } RFVBAT_Type, *RFVBAT_MemMapPtr;
Kojto 90:cb3d968589d8 10654
Kojto 90:cb3d968589d8 10655 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10656 -- RFVBAT - Register accessor macros
Kojto 90:cb3d968589d8 10657 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10658
Kojto 90:cb3d968589d8 10659 /*!
Kojto 90:cb3d968589d8 10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
Kojto 90:cb3d968589d8 10661 * @{
Kojto 90:cb3d968589d8 10662 */
Kojto 90:cb3d968589d8 10663
Kojto 90:cb3d968589d8 10664
Kojto 90:cb3d968589d8 10665 /* RFVBAT - Register accessors */
Kojto 90:cb3d968589d8 10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
Kojto 90:cb3d968589d8 10667
Kojto 90:cb3d968589d8 10668 /*!
Kojto 90:cb3d968589d8 10669 * @}
Kojto 90:cb3d968589d8 10670 */ /* end of group RFVBAT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10671
Kojto 90:cb3d968589d8 10672
Kojto 90:cb3d968589d8 10673 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10674 -- RFVBAT Register Masks
Kojto 90:cb3d968589d8 10675 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10676
Kojto 90:cb3d968589d8 10677 /*!
Kojto 90:cb3d968589d8 10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
Kojto 90:cb3d968589d8 10679 * @{
Kojto 90:cb3d968589d8 10680 */
Kojto 90:cb3d968589d8 10681
Kojto 90:cb3d968589d8 10682 /* REG Bit Fields */
Kojto 90:cb3d968589d8 10683 #define RFVBAT_REG_LL_MASK 0xFFu
Kojto 90:cb3d968589d8 10684 #define RFVBAT_REG_LL_SHIFT 0
Kojto 90:cb3d968589d8 10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
Kojto 90:cb3d968589d8 10686 #define RFVBAT_REG_LH_MASK 0xFF00u
Kojto 90:cb3d968589d8 10687 #define RFVBAT_REG_LH_SHIFT 8
Kojto 90:cb3d968589d8 10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
Kojto 90:cb3d968589d8 10689 #define RFVBAT_REG_HL_MASK 0xFF0000u
Kojto 90:cb3d968589d8 10690 #define RFVBAT_REG_HL_SHIFT 16
Kojto 90:cb3d968589d8 10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
Kojto 90:cb3d968589d8 10692 #define RFVBAT_REG_HH_MASK 0xFF000000u
Kojto 90:cb3d968589d8 10693 #define RFVBAT_REG_HH_SHIFT 24
Kojto 90:cb3d968589d8 10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
Kojto 90:cb3d968589d8 10695
Kojto 90:cb3d968589d8 10696 /*!
Kojto 90:cb3d968589d8 10697 * @}
Kojto 90:cb3d968589d8 10698 */ /* end of group RFVBAT_Register_Masks */
Kojto 90:cb3d968589d8 10699
Kojto 90:cb3d968589d8 10700
Kojto 90:cb3d968589d8 10701 /* RFVBAT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10702 /** Peripheral RFVBAT base address */
Kojto 90:cb3d968589d8 10703 #define RFVBAT_BASE (0x4003E000u)
Kojto 90:cb3d968589d8 10704 /** Peripheral RFVBAT base pointer */
Kojto 90:cb3d968589d8 10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
Kojto 90:cb3d968589d8 10706 #define RFVBAT_BASE_PTR (RFVBAT)
Kojto 90:cb3d968589d8 10707 /** Array initializer of RFVBAT peripheral base addresses */
Kojto 90:cb3d968589d8 10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
Kojto 90:cb3d968589d8 10709 /** Array initializer of RFVBAT peripheral base pointers */
Kojto 90:cb3d968589d8 10710 #define RFVBAT_BASE_PTRS { RFVBAT }
Kojto 90:cb3d968589d8 10711
Kojto 90:cb3d968589d8 10712 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10713 -- RFVBAT - Register accessor macros
Kojto 90:cb3d968589d8 10714 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10715
Kojto 90:cb3d968589d8 10716 /*!
Kojto 90:cb3d968589d8 10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
Kojto 90:cb3d968589d8 10718 * @{
Kojto 90:cb3d968589d8 10719 */
Kojto 90:cb3d968589d8 10720
Kojto 90:cb3d968589d8 10721
Kojto 90:cb3d968589d8 10722 /* RFVBAT - Register instance definitions */
Kojto 90:cb3d968589d8 10723 /* RFVBAT */
Kojto 90:cb3d968589d8 10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
Kojto 90:cb3d968589d8 10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
Kojto 90:cb3d968589d8 10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
Kojto 90:cb3d968589d8 10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
Kojto 90:cb3d968589d8 10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
Kojto 90:cb3d968589d8 10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
Kojto 90:cb3d968589d8 10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
Kojto 90:cb3d968589d8 10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
Kojto 90:cb3d968589d8 10732
Kojto 90:cb3d968589d8 10733 /* RFVBAT - Register array accessors */
Kojto 90:cb3d968589d8 10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
Kojto 90:cb3d968589d8 10735
Kojto 90:cb3d968589d8 10736 /*!
Kojto 90:cb3d968589d8 10737 * @}
Kojto 90:cb3d968589d8 10738 */ /* end of group RFVBAT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10739
Kojto 90:cb3d968589d8 10740
Kojto 90:cb3d968589d8 10741 /*!
Kojto 90:cb3d968589d8 10742 * @}
Kojto 90:cb3d968589d8 10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10744
Kojto 90:cb3d968589d8 10745
Kojto 90:cb3d968589d8 10746 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10747 -- RNG Peripheral Access Layer
Kojto 90:cb3d968589d8 10748 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10749
Kojto 90:cb3d968589d8 10750 /*!
Kojto 90:cb3d968589d8 10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
Kojto 90:cb3d968589d8 10752 * @{
Kojto 90:cb3d968589d8 10753 */
Kojto 90:cb3d968589d8 10754
Kojto 90:cb3d968589d8 10755 /** RNG - Register Layout Typedef */
Kojto 90:cb3d968589d8 10756 typedef struct {
Kojto 90:cb3d968589d8 10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
Kojto 90:cb3d968589d8 10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
Kojto 90:cb3d968589d8 10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
Kojto 90:cb3d968589d8 10761 } RNG_Type, *RNG_MemMapPtr;
Kojto 90:cb3d968589d8 10762
Kojto 90:cb3d968589d8 10763 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10764 -- RNG - Register accessor macros
Kojto 90:cb3d968589d8 10765 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10766
Kojto 90:cb3d968589d8 10767 /*!
Kojto 90:cb3d968589d8 10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
Kojto 90:cb3d968589d8 10769 * @{
Kojto 90:cb3d968589d8 10770 */
Kojto 90:cb3d968589d8 10771
Kojto 90:cb3d968589d8 10772
Kojto 90:cb3d968589d8 10773 /* RNG - Register accessors */
Kojto 90:cb3d968589d8 10774 #define RNG_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 10775 #define RNG_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 10776 #define RNG_ER_REG(base) ((base)->ER)
Kojto 90:cb3d968589d8 10777 #define RNG_OR_REG(base) ((base)->OR)
Kojto 90:cb3d968589d8 10778
Kojto 90:cb3d968589d8 10779 /*!
Kojto 90:cb3d968589d8 10780 * @}
Kojto 90:cb3d968589d8 10781 */ /* end of group RNG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10782
Kojto 90:cb3d968589d8 10783
Kojto 90:cb3d968589d8 10784 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10785 -- RNG Register Masks
Kojto 90:cb3d968589d8 10786 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10787
Kojto 90:cb3d968589d8 10788 /*!
Kojto 90:cb3d968589d8 10789 * @addtogroup RNG_Register_Masks RNG Register Masks
Kojto 90:cb3d968589d8 10790 * @{
Kojto 90:cb3d968589d8 10791 */
Kojto 90:cb3d968589d8 10792
Kojto 90:cb3d968589d8 10793 /* CR Bit Fields */
Kojto 90:cb3d968589d8 10794 #define RNG_CR_GO_MASK 0x1u
Kojto 90:cb3d968589d8 10795 #define RNG_CR_GO_SHIFT 0
Kojto 90:cb3d968589d8 10796 #define RNG_CR_HA_MASK 0x2u
Kojto 90:cb3d968589d8 10797 #define RNG_CR_HA_SHIFT 1
Kojto 90:cb3d968589d8 10798 #define RNG_CR_INTM_MASK 0x4u
Kojto 90:cb3d968589d8 10799 #define RNG_CR_INTM_SHIFT 2
Kojto 90:cb3d968589d8 10800 #define RNG_CR_CLRI_MASK 0x8u
Kojto 90:cb3d968589d8 10801 #define RNG_CR_CLRI_SHIFT 3
Kojto 90:cb3d968589d8 10802 #define RNG_CR_SLP_MASK 0x10u
Kojto 90:cb3d968589d8 10803 #define RNG_CR_SLP_SHIFT 4
Kojto 90:cb3d968589d8 10804 /* SR Bit Fields */
Kojto 90:cb3d968589d8 10805 #define RNG_SR_SECV_MASK 0x1u
Kojto 90:cb3d968589d8 10806 #define RNG_SR_SECV_SHIFT 0
Kojto 90:cb3d968589d8 10807 #define RNG_SR_LRS_MASK 0x2u
Kojto 90:cb3d968589d8 10808 #define RNG_SR_LRS_SHIFT 1
Kojto 90:cb3d968589d8 10809 #define RNG_SR_ORU_MASK 0x4u
Kojto 90:cb3d968589d8 10810 #define RNG_SR_ORU_SHIFT 2
Kojto 90:cb3d968589d8 10811 #define RNG_SR_ERRI_MASK 0x8u
Kojto 90:cb3d968589d8 10812 #define RNG_SR_ERRI_SHIFT 3
Kojto 90:cb3d968589d8 10813 #define RNG_SR_SLP_MASK 0x10u
Kojto 90:cb3d968589d8 10814 #define RNG_SR_SLP_SHIFT 4
Kojto 90:cb3d968589d8 10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u
Kojto 90:cb3d968589d8 10816 #define RNG_SR_OREG_LVL_SHIFT 8
Kojto 90:cb3d968589d8 10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
Kojto 90:cb3d968589d8 10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
Kojto 90:cb3d968589d8 10819 #define RNG_SR_OREG_SIZE_SHIFT 16
Kojto 90:cb3d968589d8 10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
Kojto 90:cb3d968589d8 10821 /* ER Bit Fields */
Kojto 90:cb3d968589d8 10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10823 #define RNG_ER_EXT_ENT_SHIFT 0
Kojto 90:cb3d968589d8 10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
Kojto 90:cb3d968589d8 10825 /* OR Bit Fields */
Kojto 90:cb3d968589d8 10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10827 #define RNG_OR_RANDOUT_SHIFT 0
Kojto 90:cb3d968589d8 10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
Kojto 90:cb3d968589d8 10829
Kojto 90:cb3d968589d8 10830 /*!
Kojto 90:cb3d968589d8 10831 * @}
Kojto 90:cb3d968589d8 10832 */ /* end of group RNG_Register_Masks */
Kojto 90:cb3d968589d8 10833
Kojto 90:cb3d968589d8 10834
Kojto 90:cb3d968589d8 10835 /* RNG - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 10836 /** Peripheral RNG base address */
Kojto 90:cb3d968589d8 10837 #define RNG_BASE (0x40029000u)
Kojto 90:cb3d968589d8 10838 /** Peripheral RNG base pointer */
Kojto 90:cb3d968589d8 10839 #define RNG ((RNG_Type *)RNG_BASE)
Kojto 90:cb3d968589d8 10840 #define RNG_BASE_PTR (RNG)
Kojto 90:cb3d968589d8 10841 /** Array initializer of RNG peripheral base addresses */
Kojto 90:cb3d968589d8 10842 #define RNG_BASE_ADDRS { RNG_BASE }
Kojto 90:cb3d968589d8 10843 /** Array initializer of RNG peripheral base pointers */
Kojto 90:cb3d968589d8 10844 #define RNG_BASE_PTRS { RNG }
Kojto 90:cb3d968589d8 10845 /** Interrupt vectors for the RNG peripheral type */
Kojto 90:cb3d968589d8 10846 #define RNG_IRQS { RNG_IRQn }
Kojto 90:cb3d968589d8 10847
Kojto 90:cb3d968589d8 10848 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10849 -- RNG - Register accessor macros
Kojto 90:cb3d968589d8 10850 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10851
Kojto 90:cb3d968589d8 10852 /*!
Kojto 90:cb3d968589d8 10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
Kojto 90:cb3d968589d8 10854 * @{
Kojto 90:cb3d968589d8 10855 */
Kojto 90:cb3d968589d8 10856
Kojto 90:cb3d968589d8 10857
Kojto 90:cb3d968589d8 10858 /* RNG - Register instance definitions */
Kojto 90:cb3d968589d8 10859 /* RNG */
Kojto 90:cb3d968589d8 10860 #define RNG_CR RNG_CR_REG(RNG)
Kojto 90:cb3d968589d8 10861 #define RNG_SR RNG_SR_REG(RNG)
Kojto 90:cb3d968589d8 10862 #define RNG_ER RNG_ER_REG(RNG)
Kojto 90:cb3d968589d8 10863 #define RNG_OR RNG_OR_REG(RNG)
Kojto 90:cb3d968589d8 10864
Kojto 90:cb3d968589d8 10865 /*!
Kojto 90:cb3d968589d8 10866 * @}
Kojto 90:cb3d968589d8 10867 */ /* end of group RNG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10868
Kojto 90:cb3d968589d8 10869
Kojto 90:cb3d968589d8 10870 /*!
Kojto 90:cb3d968589d8 10871 * @}
Kojto 90:cb3d968589d8 10872 */ /* end of group RNG_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 10873
Kojto 90:cb3d968589d8 10874
Kojto 90:cb3d968589d8 10875 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10876 -- RTC Peripheral Access Layer
Kojto 90:cb3d968589d8 10877 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10878
Kojto 90:cb3d968589d8 10879 /*!
Kojto 90:cb3d968589d8 10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Kojto 90:cb3d968589d8 10881 * @{
Kojto 90:cb3d968589d8 10882 */
Kojto 90:cb3d968589d8 10883
Kojto 90:cb3d968589d8 10884 /** RTC - Register Layout Typedef */
Kojto 90:cb3d968589d8 10885 typedef struct {
Kojto 90:cb3d968589d8 10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
Kojto 90:cb3d968589d8 10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
Kojto 90:cb3d968589d8 10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
Kojto 90:cb3d968589d8 10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
Kojto 90:cb3d968589d8 10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
Kojto 90:cb3d968589d8 10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
Kojto 90:cb3d968589d8 10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
Kojto 90:cb3d968589d8 10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
Kojto 90:cb3d968589d8 10894 uint8_t RESERVED_0[2016];
Kojto 90:cb3d968589d8 10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
Kojto 90:cb3d968589d8 10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
Kojto 90:cb3d968589d8 10897 } RTC_Type, *RTC_MemMapPtr;
Kojto 90:cb3d968589d8 10898
Kojto 90:cb3d968589d8 10899 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10900 -- RTC - Register accessor macros
Kojto 90:cb3d968589d8 10901 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10902
Kojto 90:cb3d968589d8 10903 /*!
Kojto 90:cb3d968589d8 10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Kojto 90:cb3d968589d8 10905 * @{
Kojto 90:cb3d968589d8 10906 */
Kojto 90:cb3d968589d8 10907
Kojto 90:cb3d968589d8 10908
Kojto 90:cb3d968589d8 10909 /* RTC - Register accessors */
Kojto 90:cb3d968589d8 10910 #define RTC_TSR_REG(base) ((base)->TSR)
Kojto 90:cb3d968589d8 10911 #define RTC_TPR_REG(base) ((base)->TPR)
Kojto 90:cb3d968589d8 10912 #define RTC_TAR_REG(base) ((base)->TAR)
Kojto 90:cb3d968589d8 10913 #define RTC_TCR_REG(base) ((base)->TCR)
Kojto 90:cb3d968589d8 10914 #define RTC_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 10915 #define RTC_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 10916 #define RTC_LR_REG(base) ((base)->LR)
Kojto 90:cb3d968589d8 10917 #define RTC_IER_REG(base) ((base)->IER)
Kojto 90:cb3d968589d8 10918 #define RTC_WAR_REG(base) ((base)->WAR)
Kojto 90:cb3d968589d8 10919 #define RTC_RAR_REG(base) ((base)->RAR)
Kojto 90:cb3d968589d8 10920
Kojto 90:cb3d968589d8 10921 /*!
Kojto 90:cb3d968589d8 10922 * @}
Kojto 90:cb3d968589d8 10923 */ /* end of group RTC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 10924
Kojto 90:cb3d968589d8 10925
Kojto 90:cb3d968589d8 10926 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 10927 -- RTC Register Masks
Kojto 90:cb3d968589d8 10928 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 10929
Kojto 90:cb3d968589d8 10930 /*!
Kojto 90:cb3d968589d8 10931 * @addtogroup RTC_Register_Masks RTC Register Masks
Kojto 90:cb3d968589d8 10932 * @{
Kojto 90:cb3d968589d8 10933 */
Kojto 90:cb3d968589d8 10934
Kojto 90:cb3d968589d8 10935 /* TSR Bit Fields */
Kojto 90:cb3d968589d8 10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10937 #define RTC_TSR_TSR_SHIFT 0
Kojto 90:cb3d968589d8 10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
Kojto 90:cb3d968589d8 10939 /* TPR Bit Fields */
Kojto 90:cb3d968589d8 10940 #define RTC_TPR_TPR_MASK 0xFFFFu
Kojto 90:cb3d968589d8 10941 #define RTC_TPR_TPR_SHIFT 0
Kojto 90:cb3d968589d8 10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
Kojto 90:cb3d968589d8 10943 /* TAR Bit Fields */
Kojto 90:cb3d968589d8 10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 10945 #define RTC_TAR_TAR_SHIFT 0
Kojto 90:cb3d968589d8 10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
Kojto 90:cb3d968589d8 10947 /* TCR Bit Fields */
Kojto 90:cb3d968589d8 10948 #define RTC_TCR_TCR_MASK 0xFFu
Kojto 90:cb3d968589d8 10949 #define RTC_TCR_TCR_SHIFT 0
Kojto 90:cb3d968589d8 10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
Kojto 90:cb3d968589d8 10951 #define RTC_TCR_CIR_MASK 0xFF00u
Kojto 90:cb3d968589d8 10952 #define RTC_TCR_CIR_SHIFT 8
Kojto 90:cb3d968589d8 10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
Kojto 90:cb3d968589d8 10954 #define RTC_TCR_TCV_MASK 0xFF0000u
Kojto 90:cb3d968589d8 10955 #define RTC_TCR_TCV_SHIFT 16
Kojto 90:cb3d968589d8 10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
Kojto 90:cb3d968589d8 10957 #define RTC_TCR_CIC_MASK 0xFF000000u
Kojto 90:cb3d968589d8 10958 #define RTC_TCR_CIC_SHIFT 24
Kojto 90:cb3d968589d8 10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
Kojto 90:cb3d968589d8 10960 /* CR Bit Fields */
Kojto 90:cb3d968589d8 10961 #define RTC_CR_SWR_MASK 0x1u
Kojto 90:cb3d968589d8 10962 #define RTC_CR_SWR_SHIFT 0
Kojto 90:cb3d968589d8 10963 #define RTC_CR_WPE_MASK 0x2u
Kojto 90:cb3d968589d8 10964 #define RTC_CR_WPE_SHIFT 1
Kojto 90:cb3d968589d8 10965 #define RTC_CR_SUP_MASK 0x4u
Kojto 90:cb3d968589d8 10966 #define RTC_CR_SUP_SHIFT 2
Kojto 90:cb3d968589d8 10967 #define RTC_CR_UM_MASK 0x8u
Kojto 90:cb3d968589d8 10968 #define RTC_CR_UM_SHIFT 3
Kojto 90:cb3d968589d8 10969 #define RTC_CR_WPS_MASK 0x10u
Kojto 90:cb3d968589d8 10970 #define RTC_CR_WPS_SHIFT 4
Kojto 90:cb3d968589d8 10971 #define RTC_CR_OSCE_MASK 0x100u
Kojto 90:cb3d968589d8 10972 #define RTC_CR_OSCE_SHIFT 8
Kojto 90:cb3d968589d8 10973 #define RTC_CR_CLKO_MASK 0x200u
Kojto 90:cb3d968589d8 10974 #define RTC_CR_CLKO_SHIFT 9
Kojto 90:cb3d968589d8 10975 #define RTC_CR_SC16P_MASK 0x400u
Kojto 90:cb3d968589d8 10976 #define RTC_CR_SC16P_SHIFT 10
Kojto 90:cb3d968589d8 10977 #define RTC_CR_SC8P_MASK 0x800u
Kojto 90:cb3d968589d8 10978 #define RTC_CR_SC8P_SHIFT 11
Kojto 90:cb3d968589d8 10979 #define RTC_CR_SC4P_MASK 0x1000u
Kojto 90:cb3d968589d8 10980 #define RTC_CR_SC4P_SHIFT 12
Kojto 90:cb3d968589d8 10981 #define RTC_CR_SC2P_MASK 0x2000u
Kojto 90:cb3d968589d8 10982 #define RTC_CR_SC2P_SHIFT 13
Kojto 90:cb3d968589d8 10983 /* SR Bit Fields */
Kojto 90:cb3d968589d8 10984 #define RTC_SR_TIF_MASK 0x1u
Kojto 90:cb3d968589d8 10985 #define RTC_SR_TIF_SHIFT 0
Kojto 90:cb3d968589d8 10986 #define RTC_SR_TOF_MASK 0x2u
Kojto 90:cb3d968589d8 10987 #define RTC_SR_TOF_SHIFT 1
Kojto 90:cb3d968589d8 10988 #define RTC_SR_TAF_MASK 0x4u
Kojto 90:cb3d968589d8 10989 #define RTC_SR_TAF_SHIFT 2
Kojto 90:cb3d968589d8 10990 #define RTC_SR_TCE_MASK 0x10u
Kojto 90:cb3d968589d8 10991 #define RTC_SR_TCE_SHIFT 4
Kojto 90:cb3d968589d8 10992 /* LR Bit Fields */
Kojto 90:cb3d968589d8 10993 #define RTC_LR_TCL_MASK 0x8u
Kojto 90:cb3d968589d8 10994 #define RTC_LR_TCL_SHIFT 3
Kojto 90:cb3d968589d8 10995 #define RTC_LR_CRL_MASK 0x10u
Kojto 90:cb3d968589d8 10996 #define RTC_LR_CRL_SHIFT 4
Kojto 90:cb3d968589d8 10997 #define RTC_LR_SRL_MASK 0x20u
Kojto 90:cb3d968589d8 10998 #define RTC_LR_SRL_SHIFT 5
Kojto 90:cb3d968589d8 10999 #define RTC_LR_LRL_MASK 0x40u
Kojto 90:cb3d968589d8 11000 #define RTC_LR_LRL_SHIFT 6
Kojto 90:cb3d968589d8 11001 /* IER Bit Fields */
Kojto 90:cb3d968589d8 11002 #define RTC_IER_TIIE_MASK 0x1u
Kojto 90:cb3d968589d8 11003 #define RTC_IER_TIIE_SHIFT 0
Kojto 90:cb3d968589d8 11004 #define RTC_IER_TOIE_MASK 0x2u
Kojto 90:cb3d968589d8 11005 #define RTC_IER_TOIE_SHIFT 1
Kojto 90:cb3d968589d8 11006 #define RTC_IER_TAIE_MASK 0x4u
Kojto 90:cb3d968589d8 11007 #define RTC_IER_TAIE_SHIFT 2
Kojto 90:cb3d968589d8 11008 #define RTC_IER_TSIE_MASK 0x10u
Kojto 90:cb3d968589d8 11009 #define RTC_IER_TSIE_SHIFT 4
Kojto 90:cb3d968589d8 11010 #define RTC_IER_WPON_MASK 0x80u
Kojto 90:cb3d968589d8 11011 #define RTC_IER_WPON_SHIFT 7
Kojto 90:cb3d968589d8 11012 /* WAR Bit Fields */
Kojto 90:cb3d968589d8 11013 #define RTC_WAR_TSRW_MASK 0x1u
Kojto 90:cb3d968589d8 11014 #define RTC_WAR_TSRW_SHIFT 0
Kojto 90:cb3d968589d8 11015 #define RTC_WAR_TPRW_MASK 0x2u
Kojto 90:cb3d968589d8 11016 #define RTC_WAR_TPRW_SHIFT 1
Kojto 90:cb3d968589d8 11017 #define RTC_WAR_TARW_MASK 0x4u
Kojto 90:cb3d968589d8 11018 #define RTC_WAR_TARW_SHIFT 2
Kojto 90:cb3d968589d8 11019 #define RTC_WAR_TCRW_MASK 0x8u
Kojto 90:cb3d968589d8 11020 #define RTC_WAR_TCRW_SHIFT 3
Kojto 90:cb3d968589d8 11021 #define RTC_WAR_CRW_MASK 0x10u
Kojto 90:cb3d968589d8 11022 #define RTC_WAR_CRW_SHIFT 4
Kojto 90:cb3d968589d8 11023 #define RTC_WAR_SRW_MASK 0x20u
Kojto 90:cb3d968589d8 11024 #define RTC_WAR_SRW_SHIFT 5
Kojto 90:cb3d968589d8 11025 #define RTC_WAR_LRW_MASK 0x40u
Kojto 90:cb3d968589d8 11026 #define RTC_WAR_LRW_SHIFT 6
Kojto 90:cb3d968589d8 11027 #define RTC_WAR_IERW_MASK 0x80u
Kojto 90:cb3d968589d8 11028 #define RTC_WAR_IERW_SHIFT 7
Kojto 90:cb3d968589d8 11029 /* RAR Bit Fields */
Kojto 90:cb3d968589d8 11030 #define RTC_RAR_TSRR_MASK 0x1u
Kojto 90:cb3d968589d8 11031 #define RTC_RAR_TSRR_SHIFT 0
Kojto 90:cb3d968589d8 11032 #define RTC_RAR_TPRR_MASK 0x2u
Kojto 90:cb3d968589d8 11033 #define RTC_RAR_TPRR_SHIFT 1
Kojto 90:cb3d968589d8 11034 #define RTC_RAR_TARR_MASK 0x4u
Kojto 90:cb3d968589d8 11035 #define RTC_RAR_TARR_SHIFT 2
Kojto 90:cb3d968589d8 11036 #define RTC_RAR_TCRR_MASK 0x8u
Kojto 90:cb3d968589d8 11037 #define RTC_RAR_TCRR_SHIFT 3
Kojto 90:cb3d968589d8 11038 #define RTC_RAR_CRR_MASK 0x10u
Kojto 90:cb3d968589d8 11039 #define RTC_RAR_CRR_SHIFT 4
Kojto 90:cb3d968589d8 11040 #define RTC_RAR_SRR_MASK 0x20u
Kojto 90:cb3d968589d8 11041 #define RTC_RAR_SRR_SHIFT 5
Kojto 90:cb3d968589d8 11042 #define RTC_RAR_LRR_MASK 0x40u
Kojto 90:cb3d968589d8 11043 #define RTC_RAR_LRR_SHIFT 6
Kojto 90:cb3d968589d8 11044 #define RTC_RAR_IERR_MASK 0x80u
Kojto 90:cb3d968589d8 11045 #define RTC_RAR_IERR_SHIFT 7
Kojto 90:cb3d968589d8 11046
Kojto 90:cb3d968589d8 11047 /*!
Kojto 90:cb3d968589d8 11048 * @}
Kojto 90:cb3d968589d8 11049 */ /* end of group RTC_Register_Masks */
Kojto 90:cb3d968589d8 11050
Kojto 90:cb3d968589d8 11051
Kojto 90:cb3d968589d8 11052 /* RTC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 11053 /** Peripheral RTC base address */
Kojto 90:cb3d968589d8 11054 #define RTC_BASE (0x4003D000u)
Kojto 90:cb3d968589d8 11055 /** Peripheral RTC base pointer */
Kojto 90:cb3d968589d8 11056 #define RTC ((RTC_Type *)RTC_BASE)
Kojto 90:cb3d968589d8 11057 #define RTC_BASE_PTR (RTC)
Kojto 90:cb3d968589d8 11058 /** Array initializer of RTC peripheral base addresses */
Kojto 90:cb3d968589d8 11059 #define RTC_BASE_ADDRS { RTC_BASE }
Kojto 90:cb3d968589d8 11060 /** Array initializer of RTC peripheral base pointers */
Kojto 90:cb3d968589d8 11061 #define RTC_BASE_PTRS { RTC }
Kojto 90:cb3d968589d8 11062 /** Interrupt vectors for the RTC peripheral type */
Kojto 90:cb3d968589d8 11063 #define RTC_IRQS { RTC_IRQn }
Kojto 90:cb3d968589d8 11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
Kojto 90:cb3d968589d8 11065
Kojto 90:cb3d968589d8 11066 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11067 -- RTC - Register accessor macros
Kojto 90:cb3d968589d8 11068 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11069
Kojto 90:cb3d968589d8 11070 /*!
Kojto 90:cb3d968589d8 11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Kojto 90:cb3d968589d8 11072 * @{
Kojto 90:cb3d968589d8 11073 */
Kojto 90:cb3d968589d8 11074
Kojto 90:cb3d968589d8 11075
Kojto 90:cb3d968589d8 11076 /* RTC - Register instance definitions */
Kojto 90:cb3d968589d8 11077 /* RTC */
Kojto 90:cb3d968589d8 11078 #define RTC_TSR RTC_TSR_REG(RTC)
Kojto 90:cb3d968589d8 11079 #define RTC_TPR RTC_TPR_REG(RTC)
Kojto 90:cb3d968589d8 11080 #define RTC_TAR RTC_TAR_REG(RTC)
Kojto 90:cb3d968589d8 11081 #define RTC_TCR RTC_TCR_REG(RTC)
Kojto 90:cb3d968589d8 11082 #define RTC_CR RTC_CR_REG(RTC)
Kojto 90:cb3d968589d8 11083 #define RTC_SR RTC_SR_REG(RTC)
Kojto 90:cb3d968589d8 11084 #define RTC_LR RTC_LR_REG(RTC)
Kojto 90:cb3d968589d8 11085 #define RTC_IER RTC_IER_REG(RTC)
Kojto 90:cb3d968589d8 11086 #define RTC_WAR RTC_WAR_REG(RTC)
Kojto 90:cb3d968589d8 11087 #define RTC_RAR RTC_RAR_REG(RTC)
Kojto 90:cb3d968589d8 11088
Kojto 90:cb3d968589d8 11089 /*!
Kojto 90:cb3d968589d8 11090 * @}
Kojto 90:cb3d968589d8 11091 */ /* end of group RTC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 11092
Kojto 90:cb3d968589d8 11093
Kojto 90:cb3d968589d8 11094 /*!
Kojto 90:cb3d968589d8 11095 * @}
Kojto 90:cb3d968589d8 11096 */ /* end of group RTC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 11097
Kojto 90:cb3d968589d8 11098
Kojto 90:cb3d968589d8 11099 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11100 -- SDHC Peripheral Access Layer
Kojto 90:cb3d968589d8 11101 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11102
Kojto 90:cb3d968589d8 11103 /*!
Kojto 90:cb3d968589d8 11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
Kojto 90:cb3d968589d8 11105 * @{
Kojto 90:cb3d968589d8 11106 */
Kojto 90:cb3d968589d8 11107
Kojto 90:cb3d968589d8 11108 /** SDHC - Register Layout Typedef */
Kojto 90:cb3d968589d8 11109 typedef struct {
Kojto 90:cb3d968589d8 11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
Kojto 90:cb3d968589d8 11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
Kojto 90:cb3d968589d8 11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
Kojto 90:cb3d968589d8 11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
Kojto 90:cb3d968589d8 11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
Kojto 90:cb3d968589d8 11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
Kojto 90:cb3d968589d8 11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
Kojto 90:cb3d968589d8 11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
Kojto 90:cb3d968589d8 11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
Kojto 90:cb3d968589d8 11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
Kojto 90:cb3d968589d8 11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
Kojto 90:cb3d968589d8 11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
Kojto 90:cb3d968589d8 11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
Kojto 90:cb3d968589d8 11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
Kojto 90:cb3d968589d8 11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
Kojto 90:cb3d968589d8 11125 uint8_t RESERVED_0[8];
Kojto 90:cb3d968589d8 11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
Kojto 90:cb3d968589d8 11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
Kojto 90:cb3d968589d8 11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
Kojto 90:cb3d968589d8 11129 uint8_t RESERVED_1[100];
Kojto 90:cb3d968589d8 11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
Kojto 90:cb3d968589d8 11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
Kojto 90:cb3d968589d8 11132 uint8_t RESERVED_2[52];
Kojto 90:cb3d968589d8 11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
Kojto 90:cb3d968589d8 11134 } SDHC_Type, *SDHC_MemMapPtr;
Kojto 90:cb3d968589d8 11135
Kojto 90:cb3d968589d8 11136 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11137 -- SDHC - Register accessor macros
Kojto 90:cb3d968589d8 11138 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11139
Kojto 90:cb3d968589d8 11140 /*!
Kojto 90:cb3d968589d8 11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
Kojto 90:cb3d968589d8 11142 * @{
Kojto 90:cb3d968589d8 11143 */
Kojto 90:cb3d968589d8 11144
Kojto 90:cb3d968589d8 11145
Kojto 90:cb3d968589d8 11146 /* SDHC - Register accessors */
Kojto 90:cb3d968589d8 11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
Kojto 90:cb3d968589d8 11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
Kojto 90:cb3d968589d8 11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
Kojto 90:cb3d968589d8 11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
Kojto 90:cb3d968589d8 11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
Kojto 90:cb3d968589d8 11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
Kojto 90:cb3d968589d8 11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
Kojto 90:cb3d968589d8 11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
Kojto 90:cb3d968589d8 11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
Kojto 90:cb3d968589d8 11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
Kojto 90:cb3d968589d8 11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
Kojto 90:cb3d968589d8 11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
Kojto 90:cb3d968589d8 11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
Kojto 90:cb3d968589d8 11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
Kojto 90:cb3d968589d8 11161 #define SDHC_WML_REG(base) ((base)->WML)
Kojto 90:cb3d968589d8 11162 #define SDHC_FEVT_REG(base) ((base)->FEVT)
Kojto 90:cb3d968589d8 11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
Kojto 90:cb3d968589d8 11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
Kojto 90:cb3d968589d8 11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
Kojto 90:cb3d968589d8 11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
Kojto 90:cb3d968589d8 11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
Kojto 90:cb3d968589d8 11168
Kojto 90:cb3d968589d8 11169 /*!
Kojto 90:cb3d968589d8 11170 * @}
Kojto 90:cb3d968589d8 11171 */ /* end of group SDHC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 11172
Kojto 90:cb3d968589d8 11173
Kojto 90:cb3d968589d8 11174 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11175 -- SDHC Register Masks
Kojto 90:cb3d968589d8 11176 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11177
Kojto 90:cb3d968589d8 11178 /*!
Kojto 90:cb3d968589d8 11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks
Kojto 90:cb3d968589d8 11180 * @{
Kojto 90:cb3d968589d8 11181 */
Kojto 90:cb3d968589d8 11182
Kojto 90:cb3d968589d8 11183 /* DSADDR Bit Fields */
Kojto 90:cb3d968589d8 11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
Kojto 90:cb3d968589d8 11185 #define SDHC_DSADDR_DSADDR_SHIFT 2
Kojto 90:cb3d968589d8 11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
Kojto 90:cb3d968589d8 11187 /* BLKATTR Bit Fields */
Kojto 90:cb3d968589d8 11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
Kojto 90:cb3d968589d8 11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
Kojto 90:cb3d968589d8 11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
Kojto 90:cb3d968589d8 11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
Kojto 90:cb3d968589d8 11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
Kojto 90:cb3d968589d8 11194 /* CMDARG Bit Fields */
Kojto 90:cb3d968589d8 11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11196 #define SDHC_CMDARG_CMDARG_SHIFT 0
Kojto 90:cb3d968589d8 11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
Kojto 90:cb3d968589d8 11198 /* XFERTYP Bit Fields */
Kojto 90:cb3d968589d8 11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
Kojto 90:cb3d968589d8 11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0
Kojto 90:cb3d968589d8 11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u
Kojto 90:cb3d968589d8 11202 #define SDHC_XFERTYP_BCEN_SHIFT 1
Kojto 90:cb3d968589d8 11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
Kojto 90:cb3d968589d8 11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2
Kojto 90:cb3d968589d8 11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
Kojto 90:cb3d968589d8 11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
Kojto 90:cb3d968589d8 11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
Kojto 90:cb3d968589d8 11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
Kojto 90:cb3d968589d8 11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
Kojto 90:cb3d968589d8 11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
Kojto 90:cb3d968589d8 11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
Kojto 90:cb3d968589d8 11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
Kojto 90:cb3d968589d8 11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19
Kojto 90:cb3d968589d8 11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
Kojto 90:cb3d968589d8 11215 #define SDHC_XFERTYP_CICEN_SHIFT 20
Kojto 90:cb3d968589d8 11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
Kojto 90:cb3d968589d8 11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21
Kojto 90:cb3d968589d8 11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
Kojto 90:cb3d968589d8 11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
Kojto 90:cb3d968589d8 11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
Kojto 90:cb3d968589d8 11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
Kojto 90:cb3d968589d8 11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24
Kojto 90:cb3d968589d8 11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
Kojto 90:cb3d968589d8 11224 /* CMDRSP Bit Fields */
Kojto 90:cb3d968589d8 11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
Kojto 90:cb3d968589d8 11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
Kojto 90:cb3d968589d8 11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
Kojto 90:cb3d968589d8 11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
Kojto 90:cb3d968589d8 11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
Kojto 90:cb3d968589d8 11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
Kojto 90:cb3d968589d8 11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
Kojto 90:cb3d968589d8 11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
Kojto 90:cb3d968589d8 11237 /* DATPORT Bit Fields */
Kojto 90:cb3d968589d8 11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11239 #define SDHC_DATPORT_DATCONT_SHIFT 0
Kojto 90:cb3d968589d8 11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
Kojto 90:cb3d968589d8 11241 /* PRSSTAT Bit Fields */
Kojto 90:cb3d968589d8 11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
Kojto 90:cb3d968589d8 11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0
Kojto 90:cb3d968589d8 11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
Kojto 90:cb3d968589d8 11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
Kojto 90:cb3d968589d8 11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u
Kojto 90:cb3d968589d8 11247 #define SDHC_PRSSTAT_DLA_SHIFT 2
Kojto 90:cb3d968589d8 11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
Kojto 90:cb3d968589d8 11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
Kojto 90:cb3d968589d8 11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
Kojto 90:cb3d968589d8 11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
Kojto 90:cb3d968589d8 11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
Kojto 90:cb3d968589d8 11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
Kojto 90:cb3d968589d8 11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
Kojto 90:cb3d968589d8 11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
Kojto 90:cb3d968589d8 11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
Kojto 90:cb3d968589d8 11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
Kojto 90:cb3d968589d8 11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u
Kojto 90:cb3d968589d8 11259 #define SDHC_PRSSTAT_WTA_SHIFT 8
Kojto 90:cb3d968589d8 11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u
Kojto 90:cb3d968589d8 11261 #define SDHC_PRSSTAT_RTA_SHIFT 9
Kojto 90:cb3d968589d8 11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
Kojto 90:cb3d968589d8 11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10
Kojto 90:cb3d968589d8 11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u
Kojto 90:cb3d968589d8 11265 #define SDHC_PRSSTAT_BREN_SHIFT 11
Kojto 90:cb3d968589d8 11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
Kojto 90:cb3d968589d8 11267 #define SDHC_PRSSTAT_CINS_SHIFT 16
Kojto 90:cb3d968589d8 11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
Kojto 90:cb3d968589d8 11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23
Kojto 90:cb3d968589d8 11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
Kojto 90:cb3d968589d8 11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24
Kojto 90:cb3d968589d8 11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
Kojto 90:cb3d968589d8 11273 /* PROCTL Bit Fields */
Kojto 90:cb3d968589d8 11274 #define SDHC_PROCTL_LCTL_MASK 0x1u
Kojto 90:cb3d968589d8 11275 #define SDHC_PROCTL_LCTL_SHIFT 0
Kojto 90:cb3d968589d8 11276 #define SDHC_PROCTL_DTW_MASK 0x6u
Kojto 90:cb3d968589d8 11277 #define SDHC_PROCTL_DTW_SHIFT 1
Kojto 90:cb3d968589d8 11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
Kojto 90:cb3d968589d8 11279 #define SDHC_PROCTL_D3CD_MASK 0x8u
Kojto 90:cb3d968589d8 11280 #define SDHC_PROCTL_D3CD_SHIFT 3
Kojto 90:cb3d968589d8 11281 #define SDHC_PROCTL_EMODE_MASK 0x30u
Kojto 90:cb3d968589d8 11282 #define SDHC_PROCTL_EMODE_SHIFT 4
Kojto 90:cb3d968589d8 11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
Kojto 90:cb3d968589d8 11284 #define SDHC_PROCTL_CDTL_MASK 0x40u
Kojto 90:cb3d968589d8 11285 #define SDHC_PROCTL_CDTL_SHIFT 6
Kojto 90:cb3d968589d8 11286 #define SDHC_PROCTL_CDSS_MASK 0x80u
Kojto 90:cb3d968589d8 11287 #define SDHC_PROCTL_CDSS_SHIFT 7
Kojto 90:cb3d968589d8 11288 #define SDHC_PROCTL_DMAS_MASK 0x300u
Kojto 90:cb3d968589d8 11289 #define SDHC_PROCTL_DMAS_SHIFT 8
Kojto 90:cb3d968589d8 11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
Kojto 90:cb3d968589d8 11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
Kojto 90:cb3d968589d8 11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16
Kojto 90:cb3d968589d8 11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u
Kojto 90:cb3d968589d8 11294 #define SDHC_PROCTL_CREQ_SHIFT 17
Kojto 90:cb3d968589d8 11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
Kojto 90:cb3d968589d8 11296 #define SDHC_PROCTL_RWCTL_SHIFT 18
Kojto 90:cb3d968589d8 11297 #define SDHC_PROCTL_IABG_MASK 0x80000u
Kojto 90:cb3d968589d8 11298 #define SDHC_PROCTL_IABG_SHIFT 19
Kojto 90:cb3d968589d8 11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
Kojto 90:cb3d968589d8 11300 #define SDHC_PROCTL_WECINT_SHIFT 24
Kojto 90:cb3d968589d8 11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
Kojto 90:cb3d968589d8 11302 #define SDHC_PROCTL_WECINS_SHIFT 25
Kojto 90:cb3d968589d8 11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
Kojto 90:cb3d968589d8 11304 #define SDHC_PROCTL_WECRM_SHIFT 26
Kojto 90:cb3d968589d8 11305 /* SYSCTL Bit Fields */
Kojto 90:cb3d968589d8 11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
Kojto 90:cb3d968589d8 11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0
Kojto 90:cb3d968589d8 11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
Kojto 90:cb3d968589d8 11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1
Kojto 90:cb3d968589d8 11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u
Kojto 90:cb3d968589d8 11311 #define SDHC_SYSCTL_PEREN_SHIFT 2
Kojto 90:cb3d968589d8 11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
Kojto 90:cb3d968589d8 11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
Kojto 90:cb3d968589d8 11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u
Kojto 90:cb3d968589d8 11315 #define SDHC_SYSCTL_DVS_SHIFT 4
Kojto 90:cb3d968589d8 11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
Kojto 90:cb3d968589d8 11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
Kojto 90:cb3d968589d8 11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
Kojto 90:cb3d968589d8 11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
Kojto 90:cb3d968589d8 11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
Kojto 90:cb3d968589d8 11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16
Kojto 90:cb3d968589d8 11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
Kojto 90:cb3d968589d8 11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
Kojto 90:cb3d968589d8 11324 #define SDHC_SYSCTL_RSTA_SHIFT 24
Kojto 90:cb3d968589d8 11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
Kojto 90:cb3d968589d8 11326 #define SDHC_SYSCTL_RSTC_SHIFT 25
Kojto 90:cb3d968589d8 11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
Kojto 90:cb3d968589d8 11328 #define SDHC_SYSCTL_RSTD_SHIFT 26
Kojto 90:cb3d968589d8 11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
Kojto 90:cb3d968589d8 11330 #define SDHC_SYSCTL_INITA_SHIFT 27
Kojto 90:cb3d968589d8 11331 /* IRQSTAT Bit Fields */
Kojto 90:cb3d968589d8 11332 #define SDHC_IRQSTAT_CC_MASK 0x1u
Kojto 90:cb3d968589d8 11333 #define SDHC_IRQSTAT_CC_SHIFT 0
Kojto 90:cb3d968589d8 11334 #define SDHC_IRQSTAT_TC_MASK 0x2u
Kojto 90:cb3d968589d8 11335 #define SDHC_IRQSTAT_TC_SHIFT 1
Kojto 90:cb3d968589d8 11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u
Kojto 90:cb3d968589d8 11337 #define SDHC_IRQSTAT_BGE_SHIFT 2
Kojto 90:cb3d968589d8 11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u
Kojto 90:cb3d968589d8 11339 #define SDHC_IRQSTAT_DINT_SHIFT 3
Kojto 90:cb3d968589d8 11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u
Kojto 90:cb3d968589d8 11341 #define SDHC_IRQSTAT_BWR_SHIFT 4
Kojto 90:cb3d968589d8 11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u
Kojto 90:cb3d968589d8 11343 #define SDHC_IRQSTAT_BRR_SHIFT 5
Kojto 90:cb3d968589d8 11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u
Kojto 90:cb3d968589d8 11345 #define SDHC_IRQSTAT_CINS_SHIFT 6
Kojto 90:cb3d968589d8 11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u
Kojto 90:cb3d968589d8 11347 #define SDHC_IRQSTAT_CRM_SHIFT 7
Kojto 90:cb3d968589d8 11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u
Kojto 90:cb3d968589d8 11349 #define SDHC_IRQSTAT_CINT_SHIFT 8
Kojto 90:cb3d968589d8 11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
Kojto 90:cb3d968589d8 11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16
Kojto 90:cb3d968589d8 11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
Kojto 90:cb3d968589d8 11353 #define SDHC_IRQSTAT_CCE_SHIFT 17
Kojto 90:cb3d968589d8 11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
Kojto 90:cb3d968589d8 11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18
Kojto 90:cb3d968589d8 11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
Kojto 90:cb3d968589d8 11357 #define SDHC_IRQSTAT_CIE_SHIFT 19
Kojto 90:cb3d968589d8 11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
Kojto 90:cb3d968589d8 11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20
Kojto 90:cb3d968589d8 11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
Kojto 90:cb3d968589d8 11361 #define SDHC_IRQSTAT_DCE_SHIFT 21
Kojto 90:cb3d968589d8 11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
Kojto 90:cb3d968589d8 11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22
Kojto 90:cb3d968589d8 11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
Kojto 90:cb3d968589d8 11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24
Kojto 90:cb3d968589d8 11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
Kojto 90:cb3d968589d8 11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28
Kojto 90:cb3d968589d8 11368 /* IRQSTATEN Bit Fields */
Kojto 90:cb3d968589d8 11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
Kojto 90:cb3d968589d8 11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
Kojto 90:cb3d968589d8 11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
Kojto 90:cb3d968589d8 11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
Kojto 90:cb3d968589d8 11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
Kojto 90:cb3d968589d8 11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
Kojto 90:cb3d968589d8 11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
Kojto 90:cb3d968589d8 11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
Kojto 90:cb3d968589d8 11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
Kojto 90:cb3d968589d8 11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
Kojto 90:cb3d968589d8 11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
Kojto 90:cb3d968589d8 11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
Kojto 90:cb3d968589d8 11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
Kojto 90:cb3d968589d8 11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
Kojto 90:cb3d968589d8 11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
Kojto 90:cb3d968589d8 11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
Kojto 90:cb3d968589d8 11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
Kojto 90:cb3d968589d8 11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
Kojto 90:cb3d968589d8 11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
Kojto 90:cb3d968589d8 11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
Kojto 90:cb3d968589d8 11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
Kojto 90:cb3d968589d8 11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
Kojto 90:cb3d968589d8 11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
Kojto 90:cb3d968589d8 11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
Kojto 90:cb3d968589d8 11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
Kojto 90:cb3d968589d8 11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
Kojto 90:cb3d968589d8 11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
Kojto 90:cb3d968589d8 11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
Kojto 90:cb3d968589d8 11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
Kojto 90:cb3d968589d8 11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
Kojto 90:cb3d968589d8 11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
Kojto 90:cb3d968589d8 11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
Kojto 90:cb3d968589d8 11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
Kojto 90:cb3d968589d8 11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
Kojto 90:cb3d968589d8 11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
Kojto 90:cb3d968589d8 11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
Kojto 90:cb3d968589d8 11405 /* IRQSIGEN Bit Fields */
Kojto 90:cb3d968589d8 11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
Kojto 90:cb3d968589d8 11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
Kojto 90:cb3d968589d8 11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
Kojto 90:cb3d968589d8 11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
Kojto 90:cb3d968589d8 11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
Kojto 90:cb3d968589d8 11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
Kojto 90:cb3d968589d8 11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
Kojto 90:cb3d968589d8 11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
Kojto 90:cb3d968589d8 11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
Kojto 90:cb3d968589d8 11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
Kojto 90:cb3d968589d8 11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
Kojto 90:cb3d968589d8 11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
Kojto 90:cb3d968589d8 11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
Kojto 90:cb3d968589d8 11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
Kojto 90:cb3d968589d8 11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
Kojto 90:cb3d968589d8 11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
Kojto 90:cb3d968589d8 11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
Kojto 90:cb3d968589d8 11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
Kojto 90:cb3d968589d8 11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
Kojto 90:cb3d968589d8 11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
Kojto 90:cb3d968589d8 11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
Kojto 90:cb3d968589d8 11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
Kojto 90:cb3d968589d8 11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
Kojto 90:cb3d968589d8 11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
Kojto 90:cb3d968589d8 11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
Kojto 90:cb3d968589d8 11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
Kojto 90:cb3d968589d8 11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
Kojto 90:cb3d968589d8 11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
Kojto 90:cb3d968589d8 11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
Kojto 90:cb3d968589d8 11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
Kojto 90:cb3d968589d8 11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
Kojto 90:cb3d968589d8 11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
Kojto 90:cb3d968589d8 11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
Kojto 90:cb3d968589d8 11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
Kojto 90:cb3d968589d8 11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
Kojto 90:cb3d968589d8 11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
Kojto 90:cb3d968589d8 11442 /* AC12ERR Bit Fields */
Kojto 90:cb3d968589d8 11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
Kojto 90:cb3d968589d8 11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0
Kojto 90:cb3d968589d8 11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
Kojto 90:cb3d968589d8 11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
Kojto 90:cb3d968589d8 11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
Kojto 90:cb3d968589d8 11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
Kojto 90:cb3d968589d8 11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
Kojto 90:cb3d968589d8 11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3
Kojto 90:cb3d968589d8 11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
Kojto 90:cb3d968589d8 11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4
Kojto 90:cb3d968589d8 11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
Kojto 90:cb3d968589d8 11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
Kojto 90:cb3d968589d8 11455 /* HTCAPBLT Bit Fields */
Kojto 90:cb3d968589d8 11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
Kojto 90:cb3d968589d8 11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16
Kojto 90:cb3d968589d8 11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
Kojto 90:cb3d968589d8 11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
Kojto 90:cb3d968589d8 11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
Kojto 90:cb3d968589d8 11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
Kojto 90:cb3d968589d8 11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21
Kojto 90:cb3d968589d8 11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
Kojto 90:cb3d968589d8 11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
Kojto 90:cb3d968589d8 11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
Kojto 90:cb3d968589d8 11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23
Kojto 90:cb3d968589d8 11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
Kojto 90:cb3d968589d8 11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24
Kojto 90:cb3d968589d8 11469 /* WML Bit Fields */
Kojto 90:cb3d968589d8 11470 #define SDHC_WML_RDWML_MASK 0xFFu
Kojto 90:cb3d968589d8 11471 #define SDHC_WML_RDWML_SHIFT 0
Kojto 90:cb3d968589d8 11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
Kojto 90:cb3d968589d8 11473 #define SDHC_WML_WRWML_MASK 0xFF0000u
Kojto 90:cb3d968589d8 11474 #define SDHC_WML_WRWML_SHIFT 16
Kojto 90:cb3d968589d8 11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
Kojto 90:cb3d968589d8 11476 /* FEVT Bit Fields */
Kojto 90:cb3d968589d8 11477 #define SDHC_FEVT_AC12NE_MASK 0x1u
Kojto 90:cb3d968589d8 11478 #define SDHC_FEVT_AC12NE_SHIFT 0
Kojto 90:cb3d968589d8 11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u
Kojto 90:cb3d968589d8 11480 #define SDHC_FEVT_AC12TOE_SHIFT 1
Kojto 90:cb3d968589d8 11481 #define SDHC_FEVT_AC12CE_MASK 0x4u
Kojto 90:cb3d968589d8 11482 #define SDHC_FEVT_AC12CE_SHIFT 2
Kojto 90:cb3d968589d8 11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u
Kojto 90:cb3d968589d8 11484 #define SDHC_FEVT_AC12EBE_SHIFT 3
Kojto 90:cb3d968589d8 11485 #define SDHC_FEVT_AC12IE_MASK 0x10u
Kojto 90:cb3d968589d8 11486 #define SDHC_FEVT_AC12IE_SHIFT 4
Kojto 90:cb3d968589d8 11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
Kojto 90:cb3d968589d8 11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
Kojto 90:cb3d968589d8 11489 #define SDHC_FEVT_CTOE_MASK 0x10000u
Kojto 90:cb3d968589d8 11490 #define SDHC_FEVT_CTOE_SHIFT 16
Kojto 90:cb3d968589d8 11491 #define SDHC_FEVT_CCE_MASK 0x20000u
Kojto 90:cb3d968589d8 11492 #define SDHC_FEVT_CCE_SHIFT 17
Kojto 90:cb3d968589d8 11493 #define SDHC_FEVT_CEBE_MASK 0x40000u
Kojto 90:cb3d968589d8 11494 #define SDHC_FEVT_CEBE_SHIFT 18
Kojto 90:cb3d968589d8 11495 #define SDHC_FEVT_CIE_MASK 0x80000u
Kojto 90:cb3d968589d8 11496 #define SDHC_FEVT_CIE_SHIFT 19
Kojto 90:cb3d968589d8 11497 #define SDHC_FEVT_DTOE_MASK 0x100000u
Kojto 90:cb3d968589d8 11498 #define SDHC_FEVT_DTOE_SHIFT 20
Kojto 90:cb3d968589d8 11499 #define SDHC_FEVT_DCE_MASK 0x200000u
Kojto 90:cb3d968589d8 11500 #define SDHC_FEVT_DCE_SHIFT 21
Kojto 90:cb3d968589d8 11501 #define SDHC_FEVT_DEBE_MASK 0x400000u
Kojto 90:cb3d968589d8 11502 #define SDHC_FEVT_DEBE_SHIFT 22
Kojto 90:cb3d968589d8 11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u
Kojto 90:cb3d968589d8 11504 #define SDHC_FEVT_AC12E_SHIFT 24
Kojto 90:cb3d968589d8 11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u
Kojto 90:cb3d968589d8 11506 #define SDHC_FEVT_DMAE_SHIFT 28
Kojto 90:cb3d968589d8 11507 #define SDHC_FEVT_CINT_MASK 0x80000000u
Kojto 90:cb3d968589d8 11508 #define SDHC_FEVT_CINT_SHIFT 31
Kojto 90:cb3d968589d8 11509 /* ADMAES Bit Fields */
Kojto 90:cb3d968589d8 11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u
Kojto 90:cb3d968589d8 11511 #define SDHC_ADMAES_ADMAES_SHIFT 0
Kojto 90:cb3d968589d8 11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
Kojto 90:cb3d968589d8 11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u
Kojto 90:cb3d968589d8 11514 #define SDHC_ADMAES_ADMALME_SHIFT 2
Kojto 90:cb3d968589d8 11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
Kojto 90:cb3d968589d8 11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3
Kojto 90:cb3d968589d8 11517 /* ADSADDR Bit Fields */
Kojto 90:cb3d968589d8 11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
Kojto 90:cb3d968589d8 11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
Kojto 90:cb3d968589d8 11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
Kojto 90:cb3d968589d8 11521 /* VENDOR Bit Fields */
Kojto 90:cb3d968589d8 11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
Kojto 90:cb3d968589d8 11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
Kojto 90:cb3d968589d8 11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
Kojto 90:cb3d968589d8 11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
Kojto 90:cb3d968589d8 11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
Kojto 90:cb3d968589d8 11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
Kojto 90:cb3d968589d8 11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
Kojto 90:cb3d968589d8 11529 /* MMCBOOT Bit Fields */
Kojto 90:cb3d968589d8 11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
Kojto 90:cb3d968589d8 11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
Kojto 90:cb3d968589d8 11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
Kojto 90:cb3d968589d8 11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
Kojto 90:cb3d968589d8 11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
Kojto 90:cb3d968589d8 11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
Kojto 90:cb3d968589d8 11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
Kojto 90:cb3d968589d8 11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
Kojto 90:cb3d968589d8 11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
Kojto 90:cb3d968589d8 11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
Kojto 90:cb3d968589d8 11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
Kojto 90:cb3d968589d8 11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
Kojto 90:cb3d968589d8 11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
Kojto 90:cb3d968589d8 11544 /* HOSTVER Bit Fields */
Kojto 90:cb3d968589d8 11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu
Kojto 90:cb3d968589d8 11546 #define SDHC_HOSTVER_SVN_SHIFT 0
Kojto 90:cb3d968589d8 11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
Kojto 90:cb3d968589d8 11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
Kojto 90:cb3d968589d8 11549 #define SDHC_HOSTVER_VVN_SHIFT 8
Kojto 90:cb3d968589d8 11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
Kojto 90:cb3d968589d8 11551
Kojto 90:cb3d968589d8 11552 /*!
Kojto 90:cb3d968589d8 11553 * @}
Kojto 90:cb3d968589d8 11554 */ /* end of group SDHC_Register_Masks */
Kojto 90:cb3d968589d8 11555
Kojto 90:cb3d968589d8 11556
Kojto 90:cb3d968589d8 11557 /* SDHC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 11558 /** Peripheral SDHC base address */
Kojto 90:cb3d968589d8 11559 #define SDHC_BASE (0x400B1000u)
Kojto 90:cb3d968589d8 11560 /** Peripheral SDHC base pointer */
Kojto 90:cb3d968589d8 11561 #define SDHC ((SDHC_Type *)SDHC_BASE)
Kojto 90:cb3d968589d8 11562 #define SDHC_BASE_PTR (SDHC)
Kojto 90:cb3d968589d8 11563 /** Array initializer of SDHC peripheral base addresses */
Kojto 90:cb3d968589d8 11564 #define SDHC_BASE_ADDRS { SDHC_BASE }
Kojto 90:cb3d968589d8 11565 /** Array initializer of SDHC peripheral base pointers */
Kojto 90:cb3d968589d8 11566 #define SDHC_BASE_PTRS { SDHC }
Kojto 90:cb3d968589d8 11567 /** Interrupt vectors for the SDHC peripheral type */
Kojto 90:cb3d968589d8 11568 #define SDHC_IRQS { SDHC_IRQn }
Kojto 90:cb3d968589d8 11569
Kojto 90:cb3d968589d8 11570 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11571 -- SDHC - Register accessor macros
Kojto 90:cb3d968589d8 11572 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11573
Kojto 90:cb3d968589d8 11574 /*!
Kojto 90:cb3d968589d8 11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
Kojto 90:cb3d968589d8 11576 * @{
Kojto 90:cb3d968589d8 11577 */
Kojto 90:cb3d968589d8 11578
Kojto 90:cb3d968589d8 11579
Kojto 90:cb3d968589d8 11580 /* SDHC - Register instance definitions */
Kojto 90:cb3d968589d8 11581 /* SDHC */
Kojto 90:cb3d968589d8 11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
Kojto 90:cb3d968589d8 11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
Kojto 90:cb3d968589d8 11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
Kojto 90:cb3d968589d8 11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
Kojto 90:cb3d968589d8 11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
Kojto 90:cb3d968589d8 11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
Kojto 90:cb3d968589d8 11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
Kojto 90:cb3d968589d8 11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
Kojto 90:cb3d968589d8 11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
Kojto 90:cb3d968589d8 11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
Kojto 90:cb3d968589d8 11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
Kojto 90:cb3d968589d8 11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
Kojto 90:cb3d968589d8 11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
Kojto 90:cb3d968589d8 11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
Kojto 90:cb3d968589d8 11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
Kojto 90:cb3d968589d8 11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
Kojto 90:cb3d968589d8 11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
Kojto 90:cb3d968589d8 11599 #define SDHC_WML SDHC_WML_REG(SDHC)
Kojto 90:cb3d968589d8 11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
Kojto 90:cb3d968589d8 11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
Kojto 90:cb3d968589d8 11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
Kojto 90:cb3d968589d8 11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
Kojto 90:cb3d968589d8 11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
Kojto 90:cb3d968589d8 11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
Kojto 90:cb3d968589d8 11606
Kojto 90:cb3d968589d8 11607 /* SDHC - Register array accessors */
Kojto 90:cb3d968589d8 11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
Kojto 90:cb3d968589d8 11609
Kojto 90:cb3d968589d8 11610 /*!
Kojto 90:cb3d968589d8 11611 * @}
Kojto 90:cb3d968589d8 11612 */ /* end of group SDHC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 11613
Kojto 90:cb3d968589d8 11614
Kojto 90:cb3d968589d8 11615 /*!
Kojto 90:cb3d968589d8 11616 * @}
Kojto 90:cb3d968589d8 11617 */ /* end of group SDHC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 11618
Kojto 90:cb3d968589d8 11619
Kojto 90:cb3d968589d8 11620 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11621 -- SIM Peripheral Access Layer
Kojto 90:cb3d968589d8 11622 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11623
Kojto 90:cb3d968589d8 11624 /*!
Kojto 90:cb3d968589d8 11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Kojto 90:cb3d968589d8 11626 * @{
Kojto 90:cb3d968589d8 11627 */
Kojto 90:cb3d968589d8 11628
Kojto 90:cb3d968589d8 11629 /** SIM - Register Layout Typedef */
Kojto 90:cb3d968589d8 11630 typedef struct {
Kojto 90:cb3d968589d8 11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
Kojto 90:cb3d968589d8 11633 uint8_t RESERVED_0[4092];
Kojto 90:cb3d968589d8 11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
Kojto 90:cb3d968589d8 11635 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
Kojto 90:cb3d968589d8 11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
Kojto 90:cb3d968589d8 11638 uint8_t RESERVED_2[4];
Kojto 90:cb3d968589d8 11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
Kojto 90:cb3d968589d8 11640 uint8_t RESERVED_3[8];
Kojto 90:cb3d968589d8 11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
Kojto 90:cb3d968589d8 11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
Kojto 90:cb3d968589d8 11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
Kojto 90:cb3d968589d8 11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
Kojto 90:cb3d968589d8 11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
Kojto 90:cb3d968589d8 11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
Kojto 90:cb3d968589d8 11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
Kojto 90:cb3d968589d8 11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
Kojto 90:cb3d968589d8 11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
Kojto 90:cb3d968589d8 11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
Kojto 90:cb3d968589d8 11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
Kojto 90:cb3d968589d8 11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
Kojto 90:cb3d968589d8 11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
Kojto 90:cb3d968589d8 11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
Kojto 90:cb3d968589d8 11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
Kojto 90:cb3d968589d8 11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
Kojto 90:cb3d968589d8 11657 } SIM_Type, *SIM_MemMapPtr;
Kojto 90:cb3d968589d8 11658
Kojto 90:cb3d968589d8 11659 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11660 -- SIM - Register accessor macros
Kojto 90:cb3d968589d8 11661 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11662
Kojto 90:cb3d968589d8 11663 /*!
Kojto 90:cb3d968589d8 11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Kojto 90:cb3d968589d8 11665 * @{
Kojto 90:cb3d968589d8 11666 */
Kojto 90:cb3d968589d8 11667
Kojto 90:cb3d968589d8 11668
Kojto 90:cb3d968589d8 11669 /* SIM - Register accessors */
Kojto 90:cb3d968589d8 11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
Kojto 90:cb3d968589d8 11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
Kojto 90:cb3d968589d8 11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
Kojto 90:cb3d968589d8 11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
Kojto 90:cb3d968589d8 11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
Kojto 90:cb3d968589d8 11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
Kojto 90:cb3d968589d8 11676 #define SIM_SDID_REG(base) ((base)->SDID)
Kojto 90:cb3d968589d8 11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
Kojto 90:cb3d968589d8 11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
Kojto 90:cb3d968589d8 11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
Kojto 90:cb3d968589d8 11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
Kojto 90:cb3d968589d8 11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
Kojto 90:cb3d968589d8 11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
Kojto 90:cb3d968589d8 11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
Kojto 90:cb3d968589d8 11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
Kojto 90:cb3d968589d8 11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
Kojto 90:cb3d968589d8 11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
Kojto 90:cb3d968589d8 11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
Kojto 90:cb3d968589d8 11688 #define SIM_UIDH_REG(base) ((base)->UIDH)
Kojto 90:cb3d968589d8 11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
Kojto 90:cb3d968589d8 11690 #define SIM_UIDML_REG(base) ((base)->UIDML)
Kojto 90:cb3d968589d8 11691 #define SIM_UIDL_REG(base) ((base)->UIDL)
Kojto 90:cb3d968589d8 11692
Kojto 90:cb3d968589d8 11693 /*!
Kojto 90:cb3d968589d8 11694 * @}
Kojto 90:cb3d968589d8 11695 */ /* end of group SIM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 11696
Kojto 90:cb3d968589d8 11697
Kojto 90:cb3d968589d8 11698 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 11699 -- SIM Register Masks
Kojto 90:cb3d968589d8 11700 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 11701
Kojto 90:cb3d968589d8 11702 /*!
Kojto 90:cb3d968589d8 11703 * @addtogroup SIM_Register_Masks SIM Register Masks
Kojto 90:cb3d968589d8 11704 * @{
Kojto 90:cb3d968589d8 11705 */
Kojto 90:cb3d968589d8 11706
Kojto 90:cb3d968589d8 11707 /* SOPT1 Bit Fields */
Kojto 90:cb3d968589d8 11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
Kojto 90:cb3d968589d8 11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12
Kojto 90:cb3d968589d8 11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
Kojto 90:cb3d968589d8 11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
Kojto 90:cb3d968589d8 11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
Kojto 90:cb3d968589d8 11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
Kojto 90:cb3d968589d8 11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
Kojto 90:cb3d968589d8 11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29
Kojto 90:cb3d968589d8 11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
Kojto 90:cb3d968589d8 11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30
Kojto 90:cb3d968589d8 11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
Kojto 90:cb3d968589d8 11719 #define SIM_SOPT1_USBREGEN_SHIFT 31
Kojto 90:cb3d968589d8 11720 /* SOPT1CFG Bit Fields */
Kojto 90:cb3d968589d8 11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
Kojto 90:cb3d968589d8 11722 #define SIM_SOPT1CFG_URWE_SHIFT 24
Kojto 90:cb3d968589d8 11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
Kojto 90:cb3d968589d8 11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
Kojto 90:cb3d968589d8 11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
Kojto 90:cb3d968589d8 11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26
Kojto 90:cb3d968589d8 11727 /* SOPT2 Bit Fields */
Kojto 90:cb3d968589d8 11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
Kojto 90:cb3d968589d8 11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
Kojto 90:cb3d968589d8 11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
Kojto 90:cb3d968589d8 11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
Kojto 90:cb3d968589d8 11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
Kojto 90:cb3d968589d8 11733 #define SIM_SOPT2_FBSL_MASK 0x300u
Kojto 90:cb3d968589d8 11734 #define SIM_SOPT2_FBSL_SHIFT 8
Kojto 90:cb3d968589d8 11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
Kojto 90:cb3d968589d8 11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
Kojto 90:cb3d968589d8 11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11
Kojto 90:cb3d968589d8 11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
Kojto 90:cb3d968589d8 11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
Kojto 90:cb3d968589d8 11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
Kojto 90:cb3d968589d8 11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
Kojto 90:cb3d968589d8 11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
Kojto 90:cb3d968589d8 11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u
Kojto 90:cb3d968589d8 11744 #define SIM_SOPT2_USBSRC_SHIFT 18
Kojto 90:cb3d968589d8 11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
Kojto 90:cb3d968589d8 11746 #define SIM_SOPT2_RMIISRC_SHIFT 19
Kojto 90:cb3d968589d8 11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
Kojto 90:cb3d968589d8 11748 #define SIM_SOPT2_TIMESRC_SHIFT 20
Kojto 90:cb3d968589d8 11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
Kojto 90:cb3d968589d8 11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
Kojto 90:cb3d968589d8 11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28
Kojto 90:cb3d968589d8 11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
Kojto 90:cb3d968589d8 11753 /* SOPT4 Bit Fields */
Kojto 90:cb3d968589d8 11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
Kojto 90:cb3d968589d8 11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
Kojto 90:cb3d968589d8 11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
Kojto 90:cb3d968589d8 11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
Kojto 90:cb3d968589d8 11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
Kojto 90:cb3d968589d8 11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
Kojto 90:cb3d968589d8 11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
Kojto 90:cb3d968589d8 11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
Kojto 90:cb3d968589d8 11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
Kojto 90:cb3d968589d8 11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
Kojto 90:cb3d968589d8 11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
Kojto 90:cb3d968589d8 11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
Kojto 90:cb3d968589d8 11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
Kojto 90:cb3d968589d8 11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
Kojto 90:cb3d968589d8 11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
Kojto 90:cb3d968589d8 11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
Kojto 90:cb3d968589d8 11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
Kojto 90:cb3d968589d8 11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
Kojto 90:cb3d968589d8 11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
Kojto 90:cb3d968589d8 11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
Kojto 90:cb3d968589d8 11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
Kojto 90:cb3d968589d8 11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
Kojto 90:cb3d968589d8 11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
Kojto 90:cb3d968589d8 11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
Kojto 90:cb3d968589d8 11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
Kojto 90:cb3d968589d8 11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
Kojto 90:cb3d968589d8 11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
Kojto 90:cb3d968589d8 11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
Kojto 90:cb3d968589d8 11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
Kojto 90:cb3d968589d8 11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
Kojto 90:cb3d968589d8 11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
Kojto 90:cb3d968589d8 11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
Kojto 90:cb3d968589d8 11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
Kojto 90:cb3d968589d8 11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
Kojto 90:cb3d968589d8 11788 /* SOPT5 Bit Fields */
Kojto 90:cb3d968589d8 11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
Kojto 90:cb3d968589d8 11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
Kojto 90:cb3d968589d8 11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
Kojto 90:cb3d968589d8 11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
Kojto 90:cb3d968589d8 11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
Kojto 90:cb3d968589d8 11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
Kojto 90:cb3d968589d8 11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
Kojto 90:cb3d968589d8 11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
Kojto 90:cb3d968589d8 11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
Kojto 90:cb3d968589d8 11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
Kojto 90:cb3d968589d8 11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
Kojto 90:cb3d968589d8 11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
Kojto 90:cb3d968589d8 11801 /* SOPT7 Bit Fields */
Kojto 90:cb3d968589d8 11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
Kojto 90:cb3d968589d8 11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
Kojto 90:cb3d968589d8 11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
Kojto 90:cb3d968589d8 11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
Kojto 90:cb3d968589d8 11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
Kojto 90:cb3d968589d8 11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
Kojto 90:cb3d968589d8 11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
Kojto 90:cb3d968589d8 11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
Kojto 90:cb3d968589d8 11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
Kojto 90:cb3d968589d8 11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
Kojto 90:cb3d968589d8 11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
Kojto 90:cb3d968589d8 11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
Kojto 90:cb3d968589d8 11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
Kojto 90:cb3d968589d8 11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
Kojto 90:cb3d968589d8 11816 /* SDID Bit Fields */
Kojto 90:cb3d968589d8 11817 #define SIM_SDID_PINID_MASK 0xFu
Kojto 90:cb3d968589d8 11818 #define SIM_SDID_PINID_SHIFT 0
Kojto 90:cb3d968589d8 11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
Kojto 90:cb3d968589d8 11820 #define SIM_SDID_FAMID_MASK 0x70u
Kojto 90:cb3d968589d8 11821 #define SIM_SDID_FAMID_SHIFT 4
Kojto 90:cb3d968589d8 11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
Kojto 90:cb3d968589d8 11823 #define SIM_SDID_DIEID_MASK 0xF80u
Kojto 90:cb3d968589d8 11824 #define SIM_SDID_DIEID_SHIFT 7
Kojto 90:cb3d968589d8 11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
Kojto 90:cb3d968589d8 11826 #define SIM_SDID_REVID_MASK 0xF000u
Kojto 90:cb3d968589d8 11827 #define SIM_SDID_REVID_SHIFT 12
Kojto 90:cb3d968589d8 11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
Kojto 90:cb3d968589d8 11829 #define SIM_SDID_SERIESID_MASK 0xF00000u
Kojto 90:cb3d968589d8 11830 #define SIM_SDID_SERIESID_SHIFT 20
Kojto 90:cb3d968589d8 11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
Kojto 90:cb3d968589d8 11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
Kojto 90:cb3d968589d8 11833 #define SIM_SDID_SUBFAMID_SHIFT 24
Kojto 90:cb3d968589d8 11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
Kojto 90:cb3d968589d8 11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
Kojto 90:cb3d968589d8 11836 #define SIM_SDID_FAMILYID_SHIFT 28
Kojto 90:cb3d968589d8 11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
Kojto 90:cb3d968589d8 11838 /* SCGC1 Bit Fields */
Kojto 90:cb3d968589d8 11839 #define SIM_SCGC1_I2C2_MASK 0x40u
Kojto 90:cb3d968589d8 11840 #define SIM_SCGC1_I2C2_SHIFT 6
Kojto 90:cb3d968589d8 11841 #define SIM_SCGC1_UART4_MASK 0x400u
Kojto 90:cb3d968589d8 11842 #define SIM_SCGC1_UART4_SHIFT 10
Kojto 90:cb3d968589d8 11843 #define SIM_SCGC1_UART5_MASK 0x800u
Kojto 90:cb3d968589d8 11844 #define SIM_SCGC1_UART5_SHIFT 11
Kojto 90:cb3d968589d8 11845 /* SCGC2 Bit Fields */
Kojto 90:cb3d968589d8 11846 #define SIM_SCGC2_ENET_MASK 0x1u
Kojto 90:cb3d968589d8 11847 #define SIM_SCGC2_ENET_SHIFT 0
Kojto 90:cb3d968589d8 11848 #define SIM_SCGC2_DAC0_MASK 0x1000u
Kojto 90:cb3d968589d8 11849 #define SIM_SCGC2_DAC0_SHIFT 12
Kojto 90:cb3d968589d8 11850 #define SIM_SCGC2_DAC1_MASK 0x2000u
Kojto 90:cb3d968589d8 11851 #define SIM_SCGC2_DAC1_SHIFT 13
Kojto 90:cb3d968589d8 11852 /* SCGC3 Bit Fields */
Kojto 90:cb3d968589d8 11853 #define SIM_SCGC3_RNGA_MASK 0x1u
Kojto 90:cb3d968589d8 11854 #define SIM_SCGC3_RNGA_SHIFT 0
Kojto 90:cb3d968589d8 11855 #define SIM_SCGC3_SPI2_MASK 0x1000u
Kojto 90:cb3d968589d8 11856 #define SIM_SCGC3_SPI2_SHIFT 12
Kojto 90:cb3d968589d8 11857 #define SIM_SCGC3_SDHC_MASK 0x20000u
Kojto 90:cb3d968589d8 11858 #define SIM_SCGC3_SDHC_SHIFT 17
Kojto 90:cb3d968589d8 11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u
Kojto 90:cb3d968589d8 11860 #define SIM_SCGC3_FTM2_SHIFT 24
Kojto 90:cb3d968589d8 11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u
Kojto 90:cb3d968589d8 11862 #define SIM_SCGC3_FTM3_SHIFT 25
Kojto 90:cb3d968589d8 11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u
Kojto 90:cb3d968589d8 11864 #define SIM_SCGC3_ADC1_SHIFT 27
Kojto 90:cb3d968589d8 11865 /* SCGC4 Bit Fields */
Kojto 90:cb3d968589d8 11866 #define SIM_SCGC4_EWM_MASK 0x2u
Kojto 90:cb3d968589d8 11867 #define SIM_SCGC4_EWM_SHIFT 1
Kojto 90:cb3d968589d8 11868 #define SIM_SCGC4_CMT_MASK 0x4u
Kojto 90:cb3d968589d8 11869 #define SIM_SCGC4_CMT_SHIFT 2
Kojto 90:cb3d968589d8 11870 #define SIM_SCGC4_I2C0_MASK 0x40u
Kojto 90:cb3d968589d8 11871 #define SIM_SCGC4_I2C0_SHIFT 6
Kojto 90:cb3d968589d8 11872 #define SIM_SCGC4_I2C1_MASK 0x80u
Kojto 90:cb3d968589d8 11873 #define SIM_SCGC4_I2C1_SHIFT 7
Kojto 90:cb3d968589d8 11874 #define SIM_SCGC4_UART0_MASK 0x400u
Kojto 90:cb3d968589d8 11875 #define SIM_SCGC4_UART0_SHIFT 10
Kojto 90:cb3d968589d8 11876 #define SIM_SCGC4_UART1_MASK 0x800u
Kojto 90:cb3d968589d8 11877 #define SIM_SCGC4_UART1_SHIFT 11
Kojto 90:cb3d968589d8 11878 #define SIM_SCGC4_UART2_MASK 0x1000u
Kojto 90:cb3d968589d8 11879 #define SIM_SCGC4_UART2_SHIFT 12
Kojto 90:cb3d968589d8 11880 #define SIM_SCGC4_UART3_MASK 0x2000u
Kojto 90:cb3d968589d8 11881 #define SIM_SCGC4_UART3_SHIFT 13
Kojto 90:cb3d968589d8 11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u
Kojto 90:cb3d968589d8 11883 #define SIM_SCGC4_USBOTG_SHIFT 18
Kojto 90:cb3d968589d8 11884 #define SIM_SCGC4_CMP_MASK 0x80000u
Kojto 90:cb3d968589d8 11885 #define SIM_SCGC4_CMP_SHIFT 19
Kojto 90:cb3d968589d8 11886 #define SIM_SCGC4_VREF_MASK 0x100000u
Kojto 90:cb3d968589d8 11887 #define SIM_SCGC4_VREF_SHIFT 20
Kojto 90:cb3d968589d8 11888 /* SCGC5 Bit Fields */
Kojto 90:cb3d968589d8 11889 #define SIM_SCGC5_LPTMR_MASK 0x1u
Kojto 90:cb3d968589d8 11890 #define SIM_SCGC5_LPTMR_SHIFT 0
Kojto 90:cb3d968589d8 11891 #define SIM_SCGC5_PORTA_MASK 0x200u
Kojto 90:cb3d968589d8 11892 #define SIM_SCGC5_PORTA_SHIFT 9
Kojto 90:cb3d968589d8 11893 #define SIM_SCGC5_PORTB_MASK 0x400u
Kojto 90:cb3d968589d8 11894 #define SIM_SCGC5_PORTB_SHIFT 10
Kojto 90:cb3d968589d8 11895 #define SIM_SCGC5_PORTC_MASK 0x800u
Kojto 90:cb3d968589d8 11896 #define SIM_SCGC5_PORTC_SHIFT 11
Kojto 90:cb3d968589d8 11897 #define SIM_SCGC5_PORTD_MASK 0x1000u
Kojto 90:cb3d968589d8 11898 #define SIM_SCGC5_PORTD_SHIFT 12
Kojto 90:cb3d968589d8 11899 #define SIM_SCGC5_PORTE_MASK 0x2000u
Kojto 90:cb3d968589d8 11900 #define SIM_SCGC5_PORTE_SHIFT 13
Kojto 90:cb3d968589d8 11901 /* SCGC6 Bit Fields */
Kojto 90:cb3d968589d8 11902 #define SIM_SCGC6_FTF_MASK 0x1u
Kojto 90:cb3d968589d8 11903 #define SIM_SCGC6_FTF_SHIFT 0
Kojto 90:cb3d968589d8 11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u
Kojto 90:cb3d968589d8 11905 #define SIM_SCGC6_DMAMUX_SHIFT 1
Kojto 90:cb3d968589d8 11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
Kojto 90:cb3d968589d8 11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
Kojto 90:cb3d968589d8 11908 #define SIM_SCGC6_RNGA_MASK 0x200u
Kojto 90:cb3d968589d8 11909 #define SIM_SCGC6_RNGA_SHIFT 9
Kojto 90:cb3d968589d8 11910 #define SIM_SCGC6_SPI0_MASK 0x1000u
Kojto 90:cb3d968589d8 11911 #define SIM_SCGC6_SPI0_SHIFT 12
Kojto 90:cb3d968589d8 11912 #define SIM_SCGC6_SPI1_MASK 0x2000u
Kojto 90:cb3d968589d8 11913 #define SIM_SCGC6_SPI1_SHIFT 13
Kojto 90:cb3d968589d8 11914 #define SIM_SCGC6_I2S_MASK 0x8000u
Kojto 90:cb3d968589d8 11915 #define SIM_SCGC6_I2S_SHIFT 15
Kojto 90:cb3d968589d8 11916 #define SIM_SCGC6_CRC_MASK 0x40000u
Kojto 90:cb3d968589d8 11917 #define SIM_SCGC6_CRC_SHIFT 18
Kojto 90:cb3d968589d8 11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u
Kojto 90:cb3d968589d8 11919 #define SIM_SCGC6_USBDCD_SHIFT 21
Kojto 90:cb3d968589d8 11920 #define SIM_SCGC6_PDB_MASK 0x400000u
Kojto 90:cb3d968589d8 11921 #define SIM_SCGC6_PDB_SHIFT 22
Kojto 90:cb3d968589d8 11922 #define SIM_SCGC6_PIT_MASK 0x800000u
Kojto 90:cb3d968589d8 11923 #define SIM_SCGC6_PIT_SHIFT 23
Kojto 90:cb3d968589d8 11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u
Kojto 90:cb3d968589d8 11925 #define SIM_SCGC6_FTM0_SHIFT 24
Kojto 90:cb3d968589d8 11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u
Kojto 90:cb3d968589d8 11927 #define SIM_SCGC6_FTM1_SHIFT 25
Kojto 90:cb3d968589d8 11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u
Kojto 90:cb3d968589d8 11929 #define SIM_SCGC6_FTM2_SHIFT 26
Kojto 90:cb3d968589d8 11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u
Kojto 90:cb3d968589d8 11931 #define SIM_SCGC6_ADC0_SHIFT 27
Kojto 90:cb3d968589d8 11932 #define SIM_SCGC6_RTC_MASK 0x20000000u
Kojto 90:cb3d968589d8 11933 #define SIM_SCGC6_RTC_SHIFT 29
Kojto 90:cb3d968589d8 11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u
Kojto 90:cb3d968589d8 11935 #define SIM_SCGC6_DAC0_SHIFT 31
Kojto 90:cb3d968589d8 11936 /* SCGC7 Bit Fields */
Kojto 90:cb3d968589d8 11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
Kojto 90:cb3d968589d8 11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0
Kojto 90:cb3d968589d8 11939 #define SIM_SCGC7_DMA_MASK 0x2u
Kojto 90:cb3d968589d8 11940 #define SIM_SCGC7_DMA_SHIFT 1
Kojto 90:cb3d968589d8 11941 #define SIM_SCGC7_MPU_MASK 0x4u
Kojto 90:cb3d968589d8 11942 #define SIM_SCGC7_MPU_SHIFT 2
Kojto 90:cb3d968589d8 11943 /* CLKDIV1 Bit Fields */
Kojto 90:cb3d968589d8 11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
Kojto 90:cb3d968589d8 11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
Kojto 90:cb3d968589d8 11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
Kojto 90:cb3d968589d8 11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
Kojto 90:cb3d968589d8 11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
Kojto 90:cb3d968589d8 11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
Kojto 90:cb3d968589d8 11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
Kojto 90:cb3d968589d8 11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
Kojto 90:cb3d968589d8 11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
Kojto 90:cb3d968589d8 11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
Kojto 90:cb3d968589d8 11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
Kojto 90:cb3d968589d8 11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
Kojto 90:cb3d968589d8 11956 /* CLKDIV2 Bit Fields */
Kojto 90:cb3d968589d8 11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
Kojto 90:cb3d968589d8 11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
Kojto 90:cb3d968589d8 11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
Kojto 90:cb3d968589d8 11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1
Kojto 90:cb3d968589d8 11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
Kojto 90:cb3d968589d8 11962 /* FCFG1 Bit Fields */
Kojto 90:cb3d968589d8 11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
Kojto 90:cb3d968589d8 11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0
Kojto 90:cb3d968589d8 11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
Kojto 90:cb3d968589d8 11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
Kojto 90:cb3d968589d8 11967 #define SIM_FCFG1_DEPART_MASK 0xF00u
Kojto 90:cb3d968589d8 11968 #define SIM_FCFG1_DEPART_SHIFT 8
Kojto 90:cb3d968589d8 11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
Kojto 90:cb3d968589d8 11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
Kojto 90:cb3d968589d8 11971 #define SIM_FCFG1_EESIZE_SHIFT 16
Kojto 90:cb3d968589d8 11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
Kojto 90:cb3d968589d8 11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
Kojto 90:cb3d968589d8 11974 #define SIM_FCFG1_PFSIZE_SHIFT 24
Kojto 90:cb3d968589d8 11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
Kojto 90:cb3d968589d8 11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
Kojto 90:cb3d968589d8 11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28
Kojto 90:cb3d968589d8 11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
Kojto 90:cb3d968589d8 11979 /* FCFG2 Bit Fields */
Kojto 90:cb3d968589d8 11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
Kojto 90:cb3d968589d8 11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16
Kojto 90:cb3d968589d8 11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
Kojto 90:cb3d968589d8 11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u
Kojto 90:cb3d968589d8 11984 #define SIM_FCFG2_PFLSH_SHIFT 23
Kojto 90:cb3d968589d8 11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
Kojto 90:cb3d968589d8 11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24
Kojto 90:cb3d968589d8 11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
Kojto 90:cb3d968589d8 11988 /* UIDH Bit Fields */
Kojto 90:cb3d968589d8 11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11990 #define SIM_UIDH_UID_SHIFT 0
Kojto 90:cb3d968589d8 11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
Kojto 90:cb3d968589d8 11992 /* UIDMH Bit Fields */
Kojto 90:cb3d968589d8 11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11994 #define SIM_UIDMH_UID_SHIFT 0
Kojto 90:cb3d968589d8 11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
Kojto 90:cb3d968589d8 11996 /* UIDML Bit Fields */
Kojto 90:cb3d968589d8 11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 11998 #define SIM_UIDML_UID_SHIFT 0
Kojto 90:cb3d968589d8 11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
Kojto 90:cb3d968589d8 12000 /* UIDL Bit Fields */
Kojto 90:cb3d968589d8 12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12002 #define SIM_UIDL_UID_SHIFT 0
Kojto 90:cb3d968589d8 12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
Kojto 90:cb3d968589d8 12004
Kojto 90:cb3d968589d8 12005 /*!
Kojto 90:cb3d968589d8 12006 * @}
Kojto 90:cb3d968589d8 12007 */ /* end of group SIM_Register_Masks */
Kojto 90:cb3d968589d8 12008
Kojto 90:cb3d968589d8 12009
Kojto 90:cb3d968589d8 12010 /* SIM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 12011 /** Peripheral SIM base address */
Kojto 90:cb3d968589d8 12012 #define SIM_BASE (0x40047000u)
Kojto 90:cb3d968589d8 12013 /** Peripheral SIM base pointer */
Kojto 90:cb3d968589d8 12014 #define SIM ((SIM_Type *)SIM_BASE)
Kojto 90:cb3d968589d8 12015 #define SIM_BASE_PTR (SIM)
Kojto 90:cb3d968589d8 12016 /** Array initializer of SIM peripheral base addresses */
Kojto 90:cb3d968589d8 12017 #define SIM_BASE_ADDRS { SIM_BASE }
Kojto 90:cb3d968589d8 12018 /** Array initializer of SIM peripheral base pointers */
Kojto 90:cb3d968589d8 12019 #define SIM_BASE_PTRS { SIM }
Kojto 90:cb3d968589d8 12020
Kojto 90:cb3d968589d8 12021 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12022 -- SIM - Register accessor macros
Kojto 90:cb3d968589d8 12023 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12024
Kojto 90:cb3d968589d8 12025 /*!
Kojto 90:cb3d968589d8 12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Kojto 90:cb3d968589d8 12027 * @{
Kojto 90:cb3d968589d8 12028 */
Kojto 90:cb3d968589d8 12029
Kojto 90:cb3d968589d8 12030
Kojto 90:cb3d968589d8 12031 /* SIM - Register instance definitions */
Kojto 90:cb3d968589d8 12032 /* SIM */
Kojto 90:cb3d968589d8 12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
Kojto 90:cb3d968589d8 12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
Kojto 90:cb3d968589d8 12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
Kojto 90:cb3d968589d8 12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
Kojto 90:cb3d968589d8 12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
Kojto 90:cb3d968589d8 12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
Kojto 90:cb3d968589d8 12039 #define SIM_SDID SIM_SDID_REG(SIM)
Kojto 90:cb3d968589d8 12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
Kojto 90:cb3d968589d8 12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
Kojto 90:cb3d968589d8 12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
Kojto 90:cb3d968589d8 12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
Kojto 90:cb3d968589d8 12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
Kojto 90:cb3d968589d8 12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
Kojto 90:cb3d968589d8 12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
Kojto 90:cb3d968589d8 12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
Kojto 90:cb3d968589d8 12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
Kojto 90:cb3d968589d8 12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
Kojto 90:cb3d968589d8 12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
Kojto 90:cb3d968589d8 12051 #define SIM_UIDH SIM_UIDH_REG(SIM)
Kojto 90:cb3d968589d8 12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
Kojto 90:cb3d968589d8 12053 #define SIM_UIDML SIM_UIDML_REG(SIM)
Kojto 90:cb3d968589d8 12054 #define SIM_UIDL SIM_UIDL_REG(SIM)
Kojto 90:cb3d968589d8 12055
Kojto 90:cb3d968589d8 12056 /*!
Kojto 90:cb3d968589d8 12057 * @}
Kojto 90:cb3d968589d8 12058 */ /* end of group SIM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12059
Kojto 90:cb3d968589d8 12060
Kojto 90:cb3d968589d8 12061 /*!
Kojto 90:cb3d968589d8 12062 * @}
Kojto 90:cb3d968589d8 12063 */ /* end of group SIM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 12064
Kojto 90:cb3d968589d8 12065
Kojto 90:cb3d968589d8 12066 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12067 -- SMC Peripheral Access Layer
Kojto 90:cb3d968589d8 12068 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12069
Kojto 90:cb3d968589d8 12070 /*!
Kojto 90:cb3d968589d8 12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Kojto 90:cb3d968589d8 12072 * @{
Kojto 90:cb3d968589d8 12073 */
Kojto 90:cb3d968589d8 12074
Kojto 90:cb3d968589d8 12075 /** SMC - Register Layout Typedef */
Kojto 90:cb3d968589d8 12076 typedef struct {
Kojto 90:cb3d968589d8 12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
Kojto 90:cb3d968589d8 12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
Kojto 90:cb3d968589d8 12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
Kojto 90:cb3d968589d8 12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
Kojto 90:cb3d968589d8 12081 } SMC_Type, *SMC_MemMapPtr;
Kojto 90:cb3d968589d8 12082
Kojto 90:cb3d968589d8 12083 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12084 -- SMC - Register accessor macros
Kojto 90:cb3d968589d8 12085 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12086
Kojto 90:cb3d968589d8 12087 /*!
Kojto 90:cb3d968589d8 12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Kojto 90:cb3d968589d8 12089 * @{
Kojto 90:cb3d968589d8 12090 */
Kojto 90:cb3d968589d8 12091
Kojto 90:cb3d968589d8 12092
Kojto 90:cb3d968589d8 12093 /* SMC - Register accessors */
Kojto 90:cb3d968589d8 12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
Kojto 90:cb3d968589d8 12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
Kojto 90:cb3d968589d8 12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
Kojto 90:cb3d968589d8 12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
Kojto 90:cb3d968589d8 12098
Kojto 90:cb3d968589d8 12099 /*!
Kojto 90:cb3d968589d8 12100 * @}
Kojto 90:cb3d968589d8 12101 */ /* end of group SMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12102
Kojto 90:cb3d968589d8 12103
Kojto 90:cb3d968589d8 12104 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12105 -- SMC Register Masks
Kojto 90:cb3d968589d8 12106 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12107
Kojto 90:cb3d968589d8 12108 /*!
Kojto 90:cb3d968589d8 12109 * @addtogroup SMC_Register_Masks SMC Register Masks
Kojto 90:cb3d968589d8 12110 * @{
Kojto 90:cb3d968589d8 12111 */
Kojto 90:cb3d968589d8 12112
Kojto 90:cb3d968589d8 12113 /* PMPROT Bit Fields */
Kojto 90:cb3d968589d8 12114 #define SMC_PMPROT_AVLLS_MASK 0x2u
Kojto 90:cb3d968589d8 12115 #define SMC_PMPROT_AVLLS_SHIFT 1
Kojto 90:cb3d968589d8 12116 #define SMC_PMPROT_ALLS_MASK 0x8u
Kojto 90:cb3d968589d8 12117 #define SMC_PMPROT_ALLS_SHIFT 3
Kojto 90:cb3d968589d8 12118 #define SMC_PMPROT_AVLP_MASK 0x20u
Kojto 90:cb3d968589d8 12119 #define SMC_PMPROT_AVLP_SHIFT 5
Kojto 90:cb3d968589d8 12120 /* PMCTRL Bit Fields */
Kojto 90:cb3d968589d8 12121 #define SMC_PMCTRL_STOPM_MASK 0x7u
Kojto 90:cb3d968589d8 12122 #define SMC_PMCTRL_STOPM_SHIFT 0
Kojto 90:cb3d968589d8 12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
Kojto 90:cb3d968589d8 12124 #define SMC_PMCTRL_STOPA_MASK 0x8u
Kojto 90:cb3d968589d8 12125 #define SMC_PMCTRL_STOPA_SHIFT 3
Kojto 90:cb3d968589d8 12126 #define SMC_PMCTRL_RUNM_MASK 0x60u
Kojto 90:cb3d968589d8 12127 #define SMC_PMCTRL_RUNM_SHIFT 5
Kojto 90:cb3d968589d8 12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
Kojto 90:cb3d968589d8 12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u
Kojto 90:cb3d968589d8 12130 #define SMC_PMCTRL_LPWUI_SHIFT 7
Kojto 90:cb3d968589d8 12131 /* VLLSCTRL Bit Fields */
Kojto 90:cb3d968589d8 12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
Kojto 90:cb3d968589d8 12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
Kojto 90:cb3d968589d8 12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
Kojto 90:cb3d968589d8 12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
Kojto 90:cb3d968589d8 12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5
Kojto 90:cb3d968589d8 12137 /* PMSTAT Bit Fields */
Kojto 90:cb3d968589d8 12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
Kojto 90:cb3d968589d8 12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0
Kojto 90:cb3d968589d8 12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
Kojto 90:cb3d968589d8 12141
Kojto 90:cb3d968589d8 12142 /*!
Kojto 90:cb3d968589d8 12143 * @}
Kojto 90:cb3d968589d8 12144 */ /* end of group SMC_Register_Masks */
Kojto 90:cb3d968589d8 12145
Kojto 90:cb3d968589d8 12146
Kojto 90:cb3d968589d8 12147 /* SMC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 12148 /** Peripheral SMC base address */
Kojto 90:cb3d968589d8 12149 #define SMC_BASE (0x4007E000u)
Kojto 90:cb3d968589d8 12150 /** Peripheral SMC base pointer */
Kojto 90:cb3d968589d8 12151 #define SMC ((SMC_Type *)SMC_BASE)
Kojto 90:cb3d968589d8 12152 #define SMC_BASE_PTR (SMC)
Kojto 90:cb3d968589d8 12153 /** Array initializer of SMC peripheral base addresses */
Kojto 90:cb3d968589d8 12154 #define SMC_BASE_ADDRS { SMC_BASE }
Kojto 90:cb3d968589d8 12155 /** Array initializer of SMC peripheral base pointers */
Kojto 90:cb3d968589d8 12156 #define SMC_BASE_PTRS { SMC }
Kojto 90:cb3d968589d8 12157
Kojto 90:cb3d968589d8 12158 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12159 -- SMC - Register accessor macros
Kojto 90:cb3d968589d8 12160 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12161
Kojto 90:cb3d968589d8 12162 /*!
Kojto 90:cb3d968589d8 12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Kojto 90:cb3d968589d8 12164 * @{
Kojto 90:cb3d968589d8 12165 */
Kojto 90:cb3d968589d8 12166
Kojto 90:cb3d968589d8 12167
Kojto 90:cb3d968589d8 12168 /* SMC - Register instance definitions */
Kojto 90:cb3d968589d8 12169 /* SMC */
Kojto 90:cb3d968589d8 12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
Kojto 90:cb3d968589d8 12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
Kojto 90:cb3d968589d8 12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
Kojto 90:cb3d968589d8 12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
Kojto 90:cb3d968589d8 12174
Kojto 90:cb3d968589d8 12175 /*!
Kojto 90:cb3d968589d8 12176 * @}
Kojto 90:cb3d968589d8 12177 */ /* end of group SMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12178
Kojto 90:cb3d968589d8 12179
Kojto 90:cb3d968589d8 12180 /*!
Kojto 90:cb3d968589d8 12181 * @}
Kojto 90:cb3d968589d8 12182 */ /* end of group SMC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 12183
Kojto 90:cb3d968589d8 12184
Kojto 90:cb3d968589d8 12185 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12186 -- SPI Peripheral Access Layer
Kojto 90:cb3d968589d8 12187 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12188
Kojto 90:cb3d968589d8 12189 /*!
Kojto 90:cb3d968589d8 12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Kojto 90:cb3d968589d8 12191 * @{
Kojto 90:cb3d968589d8 12192 */
Kojto 90:cb3d968589d8 12193
Kojto 90:cb3d968589d8 12194 /** SPI - Register Layout Typedef */
Kojto 90:cb3d968589d8 12195 typedef struct {
Kojto 90:cb3d968589d8 12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
Kojto 90:cb3d968589d8 12197 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
Kojto 90:cb3d968589d8 12199 union { /* offset: 0xC */
Kojto 90:cb3d968589d8 12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
Kojto 90:cb3d968589d8 12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
Kojto 90:cb3d968589d8 12202 };
Kojto 90:cb3d968589d8 12203 uint8_t RESERVED_1[24];
Kojto 90:cb3d968589d8 12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
Kojto 90:cb3d968589d8 12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
Kojto 90:cb3d968589d8 12206 union { /* offset: 0x34 */
Kojto 90:cb3d968589d8 12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
Kojto 90:cb3d968589d8 12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
Kojto 90:cb3d968589d8 12209 };
Kojto 90:cb3d968589d8 12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
Kojto 90:cb3d968589d8 12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
Kojto 90:cb3d968589d8 12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
Kojto 90:cb3d968589d8 12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
Kojto 90:cb3d968589d8 12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
Kojto 90:cb3d968589d8 12215 uint8_t RESERVED_2[48];
Kojto 90:cb3d968589d8 12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
Kojto 90:cb3d968589d8 12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
Kojto 90:cb3d968589d8 12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
Kojto 90:cb3d968589d8 12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
Kojto 90:cb3d968589d8 12220 } SPI_Type, *SPI_MemMapPtr;
Kojto 90:cb3d968589d8 12221
Kojto 90:cb3d968589d8 12222 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12223 -- SPI - Register accessor macros
Kojto 90:cb3d968589d8 12224 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12225
Kojto 90:cb3d968589d8 12226 /*!
Kojto 90:cb3d968589d8 12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Kojto 90:cb3d968589d8 12228 * @{
Kojto 90:cb3d968589d8 12229 */
Kojto 90:cb3d968589d8 12230
Kojto 90:cb3d968589d8 12231
Kojto 90:cb3d968589d8 12232 /* SPI - Register accessors */
Kojto 90:cb3d968589d8 12233 #define SPI_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 12234 #define SPI_TCR_REG(base) ((base)->TCR)
Kojto 90:cb3d968589d8 12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
Kojto 90:cb3d968589d8 12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
Kojto 90:cb3d968589d8 12237 #define SPI_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 12238 #define SPI_RSER_REG(base) ((base)->RSER)
Kojto 90:cb3d968589d8 12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
Kojto 90:cb3d968589d8 12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
Kojto 90:cb3d968589d8 12241 #define SPI_POPR_REG(base) ((base)->POPR)
Kojto 90:cb3d968589d8 12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
Kojto 90:cb3d968589d8 12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
Kojto 90:cb3d968589d8 12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
Kojto 90:cb3d968589d8 12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
Kojto 90:cb3d968589d8 12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
Kojto 90:cb3d968589d8 12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
Kojto 90:cb3d968589d8 12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
Kojto 90:cb3d968589d8 12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
Kojto 90:cb3d968589d8 12250
Kojto 90:cb3d968589d8 12251 /*!
Kojto 90:cb3d968589d8 12252 * @}
Kojto 90:cb3d968589d8 12253 */ /* end of group SPI_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12254
Kojto 90:cb3d968589d8 12255
Kojto 90:cb3d968589d8 12256 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12257 -- SPI Register Masks
Kojto 90:cb3d968589d8 12258 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12259
Kojto 90:cb3d968589d8 12260 /*!
Kojto 90:cb3d968589d8 12261 * @addtogroup SPI_Register_Masks SPI Register Masks
Kojto 90:cb3d968589d8 12262 * @{
Kojto 90:cb3d968589d8 12263 */
Kojto 90:cb3d968589d8 12264
Kojto 90:cb3d968589d8 12265 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 12266 #define SPI_MCR_HALT_MASK 0x1u
Kojto 90:cb3d968589d8 12267 #define SPI_MCR_HALT_SHIFT 0
Kojto 90:cb3d968589d8 12268 #define SPI_MCR_SMPL_PT_MASK 0x300u
Kojto 90:cb3d968589d8 12269 #define SPI_MCR_SMPL_PT_SHIFT 8
Kojto 90:cb3d968589d8 12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
Kojto 90:cb3d968589d8 12271 #define SPI_MCR_CLR_RXF_MASK 0x400u
Kojto 90:cb3d968589d8 12272 #define SPI_MCR_CLR_RXF_SHIFT 10
Kojto 90:cb3d968589d8 12273 #define SPI_MCR_CLR_TXF_MASK 0x800u
Kojto 90:cb3d968589d8 12274 #define SPI_MCR_CLR_TXF_SHIFT 11
Kojto 90:cb3d968589d8 12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u
Kojto 90:cb3d968589d8 12276 #define SPI_MCR_DIS_RXF_SHIFT 12
Kojto 90:cb3d968589d8 12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u
Kojto 90:cb3d968589d8 12278 #define SPI_MCR_DIS_TXF_SHIFT 13
Kojto 90:cb3d968589d8 12279 #define SPI_MCR_MDIS_MASK 0x4000u
Kojto 90:cb3d968589d8 12280 #define SPI_MCR_MDIS_SHIFT 14
Kojto 90:cb3d968589d8 12281 #define SPI_MCR_DOZE_MASK 0x8000u
Kojto 90:cb3d968589d8 12282 #define SPI_MCR_DOZE_SHIFT 15
Kojto 90:cb3d968589d8 12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u
Kojto 90:cb3d968589d8 12284 #define SPI_MCR_PCSIS_SHIFT 16
Kojto 90:cb3d968589d8 12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
Kojto 90:cb3d968589d8 12286 #define SPI_MCR_ROOE_MASK 0x1000000u
Kojto 90:cb3d968589d8 12287 #define SPI_MCR_ROOE_SHIFT 24
Kojto 90:cb3d968589d8 12288 #define SPI_MCR_PCSSE_MASK 0x2000000u
Kojto 90:cb3d968589d8 12289 #define SPI_MCR_PCSSE_SHIFT 25
Kojto 90:cb3d968589d8 12290 #define SPI_MCR_MTFE_MASK 0x4000000u
Kojto 90:cb3d968589d8 12291 #define SPI_MCR_MTFE_SHIFT 26
Kojto 90:cb3d968589d8 12292 #define SPI_MCR_FRZ_MASK 0x8000000u
Kojto 90:cb3d968589d8 12293 #define SPI_MCR_FRZ_SHIFT 27
Kojto 90:cb3d968589d8 12294 #define SPI_MCR_DCONF_MASK 0x30000000u
Kojto 90:cb3d968589d8 12295 #define SPI_MCR_DCONF_SHIFT 28
Kojto 90:cb3d968589d8 12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
Kojto 90:cb3d968589d8 12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
Kojto 90:cb3d968589d8 12298 #define SPI_MCR_CONT_SCKE_SHIFT 30
Kojto 90:cb3d968589d8 12299 #define SPI_MCR_MSTR_MASK 0x80000000u
Kojto 90:cb3d968589d8 12300 #define SPI_MCR_MSTR_SHIFT 31
Kojto 90:cb3d968589d8 12301 /* TCR Bit Fields */
Kojto 90:cb3d968589d8 12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 12303 #define SPI_TCR_SPI_TCNT_SHIFT 16
Kojto 90:cb3d968589d8 12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
Kojto 90:cb3d968589d8 12305 /* CTAR Bit Fields */
Kojto 90:cb3d968589d8 12306 #define SPI_CTAR_BR_MASK 0xFu
Kojto 90:cb3d968589d8 12307 #define SPI_CTAR_BR_SHIFT 0
Kojto 90:cb3d968589d8 12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
Kojto 90:cb3d968589d8 12309 #define SPI_CTAR_DT_MASK 0xF0u
Kojto 90:cb3d968589d8 12310 #define SPI_CTAR_DT_SHIFT 4
Kojto 90:cb3d968589d8 12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
Kojto 90:cb3d968589d8 12312 #define SPI_CTAR_ASC_MASK 0xF00u
Kojto 90:cb3d968589d8 12313 #define SPI_CTAR_ASC_SHIFT 8
Kojto 90:cb3d968589d8 12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
Kojto 90:cb3d968589d8 12315 #define SPI_CTAR_CSSCK_MASK 0xF000u
Kojto 90:cb3d968589d8 12316 #define SPI_CTAR_CSSCK_SHIFT 12
Kojto 90:cb3d968589d8 12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
Kojto 90:cb3d968589d8 12318 #define SPI_CTAR_PBR_MASK 0x30000u
Kojto 90:cb3d968589d8 12319 #define SPI_CTAR_PBR_SHIFT 16
Kojto 90:cb3d968589d8 12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
Kojto 90:cb3d968589d8 12321 #define SPI_CTAR_PDT_MASK 0xC0000u
Kojto 90:cb3d968589d8 12322 #define SPI_CTAR_PDT_SHIFT 18
Kojto 90:cb3d968589d8 12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
Kojto 90:cb3d968589d8 12324 #define SPI_CTAR_PASC_MASK 0x300000u
Kojto 90:cb3d968589d8 12325 #define SPI_CTAR_PASC_SHIFT 20
Kojto 90:cb3d968589d8 12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
Kojto 90:cb3d968589d8 12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
Kojto 90:cb3d968589d8 12328 #define SPI_CTAR_PCSSCK_SHIFT 22
Kojto 90:cb3d968589d8 12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
Kojto 90:cb3d968589d8 12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u
Kojto 90:cb3d968589d8 12331 #define SPI_CTAR_LSBFE_SHIFT 24
Kojto 90:cb3d968589d8 12332 #define SPI_CTAR_CPHA_MASK 0x2000000u
Kojto 90:cb3d968589d8 12333 #define SPI_CTAR_CPHA_SHIFT 25
Kojto 90:cb3d968589d8 12334 #define SPI_CTAR_CPOL_MASK 0x4000000u
Kojto 90:cb3d968589d8 12335 #define SPI_CTAR_CPOL_SHIFT 26
Kojto 90:cb3d968589d8 12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u
Kojto 90:cb3d968589d8 12337 #define SPI_CTAR_FMSZ_SHIFT 27
Kojto 90:cb3d968589d8 12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
Kojto 90:cb3d968589d8 12339 #define SPI_CTAR_DBR_MASK 0x80000000u
Kojto 90:cb3d968589d8 12340 #define SPI_CTAR_DBR_SHIFT 31
Kojto 90:cb3d968589d8 12341 /* CTAR_SLAVE Bit Fields */
Kojto 90:cb3d968589d8 12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
Kojto 90:cb3d968589d8 12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
Kojto 90:cb3d968589d8 12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
Kojto 90:cb3d968589d8 12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
Kojto 90:cb3d968589d8 12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
Kojto 90:cb3d968589d8 12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
Kojto 90:cb3d968589d8 12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
Kojto 90:cb3d968589d8 12349 /* SR Bit Fields */
Kojto 90:cb3d968589d8 12350 #define SPI_SR_POPNXTPTR_MASK 0xFu
Kojto 90:cb3d968589d8 12351 #define SPI_SR_POPNXTPTR_SHIFT 0
Kojto 90:cb3d968589d8 12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
Kojto 90:cb3d968589d8 12353 #define SPI_SR_RXCTR_MASK 0xF0u
Kojto 90:cb3d968589d8 12354 #define SPI_SR_RXCTR_SHIFT 4
Kojto 90:cb3d968589d8 12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
Kojto 90:cb3d968589d8 12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u
Kojto 90:cb3d968589d8 12357 #define SPI_SR_TXNXTPTR_SHIFT 8
Kojto 90:cb3d968589d8 12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
Kojto 90:cb3d968589d8 12359 #define SPI_SR_TXCTR_MASK 0xF000u
Kojto 90:cb3d968589d8 12360 #define SPI_SR_TXCTR_SHIFT 12
Kojto 90:cb3d968589d8 12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
Kojto 90:cb3d968589d8 12362 #define SPI_SR_RFDF_MASK 0x20000u
Kojto 90:cb3d968589d8 12363 #define SPI_SR_RFDF_SHIFT 17
Kojto 90:cb3d968589d8 12364 #define SPI_SR_RFOF_MASK 0x80000u
Kojto 90:cb3d968589d8 12365 #define SPI_SR_RFOF_SHIFT 19
Kojto 90:cb3d968589d8 12366 #define SPI_SR_TFFF_MASK 0x2000000u
Kojto 90:cb3d968589d8 12367 #define SPI_SR_TFFF_SHIFT 25
Kojto 90:cb3d968589d8 12368 #define SPI_SR_TFUF_MASK 0x8000000u
Kojto 90:cb3d968589d8 12369 #define SPI_SR_TFUF_SHIFT 27
Kojto 90:cb3d968589d8 12370 #define SPI_SR_EOQF_MASK 0x10000000u
Kojto 90:cb3d968589d8 12371 #define SPI_SR_EOQF_SHIFT 28
Kojto 90:cb3d968589d8 12372 #define SPI_SR_TXRXS_MASK 0x40000000u
Kojto 90:cb3d968589d8 12373 #define SPI_SR_TXRXS_SHIFT 30
Kojto 90:cb3d968589d8 12374 #define SPI_SR_TCF_MASK 0x80000000u
Kojto 90:cb3d968589d8 12375 #define SPI_SR_TCF_SHIFT 31
Kojto 90:cb3d968589d8 12376 /* RSER Bit Fields */
Kojto 90:cb3d968589d8 12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
Kojto 90:cb3d968589d8 12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16
Kojto 90:cb3d968589d8 12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u
Kojto 90:cb3d968589d8 12380 #define SPI_RSER_RFDF_RE_SHIFT 17
Kojto 90:cb3d968589d8 12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u
Kojto 90:cb3d968589d8 12382 #define SPI_RSER_RFOF_RE_SHIFT 19
Kojto 90:cb3d968589d8 12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
Kojto 90:cb3d968589d8 12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24
Kojto 90:cb3d968589d8 12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
Kojto 90:cb3d968589d8 12386 #define SPI_RSER_TFFF_RE_SHIFT 25
Kojto 90:cb3d968589d8 12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
Kojto 90:cb3d968589d8 12388 #define SPI_RSER_TFUF_RE_SHIFT 27
Kojto 90:cb3d968589d8 12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
Kojto 90:cb3d968589d8 12390 #define SPI_RSER_EOQF_RE_SHIFT 28
Kojto 90:cb3d968589d8 12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u
Kojto 90:cb3d968589d8 12392 #define SPI_RSER_TCF_RE_SHIFT 31
Kojto 90:cb3d968589d8 12393 /* PUSHR Bit Fields */
Kojto 90:cb3d968589d8 12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 12395 #define SPI_PUSHR_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
Kojto 90:cb3d968589d8 12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u
Kojto 90:cb3d968589d8 12398 #define SPI_PUSHR_PCS_SHIFT 16
Kojto 90:cb3d968589d8 12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
Kojto 90:cb3d968589d8 12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
Kojto 90:cb3d968589d8 12401 #define SPI_PUSHR_CTCNT_SHIFT 26
Kojto 90:cb3d968589d8 12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u
Kojto 90:cb3d968589d8 12403 #define SPI_PUSHR_EOQ_SHIFT 27
Kojto 90:cb3d968589d8 12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u
Kojto 90:cb3d968589d8 12405 #define SPI_PUSHR_CTAS_SHIFT 28
Kojto 90:cb3d968589d8 12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
Kojto 90:cb3d968589d8 12407 #define SPI_PUSHR_CONT_MASK 0x80000000u
Kojto 90:cb3d968589d8 12408 #define SPI_PUSHR_CONT_SHIFT 31
Kojto 90:cb3d968589d8 12409 /* PUSHR_SLAVE Bit Fields */
Kojto 90:cb3d968589d8 12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
Kojto 90:cb3d968589d8 12413 /* POPR Bit Fields */
Kojto 90:cb3d968589d8 12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12415 #define SPI_POPR_RXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
Kojto 90:cb3d968589d8 12417 /* TXFR0 Bit Fields */
Kojto 90:cb3d968589d8 12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 12419 #define SPI_TXFR0_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
Kojto 90:cb3d968589d8 12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
Kojto 90:cb3d968589d8 12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
Kojto 90:cb3d968589d8 12424 /* TXFR1 Bit Fields */
Kojto 90:cb3d968589d8 12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 12426 #define SPI_TXFR1_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
Kojto 90:cb3d968589d8 12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
Kojto 90:cb3d968589d8 12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
Kojto 90:cb3d968589d8 12431 /* TXFR2 Bit Fields */
Kojto 90:cb3d968589d8 12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 12433 #define SPI_TXFR2_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
Kojto 90:cb3d968589d8 12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
Kojto 90:cb3d968589d8 12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
Kojto 90:cb3d968589d8 12438 /* TXFR3 Bit Fields */
Kojto 90:cb3d968589d8 12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
Kojto 90:cb3d968589d8 12440 #define SPI_TXFR3_TXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
Kojto 90:cb3d968589d8 12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
Kojto 90:cb3d968589d8 12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
Kojto 90:cb3d968589d8 12445 /* RXFR0 Bit Fields */
Kojto 90:cb3d968589d8 12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12447 #define SPI_RXFR0_RXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
Kojto 90:cb3d968589d8 12449 /* RXFR1 Bit Fields */
Kojto 90:cb3d968589d8 12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12451 #define SPI_RXFR1_RXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
Kojto 90:cb3d968589d8 12453 /* RXFR2 Bit Fields */
Kojto 90:cb3d968589d8 12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12455 #define SPI_RXFR2_RXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
Kojto 90:cb3d968589d8 12457 /* RXFR3 Bit Fields */
Kojto 90:cb3d968589d8 12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 12459 #define SPI_RXFR3_RXDATA_SHIFT 0
Kojto 90:cb3d968589d8 12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
Kojto 90:cb3d968589d8 12461
Kojto 90:cb3d968589d8 12462 /*!
Kojto 90:cb3d968589d8 12463 * @}
Kojto 90:cb3d968589d8 12464 */ /* end of group SPI_Register_Masks */
Kojto 90:cb3d968589d8 12465
Kojto 90:cb3d968589d8 12466
Kojto 90:cb3d968589d8 12467 /* SPI - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 12468 /** Peripheral SPI0 base address */
Kojto 90:cb3d968589d8 12469 #define SPI0_BASE (0x4002C000u)
Kojto 90:cb3d968589d8 12470 /** Peripheral SPI0 base pointer */
Kojto 90:cb3d968589d8 12471 #define SPI0 ((SPI_Type *)SPI0_BASE)
Kojto 90:cb3d968589d8 12472 #define SPI0_BASE_PTR (SPI0)
Kojto 90:cb3d968589d8 12473 /** Peripheral SPI1 base address */
Kojto 90:cb3d968589d8 12474 #define SPI1_BASE (0x4002D000u)
Kojto 90:cb3d968589d8 12475 /** Peripheral SPI1 base pointer */
Kojto 90:cb3d968589d8 12476 #define SPI1 ((SPI_Type *)SPI1_BASE)
Kojto 90:cb3d968589d8 12477 #define SPI1_BASE_PTR (SPI1)
Kojto 90:cb3d968589d8 12478 /** Peripheral SPI2 base address */
Kojto 90:cb3d968589d8 12479 #define SPI2_BASE (0x400AC000u)
Kojto 90:cb3d968589d8 12480 /** Peripheral SPI2 base pointer */
Kojto 90:cb3d968589d8 12481 #define SPI2 ((SPI_Type *)SPI2_BASE)
Kojto 90:cb3d968589d8 12482 #define SPI2_BASE_PTR (SPI2)
Kojto 90:cb3d968589d8 12483 /** Array initializer of SPI peripheral base addresses */
Kojto 90:cb3d968589d8 12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
Kojto 90:cb3d968589d8 12485 /** Array initializer of SPI peripheral base pointers */
Kojto 90:cb3d968589d8 12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
Kojto 90:cb3d968589d8 12487 /** Interrupt vectors for the SPI peripheral type */
Kojto 90:cb3d968589d8 12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
Kojto 90:cb3d968589d8 12489
Kojto 90:cb3d968589d8 12490 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12491 -- SPI - Register accessor macros
Kojto 90:cb3d968589d8 12492 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12493
Kojto 90:cb3d968589d8 12494 /*!
Kojto 90:cb3d968589d8 12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Kojto 90:cb3d968589d8 12496 * @{
Kojto 90:cb3d968589d8 12497 */
Kojto 90:cb3d968589d8 12498
Kojto 90:cb3d968589d8 12499
Kojto 90:cb3d968589d8 12500 /* SPI - Register instance definitions */
Kojto 90:cb3d968589d8 12501 /* SPI0 */
Kojto 90:cb3d968589d8 12502 #define SPI0_MCR SPI_MCR_REG(SPI0)
Kojto 90:cb3d968589d8 12503 #define SPI0_TCR SPI_TCR_REG(SPI0)
Kojto 90:cb3d968589d8 12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
Kojto 90:cb3d968589d8 12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
Kojto 90:cb3d968589d8 12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
Kojto 90:cb3d968589d8 12507 #define SPI0_SR SPI_SR_REG(SPI0)
Kojto 90:cb3d968589d8 12508 #define SPI0_RSER SPI_RSER_REG(SPI0)
Kojto 90:cb3d968589d8 12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
Kojto 90:cb3d968589d8 12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
Kojto 90:cb3d968589d8 12511 #define SPI0_POPR SPI_POPR_REG(SPI0)
Kojto 90:cb3d968589d8 12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
Kojto 90:cb3d968589d8 12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
Kojto 90:cb3d968589d8 12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
Kojto 90:cb3d968589d8 12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
Kojto 90:cb3d968589d8 12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
Kojto 90:cb3d968589d8 12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
Kojto 90:cb3d968589d8 12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
Kojto 90:cb3d968589d8 12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
Kojto 90:cb3d968589d8 12520 /* SPI1 */
Kojto 90:cb3d968589d8 12521 #define SPI1_MCR SPI_MCR_REG(SPI1)
Kojto 90:cb3d968589d8 12522 #define SPI1_TCR SPI_TCR_REG(SPI1)
Kojto 90:cb3d968589d8 12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
Kojto 90:cb3d968589d8 12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
Kojto 90:cb3d968589d8 12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
Kojto 90:cb3d968589d8 12526 #define SPI1_SR SPI_SR_REG(SPI1)
Kojto 90:cb3d968589d8 12527 #define SPI1_RSER SPI_RSER_REG(SPI1)
Kojto 90:cb3d968589d8 12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
Kojto 90:cb3d968589d8 12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
Kojto 90:cb3d968589d8 12530 #define SPI1_POPR SPI_POPR_REG(SPI1)
Kojto 90:cb3d968589d8 12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
Kojto 90:cb3d968589d8 12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
Kojto 90:cb3d968589d8 12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
Kojto 90:cb3d968589d8 12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
Kojto 90:cb3d968589d8 12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
Kojto 90:cb3d968589d8 12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
Kojto 90:cb3d968589d8 12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
Kojto 90:cb3d968589d8 12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
Kojto 90:cb3d968589d8 12539 /* SPI2 */
Kojto 90:cb3d968589d8 12540 #define SPI2_MCR SPI_MCR_REG(SPI2)
Kojto 90:cb3d968589d8 12541 #define SPI2_TCR SPI_TCR_REG(SPI2)
Kojto 90:cb3d968589d8 12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
Kojto 90:cb3d968589d8 12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
Kojto 90:cb3d968589d8 12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
Kojto 90:cb3d968589d8 12545 #define SPI2_SR SPI_SR_REG(SPI2)
Kojto 90:cb3d968589d8 12546 #define SPI2_RSER SPI_RSER_REG(SPI2)
Kojto 90:cb3d968589d8 12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
Kojto 90:cb3d968589d8 12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
Kojto 90:cb3d968589d8 12549 #define SPI2_POPR SPI_POPR_REG(SPI2)
Kojto 90:cb3d968589d8 12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
Kojto 90:cb3d968589d8 12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
Kojto 90:cb3d968589d8 12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
Kojto 90:cb3d968589d8 12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
Kojto 90:cb3d968589d8 12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
Kojto 90:cb3d968589d8 12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
Kojto 90:cb3d968589d8 12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
Kojto 90:cb3d968589d8 12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
Kojto 90:cb3d968589d8 12558
Kojto 90:cb3d968589d8 12559 /* SPI - Register array accessors */
Kojto 90:cb3d968589d8 12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
Kojto 90:cb3d968589d8 12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
Kojto 90:cb3d968589d8 12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
Kojto 90:cb3d968589d8 12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
Kojto 90:cb3d968589d8 12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
Kojto 90:cb3d968589d8 12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
Kojto 90:cb3d968589d8 12566
Kojto 90:cb3d968589d8 12567 /*!
Kojto 90:cb3d968589d8 12568 * @}
Kojto 90:cb3d968589d8 12569 */ /* end of group SPI_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12570
Kojto 90:cb3d968589d8 12571
Kojto 90:cb3d968589d8 12572 /*!
Kojto 90:cb3d968589d8 12573 * @}
Kojto 90:cb3d968589d8 12574 */ /* end of group SPI_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 12575
Kojto 90:cb3d968589d8 12576
Kojto 90:cb3d968589d8 12577 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12578 -- UART Peripheral Access Layer
Kojto 90:cb3d968589d8 12579 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12580
Kojto 90:cb3d968589d8 12581 /*!
Kojto 90:cb3d968589d8 12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Kojto 90:cb3d968589d8 12583 * @{
Kojto 90:cb3d968589d8 12584 */
Kojto 90:cb3d968589d8 12585
Kojto 90:cb3d968589d8 12586 /** UART - Register Layout Typedef */
Kojto 90:cb3d968589d8 12587 typedef struct {
Kojto 90:cb3d968589d8 12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
Kojto 90:cb3d968589d8 12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
Kojto 90:cb3d968589d8 12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
Kojto 90:cb3d968589d8 12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
Kojto 90:cb3d968589d8 12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
Kojto 90:cb3d968589d8 12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
Kojto 90:cb3d968589d8 12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
Kojto 90:cb3d968589d8 12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
Kojto 90:cb3d968589d8 12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
Kojto 90:cb3d968589d8 12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
Kojto 90:cb3d968589d8 12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
Kojto 90:cb3d968589d8 12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
Kojto 90:cb3d968589d8 12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
Kojto 90:cb3d968589d8 12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
Kojto 90:cb3d968589d8 12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
Kojto 90:cb3d968589d8 12603 uint8_t RESERVED_0[1];
Kojto 90:cb3d968589d8 12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
Kojto 90:cb3d968589d8 12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
Kojto 90:cb3d968589d8 12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
Kojto 90:cb3d968589d8 12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
Kojto 90:cb3d968589d8 12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
Kojto 90:cb3d968589d8 12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
Kojto 90:cb3d968589d8 12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
Kojto 90:cb3d968589d8 12611 uint8_t RESERVED_1[1];
Kojto 90:cb3d968589d8 12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
Kojto 90:cb3d968589d8 12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
Kojto 90:cb3d968589d8 12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
Kojto 90:cb3d968589d8 12615 union { /* offset: 0x1B */
Kojto 90:cb3d968589d8 12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
Kojto 90:cb3d968589d8 12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
Kojto 90:cb3d968589d8 12618 };
Kojto 90:cb3d968589d8 12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
Kojto 90:cb3d968589d8 12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
Kojto 90:cb3d968589d8 12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
Kojto 90:cb3d968589d8 12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
Kojto 90:cb3d968589d8 12623 } UART_Type, *UART_MemMapPtr;
Kojto 90:cb3d968589d8 12624
Kojto 90:cb3d968589d8 12625 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12626 -- UART - Register accessor macros
Kojto 90:cb3d968589d8 12627 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12628
Kojto 90:cb3d968589d8 12629 /*!
Kojto 90:cb3d968589d8 12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Kojto 90:cb3d968589d8 12631 * @{
Kojto 90:cb3d968589d8 12632 */
Kojto 90:cb3d968589d8 12633
Kojto 90:cb3d968589d8 12634
Kojto 90:cb3d968589d8 12635 /* UART - Register accessors */
Kojto 90:cb3d968589d8 12636 #define UART_BDH_REG(base) ((base)->BDH)
Kojto 90:cb3d968589d8 12637 #define UART_BDL_REG(base) ((base)->BDL)
Kojto 90:cb3d968589d8 12638 #define UART_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 12639 #define UART_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 12640 #define UART_S1_REG(base) ((base)->S1)
Kojto 90:cb3d968589d8 12641 #define UART_S2_REG(base) ((base)->S2)
Kojto 90:cb3d968589d8 12642 #define UART_C3_REG(base) ((base)->C3)
Kojto 90:cb3d968589d8 12643 #define UART_D_REG(base) ((base)->D)
Kojto 90:cb3d968589d8 12644 #define UART_MA1_REG(base) ((base)->MA1)
Kojto 90:cb3d968589d8 12645 #define UART_MA2_REG(base) ((base)->MA2)
Kojto 90:cb3d968589d8 12646 #define UART_C4_REG(base) ((base)->C4)
Kojto 90:cb3d968589d8 12647 #define UART_C5_REG(base) ((base)->C5)
Kojto 90:cb3d968589d8 12648 #define UART_ED_REG(base) ((base)->ED)
Kojto 90:cb3d968589d8 12649 #define UART_MODEM_REG(base) ((base)->MODEM)
Kojto 90:cb3d968589d8 12650 #define UART_IR_REG(base) ((base)->IR)
Kojto 90:cb3d968589d8 12651 #define UART_PFIFO_REG(base) ((base)->PFIFO)
Kojto 90:cb3d968589d8 12652 #define UART_CFIFO_REG(base) ((base)->CFIFO)
Kojto 90:cb3d968589d8 12653 #define UART_SFIFO_REG(base) ((base)->SFIFO)
Kojto 90:cb3d968589d8 12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
Kojto 90:cb3d968589d8 12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
Kojto 90:cb3d968589d8 12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
Kojto 90:cb3d968589d8 12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
Kojto 90:cb3d968589d8 12658 #define UART_C7816_REG(base) ((base)->C7816)
Kojto 90:cb3d968589d8 12659 #define UART_IE7816_REG(base) ((base)->IE7816)
Kojto 90:cb3d968589d8 12660 #define UART_IS7816_REG(base) ((base)->IS7816)
Kojto 90:cb3d968589d8 12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0)
Kojto 90:cb3d968589d8 12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1)
Kojto 90:cb3d968589d8 12663 #define UART_WN7816_REG(base) ((base)->WN7816)
Kojto 90:cb3d968589d8 12664 #define UART_WF7816_REG(base) ((base)->WF7816)
Kojto 90:cb3d968589d8 12665 #define UART_ET7816_REG(base) ((base)->ET7816)
Kojto 90:cb3d968589d8 12666 #define UART_TL7816_REG(base) ((base)->TL7816)
Kojto 90:cb3d968589d8 12667
Kojto 90:cb3d968589d8 12668 /*!
Kojto 90:cb3d968589d8 12669 * @}
Kojto 90:cb3d968589d8 12670 */ /* end of group UART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 12671
Kojto 90:cb3d968589d8 12672
Kojto 90:cb3d968589d8 12673 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 12674 -- UART Register Masks
Kojto 90:cb3d968589d8 12675 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 12676
Kojto 90:cb3d968589d8 12677 /*!
Kojto 90:cb3d968589d8 12678 * @addtogroup UART_Register_Masks UART Register Masks
Kojto 90:cb3d968589d8 12679 * @{
Kojto 90:cb3d968589d8 12680 */
Kojto 90:cb3d968589d8 12681
Kojto 90:cb3d968589d8 12682 /* BDH Bit Fields */
Kojto 90:cb3d968589d8 12683 #define UART_BDH_SBR_MASK 0x1Fu
Kojto 90:cb3d968589d8 12684 #define UART_BDH_SBR_SHIFT 0
Kojto 90:cb3d968589d8 12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
Kojto 90:cb3d968589d8 12686 #define UART_BDH_SBNS_MASK 0x20u
Kojto 90:cb3d968589d8 12687 #define UART_BDH_SBNS_SHIFT 5
Kojto 90:cb3d968589d8 12688 #define UART_BDH_RXEDGIE_MASK 0x40u
Kojto 90:cb3d968589d8 12689 #define UART_BDH_RXEDGIE_SHIFT 6
Kojto 90:cb3d968589d8 12690 #define UART_BDH_LBKDIE_MASK 0x80u
Kojto 90:cb3d968589d8 12691 #define UART_BDH_LBKDIE_SHIFT 7
Kojto 90:cb3d968589d8 12692 /* BDL Bit Fields */
Kojto 90:cb3d968589d8 12693 #define UART_BDL_SBR_MASK 0xFFu
Kojto 90:cb3d968589d8 12694 #define UART_BDL_SBR_SHIFT 0
Kojto 90:cb3d968589d8 12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
Kojto 90:cb3d968589d8 12696 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 12697 #define UART_C1_PT_MASK 0x1u
Kojto 90:cb3d968589d8 12698 #define UART_C1_PT_SHIFT 0
Kojto 90:cb3d968589d8 12699 #define UART_C1_PE_MASK 0x2u
Kojto 90:cb3d968589d8 12700 #define UART_C1_PE_SHIFT 1
Kojto 90:cb3d968589d8 12701 #define UART_C1_ILT_MASK 0x4u
Kojto 90:cb3d968589d8 12702 #define UART_C1_ILT_SHIFT 2
Kojto 90:cb3d968589d8 12703 #define UART_C1_WAKE_MASK 0x8u
Kojto 90:cb3d968589d8 12704 #define UART_C1_WAKE_SHIFT 3
Kojto 90:cb3d968589d8 12705 #define UART_C1_M_MASK 0x10u
Kojto 90:cb3d968589d8 12706 #define UART_C1_M_SHIFT 4
Kojto 90:cb3d968589d8 12707 #define UART_C1_RSRC_MASK 0x20u
Kojto 90:cb3d968589d8 12708 #define UART_C1_RSRC_SHIFT 5
Kojto 90:cb3d968589d8 12709 #define UART_C1_UARTSWAI_MASK 0x40u
Kojto 90:cb3d968589d8 12710 #define UART_C1_UARTSWAI_SHIFT 6
Kojto 90:cb3d968589d8 12711 #define UART_C1_LOOPS_MASK 0x80u
Kojto 90:cb3d968589d8 12712 #define UART_C1_LOOPS_SHIFT 7
Kojto 90:cb3d968589d8 12713 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 12714 #define UART_C2_SBK_MASK 0x1u
Kojto 90:cb3d968589d8 12715 #define UART_C2_SBK_SHIFT 0
Kojto 90:cb3d968589d8 12716 #define UART_C2_RWU_MASK 0x2u
Kojto 90:cb3d968589d8 12717 #define UART_C2_RWU_SHIFT 1
Kojto 90:cb3d968589d8 12718 #define UART_C2_RE_MASK 0x4u
Kojto 90:cb3d968589d8 12719 #define UART_C2_RE_SHIFT 2
Kojto 90:cb3d968589d8 12720 #define UART_C2_TE_MASK 0x8u
Kojto 90:cb3d968589d8 12721 #define UART_C2_TE_SHIFT 3
Kojto 90:cb3d968589d8 12722 #define UART_C2_ILIE_MASK 0x10u
Kojto 90:cb3d968589d8 12723 #define UART_C2_ILIE_SHIFT 4
Kojto 90:cb3d968589d8 12724 #define UART_C2_RIE_MASK 0x20u
Kojto 90:cb3d968589d8 12725 #define UART_C2_RIE_SHIFT 5
Kojto 90:cb3d968589d8 12726 #define UART_C2_TCIE_MASK 0x40u
Kojto 90:cb3d968589d8 12727 #define UART_C2_TCIE_SHIFT 6
Kojto 90:cb3d968589d8 12728 #define UART_C2_TIE_MASK 0x80u
Kojto 90:cb3d968589d8 12729 #define UART_C2_TIE_SHIFT 7
Kojto 90:cb3d968589d8 12730 /* S1 Bit Fields */
Kojto 90:cb3d968589d8 12731 #define UART_S1_PF_MASK 0x1u
Kojto 90:cb3d968589d8 12732 #define UART_S1_PF_SHIFT 0
Kojto 90:cb3d968589d8 12733 #define UART_S1_FE_MASK 0x2u
Kojto 90:cb3d968589d8 12734 #define UART_S1_FE_SHIFT 1
Kojto 90:cb3d968589d8 12735 #define UART_S1_NF_MASK 0x4u
Kojto 90:cb3d968589d8 12736 #define UART_S1_NF_SHIFT 2
Kojto 90:cb3d968589d8 12737 #define UART_S1_OR_MASK 0x8u
Kojto 90:cb3d968589d8 12738 #define UART_S1_OR_SHIFT 3
Kojto 90:cb3d968589d8 12739 #define UART_S1_IDLE_MASK 0x10u
Kojto 90:cb3d968589d8 12740 #define UART_S1_IDLE_SHIFT 4
Kojto 90:cb3d968589d8 12741 #define UART_S1_RDRF_MASK 0x20u
Kojto 90:cb3d968589d8 12742 #define UART_S1_RDRF_SHIFT 5
Kojto 90:cb3d968589d8 12743 #define UART_S1_TC_MASK 0x40u
Kojto 90:cb3d968589d8 12744 #define UART_S1_TC_SHIFT 6
Kojto 90:cb3d968589d8 12745 #define UART_S1_TDRE_MASK 0x80u
Kojto 90:cb3d968589d8 12746 #define UART_S1_TDRE_SHIFT 7
Kojto 90:cb3d968589d8 12747 /* S2 Bit Fields */
Kojto 90:cb3d968589d8 12748 #define UART_S2_RAF_MASK 0x1u
Kojto 90:cb3d968589d8 12749 #define UART_S2_RAF_SHIFT 0
Kojto 90:cb3d968589d8 12750 #define UART_S2_LBKDE_MASK 0x2u
Kojto 90:cb3d968589d8 12751 #define UART_S2_LBKDE_SHIFT 1
Kojto 90:cb3d968589d8 12752 #define UART_S2_BRK13_MASK 0x4u
Kojto 90:cb3d968589d8 12753 #define UART_S2_BRK13_SHIFT 2
Kojto 90:cb3d968589d8 12754 #define UART_S2_RWUID_MASK 0x8u
Kojto 90:cb3d968589d8 12755 #define UART_S2_RWUID_SHIFT 3
Kojto 90:cb3d968589d8 12756 #define UART_S2_RXINV_MASK 0x10u
Kojto 90:cb3d968589d8 12757 #define UART_S2_RXINV_SHIFT 4
Kojto 90:cb3d968589d8 12758 #define UART_S2_MSBF_MASK 0x20u
Kojto 90:cb3d968589d8 12759 #define UART_S2_MSBF_SHIFT 5
Kojto 90:cb3d968589d8 12760 #define UART_S2_RXEDGIF_MASK 0x40u
Kojto 90:cb3d968589d8 12761 #define UART_S2_RXEDGIF_SHIFT 6
Kojto 90:cb3d968589d8 12762 #define UART_S2_LBKDIF_MASK 0x80u
Kojto 90:cb3d968589d8 12763 #define UART_S2_LBKDIF_SHIFT 7
Kojto 90:cb3d968589d8 12764 /* C3 Bit Fields */
Kojto 90:cb3d968589d8 12765 #define UART_C3_PEIE_MASK 0x1u
Kojto 90:cb3d968589d8 12766 #define UART_C3_PEIE_SHIFT 0
Kojto 90:cb3d968589d8 12767 #define UART_C3_FEIE_MASK 0x2u
Kojto 90:cb3d968589d8 12768 #define UART_C3_FEIE_SHIFT 1
Kojto 90:cb3d968589d8 12769 #define UART_C3_NEIE_MASK 0x4u
Kojto 90:cb3d968589d8 12770 #define UART_C3_NEIE_SHIFT 2
Kojto 90:cb3d968589d8 12771 #define UART_C3_ORIE_MASK 0x8u
Kojto 90:cb3d968589d8 12772 #define UART_C3_ORIE_SHIFT 3
Kojto 90:cb3d968589d8 12773 #define UART_C3_TXINV_MASK 0x10u
Kojto 90:cb3d968589d8 12774 #define UART_C3_TXINV_SHIFT 4
Kojto 90:cb3d968589d8 12775 #define UART_C3_TXDIR_MASK 0x20u
Kojto 90:cb3d968589d8 12776 #define UART_C3_TXDIR_SHIFT 5
Kojto 90:cb3d968589d8 12777 #define UART_C3_T8_MASK 0x40u
Kojto 90:cb3d968589d8 12778 #define UART_C3_T8_SHIFT 6
Kojto 90:cb3d968589d8 12779 #define UART_C3_R8_MASK 0x80u
Kojto 90:cb3d968589d8 12780 #define UART_C3_R8_SHIFT 7
Kojto 90:cb3d968589d8 12781 /* D Bit Fields */
Kojto 90:cb3d968589d8 12782 #define UART_D_RT_MASK 0xFFu
Kojto 90:cb3d968589d8 12783 #define UART_D_RT_SHIFT 0
Kojto 90:cb3d968589d8 12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
Kojto 90:cb3d968589d8 12785 /* MA1 Bit Fields */
Kojto 90:cb3d968589d8 12786 #define UART_MA1_MA_MASK 0xFFu
Kojto 90:cb3d968589d8 12787 #define UART_MA1_MA_SHIFT 0
Kojto 90:cb3d968589d8 12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
Kojto 90:cb3d968589d8 12789 /* MA2 Bit Fields */
Kojto 90:cb3d968589d8 12790 #define UART_MA2_MA_MASK 0xFFu
Kojto 90:cb3d968589d8 12791 #define UART_MA2_MA_SHIFT 0
Kojto 90:cb3d968589d8 12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
Kojto 90:cb3d968589d8 12793 /* C4 Bit Fields */
Kojto 90:cb3d968589d8 12794 #define UART_C4_BRFA_MASK 0x1Fu
Kojto 90:cb3d968589d8 12795 #define UART_C4_BRFA_SHIFT 0
Kojto 90:cb3d968589d8 12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
Kojto 90:cb3d968589d8 12797 #define UART_C4_M10_MASK 0x20u
Kojto 90:cb3d968589d8 12798 #define UART_C4_M10_SHIFT 5
Kojto 90:cb3d968589d8 12799 #define UART_C4_MAEN2_MASK 0x40u
Kojto 90:cb3d968589d8 12800 #define UART_C4_MAEN2_SHIFT 6
Kojto 90:cb3d968589d8 12801 #define UART_C4_MAEN1_MASK 0x80u
Kojto 90:cb3d968589d8 12802 #define UART_C4_MAEN1_SHIFT 7
Kojto 90:cb3d968589d8 12803 /* C5 Bit Fields */
Kojto 90:cb3d968589d8 12804 #define UART_C5_LBKDDMAS_MASK 0x8u
Kojto 90:cb3d968589d8 12805 #define UART_C5_LBKDDMAS_SHIFT 3
Kojto 90:cb3d968589d8 12806 #define UART_C5_ILDMAS_MASK 0x10u
Kojto 90:cb3d968589d8 12807 #define UART_C5_ILDMAS_SHIFT 4
Kojto 90:cb3d968589d8 12808 #define UART_C5_RDMAS_MASK 0x20u
Kojto 90:cb3d968589d8 12809 #define UART_C5_RDMAS_SHIFT 5
Kojto 90:cb3d968589d8 12810 #define UART_C5_TCDMAS_MASK 0x40u
Kojto 90:cb3d968589d8 12811 #define UART_C5_TCDMAS_SHIFT 6
Kojto 90:cb3d968589d8 12812 #define UART_C5_TDMAS_MASK 0x80u
Kojto 90:cb3d968589d8 12813 #define UART_C5_TDMAS_SHIFT 7
Kojto 90:cb3d968589d8 12814 /* ED Bit Fields */
Kojto 90:cb3d968589d8 12815 #define UART_ED_PARITYE_MASK 0x40u
Kojto 90:cb3d968589d8 12816 #define UART_ED_PARITYE_SHIFT 6
Kojto 90:cb3d968589d8 12817 #define UART_ED_NOISY_MASK 0x80u
Kojto 90:cb3d968589d8 12818 #define UART_ED_NOISY_SHIFT 7
Kojto 90:cb3d968589d8 12819 /* MODEM Bit Fields */
Kojto 90:cb3d968589d8 12820 #define UART_MODEM_TXCTSE_MASK 0x1u
Kojto 90:cb3d968589d8 12821 #define UART_MODEM_TXCTSE_SHIFT 0
Kojto 90:cb3d968589d8 12822 #define UART_MODEM_TXRTSE_MASK 0x2u
Kojto 90:cb3d968589d8 12823 #define UART_MODEM_TXRTSE_SHIFT 1
Kojto 90:cb3d968589d8 12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u
Kojto 90:cb3d968589d8 12825 #define UART_MODEM_TXRTSPOL_SHIFT 2
Kojto 90:cb3d968589d8 12826 #define UART_MODEM_RXRTSE_MASK 0x8u
Kojto 90:cb3d968589d8 12827 #define UART_MODEM_RXRTSE_SHIFT 3
Kojto 90:cb3d968589d8 12828 /* IR Bit Fields */
Kojto 90:cb3d968589d8 12829 #define UART_IR_TNP_MASK 0x3u
Kojto 90:cb3d968589d8 12830 #define UART_IR_TNP_SHIFT 0
Kojto 90:cb3d968589d8 12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
Kojto 90:cb3d968589d8 12832 #define UART_IR_IREN_MASK 0x4u
Kojto 90:cb3d968589d8 12833 #define UART_IR_IREN_SHIFT 2
Kojto 90:cb3d968589d8 12834 /* PFIFO Bit Fields */
Kojto 90:cb3d968589d8 12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
Kojto 90:cb3d968589d8 12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
Kojto 90:cb3d968589d8 12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
Kojto 90:cb3d968589d8 12838 #define UART_PFIFO_RXFE_MASK 0x8u
Kojto 90:cb3d968589d8 12839 #define UART_PFIFO_RXFE_SHIFT 3
Kojto 90:cb3d968589d8 12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
Kojto 90:cb3d968589d8 12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
Kojto 90:cb3d968589d8 12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
Kojto 90:cb3d968589d8 12843 #define UART_PFIFO_TXFE_MASK 0x80u
Kojto 90:cb3d968589d8 12844 #define UART_PFIFO_TXFE_SHIFT 7
Kojto 90:cb3d968589d8 12845 /* CFIFO Bit Fields */
Kojto 90:cb3d968589d8 12846 #define UART_CFIFO_RXUFE_MASK 0x1u
Kojto 90:cb3d968589d8 12847 #define UART_CFIFO_RXUFE_SHIFT 0
Kojto 90:cb3d968589d8 12848 #define UART_CFIFO_TXOFE_MASK 0x2u
Kojto 90:cb3d968589d8 12849 #define UART_CFIFO_TXOFE_SHIFT 1
Kojto 90:cb3d968589d8 12850 #define UART_CFIFO_RXOFE_MASK 0x4u
Kojto 90:cb3d968589d8 12851 #define UART_CFIFO_RXOFE_SHIFT 2
Kojto 90:cb3d968589d8 12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u
Kojto 90:cb3d968589d8 12853 #define UART_CFIFO_RXFLUSH_SHIFT 6
Kojto 90:cb3d968589d8 12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u
Kojto 90:cb3d968589d8 12855 #define UART_CFIFO_TXFLUSH_SHIFT 7
Kojto 90:cb3d968589d8 12856 /* SFIFO Bit Fields */
Kojto 90:cb3d968589d8 12857 #define UART_SFIFO_RXUF_MASK 0x1u
Kojto 90:cb3d968589d8 12858 #define UART_SFIFO_RXUF_SHIFT 0
Kojto 90:cb3d968589d8 12859 #define UART_SFIFO_TXOF_MASK 0x2u
Kojto 90:cb3d968589d8 12860 #define UART_SFIFO_TXOF_SHIFT 1
Kojto 90:cb3d968589d8 12861 #define UART_SFIFO_RXOF_MASK 0x4u
Kojto 90:cb3d968589d8 12862 #define UART_SFIFO_RXOF_SHIFT 2
Kojto 90:cb3d968589d8 12863 #define UART_SFIFO_RXEMPT_MASK 0x40u
Kojto 90:cb3d968589d8 12864 #define UART_SFIFO_RXEMPT_SHIFT 6
Kojto 90:cb3d968589d8 12865 #define UART_SFIFO_TXEMPT_MASK 0x80u
Kojto 90:cb3d968589d8 12866 #define UART_SFIFO_TXEMPT_SHIFT 7
Kojto 90:cb3d968589d8 12867 /* TWFIFO Bit Fields */
Kojto 90:cb3d968589d8 12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu
Kojto 90:cb3d968589d8 12869 #define UART_TWFIFO_TXWATER_SHIFT 0
Kojto 90:cb3d968589d8 12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
Kojto 90:cb3d968589d8 12871 /* TCFIFO Bit Fields */
Kojto 90:cb3d968589d8 12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
Kojto 90:cb3d968589d8 12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0
Kojto 90:cb3d968589d8 12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
Kojto 90:cb3d968589d8 12875 /* RWFIFO Bit Fields */
Kojto 90:cb3d968589d8 12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu
Kojto 90:cb3d968589d8 12877 #define UART_RWFIFO_RXWATER_SHIFT 0
Kojto 90:cb3d968589d8 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
Kojto 90:cb3d968589d8 12879 /* RCFIFO Bit Fields */
Kojto 90:cb3d968589d8 12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
Kojto 90:cb3d968589d8 12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0
Kojto 90:cb3d968589d8 12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
Kojto 90:cb3d968589d8 12883 /* C7816 Bit Fields */
Kojto 90:cb3d968589d8 12884 #define UART_C7816_ISO_7816E_MASK 0x1u
Kojto 90:cb3d968589d8 12885 #define UART_C7816_ISO_7816E_SHIFT 0
Kojto 90:cb3d968589d8 12886 #define UART_C7816_TTYPE_MASK 0x2u
Kojto 90:cb3d968589d8 12887 #define UART_C7816_TTYPE_SHIFT 1
Kojto 90:cb3d968589d8 12888 #define UART_C7816_INIT_MASK 0x4u
Kojto 90:cb3d968589d8 12889 #define UART_C7816_INIT_SHIFT 2
Kojto 90:cb3d968589d8 12890 #define UART_C7816_ANACK_MASK 0x8u
Kojto 90:cb3d968589d8 12891 #define UART_C7816_ANACK_SHIFT 3
Kojto 90:cb3d968589d8 12892 #define UART_C7816_ONACK_MASK 0x10u
Kojto 90:cb3d968589d8 12893 #define UART_C7816_ONACK_SHIFT 4
Kojto 90:cb3d968589d8 12894 /* IE7816 Bit Fields */
Kojto 90:cb3d968589d8 12895 #define UART_IE7816_RXTE_MASK 0x1u
Kojto 90:cb3d968589d8 12896 #define UART_IE7816_RXTE_SHIFT 0
Kojto 90:cb3d968589d8 12897 #define UART_IE7816_TXTE_MASK 0x2u
Kojto 90:cb3d968589d8 12898 #define UART_IE7816_TXTE_SHIFT 1
Kojto 90:cb3d968589d8 12899 #define UART_IE7816_GTVE_MASK 0x4u
Kojto 90:cb3d968589d8 12900 #define UART_IE7816_GTVE_SHIFT 2
Kojto 90:cb3d968589d8 12901 #define UART_IE7816_INITDE_MASK 0x10u
Kojto 90:cb3d968589d8 12902 #define UART_IE7816_INITDE_SHIFT 4
Kojto 90:cb3d968589d8 12903 #define UART_IE7816_BWTE_MASK 0x20u
Kojto 90:cb3d968589d8 12904 #define UART_IE7816_BWTE_SHIFT 5
Kojto 90:cb3d968589d8 12905 #define UART_IE7816_CWTE_MASK 0x40u
Kojto 90:cb3d968589d8 12906 #define UART_IE7816_CWTE_SHIFT 6
Kojto 90:cb3d968589d8 12907 #define UART_IE7816_WTE_MASK 0x80u
Kojto 90:cb3d968589d8 12908 #define UART_IE7816_WTE_SHIFT 7
Kojto 90:cb3d968589d8 12909 /* IS7816 Bit Fields */
Kojto 90:cb3d968589d8 12910 #define UART_IS7816_RXT_MASK 0x1u
Kojto 90:cb3d968589d8 12911 #define UART_IS7816_RXT_SHIFT 0
Kojto 90:cb3d968589d8 12912 #define UART_IS7816_TXT_MASK 0x2u
Kojto 90:cb3d968589d8 12913 #define UART_IS7816_TXT_SHIFT 1
Kojto 90:cb3d968589d8 12914 #define UART_IS7816_GTV_MASK 0x4u
Kojto 90:cb3d968589d8 12915 #define UART_IS7816_GTV_SHIFT 2
Kojto 90:cb3d968589d8 12916 #define UART_IS7816_INITD_MASK 0x10u
Kojto 90:cb3d968589d8 12917 #define UART_IS7816_INITD_SHIFT 4
Kojto 90:cb3d968589d8 12918 #define UART_IS7816_BWT_MASK 0x20u
Kojto 90:cb3d968589d8 12919 #define UART_IS7816_BWT_SHIFT 5
Kojto 90:cb3d968589d8 12920 #define UART_IS7816_CWT_MASK 0x40u
Kojto 90:cb3d968589d8 12921 #define UART_IS7816_CWT_SHIFT 6
Kojto 90:cb3d968589d8 12922 #define UART_IS7816_WT_MASK 0x80u
Kojto 90:cb3d968589d8 12923 #define UART_IS7816_WT_SHIFT 7
Kojto 90:cb3d968589d8 12924 /* WP7816T0 Bit Fields */
Kojto 90:cb3d968589d8 12925 #define UART_WP7816T0_WI_MASK 0xFFu
Kojto 90:cb3d968589d8 12926 #define UART_WP7816T0_WI_SHIFT 0
Kojto 90:cb3d968589d8 12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
Kojto 90:cb3d968589d8 12928 /* WP7816T1 Bit Fields */
Kojto 90:cb3d968589d8 12929 #define UART_WP7816T1_BWI_MASK 0xFu
Kojto 90:cb3d968589d8 12930 #define UART_WP7816T1_BWI_SHIFT 0
Kojto 90:cb3d968589d8 12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
Kojto 90:cb3d968589d8 12932 #define UART_WP7816T1_CWI_MASK 0xF0u
Kojto 90:cb3d968589d8 12933 #define UART_WP7816T1_CWI_SHIFT 4
Kojto 90:cb3d968589d8 12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
Kojto 90:cb3d968589d8 12935 /* WN7816 Bit Fields */
Kojto 90:cb3d968589d8 12936 #define UART_WN7816_GTN_MASK 0xFFu
Kojto 90:cb3d968589d8 12937 #define UART_WN7816_GTN_SHIFT 0
Kojto 90:cb3d968589d8 12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
Kojto 90:cb3d968589d8 12939 /* WF7816 Bit Fields */
Kojto 90:cb3d968589d8 12940 #define UART_WF7816_GTFD_MASK 0xFFu
Kojto 90:cb3d968589d8 12941 #define UART_WF7816_GTFD_SHIFT 0
Kojto 90:cb3d968589d8 12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
Kojto 90:cb3d968589d8 12943 /* ET7816 Bit Fields */
Kojto 90:cb3d968589d8 12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
Kojto 90:cb3d968589d8 12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
Kojto 90:cb3d968589d8 12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
Kojto 90:cb3d968589d8 12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
Kojto 90:cb3d968589d8 12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
Kojto 90:cb3d968589d8 12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
Kojto 90:cb3d968589d8 12950 /* TL7816 Bit Fields */
Kojto 90:cb3d968589d8 12951 #define UART_TL7816_TLEN_MASK 0xFFu
Kojto 90:cb3d968589d8 12952 #define UART_TL7816_TLEN_SHIFT 0
Kojto 90:cb3d968589d8 12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
Kojto 90:cb3d968589d8 12954
Kojto 90:cb3d968589d8 12955 /*!
Kojto 90:cb3d968589d8 12956 * @}
Kojto 90:cb3d968589d8 12957 */ /* end of group UART_Register_Masks */
Kojto 90:cb3d968589d8 12958
Kojto 90:cb3d968589d8 12959
Kojto 90:cb3d968589d8 12960 /* UART - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 12961 /** Peripheral UART0 base address */
Kojto 90:cb3d968589d8 12962 #define UART0_BASE (0x4006A000u)
Kojto 90:cb3d968589d8 12963 /** Peripheral UART0 base pointer */
Kojto 90:cb3d968589d8 12964 #define UART0 ((UART_Type *)UART0_BASE)
Kojto 90:cb3d968589d8 12965 #define UART0_BASE_PTR (UART0)
Kojto 90:cb3d968589d8 12966 /** Peripheral UART1 base address */
Kojto 90:cb3d968589d8 12967 #define UART1_BASE (0x4006B000u)
Kojto 90:cb3d968589d8 12968 /** Peripheral UART1 base pointer */
Kojto 90:cb3d968589d8 12969 #define UART1 ((UART_Type *)UART1_BASE)
Kojto 90:cb3d968589d8 12970 #define UART1_BASE_PTR (UART1)
Kojto 90:cb3d968589d8 12971 /** Peripheral UART2 base address */
Kojto 90:cb3d968589d8 12972 #define UART2_BASE (0x4006C000u)
Kojto 90:cb3d968589d8 12973 /** Peripheral UART2 base pointer */
Kojto 90:cb3d968589d8 12974 #define UART2 ((UART_Type *)UART2_BASE)
Kojto 90:cb3d968589d8 12975 #define UART2_BASE_PTR (UART2)
Kojto 90:cb3d968589d8 12976 /** Peripheral UART3 base address */
Kojto 90:cb3d968589d8 12977 #define UART3_BASE (0x4006D000u)
Kojto 90:cb3d968589d8 12978 /** Peripheral UART3 base pointer */
Kojto 90:cb3d968589d8 12979 #define UART3 ((UART_Type *)UART3_BASE)
Kojto 90:cb3d968589d8 12980 #define UART3_BASE_PTR (UART3)
Kojto 90:cb3d968589d8 12981 /** Peripheral UART4 base address */
Kojto 90:cb3d968589d8 12982 #define UART4_BASE (0x400EA000u)
Kojto 90:cb3d968589d8 12983 /** Peripheral UART4 base pointer */
Kojto 90:cb3d968589d8 12984 #define UART4 ((UART_Type *)UART4_BASE)
Kojto 90:cb3d968589d8 12985 #define UART4_BASE_PTR (UART4)
Kojto 90:cb3d968589d8 12986 /** Peripheral UART5 base address */
Kojto 90:cb3d968589d8 12987 #define UART5_BASE (0x400EB000u)
Kojto 90:cb3d968589d8 12988 /** Peripheral UART5 base pointer */
Kojto 90:cb3d968589d8 12989 #define UART5 ((UART_Type *)UART5_BASE)
Kojto 90:cb3d968589d8 12990 #define UART5_BASE_PTR (UART5)
Kojto 90:cb3d968589d8 12991 /** Array initializer of UART peripheral base addresses */
Kojto 90:cb3d968589d8 12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
Kojto 90:cb3d968589d8 12993 /** Array initializer of UART peripheral base pointers */
Kojto 90:cb3d968589d8 12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
Kojto 90:cb3d968589d8 12995 /** Interrupt vectors for the UART peripheral type */
Kojto 90:cb3d968589d8 12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
Kojto 90:cb3d968589d8 12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
Kojto 90:cb3d968589d8 12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
Kojto 90:cb3d968589d8 12999
Kojto 90:cb3d968589d8 13000 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13001 -- UART - Register accessor macros
Kojto 90:cb3d968589d8 13002 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13003
Kojto 90:cb3d968589d8 13004 /*!
Kojto 90:cb3d968589d8 13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Kojto 90:cb3d968589d8 13006 * @{
Kojto 90:cb3d968589d8 13007 */
Kojto 90:cb3d968589d8 13008
Kojto 90:cb3d968589d8 13009
Kojto 90:cb3d968589d8 13010 /* UART - Register instance definitions */
Kojto 90:cb3d968589d8 13011 /* UART0 */
Kojto 90:cb3d968589d8 13012 #define UART0_BDH UART_BDH_REG(UART0)
Kojto 90:cb3d968589d8 13013 #define UART0_BDL UART_BDL_REG(UART0)
Kojto 90:cb3d968589d8 13014 #define UART0_C1 UART_C1_REG(UART0)
Kojto 90:cb3d968589d8 13015 #define UART0_C2 UART_C2_REG(UART0)
Kojto 90:cb3d968589d8 13016 #define UART0_S1 UART_S1_REG(UART0)
Kojto 90:cb3d968589d8 13017 #define UART0_S2 UART_S2_REG(UART0)
Kojto 90:cb3d968589d8 13018 #define UART0_C3 UART_C3_REG(UART0)
Kojto 90:cb3d968589d8 13019 #define UART0_D UART_D_REG(UART0)
Kojto 90:cb3d968589d8 13020 #define UART0_MA1 UART_MA1_REG(UART0)
Kojto 90:cb3d968589d8 13021 #define UART0_MA2 UART_MA2_REG(UART0)
Kojto 90:cb3d968589d8 13022 #define UART0_C4 UART_C4_REG(UART0)
Kojto 90:cb3d968589d8 13023 #define UART0_C5 UART_C5_REG(UART0)
Kojto 90:cb3d968589d8 13024 #define UART0_ED UART_ED_REG(UART0)
Kojto 90:cb3d968589d8 13025 #define UART0_MODEM UART_MODEM_REG(UART0)
Kojto 90:cb3d968589d8 13026 #define UART0_IR UART_IR_REG(UART0)
Kojto 90:cb3d968589d8 13027 #define UART0_PFIFO UART_PFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13028 #define UART0_CFIFO UART_CFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13029 #define UART0_SFIFO UART_SFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
Kojto 90:cb3d968589d8 13034 #define UART0_C7816 UART_C7816_REG(UART0)
Kojto 90:cb3d968589d8 13035 #define UART0_IE7816 UART_IE7816_REG(UART0)
Kojto 90:cb3d968589d8 13036 #define UART0_IS7816 UART_IS7816_REG(UART0)
Kojto 90:cb3d968589d8 13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
Kojto 90:cb3d968589d8 13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
Kojto 90:cb3d968589d8 13039 #define UART0_WN7816 UART_WN7816_REG(UART0)
Kojto 90:cb3d968589d8 13040 #define UART0_WF7816 UART_WF7816_REG(UART0)
Kojto 90:cb3d968589d8 13041 #define UART0_ET7816 UART_ET7816_REG(UART0)
Kojto 90:cb3d968589d8 13042 #define UART0_TL7816 UART_TL7816_REG(UART0)
Kojto 90:cb3d968589d8 13043 /* UART1 */
Kojto 90:cb3d968589d8 13044 #define UART1_BDH UART_BDH_REG(UART1)
Kojto 90:cb3d968589d8 13045 #define UART1_BDL UART_BDL_REG(UART1)
Kojto 90:cb3d968589d8 13046 #define UART1_C1 UART_C1_REG(UART1)
Kojto 90:cb3d968589d8 13047 #define UART1_C2 UART_C2_REG(UART1)
Kojto 90:cb3d968589d8 13048 #define UART1_S1 UART_S1_REG(UART1)
Kojto 90:cb3d968589d8 13049 #define UART1_S2 UART_S2_REG(UART1)
Kojto 90:cb3d968589d8 13050 #define UART1_C3 UART_C3_REG(UART1)
Kojto 90:cb3d968589d8 13051 #define UART1_D UART_D_REG(UART1)
Kojto 90:cb3d968589d8 13052 #define UART1_MA1 UART_MA1_REG(UART1)
Kojto 90:cb3d968589d8 13053 #define UART1_MA2 UART_MA2_REG(UART1)
Kojto 90:cb3d968589d8 13054 #define UART1_C4 UART_C4_REG(UART1)
Kojto 90:cb3d968589d8 13055 #define UART1_C5 UART_C5_REG(UART1)
Kojto 90:cb3d968589d8 13056 #define UART1_ED UART_ED_REG(UART1)
Kojto 90:cb3d968589d8 13057 #define UART1_MODEM UART_MODEM_REG(UART1)
Kojto 90:cb3d968589d8 13058 #define UART1_IR UART_IR_REG(UART1)
Kojto 90:cb3d968589d8 13059 #define UART1_PFIFO UART_PFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13060 #define UART1_CFIFO UART_CFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13061 #define UART1_SFIFO UART_SFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
Kojto 90:cb3d968589d8 13066 /* UART2 */
Kojto 90:cb3d968589d8 13067 #define UART2_BDH UART_BDH_REG(UART2)
Kojto 90:cb3d968589d8 13068 #define UART2_BDL UART_BDL_REG(UART2)
Kojto 90:cb3d968589d8 13069 #define UART2_C1 UART_C1_REG(UART2)
Kojto 90:cb3d968589d8 13070 #define UART2_C2 UART_C2_REG(UART2)
Kojto 90:cb3d968589d8 13071 #define UART2_S1 UART_S1_REG(UART2)
Kojto 90:cb3d968589d8 13072 #define UART2_S2 UART_S2_REG(UART2)
Kojto 90:cb3d968589d8 13073 #define UART2_C3 UART_C3_REG(UART2)
Kojto 90:cb3d968589d8 13074 #define UART2_D UART_D_REG(UART2)
Kojto 90:cb3d968589d8 13075 #define UART2_MA1 UART_MA1_REG(UART2)
Kojto 90:cb3d968589d8 13076 #define UART2_MA2 UART_MA2_REG(UART2)
Kojto 90:cb3d968589d8 13077 #define UART2_C4 UART_C4_REG(UART2)
Kojto 90:cb3d968589d8 13078 #define UART2_C5 UART_C5_REG(UART2)
Kojto 90:cb3d968589d8 13079 #define UART2_ED UART_ED_REG(UART2)
Kojto 90:cb3d968589d8 13080 #define UART2_MODEM UART_MODEM_REG(UART2)
Kojto 90:cb3d968589d8 13081 #define UART2_IR UART_IR_REG(UART2)
Kojto 90:cb3d968589d8 13082 #define UART2_PFIFO UART_PFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13083 #define UART2_CFIFO UART_CFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13084 #define UART2_SFIFO UART_SFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
Kojto 90:cb3d968589d8 13089 /* UART3 */
Kojto 90:cb3d968589d8 13090 #define UART3_BDH UART_BDH_REG(UART3)
Kojto 90:cb3d968589d8 13091 #define UART3_BDL UART_BDL_REG(UART3)
Kojto 90:cb3d968589d8 13092 #define UART3_C1 UART_C1_REG(UART3)
Kojto 90:cb3d968589d8 13093 #define UART3_C2 UART_C2_REG(UART3)
Kojto 90:cb3d968589d8 13094 #define UART3_S1 UART_S1_REG(UART3)
Kojto 90:cb3d968589d8 13095 #define UART3_S2 UART_S2_REG(UART3)
Kojto 90:cb3d968589d8 13096 #define UART3_C3 UART_C3_REG(UART3)
Kojto 90:cb3d968589d8 13097 #define UART3_D UART_D_REG(UART3)
Kojto 90:cb3d968589d8 13098 #define UART3_MA1 UART_MA1_REG(UART3)
Kojto 90:cb3d968589d8 13099 #define UART3_MA2 UART_MA2_REG(UART3)
Kojto 90:cb3d968589d8 13100 #define UART3_C4 UART_C4_REG(UART3)
Kojto 90:cb3d968589d8 13101 #define UART3_C5 UART_C5_REG(UART3)
Kojto 90:cb3d968589d8 13102 #define UART3_ED UART_ED_REG(UART3)
Kojto 90:cb3d968589d8 13103 #define UART3_MODEM UART_MODEM_REG(UART3)
Kojto 90:cb3d968589d8 13104 #define UART3_IR UART_IR_REG(UART3)
Kojto 90:cb3d968589d8 13105 #define UART3_PFIFO UART_PFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13106 #define UART3_CFIFO UART_CFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13107 #define UART3_SFIFO UART_SFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
Kojto 90:cb3d968589d8 13112 /* UART4 */
Kojto 90:cb3d968589d8 13113 #define UART4_BDH UART_BDH_REG(UART4)
Kojto 90:cb3d968589d8 13114 #define UART4_BDL UART_BDL_REG(UART4)
Kojto 90:cb3d968589d8 13115 #define UART4_C1 UART_C1_REG(UART4)
Kojto 90:cb3d968589d8 13116 #define UART4_C2 UART_C2_REG(UART4)
Kojto 90:cb3d968589d8 13117 #define UART4_S1 UART_S1_REG(UART4)
Kojto 90:cb3d968589d8 13118 #define UART4_S2 UART_S2_REG(UART4)
Kojto 90:cb3d968589d8 13119 #define UART4_C3 UART_C3_REG(UART4)
Kojto 90:cb3d968589d8 13120 #define UART4_D UART_D_REG(UART4)
Kojto 90:cb3d968589d8 13121 #define UART4_MA1 UART_MA1_REG(UART4)
Kojto 90:cb3d968589d8 13122 #define UART4_MA2 UART_MA2_REG(UART4)
Kojto 90:cb3d968589d8 13123 #define UART4_C4 UART_C4_REG(UART4)
Kojto 90:cb3d968589d8 13124 #define UART4_C5 UART_C5_REG(UART4)
Kojto 90:cb3d968589d8 13125 #define UART4_ED UART_ED_REG(UART4)
Kojto 90:cb3d968589d8 13126 #define UART4_MODEM UART_MODEM_REG(UART4)
Kojto 90:cb3d968589d8 13127 #define UART4_IR UART_IR_REG(UART4)
Kojto 90:cb3d968589d8 13128 #define UART4_PFIFO UART_PFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13129 #define UART4_CFIFO UART_CFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13130 #define UART4_SFIFO UART_SFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
Kojto 90:cb3d968589d8 13135 /* UART5 */
Kojto 90:cb3d968589d8 13136 #define UART5_BDH UART_BDH_REG(UART5)
Kojto 90:cb3d968589d8 13137 #define UART5_BDL UART_BDL_REG(UART5)
Kojto 90:cb3d968589d8 13138 #define UART5_C1 UART_C1_REG(UART5)
Kojto 90:cb3d968589d8 13139 #define UART5_C2 UART_C2_REG(UART5)
Kojto 90:cb3d968589d8 13140 #define UART5_S1 UART_S1_REG(UART5)
Kojto 90:cb3d968589d8 13141 #define UART5_S2 UART_S2_REG(UART5)
Kojto 90:cb3d968589d8 13142 #define UART5_C3 UART_C3_REG(UART5)
Kojto 90:cb3d968589d8 13143 #define UART5_D UART_D_REG(UART5)
Kojto 90:cb3d968589d8 13144 #define UART5_MA1 UART_MA1_REG(UART5)
Kojto 90:cb3d968589d8 13145 #define UART5_MA2 UART_MA2_REG(UART5)
Kojto 90:cb3d968589d8 13146 #define UART5_C4 UART_C4_REG(UART5)
Kojto 90:cb3d968589d8 13147 #define UART5_C5 UART_C5_REG(UART5)
Kojto 90:cb3d968589d8 13148 #define UART5_ED UART_ED_REG(UART5)
Kojto 90:cb3d968589d8 13149 #define UART5_MODEM UART_MODEM_REG(UART5)
Kojto 90:cb3d968589d8 13150 #define UART5_IR UART_IR_REG(UART5)
Kojto 90:cb3d968589d8 13151 #define UART5_PFIFO UART_PFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13152 #define UART5_CFIFO UART_CFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13153 #define UART5_SFIFO UART_SFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
Kojto 90:cb3d968589d8 13158
Kojto 90:cb3d968589d8 13159 /*!
Kojto 90:cb3d968589d8 13160 * @}
Kojto 90:cb3d968589d8 13161 */ /* end of group UART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13162
Kojto 90:cb3d968589d8 13163
Kojto 90:cb3d968589d8 13164 /*!
Kojto 90:cb3d968589d8 13165 * @}
Kojto 90:cb3d968589d8 13166 */ /* end of group UART_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 13167
Kojto 90:cb3d968589d8 13168
Kojto 90:cb3d968589d8 13169 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13170 -- USB Peripheral Access Layer
Kojto 90:cb3d968589d8 13171 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13172
Kojto 90:cb3d968589d8 13173 /*!
Kojto 90:cb3d968589d8 13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Kojto 90:cb3d968589d8 13175 * @{
Kojto 90:cb3d968589d8 13176 */
Kojto 90:cb3d968589d8 13177
Kojto 90:cb3d968589d8 13178 /** USB - Register Layout Typedef */
Kojto 90:cb3d968589d8 13179 typedef struct {
Kojto 90:cb3d968589d8 13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
Kojto 90:cb3d968589d8 13181 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
Kojto 90:cb3d968589d8 13183 uint8_t RESERVED_1[3];
Kojto 90:cb3d968589d8 13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
Kojto 90:cb3d968589d8 13185 uint8_t RESERVED_2[3];
Kojto 90:cb3d968589d8 13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
Kojto 90:cb3d968589d8 13187 uint8_t RESERVED_3[3];
Kojto 90:cb3d968589d8 13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
Kojto 90:cb3d968589d8 13189 uint8_t RESERVED_4[3];
Kojto 90:cb3d968589d8 13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
Kojto 90:cb3d968589d8 13191 uint8_t RESERVED_5[3];
Kojto 90:cb3d968589d8 13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
Kojto 90:cb3d968589d8 13193 uint8_t RESERVED_6[3];
Kojto 90:cb3d968589d8 13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
Kojto 90:cb3d968589d8 13195 uint8_t RESERVED_7[99];
Kojto 90:cb3d968589d8 13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
Kojto 90:cb3d968589d8 13197 uint8_t RESERVED_8[3];
Kojto 90:cb3d968589d8 13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
Kojto 90:cb3d968589d8 13199 uint8_t RESERVED_9[3];
Kojto 90:cb3d968589d8 13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
Kojto 90:cb3d968589d8 13201 uint8_t RESERVED_10[3];
Kojto 90:cb3d968589d8 13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
Kojto 90:cb3d968589d8 13203 uint8_t RESERVED_11[3];
Kojto 90:cb3d968589d8 13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */
Kojto 90:cb3d968589d8 13205 uint8_t RESERVED_12[3];
Kojto 90:cb3d968589d8 13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
Kojto 90:cb3d968589d8 13207 uint8_t RESERVED_13[3];
Kojto 90:cb3d968589d8 13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
Kojto 90:cb3d968589d8 13209 uint8_t RESERVED_14[3];
Kojto 90:cb3d968589d8 13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
Kojto 90:cb3d968589d8 13211 uint8_t RESERVED_15[3];
Kojto 90:cb3d968589d8 13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
Kojto 90:cb3d968589d8 13213 uint8_t RESERVED_16[3];
Kojto 90:cb3d968589d8 13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
Kojto 90:cb3d968589d8 13215 uint8_t RESERVED_17[3];
Kojto 90:cb3d968589d8 13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
Kojto 90:cb3d968589d8 13217 uint8_t RESERVED_18[3];
Kojto 90:cb3d968589d8 13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
Kojto 90:cb3d968589d8 13219 uint8_t RESERVED_19[3];
Kojto 90:cb3d968589d8 13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
Kojto 90:cb3d968589d8 13221 uint8_t RESERVED_20[3];
Kojto 90:cb3d968589d8 13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
Kojto 90:cb3d968589d8 13223 uint8_t RESERVED_21[11];
Kojto 90:cb3d968589d8 13224 struct { /* offset: 0xC0, array step: 0x4 */
Kojto 90:cb3d968589d8 13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
Kojto 90:cb3d968589d8 13226 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 13227 } ENDPOINT[16];
Kojto 90:cb3d968589d8 13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
Kojto 90:cb3d968589d8 13229 uint8_t RESERVED_22[3];
Kojto 90:cb3d968589d8 13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
Kojto 90:cb3d968589d8 13231 uint8_t RESERVED_23[3];
Kojto 90:cb3d968589d8 13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
Kojto 90:cb3d968589d8 13233 uint8_t RESERVED_24[3];
Kojto 90:cb3d968589d8 13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
Kojto 90:cb3d968589d8 13235 uint8_t RESERVED_25[7];
Kojto 90:cb3d968589d8 13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
Kojto 90:cb3d968589d8 13237 uint8_t RESERVED_26[43];
Kojto 90:cb3d968589d8 13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
Kojto 90:cb3d968589d8 13239 uint8_t RESERVED_27[3];
Kojto 90:cb3d968589d8 13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
Kojto 90:cb3d968589d8 13241 uint8_t RESERVED_28[23];
Kojto 90:cb3d968589d8 13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
Kojto 90:cb3d968589d8 13243 } USB_Type, *USB_MemMapPtr;
Kojto 90:cb3d968589d8 13244
Kojto 90:cb3d968589d8 13245 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13246 -- USB - Register accessor macros
Kojto 90:cb3d968589d8 13247 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13248
Kojto 90:cb3d968589d8 13249 /*!
Kojto 90:cb3d968589d8 13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Kojto 90:cb3d968589d8 13251 * @{
Kojto 90:cb3d968589d8 13252 */
Kojto 90:cb3d968589d8 13253
Kojto 90:cb3d968589d8 13254
Kojto 90:cb3d968589d8 13255 /* USB - Register accessors */
Kojto 90:cb3d968589d8 13256 #define USB_PERID_REG(base) ((base)->PERID)
Kojto 90:cb3d968589d8 13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
Kojto 90:cb3d968589d8 13258 #define USB_REV_REG(base) ((base)->REV)
Kojto 90:cb3d968589d8 13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
Kojto 90:cb3d968589d8 13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
Kojto 90:cb3d968589d8 13261 #define USB_OTGICR_REG(base) ((base)->OTGICR)
Kojto 90:cb3d968589d8 13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
Kojto 90:cb3d968589d8 13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
Kojto 90:cb3d968589d8 13264 #define USB_ISTAT_REG(base) ((base)->ISTAT)
Kojto 90:cb3d968589d8 13265 #define USB_INTEN_REG(base) ((base)->INTEN)
Kojto 90:cb3d968589d8 13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
Kojto 90:cb3d968589d8 13267 #define USB_ERREN_REG(base) ((base)->ERREN)
Kojto 90:cb3d968589d8 13268 #define USB_STAT_REG(base) ((base)->STAT)
Kojto 90:cb3d968589d8 13269 #define USB_CTL_REG(base) ((base)->CTL)
Kojto 90:cb3d968589d8 13270 #define USB_ADDR_REG(base) ((base)->ADDR)
Kojto 90:cb3d968589d8 13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
Kojto 90:cb3d968589d8 13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
Kojto 90:cb3d968589d8 13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
Kojto 90:cb3d968589d8 13274 #define USB_TOKEN_REG(base) ((base)->TOKEN)
Kojto 90:cb3d968589d8 13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
Kojto 90:cb3d968589d8 13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
Kojto 90:cb3d968589d8 13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
Kojto 90:cb3d968589d8 13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
Kojto 90:cb3d968589d8 13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
Kojto 90:cb3d968589d8 13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
Kojto 90:cb3d968589d8 13281 #define USB_CONTROL_REG(base) ((base)->CONTROL)
Kojto 90:cb3d968589d8 13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
Kojto 90:cb3d968589d8 13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
Kojto 90:cb3d968589d8 13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
Kojto 90:cb3d968589d8 13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
Kojto 90:cb3d968589d8 13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
Kojto 90:cb3d968589d8 13287
Kojto 90:cb3d968589d8 13288 /*!
Kojto 90:cb3d968589d8 13289 * @}
Kojto 90:cb3d968589d8 13290 */ /* end of group USB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13291
Kojto 90:cb3d968589d8 13292
Kojto 90:cb3d968589d8 13293 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13294 -- USB Register Masks
Kojto 90:cb3d968589d8 13295 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13296
Kojto 90:cb3d968589d8 13297 /*!
Kojto 90:cb3d968589d8 13298 * @addtogroup USB_Register_Masks USB Register Masks
Kojto 90:cb3d968589d8 13299 * @{
Kojto 90:cb3d968589d8 13300 */
Kojto 90:cb3d968589d8 13301
Kojto 90:cb3d968589d8 13302 /* PERID Bit Fields */
Kojto 90:cb3d968589d8 13303 #define USB_PERID_ID_MASK 0x3Fu
Kojto 90:cb3d968589d8 13304 #define USB_PERID_ID_SHIFT 0
Kojto 90:cb3d968589d8 13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
Kojto 90:cb3d968589d8 13306 /* IDCOMP Bit Fields */
Kojto 90:cb3d968589d8 13307 #define USB_IDCOMP_NID_MASK 0x3Fu
Kojto 90:cb3d968589d8 13308 #define USB_IDCOMP_NID_SHIFT 0
Kojto 90:cb3d968589d8 13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
Kojto 90:cb3d968589d8 13310 /* REV Bit Fields */
Kojto 90:cb3d968589d8 13311 #define USB_REV_REV_MASK 0xFFu
Kojto 90:cb3d968589d8 13312 #define USB_REV_REV_SHIFT 0
Kojto 90:cb3d968589d8 13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
Kojto 90:cb3d968589d8 13314 /* ADDINFO Bit Fields */
Kojto 90:cb3d968589d8 13315 #define USB_ADDINFO_IEHOST_MASK 0x1u
Kojto 90:cb3d968589d8 13316 #define USB_ADDINFO_IEHOST_SHIFT 0
Kojto 90:cb3d968589d8 13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
Kojto 90:cb3d968589d8 13318 #define USB_ADDINFO_IRQNUM_SHIFT 3
Kojto 90:cb3d968589d8 13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
Kojto 90:cb3d968589d8 13320 /* OTGISTAT Bit Fields */
Kojto 90:cb3d968589d8 13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
Kojto 90:cb3d968589d8 13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
Kojto 90:cb3d968589d8 13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
Kojto 90:cb3d968589d8 13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
Kojto 90:cb3d968589d8 13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
Kojto 90:cb3d968589d8 13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
Kojto 90:cb3d968589d8 13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
Kojto 90:cb3d968589d8 13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
Kojto 90:cb3d968589d8 13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
Kojto 90:cb3d968589d8 13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
Kojto 90:cb3d968589d8 13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u
Kojto 90:cb3d968589d8 13332 #define USB_OTGISTAT_IDCHG_SHIFT 7
Kojto 90:cb3d968589d8 13333 /* OTGICR Bit Fields */
Kojto 90:cb3d968589d8 13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u
Kojto 90:cb3d968589d8 13335 #define USB_OTGICR_AVBUSEN_SHIFT 0
Kojto 90:cb3d968589d8 13336 #define USB_OTGICR_BSESSEN_MASK 0x4u
Kojto 90:cb3d968589d8 13337 #define USB_OTGICR_BSESSEN_SHIFT 2
Kojto 90:cb3d968589d8 13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
Kojto 90:cb3d968589d8 13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3
Kojto 90:cb3d968589d8 13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
Kojto 90:cb3d968589d8 13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5
Kojto 90:cb3d968589d8 13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
Kojto 90:cb3d968589d8 13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6
Kojto 90:cb3d968589d8 13344 #define USB_OTGICR_IDEN_MASK 0x80u
Kojto 90:cb3d968589d8 13345 #define USB_OTGICR_IDEN_SHIFT 7
Kojto 90:cb3d968589d8 13346 /* OTGSTAT Bit Fields */
Kojto 90:cb3d968589d8 13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
Kojto 90:cb3d968589d8 13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
Kojto 90:cb3d968589d8 13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
Kojto 90:cb3d968589d8 13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2
Kojto 90:cb3d968589d8 13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
Kojto 90:cb3d968589d8 13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
Kojto 90:cb3d968589d8 13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
Kojto 90:cb3d968589d8 13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
Kojto 90:cb3d968589d8 13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
Kojto 90:cb3d968589d8 13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
Kojto 90:cb3d968589d8 13357 #define USB_OTGSTAT_ID_MASK 0x80u
Kojto 90:cb3d968589d8 13358 #define USB_OTGSTAT_ID_SHIFT 7
Kojto 90:cb3d968589d8 13359 /* OTGCTL Bit Fields */
Kojto 90:cb3d968589d8 13360 #define USB_OTGCTL_OTGEN_MASK 0x4u
Kojto 90:cb3d968589d8 13361 #define USB_OTGCTL_OTGEN_SHIFT 2
Kojto 90:cb3d968589d8 13362 #define USB_OTGCTL_DMLOW_MASK 0x10u
Kojto 90:cb3d968589d8 13363 #define USB_OTGCTL_DMLOW_SHIFT 4
Kojto 90:cb3d968589d8 13364 #define USB_OTGCTL_DPLOW_MASK 0x20u
Kojto 90:cb3d968589d8 13365 #define USB_OTGCTL_DPLOW_SHIFT 5
Kojto 90:cb3d968589d8 13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u
Kojto 90:cb3d968589d8 13367 #define USB_OTGCTL_DPHIGH_SHIFT 7
Kojto 90:cb3d968589d8 13368 /* ISTAT Bit Fields */
Kojto 90:cb3d968589d8 13369 #define USB_ISTAT_USBRST_MASK 0x1u
Kojto 90:cb3d968589d8 13370 #define USB_ISTAT_USBRST_SHIFT 0
Kojto 90:cb3d968589d8 13371 #define USB_ISTAT_ERROR_MASK 0x2u
Kojto 90:cb3d968589d8 13372 #define USB_ISTAT_ERROR_SHIFT 1
Kojto 90:cb3d968589d8 13373 #define USB_ISTAT_SOFTOK_MASK 0x4u
Kojto 90:cb3d968589d8 13374 #define USB_ISTAT_SOFTOK_SHIFT 2
Kojto 90:cb3d968589d8 13375 #define USB_ISTAT_TOKDNE_MASK 0x8u
Kojto 90:cb3d968589d8 13376 #define USB_ISTAT_TOKDNE_SHIFT 3
Kojto 90:cb3d968589d8 13377 #define USB_ISTAT_SLEEP_MASK 0x10u
Kojto 90:cb3d968589d8 13378 #define USB_ISTAT_SLEEP_SHIFT 4
Kojto 90:cb3d968589d8 13379 #define USB_ISTAT_RESUME_MASK 0x20u
Kojto 90:cb3d968589d8 13380 #define USB_ISTAT_RESUME_SHIFT 5
Kojto 90:cb3d968589d8 13381 #define USB_ISTAT_ATTACH_MASK 0x40u
Kojto 90:cb3d968589d8 13382 #define USB_ISTAT_ATTACH_SHIFT 6
Kojto 90:cb3d968589d8 13383 #define USB_ISTAT_STALL_MASK 0x80u
Kojto 90:cb3d968589d8 13384 #define USB_ISTAT_STALL_SHIFT 7
Kojto 90:cb3d968589d8 13385 /* INTEN Bit Fields */
Kojto 90:cb3d968589d8 13386 #define USB_INTEN_USBRSTEN_MASK 0x1u
Kojto 90:cb3d968589d8 13387 #define USB_INTEN_USBRSTEN_SHIFT 0
Kojto 90:cb3d968589d8 13388 #define USB_INTEN_ERROREN_MASK 0x2u
Kojto 90:cb3d968589d8 13389 #define USB_INTEN_ERROREN_SHIFT 1
Kojto 90:cb3d968589d8 13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u
Kojto 90:cb3d968589d8 13391 #define USB_INTEN_SOFTOKEN_SHIFT 2
Kojto 90:cb3d968589d8 13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u
Kojto 90:cb3d968589d8 13393 #define USB_INTEN_TOKDNEEN_SHIFT 3
Kojto 90:cb3d968589d8 13394 #define USB_INTEN_SLEEPEN_MASK 0x10u
Kojto 90:cb3d968589d8 13395 #define USB_INTEN_SLEEPEN_SHIFT 4
Kojto 90:cb3d968589d8 13396 #define USB_INTEN_RESUMEEN_MASK 0x20u
Kojto 90:cb3d968589d8 13397 #define USB_INTEN_RESUMEEN_SHIFT 5
Kojto 90:cb3d968589d8 13398 #define USB_INTEN_ATTACHEN_MASK 0x40u
Kojto 90:cb3d968589d8 13399 #define USB_INTEN_ATTACHEN_SHIFT 6
Kojto 90:cb3d968589d8 13400 #define USB_INTEN_STALLEN_MASK 0x80u
Kojto 90:cb3d968589d8 13401 #define USB_INTEN_STALLEN_SHIFT 7
Kojto 90:cb3d968589d8 13402 /* ERRSTAT Bit Fields */
Kojto 90:cb3d968589d8 13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u
Kojto 90:cb3d968589d8 13404 #define USB_ERRSTAT_PIDERR_SHIFT 0
Kojto 90:cb3d968589d8 13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
Kojto 90:cb3d968589d8 13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
Kojto 90:cb3d968589d8 13407 #define USB_ERRSTAT_CRC16_MASK 0x4u
Kojto 90:cb3d968589d8 13408 #define USB_ERRSTAT_CRC16_SHIFT 2
Kojto 90:cb3d968589d8 13409 #define USB_ERRSTAT_DFN8_MASK 0x8u
Kojto 90:cb3d968589d8 13410 #define USB_ERRSTAT_DFN8_SHIFT 3
Kojto 90:cb3d968589d8 13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u
Kojto 90:cb3d968589d8 13412 #define USB_ERRSTAT_BTOERR_SHIFT 4
Kojto 90:cb3d968589d8 13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u
Kojto 90:cb3d968589d8 13414 #define USB_ERRSTAT_DMAERR_SHIFT 5
Kojto 90:cb3d968589d8 13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u
Kojto 90:cb3d968589d8 13416 #define USB_ERRSTAT_BTSERR_SHIFT 7
Kojto 90:cb3d968589d8 13417 /* ERREN Bit Fields */
Kojto 90:cb3d968589d8 13418 #define USB_ERREN_PIDERREN_MASK 0x1u
Kojto 90:cb3d968589d8 13419 #define USB_ERREN_PIDERREN_SHIFT 0
Kojto 90:cb3d968589d8 13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
Kojto 90:cb3d968589d8 13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1
Kojto 90:cb3d968589d8 13422 #define USB_ERREN_CRC16EN_MASK 0x4u
Kojto 90:cb3d968589d8 13423 #define USB_ERREN_CRC16EN_SHIFT 2
Kojto 90:cb3d968589d8 13424 #define USB_ERREN_DFN8EN_MASK 0x8u
Kojto 90:cb3d968589d8 13425 #define USB_ERREN_DFN8EN_SHIFT 3
Kojto 90:cb3d968589d8 13426 #define USB_ERREN_BTOERREN_MASK 0x10u
Kojto 90:cb3d968589d8 13427 #define USB_ERREN_BTOERREN_SHIFT 4
Kojto 90:cb3d968589d8 13428 #define USB_ERREN_DMAERREN_MASK 0x20u
Kojto 90:cb3d968589d8 13429 #define USB_ERREN_DMAERREN_SHIFT 5
Kojto 90:cb3d968589d8 13430 #define USB_ERREN_BTSERREN_MASK 0x80u
Kojto 90:cb3d968589d8 13431 #define USB_ERREN_BTSERREN_SHIFT 7
Kojto 90:cb3d968589d8 13432 /* STAT Bit Fields */
Kojto 90:cb3d968589d8 13433 #define USB_STAT_ODD_MASK 0x4u
Kojto 90:cb3d968589d8 13434 #define USB_STAT_ODD_SHIFT 2
Kojto 90:cb3d968589d8 13435 #define USB_STAT_TX_MASK 0x8u
Kojto 90:cb3d968589d8 13436 #define USB_STAT_TX_SHIFT 3
Kojto 90:cb3d968589d8 13437 #define USB_STAT_ENDP_MASK 0xF0u
Kojto 90:cb3d968589d8 13438 #define USB_STAT_ENDP_SHIFT 4
Kojto 90:cb3d968589d8 13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
Kojto 90:cb3d968589d8 13440 /* CTL Bit Fields */
Kojto 90:cb3d968589d8 13441 #define USB_CTL_USBENSOFEN_MASK 0x1u
Kojto 90:cb3d968589d8 13442 #define USB_CTL_USBENSOFEN_SHIFT 0
Kojto 90:cb3d968589d8 13443 #define USB_CTL_ODDRST_MASK 0x2u
Kojto 90:cb3d968589d8 13444 #define USB_CTL_ODDRST_SHIFT 1
Kojto 90:cb3d968589d8 13445 #define USB_CTL_RESUME_MASK 0x4u
Kojto 90:cb3d968589d8 13446 #define USB_CTL_RESUME_SHIFT 2
Kojto 90:cb3d968589d8 13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u
Kojto 90:cb3d968589d8 13448 #define USB_CTL_HOSTMODEEN_SHIFT 3
Kojto 90:cb3d968589d8 13449 #define USB_CTL_RESET_MASK 0x10u
Kojto 90:cb3d968589d8 13450 #define USB_CTL_RESET_SHIFT 4
Kojto 90:cb3d968589d8 13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
Kojto 90:cb3d968589d8 13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
Kojto 90:cb3d968589d8 13453 #define USB_CTL_SE0_MASK 0x40u
Kojto 90:cb3d968589d8 13454 #define USB_CTL_SE0_SHIFT 6
Kojto 90:cb3d968589d8 13455 #define USB_CTL_JSTATE_MASK 0x80u
Kojto 90:cb3d968589d8 13456 #define USB_CTL_JSTATE_SHIFT 7
Kojto 90:cb3d968589d8 13457 /* ADDR Bit Fields */
Kojto 90:cb3d968589d8 13458 #define USB_ADDR_ADDR_MASK 0x7Fu
Kojto 90:cb3d968589d8 13459 #define USB_ADDR_ADDR_SHIFT 0
Kojto 90:cb3d968589d8 13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
Kojto 90:cb3d968589d8 13461 #define USB_ADDR_LSEN_MASK 0x80u
Kojto 90:cb3d968589d8 13462 #define USB_ADDR_LSEN_SHIFT 7
Kojto 90:cb3d968589d8 13463 /* BDTPAGE1 Bit Fields */
Kojto 90:cb3d968589d8 13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
Kojto 90:cb3d968589d8 13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1
Kojto 90:cb3d968589d8 13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
Kojto 90:cb3d968589d8 13467 /* FRMNUML Bit Fields */
Kojto 90:cb3d968589d8 13468 #define USB_FRMNUML_FRM_MASK 0xFFu
Kojto 90:cb3d968589d8 13469 #define USB_FRMNUML_FRM_SHIFT 0
Kojto 90:cb3d968589d8 13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
Kojto 90:cb3d968589d8 13471 /* FRMNUMH Bit Fields */
Kojto 90:cb3d968589d8 13472 #define USB_FRMNUMH_FRM_MASK 0x7u
Kojto 90:cb3d968589d8 13473 #define USB_FRMNUMH_FRM_SHIFT 0
Kojto 90:cb3d968589d8 13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
Kojto 90:cb3d968589d8 13475 /* TOKEN Bit Fields */
Kojto 90:cb3d968589d8 13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
Kojto 90:cb3d968589d8 13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0
Kojto 90:cb3d968589d8 13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
Kojto 90:cb3d968589d8 13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u
Kojto 90:cb3d968589d8 13480 #define USB_TOKEN_TOKENPID_SHIFT 4
Kojto 90:cb3d968589d8 13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
Kojto 90:cb3d968589d8 13482 /* SOFTHLD Bit Fields */
Kojto 90:cb3d968589d8 13483 #define USB_SOFTHLD_CNT_MASK 0xFFu
Kojto 90:cb3d968589d8 13484 #define USB_SOFTHLD_CNT_SHIFT 0
Kojto 90:cb3d968589d8 13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
Kojto 90:cb3d968589d8 13486 /* BDTPAGE2 Bit Fields */
Kojto 90:cb3d968589d8 13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
Kojto 90:cb3d968589d8 13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0
Kojto 90:cb3d968589d8 13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
Kojto 90:cb3d968589d8 13490 /* BDTPAGE3 Bit Fields */
Kojto 90:cb3d968589d8 13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
Kojto 90:cb3d968589d8 13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0
Kojto 90:cb3d968589d8 13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
Kojto 90:cb3d968589d8 13494 /* ENDPT Bit Fields */
Kojto 90:cb3d968589d8 13495 #define USB_ENDPT_EPHSHK_MASK 0x1u
Kojto 90:cb3d968589d8 13496 #define USB_ENDPT_EPHSHK_SHIFT 0
Kojto 90:cb3d968589d8 13497 #define USB_ENDPT_EPSTALL_MASK 0x2u
Kojto 90:cb3d968589d8 13498 #define USB_ENDPT_EPSTALL_SHIFT 1
Kojto 90:cb3d968589d8 13499 #define USB_ENDPT_EPTXEN_MASK 0x4u
Kojto 90:cb3d968589d8 13500 #define USB_ENDPT_EPTXEN_SHIFT 2
Kojto 90:cb3d968589d8 13501 #define USB_ENDPT_EPRXEN_MASK 0x8u
Kojto 90:cb3d968589d8 13502 #define USB_ENDPT_EPRXEN_SHIFT 3
Kojto 90:cb3d968589d8 13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
Kojto 90:cb3d968589d8 13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4
Kojto 90:cb3d968589d8 13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u
Kojto 90:cb3d968589d8 13506 #define USB_ENDPT_RETRYDIS_SHIFT 6
Kojto 90:cb3d968589d8 13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
Kojto 90:cb3d968589d8 13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
Kojto 90:cb3d968589d8 13509 /* USBCTRL Bit Fields */
Kojto 90:cb3d968589d8 13510 #define USB_USBCTRL_PDE_MASK 0x40u
Kojto 90:cb3d968589d8 13511 #define USB_USBCTRL_PDE_SHIFT 6
Kojto 90:cb3d968589d8 13512 #define USB_USBCTRL_SUSP_MASK 0x80u
Kojto 90:cb3d968589d8 13513 #define USB_USBCTRL_SUSP_SHIFT 7
Kojto 90:cb3d968589d8 13514 /* OBSERVE Bit Fields */
Kojto 90:cb3d968589d8 13515 #define USB_OBSERVE_DMPD_MASK 0x10u
Kojto 90:cb3d968589d8 13516 #define USB_OBSERVE_DMPD_SHIFT 4
Kojto 90:cb3d968589d8 13517 #define USB_OBSERVE_DPPD_MASK 0x40u
Kojto 90:cb3d968589d8 13518 #define USB_OBSERVE_DPPD_SHIFT 6
Kojto 90:cb3d968589d8 13519 #define USB_OBSERVE_DPPU_MASK 0x80u
Kojto 90:cb3d968589d8 13520 #define USB_OBSERVE_DPPU_SHIFT 7
Kojto 90:cb3d968589d8 13521 /* CONTROL Bit Fields */
Kojto 90:cb3d968589d8 13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
Kojto 90:cb3d968589d8 13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
Kojto 90:cb3d968589d8 13524 /* USBTRC0 Bit Fields */
Kojto 90:cb3d968589d8 13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
Kojto 90:cb3d968589d8 13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
Kojto 90:cb3d968589d8 13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
Kojto 90:cb3d968589d8 13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1
Kojto 90:cb3d968589d8 13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
Kojto 90:cb3d968589d8 13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
Kojto 90:cb3d968589d8 13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
Kojto 90:cb3d968589d8 13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5
Kojto 90:cb3d968589d8 13533 #define USB_USBTRC0_USBRESET_MASK 0x80u
Kojto 90:cb3d968589d8 13534 #define USB_USBTRC0_USBRESET_SHIFT 7
Kojto 90:cb3d968589d8 13535 /* USBFRMADJUST Bit Fields */
Kojto 90:cb3d968589d8 13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
Kojto 90:cb3d968589d8 13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0
Kojto 90:cb3d968589d8 13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
Kojto 90:cb3d968589d8 13539 /* CLK_RECOVER_CTRL Bit Fields */
Kojto 90:cb3d968589d8 13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
Kojto 90:cb3d968589d8 13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
Kojto 90:cb3d968589d8 13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
Kojto 90:cb3d968589d8 13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
Kojto 90:cb3d968589d8 13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
Kojto 90:cb3d968589d8 13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
Kojto 90:cb3d968589d8 13546 /* CLK_RECOVER_IRC_EN Bit Fields */
Kojto 90:cb3d968589d8 13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
Kojto 90:cb3d968589d8 13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
Kojto 90:cb3d968589d8 13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
Kojto 90:cb3d968589d8 13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
Kojto 90:cb3d968589d8 13551 /* CLK_RECOVER_INT_STATUS Bit Fields */
Kojto 90:cb3d968589d8 13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
Kojto 90:cb3d968589d8 13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
Kojto 90:cb3d968589d8 13554
Kojto 90:cb3d968589d8 13555 /*!
Kojto 90:cb3d968589d8 13556 * @}
Kojto 90:cb3d968589d8 13557 */ /* end of group USB_Register_Masks */
Kojto 90:cb3d968589d8 13558
Kojto 90:cb3d968589d8 13559
Kojto 90:cb3d968589d8 13560 /* USB - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 13561 /** Peripheral USB0 base address */
Kojto 90:cb3d968589d8 13562 #define USB0_BASE (0x40072000u)
Kojto 90:cb3d968589d8 13563 /** Peripheral USB0 base pointer */
Kojto 90:cb3d968589d8 13564 #define USB0 ((USB_Type *)USB0_BASE)
Kojto 90:cb3d968589d8 13565 #define USB0_BASE_PTR (USB0)
Kojto 90:cb3d968589d8 13566 /** Array initializer of USB peripheral base addresses */
Kojto 90:cb3d968589d8 13567 #define USB_BASE_ADDRS { USB0_BASE }
Kojto 90:cb3d968589d8 13568 /** Array initializer of USB peripheral base pointers */
Kojto 90:cb3d968589d8 13569 #define USB_BASE_PTRS { USB0 }
Kojto 90:cb3d968589d8 13570 /** Interrupt vectors for the USB peripheral type */
Kojto 90:cb3d968589d8 13571 #define USB_IRQS { USB0_IRQn }
Kojto 90:cb3d968589d8 13572
Kojto 90:cb3d968589d8 13573 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13574 -- USB - Register accessor macros
Kojto 90:cb3d968589d8 13575 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13576
Kojto 90:cb3d968589d8 13577 /*!
Kojto 90:cb3d968589d8 13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Kojto 90:cb3d968589d8 13579 * @{
Kojto 90:cb3d968589d8 13580 */
Kojto 90:cb3d968589d8 13581
Kojto 90:cb3d968589d8 13582
Kojto 90:cb3d968589d8 13583 /* USB - Register instance definitions */
Kojto 90:cb3d968589d8 13584 /* USB0 */
Kojto 90:cb3d968589d8 13585 #define USB0_PERID USB_PERID_REG(USB0)
Kojto 90:cb3d968589d8 13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
Kojto 90:cb3d968589d8 13587 #define USB0_REV USB_REV_REG(USB0)
Kojto 90:cb3d968589d8 13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
Kojto 90:cb3d968589d8 13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
Kojto 90:cb3d968589d8 13590 #define USB0_OTGICR USB_OTGICR_REG(USB0)
Kojto 90:cb3d968589d8 13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
Kojto 90:cb3d968589d8 13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
Kojto 90:cb3d968589d8 13593 #define USB0_ISTAT USB_ISTAT_REG(USB0)
Kojto 90:cb3d968589d8 13594 #define USB0_INTEN USB_INTEN_REG(USB0)
Kojto 90:cb3d968589d8 13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
Kojto 90:cb3d968589d8 13596 #define USB0_ERREN USB_ERREN_REG(USB0)
Kojto 90:cb3d968589d8 13597 #define USB0_STAT USB_STAT_REG(USB0)
Kojto 90:cb3d968589d8 13598 #define USB0_CTL USB_CTL_REG(USB0)
Kojto 90:cb3d968589d8 13599 #define USB0_ADDR USB_ADDR_REG(USB0)
Kojto 90:cb3d968589d8 13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
Kojto 90:cb3d968589d8 13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
Kojto 90:cb3d968589d8 13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
Kojto 90:cb3d968589d8 13603 #define USB0_TOKEN USB_TOKEN_REG(USB0)
Kojto 90:cb3d968589d8 13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
Kojto 90:cb3d968589d8 13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
Kojto 90:cb3d968589d8 13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
Kojto 90:cb3d968589d8 13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
Kojto 90:cb3d968589d8 13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
Kojto 90:cb3d968589d8 13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
Kojto 90:cb3d968589d8 13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
Kojto 90:cb3d968589d8 13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
Kojto 90:cb3d968589d8 13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
Kojto 90:cb3d968589d8 13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
Kojto 90:cb3d968589d8 13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
Kojto 90:cb3d968589d8 13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
Kojto 90:cb3d968589d8 13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
Kojto 90:cb3d968589d8 13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
Kojto 90:cb3d968589d8 13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
Kojto 90:cb3d968589d8 13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
Kojto 90:cb3d968589d8 13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
Kojto 90:cb3d968589d8 13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
Kojto 90:cb3d968589d8 13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
Kojto 90:cb3d968589d8 13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
Kojto 90:cb3d968589d8 13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
Kojto 90:cb3d968589d8 13625 #define USB0_CONTROL USB_CONTROL_REG(USB0)
Kojto 90:cb3d968589d8 13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
Kojto 90:cb3d968589d8 13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
Kojto 90:cb3d968589d8 13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
Kojto 90:cb3d968589d8 13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
Kojto 90:cb3d968589d8 13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
Kojto 90:cb3d968589d8 13631
Kojto 90:cb3d968589d8 13632 /* USB - Register array accessors */
Kojto 90:cb3d968589d8 13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
Kojto 90:cb3d968589d8 13634
Kojto 90:cb3d968589d8 13635 /*!
Kojto 90:cb3d968589d8 13636 * @}
Kojto 90:cb3d968589d8 13637 */ /* end of group USB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13638
Kojto 90:cb3d968589d8 13639
Kojto 90:cb3d968589d8 13640 /*!
Kojto 90:cb3d968589d8 13641 * @}
Kojto 90:cb3d968589d8 13642 */ /* end of group USB_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 13643
Kojto 90:cb3d968589d8 13644
Kojto 90:cb3d968589d8 13645 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13646 -- USBDCD Peripheral Access Layer
Kojto 90:cb3d968589d8 13647 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13648
Kojto 90:cb3d968589d8 13649 /*!
Kojto 90:cb3d968589d8 13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
Kojto 90:cb3d968589d8 13651 * @{
Kojto 90:cb3d968589d8 13652 */
Kojto 90:cb3d968589d8 13653
Kojto 90:cb3d968589d8 13654 /** USBDCD - Register Layout Typedef */
Kojto 90:cb3d968589d8 13655 typedef struct {
Kojto 90:cb3d968589d8 13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
Kojto 90:cb3d968589d8 13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
Kojto 90:cb3d968589d8 13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
Kojto 90:cb3d968589d8 13659 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
Kojto 90:cb3d968589d8 13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
Kojto 90:cb3d968589d8 13662 union { /* offset: 0x18 */
Kojto 90:cb3d968589d8 13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
Kojto 90:cb3d968589d8 13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
Kojto 90:cb3d968589d8 13665 };
Kojto 90:cb3d968589d8 13666 } USBDCD_Type, *USBDCD_MemMapPtr;
Kojto 90:cb3d968589d8 13667
Kojto 90:cb3d968589d8 13668 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13669 -- USBDCD - Register accessor macros
Kojto 90:cb3d968589d8 13670 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13671
Kojto 90:cb3d968589d8 13672 /*!
Kojto 90:cb3d968589d8 13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
Kojto 90:cb3d968589d8 13674 * @{
Kojto 90:cb3d968589d8 13675 */
Kojto 90:cb3d968589d8 13676
Kojto 90:cb3d968589d8 13677
Kojto 90:cb3d968589d8 13678 /* USBDCD - Register accessors */
Kojto 90:cb3d968589d8 13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
Kojto 90:cb3d968589d8 13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
Kojto 90:cb3d968589d8 13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
Kojto 90:cb3d968589d8 13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
Kojto 90:cb3d968589d8 13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
Kojto 90:cb3d968589d8 13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
Kojto 90:cb3d968589d8 13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
Kojto 90:cb3d968589d8 13686
Kojto 90:cb3d968589d8 13687 /*!
Kojto 90:cb3d968589d8 13688 * @}
Kojto 90:cb3d968589d8 13689 */ /* end of group USBDCD_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13690
Kojto 90:cb3d968589d8 13691
Kojto 90:cb3d968589d8 13692 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13693 -- USBDCD Register Masks
Kojto 90:cb3d968589d8 13694 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13695
Kojto 90:cb3d968589d8 13696 /*!
Kojto 90:cb3d968589d8 13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
Kojto 90:cb3d968589d8 13698 * @{
Kojto 90:cb3d968589d8 13699 */
Kojto 90:cb3d968589d8 13700
Kojto 90:cb3d968589d8 13701 /* CONTROL Bit Fields */
Kojto 90:cb3d968589d8 13702 #define USBDCD_CONTROL_IACK_MASK 0x1u
Kojto 90:cb3d968589d8 13703 #define USBDCD_CONTROL_IACK_SHIFT 0
Kojto 90:cb3d968589d8 13704 #define USBDCD_CONTROL_IF_MASK 0x100u
Kojto 90:cb3d968589d8 13705 #define USBDCD_CONTROL_IF_SHIFT 8
Kojto 90:cb3d968589d8 13706 #define USBDCD_CONTROL_IE_MASK 0x10000u
Kojto 90:cb3d968589d8 13707 #define USBDCD_CONTROL_IE_SHIFT 16
Kojto 90:cb3d968589d8 13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u
Kojto 90:cb3d968589d8 13709 #define USBDCD_CONTROL_BC12_SHIFT 17
Kojto 90:cb3d968589d8 13710 #define USBDCD_CONTROL_START_MASK 0x1000000u
Kojto 90:cb3d968589d8 13711 #define USBDCD_CONTROL_START_SHIFT 24
Kojto 90:cb3d968589d8 13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u
Kojto 90:cb3d968589d8 13713 #define USBDCD_CONTROL_SR_SHIFT 25
Kojto 90:cb3d968589d8 13714 /* CLOCK Bit Fields */
Kojto 90:cb3d968589d8 13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
Kojto 90:cb3d968589d8 13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
Kojto 90:cb3d968589d8 13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
Kojto 90:cb3d968589d8 13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
Kojto 90:cb3d968589d8 13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
Kojto 90:cb3d968589d8 13720 /* STATUS Bit Fields */
Kojto 90:cb3d968589d8 13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
Kojto 90:cb3d968589d8 13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
Kojto 90:cb3d968589d8 13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
Kojto 90:cb3d968589d8 13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
Kojto 90:cb3d968589d8 13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
Kojto 90:cb3d968589d8 13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
Kojto 90:cb3d968589d8 13727 #define USBDCD_STATUS_ERR_MASK 0x100000u
Kojto 90:cb3d968589d8 13728 #define USBDCD_STATUS_ERR_SHIFT 20
Kojto 90:cb3d968589d8 13729 #define USBDCD_STATUS_TO_MASK 0x200000u
Kojto 90:cb3d968589d8 13730 #define USBDCD_STATUS_TO_SHIFT 21
Kojto 90:cb3d968589d8 13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
Kojto 90:cb3d968589d8 13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22
Kojto 90:cb3d968589d8 13733 /* TIMER0 Bit Fields */
Kojto 90:cb3d968589d8 13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
Kojto 90:cb3d968589d8 13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
Kojto 90:cb3d968589d8 13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
Kojto 90:cb3d968589d8 13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
Kojto 90:cb3d968589d8 13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
Kojto 90:cb3d968589d8 13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
Kojto 90:cb3d968589d8 13740 /* TIMER1 Bit Fields */
Kojto 90:cb3d968589d8 13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
Kojto 90:cb3d968589d8 13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
Kojto 90:cb3d968589d8 13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
Kojto 90:cb3d968589d8 13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
Kojto 90:cb3d968589d8 13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
Kojto 90:cb3d968589d8 13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
Kojto 90:cb3d968589d8 13747 /* TIMER2_BC11 Bit Fields */
Kojto 90:cb3d968589d8 13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
Kojto 90:cb3d968589d8 13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
Kojto 90:cb3d968589d8 13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
Kojto 90:cb3d968589d8 13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
Kojto 90:cb3d968589d8 13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
Kojto 90:cb3d968589d8 13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
Kojto 90:cb3d968589d8 13754 /* TIMER2_BC12 Bit Fields */
Kojto 90:cb3d968589d8 13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
Kojto 90:cb3d968589d8 13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
Kojto 90:cb3d968589d8 13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
Kojto 90:cb3d968589d8 13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
Kojto 90:cb3d968589d8 13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
Kojto 90:cb3d968589d8 13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
Kojto 90:cb3d968589d8 13761
Kojto 90:cb3d968589d8 13762 /*!
Kojto 90:cb3d968589d8 13763 * @}
Kojto 90:cb3d968589d8 13764 */ /* end of group USBDCD_Register_Masks */
Kojto 90:cb3d968589d8 13765
Kojto 90:cb3d968589d8 13766
Kojto 90:cb3d968589d8 13767 /* USBDCD - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 13768 /** Peripheral USBDCD base address */
Kojto 90:cb3d968589d8 13769 #define USBDCD_BASE (0x40035000u)
Kojto 90:cb3d968589d8 13770 /** Peripheral USBDCD base pointer */
Kojto 90:cb3d968589d8 13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
Kojto 90:cb3d968589d8 13772 #define USBDCD_BASE_PTR (USBDCD)
Kojto 90:cb3d968589d8 13773 /** Array initializer of USBDCD peripheral base addresses */
Kojto 90:cb3d968589d8 13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
Kojto 90:cb3d968589d8 13775 /** Array initializer of USBDCD peripheral base pointers */
Kojto 90:cb3d968589d8 13776 #define USBDCD_BASE_PTRS { USBDCD }
Kojto 90:cb3d968589d8 13777 /** Interrupt vectors for the USBDCD peripheral type */
Kojto 90:cb3d968589d8 13778 #define USBDCD_IRQS { USBDCD_IRQn }
Kojto 90:cb3d968589d8 13779
Kojto 90:cb3d968589d8 13780 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13781 -- USBDCD - Register accessor macros
Kojto 90:cb3d968589d8 13782 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13783
Kojto 90:cb3d968589d8 13784 /*!
Kojto 90:cb3d968589d8 13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
Kojto 90:cb3d968589d8 13786 * @{
Kojto 90:cb3d968589d8 13787 */
Kojto 90:cb3d968589d8 13788
Kojto 90:cb3d968589d8 13789
Kojto 90:cb3d968589d8 13790 /* USBDCD - Register instance definitions */
Kojto 90:cb3d968589d8 13791 /* USBDCD */
Kojto 90:cb3d968589d8 13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
Kojto 90:cb3d968589d8 13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
Kojto 90:cb3d968589d8 13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
Kojto 90:cb3d968589d8 13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
Kojto 90:cb3d968589d8 13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
Kojto 90:cb3d968589d8 13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
Kojto 90:cb3d968589d8 13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
Kojto 90:cb3d968589d8 13799
Kojto 90:cb3d968589d8 13800 /*!
Kojto 90:cb3d968589d8 13801 * @}
Kojto 90:cb3d968589d8 13802 */ /* end of group USBDCD_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13803
Kojto 90:cb3d968589d8 13804
Kojto 90:cb3d968589d8 13805 /*!
Kojto 90:cb3d968589d8 13806 * @}
Kojto 90:cb3d968589d8 13807 */ /* end of group USBDCD_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 13808
Kojto 90:cb3d968589d8 13809
Kojto 90:cb3d968589d8 13810 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13811 -- VREF Peripheral Access Layer
Kojto 90:cb3d968589d8 13812 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13813
Kojto 90:cb3d968589d8 13814 /*!
Kojto 90:cb3d968589d8 13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
Kojto 90:cb3d968589d8 13816 * @{
Kojto 90:cb3d968589d8 13817 */
Kojto 90:cb3d968589d8 13818
Kojto 90:cb3d968589d8 13819 /** VREF - Register Layout Typedef */
Kojto 90:cb3d968589d8 13820 typedef struct {
Kojto 90:cb3d968589d8 13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
Kojto 90:cb3d968589d8 13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
Kojto 90:cb3d968589d8 13823 } VREF_Type, *VREF_MemMapPtr;
Kojto 90:cb3d968589d8 13824
Kojto 90:cb3d968589d8 13825 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13826 -- VREF - Register accessor macros
Kojto 90:cb3d968589d8 13827 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13828
Kojto 90:cb3d968589d8 13829 /*!
Kojto 90:cb3d968589d8 13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Kojto 90:cb3d968589d8 13831 * @{
Kojto 90:cb3d968589d8 13832 */
Kojto 90:cb3d968589d8 13833
Kojto 90:cb3d968589d8 13834
Kojto 90:cb3d968589d8 13835 /* VREF - Register accessors */
Kojto 90:cb3d968589d8 13836 #define VREF_TRM_REG(base) ((base)->TRM)
Kojto 90:cb3d968589d8 13837 #define VREF_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 13838
Kojto 90:cb3d968589d8 13839 /*!
Kojto 90:cb3d968589d8 13840 * @}
Kojto 90:cb3d968589d8 13841 */ /* end of group VREF_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13842
Kojto 90:cb3d968589d8 13843
Kojto 90:cb3d968589d8 13844 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13845 -- VREF Register Masks
Kojto 90:cb3d968589d8 13846 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13847
Kojto 90:cb3d968589d8 13848 /*!
Kojto 90:cb3d968589d8 13849 * @addtogroup VREF_Register_Masks VREF Register Masks
Kojto 90:cb3d968589d8 13850 * @{
Kojto 90:cb3d968589d8 13851 */
Kojto 90:cb3d968589d8 13852
Kojto 90:cb3d968589d8 13853 /* TRM Bit Fields */
Kojto 90:cb3d968589d8 13854 #define VREF_TRM_TRIM_MASK 0x3Fu
Kojto 90:cb3d968589d8 13855 #define VREF_TRM_TRIM_SHIFT 0
Kojto 90:cb3d968589d8 13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
Kojto 90:cb3d968589d8 13857 #define VREF_TRM_CHOPEN_MASK 0x40u
Kojto 90:cb3d968589d8 13858 #define VREF_TRM_CHOPEN_SHIFT 6
Kojto 90:cb3d968589d8 13859 /* SC Bit Fields */
Kojto 90:cb3d968589d8 13860 #define VREF_SC_MODE_LV_MASK 0x3u
Kojto 90:cb3d968589d8 13861 #define VREF_SC_MODE_LV_SHIFT 0
Kojto 90:cb3d968589d8 13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
Kojto 90:cb3d968589d8 13863 #define VREF_SC_VREFST_MASK 0x4u
Kojto 90:cb3d968589d8 13864 #define VREF_SC_VREFST_SHIFT 2
Kojto 90:cb3d968589d8 13865 #define VREF_SC_ICOMPEN_MASK 0x20u
Kojto 90:cb3d968589d8 13866 #define VREF_SC_ICOMPEN_SHIFT 5
Kojto 90:cb3d968589d8 13867 #define VREF_SC_REGEN_MASK 0x40u
Kojto 90:cb3d968589d8 13868 #define VREF_SC_REGEN_SHIFT 6
Kojto 90:cb3d968589d8 13869 #define VREF_SC_VREFEN_MASK 0x80u
Kojto 90:cb3d968589d8 13870 #define VREF_SC_VREFEN_SHIFT 7
Kojto 90:cb3d968589d8 13871
Kojto 90:cb3d968589d8 13872 /*!
Kojto 90:cb3d968589d8 13873 * @}
Kojto 90:cb3d968589d8 13874 */ /* end of group VREF_Register_Masks */
Kojto 90:cb3d968589d8 13875
Kojto 90:cb3d968589d8 13876
Kojto 90:cb3d968589d8 13877 /* VREF - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 13878 /** Peripheral VREF base address */
Kojto 90:cb3d968589d8 13879 #define VREF_BASE (0x40074000u)
Kojto 90:cb3d968589d8 13880 /** Peripheral VREF base pointer */
Kojto 90:cb3d968589d8 13881 #define VREF ((VREF_Type *)VREF_BASE)
Kojto 90:cb3d968589d8 13882 #define VREF_BASE_PTR (VREF)
Kojto 90:cb3d968589d8 13883 /** Array initializer of VREF peripheral base addresses */
Kojto 90:cb3d968589d8 13884 #define VREF_BASE_ADDRS { VREF_BASE }
Kojto 90:cb3d968589d8 13885 /** Array initializer of VREF peripheral base pointers */
Kojto 90:cb3d968589d8 13886 #define VREF_BASE_PTRS { VREF }
Kojto 90:cb3d968589d8 13887
Kojto 90:cb3d968589d8 13888 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13889 -- VREF - Register accessor macros
Kojto 90:cb3d968589d8 13890 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13891
Kojto 90:cb3d968589d8 13892 /*!
Kojto 90:cb3d968589d8 13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Kojto 90:cb3d968589d8 13894 * @{
Kojto 90:cb3d968589d8 13895 */
Kojto 90:cb3d968589d8 13896
Kojto 90:cb3d968589d8 13897
Kojto 90:cb3d968589d8 13898 /* VREF - Register instance definitions */
Kojto 90:cb3d968589d8 13899 /* VREF */
Kojto 90:cb3d968589d8 13900 #define VREF_TRM VREF_TRM_REG(VREF)
Kojto 90:cb3d968589d8 13901 #define VREF_SC VREF_SC_REG(VREF)
Kojto 90:cb3d968589d8 13902
Kojto 90:cb3d968589d8 13903 /*!
Kojto 90:cb3d968589d8 13904 * @}
Kojto 90:cb3d968589d8 13905 */ /* end of group VREF_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13906
Kojto 90:cb3d968589d8 13907
Kojto 90:cb3d968589d8 13908 /*!
Kojto 90:cb3d968589d8 13909 * @}
Kojto 90:cb3d968589d8 13910 */ /* end of group VREF_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 13911
Kojto 90:cb3d968589d8 13912
Kojto 90:cb3d968589d8 13913 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13914 -- WDOG Peripheral Access Layer
Kojto 90:cb3d968589d8 13915 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13916
Kojto 90:cb3d968589d8 13917 /*!
Kojto 90:cb3d968589d8 13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
Kojto 90:cb3d968589d8 13919 * @{
Kojto 90:cb3d968589d8 13920 */
Kojto 90:cb3d968589d8 13921
Kojto 90:cb3d968589d8 13922 /** WDOG - Register Layout Typedef */
Kojto 90:cb3d968589d8 13923 typedef struct {
Kojto 90:cb3d968589d8 13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
Kojto 90:cb3d968589d8 13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
Kojto 90:cb3d968589d8 13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
Kojto 90:cb3d968589d8 13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
Kojto 90:cb3d968589d8 13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
Kojto 90:cb3d968589d8 13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
Kojto 90:cb3d968589d8 13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
Kojto 90:cb3d968589d8 13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
Kojto 90:cb3d968589d8 13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
Kojto 90:cb3d968589d8 13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
Kojto 90:cb3d968589d8 13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
Kojto 90:cb3d968589d8 13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
Kojto 90:cb3d968589d8 13936 } WDOG_Type, *WDOG_MemMapPtr;
Kojto 90:cb3d968589d8 13937
Kojto 90:cb3d968589d8 13938 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13939 -- WDOG - Register accessor macros
Kojto 90:cb3d968589d8 13940 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13941
Kojto 90:cb3d968589d8 13942 /*!
Kojto 90:cb3d968589d8 13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
Kojto 90:cb3d968589d8 13944 * @{
Kojto 90:cb3d968589d8 13945 */
Kojto 90:cb3d968589d8 13946
Kojto 90:cb3d968589d8 13947
Kojto 90:cb3d968589d8 13948 /* WDOG - Register accessors */
Kojto 90:cb3d968589d8 13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
Kojto 90:cb3d968589d8 13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
Kojto 90:cb3d968589d8 13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
Kojto 90:cb3d968589d8 13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
Kojto 90:cb3d968589d8 13953 #define WDOG_WINH_REG(base) ((base)->WINH)
Kojto 90:cb3d968589d8 13954 #define WDOG_WINL_REG(base) ((base)->WINL)
Kojto 90:cb3d968589d8 13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
Kojto 90:cb3d968589d8 13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
Kojto 90:cb3d968589d8 13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
Kojto 90:cb3d968589d8 13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
Kojto 90:cb3d968589d8 13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
Kojto 90:cb3d968589d8 13960 #define WDOG_PRESC_REG(base) ((base)->PRESC)
Kojto 90:cb3d968589d8 13961
Kojto 90:cb3d968589d8 13962 /*!
Kojto 90:cb3d968589d8 13963 * @}
Kojto 90:cb3d968589d8 13964 */ /* end of group WDOG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 13965
Kojto 90:cb3d968589d8 13966
Kojto 90:cb3d968589d8 13967 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 13968 -- WDOG Register Masks
Kojto 90:cb3d968589d8 13969 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 13970
Kojto 90:cb3d968589d8 13971 /*!
Kojto 90:cb3d968589d8 13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks
Kojto 90:cb3d968589d8 13973 * @{
Kojto 90:cb3d968589d8 13974 */
Kojto 90:cb3d968589d8 13975
Kojto 90:cb3d968589d8 13976 /* STCTRLH Bit Fields */
Kojto 90:cb3d968589d8 13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
Kojto 90:cb3d968589d8 13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
Kojto 90:cb3d968589d8 13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
Kojto 90:cb3d968589d8 13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
Kojto 90:cb3d968589d8 13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
Kojto 90:cb3d968589d8 13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
Kojto 90:cb3d968589d8 13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u
Kojto 90:cb3d968589d8 13984 #define WDOG_STCTRLH_WINEN_SHIFT 3
Kojto 90:cb3d968589d8 13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
Kojto 90:cb3d968589d8 13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
Kojto 90:cb3d968589d8 13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
Kojto 90:cb3d968589d8 13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5
Kojto 90:cb3d968589d8 13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
Kojto 90:cb3d968589d8 13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6
Kojto 90:cb3d968589d8 13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
Kojto 90:cb3d968589d8 13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7
Kojto 90:cb3d968589d8 13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
Kojto 90:cb3d968589d8 13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
Kojto 90:cb3d968589d8 13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
Kojto 90:cb3d968589d8 13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
Kojto 90:cb3d968589d8 13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
Kojto 90:cb3d968589d8 13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
Kojto 90:cb3d968589d8 13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
Kojto 90:cb3d968589d8 14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
Kojto 90:cb3d968589d8 14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
Kojto 90:cb3d968589d8 14002 /* STCTRLL Bit Fields */
Kojto 90:cb3d968589d8 14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
Kojto 90:cb3d968589d8 14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15
Kojto 90:cb3d968589d8 14005 /* TOVALH Bit Fields */
Kojto 90:cb3d968589d8 14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
Kojto 90:cb3d968589d8 14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
Kojto 90:cb3d968589d8 14009 /* TOVALL Bit Fields */
Kojto 90:cb3d968589d8 14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
Kojto 90:cb3d968589d8 14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
Kojto 90:cb3d968589d8 14013 /* WINH Bit Fields */
Kojto 90:cb3d968589d8 14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14015 #define WDOG_WINH_WINHIGH_SHIFT 0
Kojto 90:cb3d968589d8 14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
Kojto 90:cb3d968589d8 14017 /* WINL Bit Fields */
Kojto 90:cb3d968589d8 14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14019 #define WDOG_WINL_WINLOW_SHIFT 0
Kojto 90:cb3d968589d8 14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
Kojto 90:cb3d968589d8 14021 /* REFRESH Bit Fields */
Kojto 90:cb3d968589d8 14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
Kojto 90:cb3d968589d8 14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
Kojto 90:cb3d968589d8 14025 /* UNLOCK Bit Fields */
Kojto 90:cb3d968589d8 14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
Kojto 90:cb3d968589d8 14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
Kojto 90:cb3d968589d8 14029 /* TMROUTH Bit Fields */
Kojto 90:cb3d968589d8 14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
Kojto 90:cb3d968589d8 14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
Kojto 90:cb3d968589d8 14033 /* TMROUTL Bit Fields */
Kojto 90:cb3d968589d8 14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
Kojto 90:cb3d968589d8 14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
Kojto 90:cb3d968589d8 14037 /* RSTCNT Bit Fields */
Kojto 90:cb3d968589d8 14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
Kojto 90:cb3d968589d8 14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
Kojto 90:cb3d968589d8 14041 /* PRESC Bit Fields */
Kojto 90:cb3d968589d8 14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
Kojto 90:cb3d968589d8 14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8
Kojto 90:cb3d968589d8 14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
Kojto 90:cb3d968589d8 14045
Kojto 90:cb3d968589d8 14046 /*!
Kojto 90:cb3d968589d8 14047 * @}
Kojto 90:cb3d968589d8 14048 */ /* end of group WDOG_Register_Masks */
Kojto 90:cb3d968589d8 14049
Kojto 90:cb3d968589d8 14050
Kojto 90:cb3d968589d8 14051 /* WDOG - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 14052 /** Peripheral WDOG base address */
Kojto 90:cb3d968589d8 14053 #define WDOG_BASE (0x40052000u)
Kojto 90:cb3d968589d8 14054 /** Peripheral WDOG base pointer */
Kojto 90:cb3d968589d8 14055 #define WDOG ((WDOG_Type *)WDOG_BASE)
Kojto 90:cb3d968589d8 14056 #define WDOG_BASE_PTR (WDOG)
Kojto 90:cb3d968589d8 14057 /** Array initializer of WDOG peripheral base addresses */
Kojto 90:cb3d968589d8 14058 #define WDOG_BASE_ADDRS { WDOG_BASE }
Kojto 90:cb3d968589d8 14059 /** Array initializer of WDOG peripheral base pointers */
Kojto 90:cb3d968589d8 14060 #define WDOG_BASE_PTRS { WDOG }
Kojto 90:cb3d968589d8 14061 /** Interrupt vectors for the WDOG peripheral type */
Kojto 90:cb3d968589d8 14062 #define WDOG_IRQS { Watchdog_IRQn }
Kojto 90:cb3d968589d8 14063
Kojto 90:cb3d968589d8 14064 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 14065 -- WDOG - Register accessor macros
Kojto 90:cb3d968589d8 14066 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 14067
Kojto 90:cb3d968589d8 14068 /*!
Kojto 90:cb3d968589d8 14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
Kojto 90:cb3d968589d8 14070 * @{
Kojto 90:cb3d968589d8 14071 */
Kojto 90:cb3d968589d8 14072
Kojto 90:cb3d968589d8 14073
Kojto 90:cb3d968589d8 14074 /* WDOG - Register instance definitions */
Kojto 90:cb3d968589d8 14075 /* WDOG */
Kojto 90:cb3d968589d8 14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
Kojto 90:cb3d968589d8 14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
Kojto 90:cb3d968589d8 14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
Kojto 90:cb3d968589d8 14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
Kojto 90:cb3d968589d8 14080 #define WDOG_WINH WDOG_WINH_REG(WDOG)
Kojto 90:cb3d968589d8 14081 #define WDOG_WINL WDOG_WINL_REG(WDOG)
Kojto 90:cb3d968589d8 14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
Kojto 90:cb3d968589d8 14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
Kojto 90:cb3d968589d8 14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
Kojto 90:cb3d968589d8 14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
Kojto 90:cb3d968589d8 14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
Kojto 90:cb3d968589d8 14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
Kojto 90:cb3d968589d8 14088
Kojto 90:cb3d968589d8 14089 /*!
Kojto 90:cb3d968589d8 14090 * @}
Kojto 90:cb3d968589d8 14091 */ /* end of group WDOG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 14092
Kojto 90:cb3d968589d8 14093
Kojto 90:cb3d968589d8 14094 /*!
Kojto 90:cb3d968589d8 14095 * @}
Kojto 90:cb3d968589d8 14096 */ /* end of group WDOG_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 14097
Kojto 90:cb3d968589d8 14098
Kojto 90:cb3d968589d8 14099 /*
Kojto 90:cb3d968589d8 14100 ** End of section using anonymous unions
Kojto 90:cb3d968589d8 14101 */
Kojto 90:cb3d968589d8 14102
Kojto 90:cb3d968589d8 14103 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 14104 #pragma pop
Kojto 90:cb3d968589d8 14105 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 14106 #pragma pop
Kojto 90:cb3d968589d8 14107 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 14108 /* leave anonymous unions enabled */
Kojto 90:cb3d968589d8 14109 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 14110 #pragma language=default
Kojto 90:cb3d968589d8 14111 #else
Kojto 90:cb3d968589d8 14112 #error Not supported compiler type
Kojto 90:cb3d968589d8 14113 #endif
Kojto 90:cb3d968589d8 14114
Kojto 90:cb3d968589d8 14115 /*!
Kojto 90:cb3d968589d8 14116 * @}
Kojto 90:cb3d968589d8 14117 */ /* end of group Peripheral_access_layer */
Kojto 90:cb3d968589d8 14118
Kojto 90:cb3d968589d8 14119
Kojto 90:cb3d968589d8 14120 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 14121 -- Backward Compatibility
Kojto 90:cb3d968589d8 14122 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 14123
Kojto 90:cb3d968589d8 14124 /*!
Kojto 90:cb3d968589d8 14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
Kojto 90:cb3d968589d8 14126 * @{
Kojto 90:cb3d968589d8 14127 */
Kojto 90:cb3d968589d8 14128
Kojto 90:cb3d968589d8 14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14130 #define DMA_EARS This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
Kojto 90:cb3d968589d8 14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
Kojto 90:cb3d968589d8 14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
Kojto 90:cb3d968589d8 14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
Kojto 90:cb3d968589d8 14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
Kojto 90:cb3d968589d8 14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
Kojto 90:cb3d968589d8 14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
Kojto 90:cb3d968589d8 14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
Kojto 90:cb3d968589d8 14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
Kojto 90:cb3d968589d8 14181 #define MCG_C9 This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14185 #define MCM_PLACR This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14186 #define ADC_BASES ADC_BASE_PTRS
Kojto 90:cb3d968589d8 14187 #define AIPS_BASES AIPS_BASE_PTRS
Kojto 90:cb3d968589d8 14188 #define AXBS_BASES AXBS_BASE_PTRS
Kojto 90:cb3d968589d8 14189 #define CAN_BASES CAN_BASE_PTRS
Kojto 90:cb3d968589d8 14190 #define CAU_BASES CAU_BASE_PTRS
Kojto 90:cb3d968589d8 14191 #define CMP_BASES CMP_BASE_PTRS
Kojto 90:cb3d968589d8 14192 #define CMT_BASES CMT_BASE_PTRS
Kojto 90:cb3d968589d8 14193 #define CRC_BASES CRC_BASE_PTRS
Kojto 90:cb3d968589d8 14194 #define DAC_BASES DAC_BASE_PTRS
Kojto 90:cb3d968589d8 14195 #define DMA_BASES DMA_BASE_PTRS
Kojto 90:cb3d968589d8 14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS
Kojto 90:cb3d968589d8 14197 #define ENET_BASES ENET_BASE_PTRS
Kojto 90:cb3d968589d8 14198 #define EWM_BASES EWM_BASE_PTRS
Kojto 90:cb3d968589d8 14199 #define FB_BASES FB_BASE_PTRS
Kojto 90:cb3d968589d8 14200 #define FMC_BASES FMC_BASE_PTRS
Kojto 90:cb3d968589d8 14201 #define FTFE_BASES FTFE_BASE_PTRS
Kojto 90:cb3d968589d8 14202 #define FTM_BASES FTM_BASE_PTRS
Kojto 90:cb3d968589d8 14203 #define GPIO_BASES GPIO_BASE_PTRS
Kojto 90:cb3d968589d8 14204 #define I2C_BASES I2C_BASE_PTRS
Kojto 90:cb3d968589d8 14205 #define I2S_BASES I2S_BASE_PTRS
Kojto 90:cb3d968589d8 14206 #define LLWU_BASES LLWU_BASE_PTRS
Kojto 90:cb3d968589d8 14207 #define LPTMR_BASES LPTMR_BASE_PTRS
Kojto 90:cb3d968589d8 14208 #define MCG_BASES MCG_BASE_PTRS
Kojto 90:cb3d968589d8 14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
Kojto 90:cb3d968589d8 14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
Kojto 90:cb3d968589d8 14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
Kojto 90:cb3d968589d8 14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
Kojto 90:cb3d968589d8 14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
Kojto 90:cb3d968589d8 14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
Kojto 90:cb3d968589d8 14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
Kojto 90:cb3d968589d8 14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
Kojto 90:cb3d968589d8 14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
Kojto 90:cb3d968589d8 14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
Kojto 90:cb3d968589d8 14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
Kojto 90:cb3d968589d8 14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
Kojto 90:cb3d968589d8 14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
Kojto 90:cb3d968589d8 14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
Kojto 90:cb3d968589d8 14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
Kojto 90:cb3d968589d8 14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
Kojto 90:cb3d968589d8 14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
Kojto 90:cb3d968589d8 14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
Kojto 90:cb3d968589d8 14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
Kojto 90:cb3d968589d8 14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
Kojto 90:cb3d968589d8 14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
Kojto 90:cb3d968589d8 14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
Kojto 90:cb3d968589d8 14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
Kojto 90:cb3d968589d8 14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
Kojto 90:cb3d968589d8 14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
Kojto 90:cb3d968589d8 14234 #define MCM_BASES MCM_BASE_PTRS
Kojto 90:cb3d968589d8 14235 #define MPU_BASES MPU_BASE_PTRS
Kojto 90:cb3d968589d8 14236 #define NV_BASES NV_BASE_PTRS
Kojto 90:cb3d968589d8 14237 #define OSC_BASES OSC_BASE_PTRS
Kojto 90:cb3d968589d8 14238 #define PDB_BASES PDB_BASE_PTRS
Kojto 90:cb3d968589d8 14239 #define PIT_BASES PIT_BASE_PTRS
Kojto 90:cb3d968589d8 14240 #define PMC_BASES PMC_BASE_PTRS
Kojto 90:cb3d968589d8 14241 #define PORT_BASES PORT_BASE_PTRS
Kojto 90:cb3d968589d8 14242 #define RCM_BASES RCM_BASE_PTRS
Kojto 90:cb3d968589d8 14243 #define RFSYS_BASES RFSYS_BASE_PTRS
Kojto 90:cb3d968589d8 14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS
Kojto 90:cb3d968589d8 14245 #define RNG_BASES RNG_BASE_PTRS
Kojto 90:cb3d968589d8 14246 #define RTC_BASES RTC_BASE_PTRS
Kojto 90:cb3d968589d8 14247 #define SDHC_BASES SDHC_BASE_PTRS
Kojto 90:cb3d968589d8 14248 #define SIM_BASES SIM_BASE_PTRS
Kojto 90:cb3d968589d8 14249 #define SMC_BASES SMC_BASE_PTRS
Kojto 90:cb3d968589d8 14250 #define SPI_BASES SPI_BASE_PTRS
Kojto 90:cb3d968589d8 14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
Kojto 90:cb3d968589d8 14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
Kojto 90:cb3d968589d8 14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
Kojto 90:cb3d968589d8 14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
Kojto 90:cb3d968589d8 14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
Kojto 90:cb3d968589d8 14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
Kojto 90:cb3d968589d8 14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
Kojto 90:cb3d968589d8 14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
Kojto 90:cb3d968589d8 14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
Kojto 90:cb3d968589d8 14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
Kojto 90:cb3d968589d8 14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
Kojto 90:cb3d968589d8 14262 #define UART_BASES UART_BASE_PTRS
Kojto 90:cb3d968589d8 14263 #define USB_BASES USB_BASE_PTRS
Kojto 90:cb3d968589d8 14264 #define USBDCD_BASES USBDCD_BASE_PTRS
Kojto 90:cb3d968589d8 14265 #define VREF_BASES VREF_BASE_PTRS
Kojto 90:cb3d968589d8 14266 #define WDOG_BASES WDOG_BASE_PTRS
Kojto 90:cb3d968589d8 14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14268 #define DMA_EARS This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
Kojto 90:cb3d968589d8 14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
Kojto 90:cb3d968589d8 14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
Kojto 90:cb3d968589d8 14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
Kojto 90:cb3d968589d8 14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
Kojto 90:cb3d968589d8 14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
Kojto 90:cb3d968589d8 14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
Kojto 90:cb3d968589d8 14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
Kojto 90:cb3d968589d8 14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
Kojto 90:cb3d968589d8 14319 #define MCG_C9 This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14323 #define MCM_PLACR This_symbol_has_been_deprecated
Kojto 90:cb3d968589d8 14324 #define ADC_BASES ADC_BASE_PTRS
Kojto 90:cb3d968589d8 14325 #define AIPS_BASES AIPS_BASE_PTRS
Kojto 90:cb3d968589d8 14326 #define AXBS_BASES AXBS_BASE_PTRS
Kojto 90:cb3d968589d8 14327 #define CAN_BASES CAN_BASE_PTRS
Kojto 90:cb3d968589d8 14328 #define CAU_BASES CAU_BASE_PTRS
Kojto 90:cb3d968589d8 14329 #define CMP_BASES CMP_BASE_PTRS
Kojto 90:cb3d968589d8 14330 #define CMT_BASES CMT_BASE_PTRS
Kojto 90:cb3d968589d8 14331 #define CRC_BASES CRC_BASE_PTRS
Kojto 90:cb3d968589d8 14332 #define DAC_BASES DAC_BASE_PTRS
Kojto 90:cb3d968589d8 14333 #define DMA_BASES DMA_BASE_PTRS
Kojto 90:cb3d968589d8 14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS
Kojto 90:cb3d968589d8 14335 #define ENET_BASES ENET_BASE_PTRS
Kojto 90:cb3d968589d8 14336 #define EWM_BASES EWM_BASE_PTRS
Kojto 90:cb3d968589d8 14337 #define FB_BASES FB_BASE_PTRS
Kojto 90:cb3d968589d8 14338 #define FMC_BASES FMC_BASE_PTRS
Kojto 90:cb3d968589d8 14339 #define FTFE_BASES FTFE_BASE_PTRS
Kojto 90:cb3d968589d8 14340 #define FTM_BASES FTM_BASE_PTRS
Kojto 90:cb3d968589d8 14341 #define GPIO_BASES GPIO_BASE_PTRS
Kojto 90:cb3d968589d8 14342 #define I2C_BASES I2C_BASE_PTRS
Kojto 90:cb3d968589d8 14343 #define I2S_BASES I2S_BASE_PTRS
Kojto 90:cb3d968589d8 14344 #define LLWU_BASES LLWU_BASE_PTRS
Kojto 90:cb3d968589d8 14345 #define LPTMR_BASES LPTMR_BASE_PTRS
Kojto 90:cb3d968589d8 14346 #define MCG_BASES MCG_BASE_PTRS
Kojto 90:cb3d968589d8 14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
Kojto 90:cb3d968589d8 14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
Kojto 90:cb3d968589d8 14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
Kojto 90:cb3d968589d8 14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
Kojto 90:cb3d968589d8 14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
Kojto 90:cb3d968589d8 14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
Kojto 90:cb3d968589d8 14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
Kojto 90:cb3d968589d8 14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
Kojto 90:cb3d968589d8 14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
Kojto 90:cb3d968589d8 14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
Kojto 90:cb3d968589d8 14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
Kojto 90:cb3d968589d8 14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
Kojto 90:cb3d968589d8 14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
Kojto 90:cb3d968589d8 14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
Kojto 90:cb3d968589d8 14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
Kojto 90:cb3d968589d8 14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
Kojto 90:cb3d968589d8 14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
Kojto 90:cb3d968589d8 14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
Kojto 90:cb3d968589d8 14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
Kojto 90:cb3d968589d8 14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
Kojto 90:cb3d968589d8 14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
Kojto 90:cb3d968589d8 14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
Kojto 90:cb3d968589d8 14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
Kojto 90:cb3d968589d8 14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
Kojto 90:cb3d968589d8 14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
Kojto 90:cb3d968589d8 14372 #define MCM_BASES MCM_BASE_PTRS
Kojto 90:cb3d968589d8 14373 #define MPU_BASES MPU_BASE_PTRS
Kojto 90:cb3d968589d8 14374 #define NV_BASES NV_BASE_PTRS
Kojto 90:cb3d968589d8 14375 #define OSC_BASES OSC_BASE_PTRS
Kojto 90:cb3d968589d8 14376 #define PDB_BASES PDB_BASE_PTRS
Kojto 90:cb3d968589d8 14377 #define PIT_BASES PIT_BASE_PTRS
Kojto 90:cb3d968589d8 14378 #define PMC_BASES PMC_BASE_PTRS
Kojto 90:cb3d968589d8 14379 #define PORT_BASES PORT_BASE_PTRS
Kojto 90:cb3d968589d8 14380 #define RCM_BASES RCM_BASE_PTRS
Kojto 90:cb3d968589d8 14381 #define RFSYS_BASES RFSYS_BASE_PTRS
Kojto 90:cb3d968589d8 14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS
Kojto 90:cb3d968589d8 14383 #define RNG_BASES RNG_BASE_PTRS
Kojto 90:cb3d968589d8 14384 #define RTC_BASES RTC_BASE_PTRS
Kojto 90:cb3d968589d8 14385 #define SDHC_BASES SDHC_BASE_PTRS
Kojto 90:cb3d968589d8 14386 #define SIM_BASES SIM_BASE_PTRS
Kojto 90:cb3d968589d8 14387 #define SMC_BASES SMC_BASE_PTRS
Kojto 90:cb3d968589d8 14388 #define SPI_BASES SPI_BASE_PTRS
Kojto 90:cb3d968589d8 14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
Kojto 90:cb3d968589d8 14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
Kojto 90:cb3d968589d8 14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
Kojto 90:cb3d968589d8 14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
Kojto 90:cb3d968589d8 14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
Kojto 90:cb3d968589d8 14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
Kojto 90:cb3d968589d8 14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
Kojto 90:cb3d968589d8 14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
Kojto 90:cb3d968589d8 14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
Kojto 90:cb3d968589d8 14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
Kojto 90:cb3d968589d8 14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
Kojto 90:cb3d968589d8 14400 #define UART_BASES UART_BASE_PTRS
Kojto 90:cb3d968589d8 14401 #define USB_BASES USB_BASE_PTRS
Kojto 90:cb3d968589d8 14402 #define USBDCD_BASES USBDCD_BASE_PTRS
Kojto 90:cb3d968589d8 14403 #define VREF_BASES VREF_BASE_PTRS
Kojto 90:cb3d968589d8 14404 #define WDOG_BASES WDOG_BASE_PTRS
Kojto 90:cb3d968589d8 14405
Kojto 90:cb3d968589d8 14406 /*!
Kojto 90:cb3d968589d8 14407 * @}
Kojto 90:cb3d968589d8 14408 */ /* end of group Backward_Compatibility_Symbols */
Kojto 90:cb3d968589d8 14409
Kojto 90:cb3d968589d8 14410
Kojto 90:cb3d968589d8 14411 #else /* #if !defined(MK64F12_H_) */
Kojto 90:cb3d968589d8 14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
Kojto 90:cb3d968589d8 14413 #if (MCU_MEM_MAP_VERSION != 0x0200u)
Kojto 90:cb3d968589d8 14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
Kojto 90:cb3d968589d8 14415 #warning There are included two not compatible versions of memory maps. Please check possible differences.
Kojto 90:cb3d968589d8 14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
Kojto 90:cb3d968589d8 14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
Kojto 90:cb3d968589d8 14418 #endif /* #if !defined(MK64F12_H_) */
Kojto 90:cb3d968589d8 14419
Kojto 90:cb3d968589d8 14420 /* MK64F12.h, eof. */