mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

drivers/SPI.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /* mbed Microcontroller Library
<> 128:9bcdf88f62b0 2 * Copyright (c) 2006-2015 ARM Limited
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 128:9bcdf88f62b0 5 * you may not use this file except in compliance with the License.
<> 128:9bcdf88f62b0 6 * You may obtain a copy of the License at
<> 128:9bcdf88f62b0 7 *
<> 128:9bcdf88f62b0 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Unless required by applicable law or agreed to in writing, software
<> 128:9bcdf88f62b0 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 128:9bcdf88f62b0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 128:9bcdf88f62b0 13 * See the License for the specific language governing permissions and
<> 128:9bcdf88f62b0 14 * limitations under the License.
<> 128:9bcdf88f62b0 15 */
<> 128:9bcdf88f62b0 16 #ifndef MBED_SPI_H
<> 128:9bcdf88f62b0 17 #define MBED_SPI_H
<> 128:9bcdf88f62b0 18
<> 128:9bcdf88f62b0 19 #include "platform/platform.h"
<> 128:9bcdf88f62b0 20
<> 128:9bcdf88f62b0 21 #if DEVICE_SPI
<> 128:9bcdf88f62b0 22
<> 128:9bcdf88f62b0 23 #include "platform/PlatformMutex.h"
<> 128:9bcdf88f62b0 24 #include "hal/spi_api.h"
<> 128:9bcdf88f62b0 25 #include "platform/SingletonPtr.h"
<> 128:9bcdf88f62b0 26
<> 128:9bcdf88f62b0 27 #if DEVICE_SPI_ASYNCH
<> 128:9bcdf88f62b0 28 #include "platform/CThunk.h"
<> 128:9bcdf88f62b0 29 #include "hal/dma_api.h"
<> 128:9bcdf88f62b0 30 #include "platform/CircularBuffer.h"
<> 128:9bcdf88f62b0 31 #include "platform/FunctionPointer.h"
<> 128:9bcdf88f62b0 32 #include "platform/Transaction.h"
<> 128:9bcdf88f62b0 33 #endif
<> 128:9bcdf88f62b0 34
<> 128:9bcdf88f62b0 35 namespace mbed {
<> 128:9bcdf88f62b0 36 /** \addtogroup drivers */
<> 128:9bcdf88f62b0 37 /** @{*/
<> 128:9bcdf88f62b0 38
<> 128:9bcdf88f62b0 39 /** A SPI Master, used for communicating with SPI slave devices
<> 128:9bcdf88f62b0 40 *
<> 128:9bcdf88f62b0 41 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
<> 128:9bcdf88f62b0 42 *
<> 128:9bcdf88f62b0 43 * Most SPI devices will also require Chip Select and Reset signals. These
<> 128:9bcdf88f62b0 44 * can be controlled using <DigitalOut> pins
<> 128:9bcdf88f62b0 45 *
<> 128:9bcdf88f62b0 46 * @Note Synchronization level: Thread safe
<> 128:9bcdf88f62b0 47 *
<> 128:9bcdf88f62b0 48 * Example:
<> 128:9bcdf88f62b0 49 * @code
<> 128:9bcdf88f62b0 50 * // Send a byte to a SPI slave, and record the response
<> 128:9bcdf88f62b0 51 *
<> 128:9bcdf88f62b0 52 * #include "mbed.h"
<> 128:9bcdf88f62b0 53 *
<> 128:9bcdf88f62b0 54 * // hardware ssel (where applicable)
<> 128:9bcdf88f62b0 55 * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
<> 128:9bcdf88f62b0 56 *
<> 128:9bcdf88f62b0 57 * // software ssel
<> 128:9bcdf88f62b0 58 * SPI device(p5, p6, p7); // mosi, miso, sclk
<> 128:9bcdf88f62b0 59 * DigitalOut cs(p8); // ssel
<> 128:9bcdf88f62b0 60 *
<> 128:9bcdf88f62b0 61 * int main() {
<> 128:9bcdf88f62b0 62 * // hardware ssel (where applicable)
<> 128:9bcdf88f62b0 63 * //int response = device.write(0xFF);
<> 128:9bcdf88f62b0 64 *
<> 128:9bcdf88f62b0 65 * device.lock();
<> 128:9bcdf88f62b0 66 * // software ssel
<> 128:9bcdf88f62b0 67 * cs = 0;
<> 128:9bcdf88f62b0 68 * int response = device.write(0xFF);
<> 128:9bcdf88f62b0 69 * cs = 1;
<> 128:9bcdf88f62b0 70 * device.unlock();
<> 128:9bcdf88f62b0 71 *
<> 128:9bcdf88f62b0 72 * }
<> 128:9bcdf88f62b0 73 * @endcode
<> 128:9bcdf88f62b0 74 */
<> 128:9bcdf88f62b0 75 class SPI {
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 public:
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /** Create a SPI master connected to the specified pins
<> 128:9bcdf88f62b0 80 *
<> 128:9bcdf88f62b0 81 * mosi or miso can be specfied as NC if not used
<> 128:9bcdf88f62b0 82 *
<> 128:9bcdf88f62b0 83 * @param mosi SPI Master Out, Slave In pin
<> 128:9bcdf88f62b0 84 * @param miso SPI Master In, Slave Out pin
<> 128:9bcdf88f62b0 85 * @param sclk SPI Clock pin
<> 128:9bcdf88f62b0 86 * @param ssel SPI chip select pin
<> 128:9bcdf88f62b0 87 */
<> 128:9bcdf88f62b0 88 SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 /** Configure the data transmission format
<> 128:9bcdf88f62b0 91 *
<> 128:9bcdf88f62b0 92 * @param bits Number of bits per SPI frame (4 - 16)
<> 128:9bcdf88f62b0 93 * @param mode Clock polarity and phase mode (0 - 3)
<> 128:9bcdf88f62b0 94 *
<> 128:9bcdf88f62b0 95 * @code
<> 128:9bcdf88f62b0 96 * mode | POL PHA
<> 128:9bcdf88f62b0 97 * -----+--------
<> 128:9bcdf88f62b0 98 * 0 | 0 0
<> 128:9bcdf88f62b0 99 * 1 | 0 1
<> 128:9bcdf88f62b0 100 * 2 | 1 0
<> 128:9bcdf88f62b0 101 * 3 | 1 1
<> 128:9bcdf88f62b0 102 * @endcode
<> 128:9bcdf88f62b0 103 */
<> 128:9bcdf88f62b0 104 void format(int bits, int mode = 0);
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 /** Set the spi bus clock frequency
<> 128:9bcdf88f62b0 107 *
<> 128:9bcdf88f62b0 108 * @param hz SCLK frequency in hz (default = 1MHz)
<> 128:9bcdf88f62b0 109 */
<> 128:9bcdf88f62b0 110 void frequency(int hz = 1000000);
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 /** Write to the SPI Slave and return the response
<> 128:9bcdf88f62b0 113 *
<> 128:9bcdf88f62b0 114 * @param value Data to be sent to the SPI slave
<> 128:9bcdf88f62b0 115 *
<> 128:9bcdf88f62b0 116 * @returns
<> 128:9bcdf88f62b0 117 * Response from the SPI slave
<> 128:9bcdf88f62b0 118 */
<> 128:9bcdf88f62b0 119 virtual int write(int value);
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 /** Acquire exclusive access to this SPI bus
<> 128:9bcdf88f62b0 122 */
<> 128:9bcdf88f62b0 123 virtual void lock(void);
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /** Release exclusive access to this SPI bus
<> 128:9bcdf88f62b0 126 */
<> 128:9bcdf88f62b0 127 virtual void unlock(void);
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 #if DEVICE_SPI_ASYNCH
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 /** Start non-blocking SPI transfer using 8bit buffers.
<> 128:9bcdf88f62b0 132 *
<> 128:9bcdf88f62b0 133 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
<> 128:9bcdf88f62b0 134 * the default SPI value is sent
<> 128:9bcdf88f62b0 135 * @param tx_length The length of TX buffer in bytes
<> 128:9bcdf88f62b0 136 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
<> 128:9bcdf88f62b0 137 * received data are ignored
<> 128:9bcdf88f62b0 138 * @param rx_length The length of RX buffer in bytes
<> 128:9bcdf88f62b0 139 * @param callback The event callback function
<> 128:9bcdf88f62b0 140 * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
<> 128:9bcdf88f62b0 141 * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
<> 128:9bcdf88f62b0 142 */
<> 128:9bcdf88f62b0 143 template<typename Type>
<> 128:9bcdf88f62b0 144 int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
<> 128:9bcdf88f62b0 145 if (spi_active(&_spi)) {
<> 128:9bcdf88f62b0 146 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
<> 128:9bcdf88f62b0 147 }
<> 128:9bcdf88f62b0 148 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
<> 128:9bcdf88f62b0 149 return 0;
<> 128:9bcdf88f62b0 150 }
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
<> 128:9bcdf88f62b0 153 */
<> 128:9bcdf88f62b0 154 void abort_transfer();
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /** Clear the transaction buffer
<> 128:9bcdf88f62b0 157 */
<> 128:9bcdf88f62b0 158 void clear_transfer_buffer();
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 /** Clear the transaction buffer and abort on-going transfer.
<> 128:9bcdf88f62b0 161 */
<> 128:9bcdf88f62b0 162 void abort_all_transfers();
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** Configure DMA usage suggestion for non-blocking transfers
<> 128:9bcdf88f62b0 165 *
<> 128:9bcdf88f62b0 166 * @param usage The usage DMA hint for peripheral
<> 128:9bcdf88f62b0 167 * @return Zero if the usage was set, -1 if a transaction is on-going
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169 int set_dma_usage(DMAUsage usage);
<> 128:9bcdf88f62b0 170
<> 128:9bcdf88f62b0 171 protected:
<> 128:9bcdf88f62b0 172 /** SPI IRQ handler
<> 128:9bcdf88f62b0 173 *
<> 128:9bcdf88f62b0 174 */
<> 128:9bcdf88f62b0 175 void irq_handler_asynch(void);
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177 /** Common transfer method
<> 128:9bcdf88f62b0 178 *
<> 128:9bcdf88f62b0 179 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
<> 128:9bcdf88f62b0 180 * the default SPI value is sent
<> 128:9bcdf88f62b0 181 * @param tx_length The length of TX buffer in bytes
<> 128:9bcdf88f62b0 182 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
<> 128:9bcdf88f62b0 183 * received data are ignored
<> 128:9bcdf88f62b0 184 * @param rx_length The length of RX buffer in bytes
<> 128:9bcdf88f62b0 185 * @param bit_width The buffers element width
<> 128:9bcdf88f62b0 186 * @param callback The event callback function
<> 128:9bcdf88f62b0 187 * @param event The logical OR of events to modify
<> 128:9bcdf88f62b0 188 * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
<> 128:9bcdf88f62b0 189 */
<> 128:9bcdf88f62b0 190 int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 /**
<> 128:9bcdf88f62b0 193 *
<> 128:9bcdf88f62b0 194 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
<> 128:9bcdf88f62b0 195 * the default SPI value is sent
<> 128:9bcdf88f62b0 196 * @param tx_length The length of TX buffer in bytes
<> 128:9bcdf88f62b0 197 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
<> 128:9bcdf88f62b0 198 * received data are ignored
<> 128:9bcdf88f62b0 199 * @param rx_length The length of RX buffer in bytes
<> 128:9bcdf88f62b0 200 * @param bit_width The buffers element width
<> 128:9bcdf88f62b0 201 * @param callback The event callback function
<> 128:9bcdf88f62b0 202 * @param event The logical OR of events to modify
<> 128:9bcdf88f62b0 203 * @return Zero if a transfer was added to the queue, or -1 if the queue is full
<> 128:9bcdf88f62b0 204 */
<> 128:9bcdf88f62b0 205 int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
<> 128:9bcdf88f62b0 206
<> 128:9bcdf88f62b0 207 /** Configures a callback, spi peripheral and initiate a new transfer
<> 128:9bcdf88f62b0 208 *
<> 128:9bcdf88f62b0 209 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
<> 128:9bcdf88f62b0 210 * the default SPI value is sent
<> 128:9bcdf88f62b0 211 * @param tx_length The length of TX buffer in bytes
<> 128:9bcdf88f62b0 212 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
<> 128:9bcdf88f62b0 213 * received data are ignored
<> 128:9bcdf88f62b0 214 * @param rx_length The length of RX buffer in bytes
<> 128:9bcdf88f62b0 215 * @param bit_width The buffers element width
<> 128:9bcdf88f62b0 216 * @param callback The event callback function
<> 128:9bcdf88f62b0 217 * @param event The logical OR of events to modify
<> 128:9bcdf88f62b0 218 */
<> 128:9bcdf88f62b0 219 void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 #if TRANSACTION_QUEUE_SIZE_SPI
<> 128:9bcdf88f62b0 222
<> 128:9bcdf88f62b0 223 /** Start a new transaction
<> 128:9bcdf88f62b0 224 *
<> 128:9bcdf88f62b0 225 * @param data Transaction data
<> 128:9bcdf88f62b0 226 */
<> 128:9bcdf88f62b0 227 void start_transaction(transaction_t *data);
<> 128:9bcdf88f62b0 228
<> 128:9bcdf88f62b0 229 /** Dequeue a transaction
<> 128:9bcdf88f62b0 230 *
<> 128:9bcdf88f62b0 231 */
<> 128:9bcdf88f62b0 232 void dequeue_transaction();
<> 128:9bcdf88f62b0 233 static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
<> 128:9bcdf88f62b0 234 #endif
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 #endif
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 public:
<> 128:9bcdf88f62b0 239 virtual ~SPI() {
<> 128:9bcdf88f62b0 240 }
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 protected:
<> 128:9bcdf88f62b0 243 spi_t _spi;
<> 128:9bcdf88f62b0 244
<> 128:9bcdf88f62b0 245 #if DEVICE_SPI_ASYNCH
<> 128:9bcdf88f62b0 246 CThunk<SPI> _irq;
<> 128:9bcdf88f62b0 247 event_callback_t _callback;
<> 128:9bcdf88f62b0 248 DMAUsage _usage;
<> 128:9bcdf88f62b0 249 #endif
<> 128:9bcdf88f62b0 250
<> 128:9bcdf88f62b0 251 void aquire(void);
<> 128:9bcdf88f62b0 252 static SPI *_owner;
<> 128:9bcdf88f62b0 253 static SingletonPtr<PlatformMutex> _mutex;
<> 128:9bcdf88f62b0 254 int _bits;
<> 128:9bcdf88f62b0 255 int _mode;
<> 128:9bcdf88f62b0 256 int _hz;
<> 128:9bcdf88f62b0 257 };
<> 128:9bcdf88f62b0 258
<> 128:9bcdf88f62b0 259 } // namespace mbed
<> 128:9bcdf88f62b0 260
<> 128:9bcdf88f62b0 261 #endif
<> 128:9bcdf88f62b0 262
<> 128:9bcdf88f62b0 263 #endif
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 /** @}*/