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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_THUNDERBOARD_SENSE/core_cmFunc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
132:9baf128c2fab 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_cmFunc.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 132:9baf128c2fab 4 * @version V4.10
<> 132:9baf128c2fab 5 * @date 18. March 2015
<> 132:9baf128c2fab 6 *
<> 132:9baf128c2fab 7 * @note
<> 132:9baf128c2fab 8 *
<> 132:9baf128c2fab 9 ******************************************************************************/
<> 132:9baf128c2fab 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 132:9baf128c2fab 11
<> 132:9baf128c2fab 12 All rights reserved.
<> 132:9baf128c2fab 13 Redistribution and use in source and binary forms, with or without
<> 132:9baf128c2fab 14 modification, are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 - Redistributions of source code must retain the above copyright
<> 132:9baf128c2fab 16 notice, this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 - Redistributions in binary form must reproduce the above copyright
<> 132:9baf128c2fab 18 notice, this list of conditions and the following disclaimer in the
<> 132:9baf128c2fab 19 documentation and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 - Neither the name of ARM nor the names of its contributors may be used
<> 132:9baf128c2fab 21 to endorse or promote products derived from this software without
<> 132:9baf128c2fab 22 specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 132:9baf128c2fab 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 132:9baf128c2fab 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 132:9baf128c2fab 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 132:9baf128c2fab 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 132:9baf128c2fab 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 132:9baf128c2fab 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 132:9baf128c2fab 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 132:9baf128c2fab 34 POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 35 ---------------------------------------------------------------------------*/
<> 132:9baf128c2fab 36
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 #ifndef __CORE_CMFUNC_H
<> 132:9baf128c2fab 39 #define __CORE_CMFUNC_H
<> 132:9baf128c2fab 40
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 /* ########################### Core Function Access ########################### */
<> 132:9baf128c2fab 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 132:9baf128c2fab 45 @{
<> 132:9baf128c2fab 46 */
<> 132:9baf128c2fab 47
<> 132:9baf128c2fab 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 132:9baf128c2fab 49 /* ARM armcc specific functions */
<> 132:9baf128c2fab 50
<> 132:9baf128c2fab 51 #if (__ARMCC_VERSION < 400677)
<> 132:9baf128c2fab 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 132:9baf128c2fab 53 #endif
<> 132:9baf128c2fab 54
<> 132:9baf128c2fab 55 /* intrinsic void __enable_irq(); */
<> 132:9baf128c2fab 56 /* intrinsic void __disable_irq(); */
<> 132:9baf128c2fab 57
<> 132:9baf128c2fab 58 /** \brief Get Control Register
<> 132:9baf128c2fab 59
<> 132:9baf128c2fab 60 This function returns the content of the Control Register.
<> 132:9baf128c2fab 61
<> 132:9baf128c2fab 62 \return Control Register value
<> 132:9baf128c2fab 63 */
<> 132:9baf128c2fab 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 132:9baf128c2fab 65 {
<> 132:9baf128c2fab 66 register uint32_t __regControl __ASM("control");
<> 132:9baf128c2fab 67 return(__regControl);
<> 132:9baf128c2fab 68 }
<> 132:9baf128c2fab 69
<> 132:9baf128c2fab 70
<> 132:9baf128c2fab 71 /** \brief Set Control Register
<> 132:9baf128c2fab 72
<> 132:9baf128c2fab 73 This function writes the given value to the Control Register.
<> 132:9baf128c2fab 74
<> 132:9baf128c2fab 75 \param [in] control Control Register value to set
<> 132:9baf128c2fab 76 */
<> 132:9baf128c2fab 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 132:9baf128c2fab 78 {
<> 132:9baf128c2fab 79 register uint32_t __regControl __ASM("control");
<> 132:9baf128c2fab 80 __regControl = control;
<> 132:9baf128c2fab 81 }
<> 132:9baf128c2fab 82
<> 132:9baf128c2fab 83
<> 132:9baf128c2fab 84 /** \brief Get IPSR Register
<> 132:9baf128c2fab 85
<> 132:9baf128c2fab 86 This function returns the content of the IPSR Register.
<> 132:9baf128c2fab 87
<> 132:9baf128c2fab 88 \return IPSR Register value
<> 132:9baf128c2fab 89 */
<> 132:9baf128c2fab 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 132:9baf128c2fab 91 {
<> 132:9baf128c2fab 92 register uint32_t __regIPSR __ASM("ipsr");
<> 132:9baf128c2fab 93 return(__regIPSR);
<> 132:9baf128c2fab 94 }
<> 132:9baf128c2fab 95
<> 132:9baf128c2fab 96
<> 132:9baf128c2fab 97 /** \brief Get APSR Register
<> 132:9baf128c2fab 98
<> 132:9baf128c2fab 99 This function returns the content of the APSR Register.
<> 132:9baf128c2fab 100
<> 132:9baf128c2fab 101 \return APSR Register value
<> 132:9baf128c2fab 102 */
<> 132:9baf128c2fab 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 132:9baf128c2fab 104 {
<> 132:9baf128c2fab 105 register uint32_t __regAPSR __ASM("apsr");
<> 132:9baf128c2fab 106 return(__regAPSR);
<> 132:9baf128c2fab 107 }
<> 132:9baf128c2fab 108
<> 132:9baf128c2fab 109
<> 132:9baf128c2fab 110 /** \brief Get xPSR Register
<> 132:9baf128c2fab 111
<> 132:9baf128c2fab 112 This function returns the content of the xPSR Register.
<> 132:9baf128c2fab 113
<> 132:9baf128c2fab 114 \return xPSR Register value
<> 132:9baf128c2fab 115 */
<> 132:9baf128c2fab 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 132:9baf128c2fab 117 {
<> 132:9baf128c2fab 118 register uint32_t __regXPSR __ASM("xpsr");
<> 132:9baf128c2fab 119 return(__regXPSR);
<> 132:9baf128c2fab 120 }
<> 132:9baf128c2fab 121
<> 132:9baf128c2fab 122
<> 132:9baf128c2fab 123 /** \brief Get Process Stack Pointer
<> 132:9baf128c2fab 124
<> 132:9baf128c2fab 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 132:9baf128c2fab 126
<> 132:9baf128c2fab 127 \return PSP Register value
<> 132:9baf128c2fab 128 */
<> 132:9baf128c2fab 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 132:9baf128c2fab 130 {
<> 132:9baf128c2fab 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 132:9baf128c2fab 132 return(__regProcessStackPointer);
<> 132:9baf128c2fab 133 }
<> 132:9baf128c2fab 134
<> 132:9baf128c2fab 135
<> 132:9baf128c2fab 136 /** \brief Set Process Stack Pointer
<> 132:9baf128c2fab 137
<> 132:9baf128c2fab 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 132:9baf128c2fab 139
<> 132:9baf128c2fab 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 132:9baf128c2fab 141 */
<> 132:9baf128c2fab 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 132:9baf128c2fab 143 {
<> 132:9baf128c2fab 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 132:9baf128c2fab 145 __regProcessStackPointer = topOfProcStack;
<> 132:9baf128c2fab 146 }
<> 132:9baf128c2fab 147
<> 132:9baf128c2fab 148
<> 132:9baf128c2fab 149 /** \brief Get Main Stack Pointer
<> 132:9baf128c2fab 150
<> 132:9baf128c2fab 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 132:9baf128c2fab 152
<> 132:9baf128c2fab 153 \return MSP Register value
<> 132:9baf128c2fab 154 */
<> 132:9baf128c2fab 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 132:9baf128c2fab 156 {
<> 132:9baf128c2fab 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 132:9baf128c2fab 158 return(__regMainStackPointer);
<> 132:9baf128c2fab 159 }
<> 132:9baf128c2fab 160
<> 132:9baf128c2fab 161
<> 132:9baf128c2fab 162 /** \brief Set Main Stack Pointer
<> 132:9baf128c2fab 163
<> 132:9baf128c2fab 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 132:9baf128c2fab 165
<> 132:9baf128c2fab 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 132:9baf128c2fab 167 */
<> 132:9baf128c2fab 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 132:9baf128c2fab 169 {
<> 132:9baf128c2fab 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 132:9baf128c2fab 171 __regMainStackPointer = topOfMainStack;
<> 132:9baf128c2fab 172 }
<> 132:9baf128c2fab 173
<> 132:9baf128c2fab 174
<> 132:9baf128c2fab 175 /** \brief Get Priority Mask
<> 132:9baf128c2fab 176
<> 132:9baf128c2fab 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 132:9baf128c2fab 178
<> 132:9baf128c2fab 179 \return Priority Mask value
<> 132:9baf128c2fab 180 */
<> 132:9baf128c2fab 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 132:9baf128c2fab 182 {
<> 132:9baf128c2fab 183 register uint32_t __regPriMask __ASM("primask");
<> 132:9baf128c2fab 184 return(__regPriMask);
<> 132:9baf128c2fab 185 }
<> 132:9baf128c2fab 186
<> 132:9baf128c2fab 187
<> 132:9baf128c2fab 188 /** \brief Set Priority Mask
<> 132:9baf128c2fab 189
<> 132:9baf128c2fab 190 This function assigns the given value to the Priority Mask Register.
<> 132:9baf128c2fab 191
<> 132:9baf128c2fab 192 \param [in] priMask Priority Mask
<> 132:9baf128c2fab 193 */
<> 132:9baf128c2fab 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 132:9baf128c2fab 195 {
<> 132:9baf128c2fab 196 register uint32_t __regPriMask __ASM("primask");
<> 132:9baf128c2fab 197 __regPriMask = (priMask);
<> 132:9baf128c2fab 198 }
<> 132:9baf128c2fab 199
<> 132:9baf128c2fab 200
<> 132:9baf128c2fab 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 132:9baf128c2fab 202
<> 132:9baf128c2fab 203 /** \brief Enable FIQ
<> 132:9baf128c2fab 204
<> 132:9baf128c2fab 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 132:9baf128c2fab 206 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 207 */
<> 132:9baf128c2fab 208 #define __enable_fault_irq __enable_fiq
<> 132:9baf128c2fab 209
<> 132:9baf128c2fab 210
<> 132:9baf128c2fab 211 /** \brief Disable FIQ
<> 132:9baf128c2fab 212
<> 132:9baf128c2fab 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 132:9baf128c2fab 214 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 215 */
<> 132:9baf128c2fab 216 #define __disable_fault_irq __disable_fiq
<> 132:9baf128c2fab 217
<> 132:9baf128c2fab 218
<> 132:9baf128c2fab 219 /** \brief Get Base Priority
<> 132:9baf128c2fab 220
<> 132:9baf128c2fab 221 This function returns the current value of the Base Priority register.
<> 132:9baf128c2fab 222
<> 132:9baf128c2fab 223 \return Base Priority register value
<> 132:9baf128c2fab 224 */
<> 132:9baf128c2fab 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 132:9baf128c2fab 226 {
<> 132:9baf128c2fab 227 register uint32_t __regBasePri __ASM("basepri");
<> 132:9baf128c2fab 228 return(__regBasePri);
<> 132:9baf128c2fab 229 }
<> 132:9baf128c2fab 230
<> 132:9baf128c2fab 231
<> 132:9baf128c2fab 232 /** \brief Set Base Priority
<> 132:9baf128c2fab 233
<> 132:9baf128c2fab 234 This function assigns the given value to the Base Priority register.
<> 132:9baf128c2fab 235
<> 132:9baf128c2fab 236 \param [in] basePri Base Priority value to set
<> 132:9baf128c2fab 237 */
<> 132:9baf128c2fab 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 132:9baf128c2fab 239 {
<> 132:9baf128c2fab 240 register uint32_t __regBasePri __ASM("basepri");
<> 132:9baf128c2fab 241 __regBasePri = (basePri & 0xff);
<> 132:9baf128c2fab 242 }
<> 132:9baf128c2fab 243
<> 132:9baf128c2fab 244
<> 132:9baf128c2fab 245 /** \brief Set Base Priority with condition
<> 132:9baf128c2fab 246
<> 132:9baf128c2fab 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 132:9baf128c2fab 248 or the new value increases the BASEPRI priority level.
<> 132:9baf128c2fab 249
<> 132:9baf128c2fab 250 \param [in] basePri Base Priority value to set
<> 132:9baf128c2fab 251 */
<> 132:9baf128c2fab 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 132:9baf128c2fab 253 {
<> 132:9baf128c2fab 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 132:9baf128c2fab 255 __regBasePriMax = (basePri & 0xff);
<> 132:9baf128c2fab 256 }
<> 132:9baf128c2fab 257
<> 132:9baf128c2fab 258
<> 132:9baf128c2fab 259 /** \brief Get Fault Mask
<> 132:9baf128c2fab 260
<> 132:9baf128c2fab 261 This function returns the current value of the Fault Mask register.
<> 132:9baf128c2fab 262
<> 132:9baf128c2fab 263 \return Fault Mask register value
<> 132:9baf128c2fab 264 */
<> 132:9baf128c2fab 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 132:9baf128c2fab 266 {
<> 132:9baf128c2fab 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 132:9baf128c2fab 268 return(__regFaultMask);
<> 132:9baf128c2fab 269 }
<> 132:9baf128c2fab 270
<> 132:9baf128c2fab 271
<> 132:9baf128c2fab 272 /** \brief Set Fault Mask
<> 132:9baf128c2fab 273
<> 132:9baf128c2fab 274 This function assigns the given value to the Fault Mask register.
<> 132:9baf128c2fab 275
<> 132:9baf128c2fab 276 \param [in] faultMask Fault Mask value to set
<> 132:9baf128c2fab 277 */
<> 132:9baf128c2fab 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 132:9baf128c2fab 279 {
<> 132:9baf128c2fab 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 132:9baf128c2fab 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 132:9baf128c2fab 282 }
<> 132:9baf128c2fab 283
<> 132:9baf128c2fab 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 132:9baf128c2fab 285
<> 132:9baf128c2fab 286
<> 132:9baf128c2fab 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 132:9baf128c2fab 288
<> 132:9baf128c2fab 289 /** \brief Get FPSCR
<> 132:9baf128c2fab 290
<> 132:9baf128c2fab 291 This function returns the current value of the Floating Point Status/Control register.
<> 132:9baf128c2fab 292
<> 132:9baf128c2fab 293 \return Floating Point Status/Control register value
<> 132:9baf128c2fab 294 */
<> 132:9baf128c2fab 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 132:9baf128c2fab 296 {
<> 132:9baf128c2fab 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 132:9baf128c2fab 298 register uint32_t __regfpscr __ASM("fpscr");
<> 132:9baf128c2fab 299 return(__regfpscr);
<> 132:9baf128c2fab 300 #else
<> 132:9baf128c2fab 301 return(0);
<> 132:9baf128c2fab 302 #endif
<> 132:9baf128c2fab 303 }
<> 132:9baf128c2fab 304
<> 132:9baf128c2fab 305
<> 132:9baf128c2fab 306 /** \brief Set FPSCR
<> 132:9baf128c2fab 307
<> 132:9baf128c2fab 308 This function assigns the given value to the Floating Point Status/Control register.
<> 132:9baf128c2fab 309
<> 132:9baf128c2fab 310 \param [in] fpscr Floating Point Status/Control value to set
<> 132:9baf128c2fab 311 */
<> 132:9baf128c2fab 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 132:9baf128c2fab 313 {
<> 132:9baf128c2fab 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 132:9baf128c2fab 315 register uint32_t __regfpscr __ASM("fpscr");
<> 132:9baf128c2fab 316 __regfpscr = (fpscr);
<> 132:9baf128c2fab 317 #endif
<> 132:9baf128c2fab 318 }
<> 132:9baf128c2fab 319
<> 132:9baf128c2fab 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 132:9baf128c2fab 321
<> 132:9baf128c2fab 322
<> 132:9baf128c2fab 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 132:9baf128c2fab 324 /* GNU gcc specific functions */
<> 132:9baf128c2fab 325
<> 132:9baf128c2fab 326 /** \brief Enable IRQ Interrupts
<> 132:9baf128c2fab 327
<> 132:9baf128c2fab 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 132:9baf128c2fab 329 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 330 */
<> 132:9baf128c2fab 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 132:9baf128c2fab 332 {
<> 132:9baf128c2fab 333 __ASM volatile ("cpsie i" : : : "memory");
<> 132:9baf128c2fab 334 }
<> 132:9baf128c2fab 335
<> 132:9baf128c2fab 336
<> 132:9baf128c2fab 337 /** \brief Disable IRQ Interrupts
<> 132:9baf128c2fab 338
<> 132:9baf128c2fab 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 132:9baf128c2fab 340 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 341 */
<> 132:9baf128c2fab 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 132:9baf128c2fab 343 {
<> 132:9baf128c2fab 344 __ASM volatile ("cpsid i" : : : "memory");
<> 132:9baf128c2fab 345 }
<> 132:9baf128c2fab 346
<> 132:9baf128c2fab 347
<> 132:9baf128c2fab 348 /** \brief Get Control Register
<> 132:9baf128c2fab 349
<> 132:9baf128c2fab 350 This function returns the content of the Control Register.
<> 132:9baf128c2fab 351
<> 132:9baf128c2fab 352 \return Control Register value
<> 132:9baf128c2fab 353 */
<> 132:9baf128c2fab 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 132:9baf128c2fab 355 {
<> 132:9baf128c2fab 356 uint32_t result;
<> 132:9baf128c2fab 357
<> 132:9baf128c2fab 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 132:9baf128c2fab 359 return(result);
<> 132:9baf128c2fab 360 }
<> 132:9baf128c2fab 361
<> 132:9baf128c2fab 362
<> 132:9baf128c2fab 363 /** \brief Set Control Register
<> 132:9baf128c2fab 364
<> 132:9baf128c2fab 365 This function writes the given value to the Control Register.
<> 132:9baf128c2fab 366
<> 132:9baf128c2fab 367 \param [in] control Control Register value to set
<> 132:9baf128c2fab 368 */
<> 132:9baf128c2fab 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 132:9baf128c2fab 370 {
<> 132:9baf128c2fab 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 132:9baf128c2fab 372 }
<> 132:9baf128c2fab 373
<> 132:9baf128c2fab 374
<> 132:9baf128c2fab 375 /** \brief Get IPSR Register
<> 132:9baf128c2fab 376
<> 132:9baf128c2fab 377 This function returns the content of the IPSR Register.
<> 132:9baf128c2fab 378
<> 132:9baf128c2fab 379 \return IPSR Register value
<> 132:9baf128c2fab 380 */
<> 132:9baf128c2fab 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 132:9baf128c2fab 382 {
<> 132:9baf128c2fab 383 uint32_t result;
<> 132:9baf128c2fab 384
<> 132:9baf128c2fab 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 132:9baf128c2fab 386 return(result);
<> 132:9baf128c2fab 387 }
<> 132:9baf128c2fab 388
<> 132:9baf128c2fab 389
<> 132:9baf128c2fab 390 /** \brief Get APSR Register
<> 132:9baf128c2fab 391
<> 132:9baf128c2fab 392 This function returns the content of the APSR Register.
<> 132:9baf128c2fab 393
<> 132:9baf128c2fab 394 \return APSR Register value
<> 132:9baf128c2fab 395 */
<> 132:9baf128c2fab 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 132:9baf128c2fab 397 {
<> 132:9baf128c2fab 398 uint32_t result;
<> 132:9baf128c2fab 399
<> 132:9baf128c2fab 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 132:9baf128c2fab 401 return(result);
<> 132:9baf128c2fab 402 }
<> 132:9baf128c2fab 403
<> 132:9baf128c2fab 404
<> 132:9baf128c2fab 405 /** \brief Get xPSR Register
<> 132:9baf128c2fab 406
<> 132:9baf128c2fab 407 This function returns the content of the xPSR Register.
<> 132:9baf128c2fab 408
<> 132:9baf128c2fab 409 \return xPSR Register value
<> 132:9baf128c2fab 410 */
<> 132:9baf128c2fab 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 132:9baf128c2fab 412 {
<> 132:9baf128c2fab 413 uint32_t result;
<> 132:9baf128c2fab 414
<> 132:9baf128c2fab 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 132:9baf128c2fab 416 return(result);
<> 132:9baf128c2fab 417 }
<> 132:9baf128c2fab 418
<> 132:9baf128c2fab 419
<> 132:9baf128c2fab 420 /** \brief Get Process Stack Pointer
<> 132:9baf128c2fab 421
<> 132:9baf128c2fab 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 132:9baf128c2fab 423
<> 132:9baf128c2fab 424 \return PSP Register value
<> 132:9baf128c2fab 425 */
<> 132:9baf128c2fab 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 132:9baf128c2fab 427 {
<> 132:9baf128c2fab 428 register uint32_t result;
<> 132:9baf128c2fab 429
<> 132:9baf128c2fab 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 132:9baf128c2fab 431 return(result);
<> 132:9baf128c2fab 432 }
<> 132:9baf128c2fab 433
<> 132:9baf128c2fab 434
<> 132:9baf128c2fab 435 /** \brief Set Process Stack Pointer
<> 132:9baf128c2fab 436
<> 132:9baf128c2fab 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 132:9baf128c2fab 438
<> 132:9baf128c2fab 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 132:9baf128c2fab 440 */
<> 132:9baf128c2fab 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 132:9baf128c2fab 442 {
<> 132:9baf128c2fab 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 132:9baf128c2fab 444 }
<> 132:9baf128c2fab 445
<> 132:9baf128c2fab 446
<> 132:9baf128c2fab 447 /** \brief Get Main Stack Pointer
<> 132:9baf128c2fab 448
<> 132:9baf128c2fab 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 132:9baf128c2fab 450
<> 132:9baf128c2fab 451 \return MSP Register value
<> 132:9baf128c2fab 452 */
<> 132:9baf128c2fab 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 132:9baf128c2fab 454 {
<> 132:9baf128c2fab 455 register uint32_t result;
<> 132:9baf128c2fab 456
<> 132:9baf128c2fab 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 132:9baf128c2fab 458 return(result);
<> 132:9baf128c2fab 459 }
<> 132:9baf128c2fab 460
<> 132:9baf128c2fab 461
<> 132:9baf128c2fab 462 /** \brief Set Main Stack Pointer
<> 132:9baf128c2fab 463
<> 132:9baf128c2fab 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 132:9baf128c2fab 465
<> 132:9baf128c2fab 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 132:9baf128c2fab 467 */
<> 132:9baf128c2fab 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 132:9baf128c2fab 469 {
<> 132:9baf128c2fab 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 132:9baf128c2fab 471 }
<> 132:9baf128c2fab 472
<> 132:9baf128c2fab 473
<> 132:9baf128c2fab 474 /** \brief Get Priority Mask
<> 132:9baf128c2fab 475
<> 132:9baf128c2fab 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 132:9baf128c2fab 477
<> 132:9baf128c2fab 478 \return Priority Mask value
<> 132:9baf128c2fab 479 */
<> 132:9baf128c2fab 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 132:9baf128c2fab 481 {
<> 132:9baf128c2fab 482 uint32_t result;
<> 132:9baf128c2fab 483
<> 132:9baf128c2fab 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 132:9baf128c2fab 485 return(result);
<> 132:9baf128c2fab 486 }
<> 132:9baf128c2fab 487
<> 132:9baf128c2fab 488
<> 132:9baf128c2fab 489 /** \brief Set Priority Mask
<> 132:9baf128c2fab 490
<> 132:9baf128c2fab 491 This function assigns the given value to the Priority Mask Register.
<> 132:9baf128c2fab 492
<> 132:9baf128c2fab 493 \param [in] priMask Priority Mask
<> 132:9baf128c2fab 494 */
<> 132:9baf128c2fab 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 132:9baf128c2fab 496 {
<> 132:9baf128c2fab 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 132:9baf128c2fab 498 }
<> 132:9baf128c2fab 499
<> 132:9baf128c2fab 500
<> 132:9baf128c2fab 501 #if (__CORTEX_M >= 0x03)
<> 132:9baf128c2fab 502
<> 132:9baf128c2fab 503 /** \brief Enable FIQ
<> 132:9baf128c2fab 504
<> 132:9baf128c2fab 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 132:9baf128c2fab 506 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 507 */
<> 132:9baf128c2fab 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 132:9baf128c2fab 509 {
<> 132:9baf128c2fab 510 __ASM volatile ("cpsie f" : : : "memory");
<> 132:9baf128c2fab 511 }
<> 132:9baf128c2fab 512
<> 132:9baf128c2fab 513
<> 132:9baf128c2fab 514 /** \brief Disable FIQ
<> 132:9baf128c2fab 515
<> 132:9baf128c2fab 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 132:9baf128c2fab 517 Can only be executed in Privileged modes.
<> 132:9baf128c2fab 518 */
<> 132:9baf128c2fab 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 132:9baf128c2fab 520 {
<> 132:9baf128c2fab 521 __ASM volatile ("cpsid f" : : : "memory");
<> 132:9baf128c2fab 522 }
<> 132:9baf128c2fab 523
<> 132:9baf128c2fab 524
<> 132:9baf128c2fab 525 /** \brief Get Base Priority
<> 132:9baf128c2fab 526
<> 132:9baf128c2fab 527 This function returns the current value of the Base Priority register.
<> 132:9baf128c2fab 528
<> 132:9baf128c2fab 529 \return Base Priority register value
<> 132:9baf128c2fab 530 */
<> 132:9baf128c2fab 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 132:9baf128c2fab 532 {
<> 132:9baf128c2fab 533 uint32_t result;
<> 132:9baf128c2fab 534
<> 132:9baf128c2fab 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 132:9baf128c2fab 536 return(result);
<> 132:9baf128c2fab 537 }
<> 132:9baf128c2fab 538
<> 132:9baf128c2fab 539
<> 132:9baf128c2fab 540 /** \brief Set Base Priority
<> 132:9baf128c2fab 541
<> 132:9baf128c2fab 542 This function assigns the given value to the Base Priority register.
<> 132:9baf128c2fab 543
<> 132:9baf128c2fab 544 \param [in] basePri Base Priority value to set
<> 132:9baf128c2fab 545 */
<> 132:9baf128c2fab 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 132:9baf128c2fab 547 {
<> 132:9baf128c2fab 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 132:9baf128c2fab 549 }
<> 132:9baf128c2fab 550
<> 132:9baf128c2fab 551
<> 132:9baf128c2fab 552 /** \brief Set Base Priority with condition
<> 132:9baf128c2fab 553
<> 132:9baf128c2fab 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 132:9baf128c2fab 555 or the new value increases the BASEPRI priority level.
<> 132:9baf128c2fab 556
<> 132:9baf128c2fab 557 \param [in] basePri Base Priority value to set
<> 132:9baf128c2fab 558 */
<> 132:9baf128c2fab 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 132:9baf128c2fab 560 {
<> 132:9baf128c2fab 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 132:9baf128c2fab 562 }
<> 132:9baf128c2fab 563
<> 132:9baf128c2fab 564
<> 132:9baf128c2fab 565 /** \brief Get Fault Mask
<> 132:9baf128c2fab 566
<> 132:9baf128c2fab 567 This function returns the current value of the Fault Mask register.
<> 132:9baf128c2fab 568
<> 132:9baf128c2fab 569 \return Fault Mask register value
<> 132:9baf128c2fab 570 */
<> 132:9baf128c2fab 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 132:9baf128c2fab 572 {
<> 132:9baf128c2fab 573 uint32_t result;
<> 132:9baf128c2fab 574
<> 132:9baf128c2fab 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 132:9baf128c2fab 576 return(result);
<> 132:9baf128c2fab 577 }
<> 132:9baf128c2fab 578
<> 132:9baf128c2fab 579
<> 132:9baf128c2fab 580 /** \brief Set Fault Mask
<> 132:9baf128c2fab 581
<> 132:9baf128c2fab 582 This function assigns the given value to the Fault Mask register.
<> 132:9baf128c2fab 583
<> 132:9baf128c2fab 584 \param [in] faultMask Fault Mask value to set
<> 132:9baf128c2fab 585 */
<> 132:9baf128c2fab 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 132:9baf128c2fab 587 {
<> 132:9baf128c2fab 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 132:9baf128c2fab 589 }
<> 132:9baf128c2fab 590
<> 132:9baf128c2fab 591 #endif /* (__CORTEX_M >= 0x03) */
<> 132:9baf128c2fab 592
<> 132:9baf128c2fab 593
<> 132:9baf128c2fab 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 132:9baf128c2fab 595
<> 132:9baf128c2fab 596 /** \brief Get FPSCR
<> 132:9baf128c2fab 597
<> 132:9baf128c2fab 598 This function returns the current value of the Floating Point Status/Control register.
<> 132:9baf128c2fab 599
<> 132:9baf128c2fab 600 \return Floating Point Status/Control register value
<> 132:9baf128c2fab 601 */
<> 132:9baf128c2fab 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 132:9baf128c2fab 603 {
<> 132:9baf128c2fab 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 132:9baf128c2fab 605 uint32_t result;
<> 132:9baf128c2fab 606
<> 132:9baf128c2fab 607 /* Empty asm statement works as a scheduling barrier */
<> 132:9baf128c2fab 608 __ASM volatile ("");
<> 132:9baf128c2fab 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 132:9baf128c2fab 610 __ASM volatile ("");
<> 132:9baf128c2fab 611 return(result);
<> 132:9baf128c2fab 612 #else
<> 132:9baf128c2fab 613 return(0);
<> 132:9baf128c2fab 614 #endif
<> 132:9baf128c2fab 615 }
<> 132:9baf128c2fab 616
<> 132:9baf128c2fab 617
<> 132:9baf128c2fab 618 /** \brief Set FPSCR
<> 132:9baf128c2fab 619
<> 132:9baf128c2fab 620 This function assigns the given value to the Floating Point Status/Control register.
<> 132:9baf128c2fab 621
<> 132:9baf128c2fab 622 \param [in] fpscr Floating Point Status/Control value to set
<> 132:9baf128c2fab 623 */
<> 132:9baf128c2fab 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 132:9baf128c2fab 625 {
<> 132:9baf128c2fab 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 132:9baf128c2fab 627 /* Empty asm statement works as a scheduling barrier */
<> 132:9baf128c2fab 628 __ASM volatile ("");
<> 132:9baf128c2fab 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 132:9baf128c2fab 630 __ASM volatile ("");
<> 132:9baf128c2fab 631 #endif
<> 132:9baf128c2fab 632 }
<> 132:9baf128c2fab 633
<> 132:9baf128c2fab 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 132:9baf128c2fab 635
<> 132:9baf128c2fab 636
<> 132:9baf128c2fab 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 132:9baf128c2fab 638 /* IAR iccarm specific functions */
<> 132:9baf128c2fab 639 #include <cmsis_iar.h>
<> 132:9baf128c2fab 640
<> 132:9baf128c2fab 641
<> 132:9baf128c2fab 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 132:9baf128c2fab 643 /* TI CCS specific functions */
<> 132:9baf128c2fab 644 #include <cmsis_ccs.h>
<> 132:9baf128c2fab 645
<> 132:9baf128c2fab 646
<> 132:9baf128c2fab 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 132:9baf128c2fab 648 /* TASKING carm specific functions */
<> 132:9baf128c2fab 649 /*
<> 132:9baf128c2fab 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 132:9baf128c2fab 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 132:9baf128c2fab 652 * Including the CMSIS ones.
<> 132:9baf128c2fab 653 */
<> 132:9baf128c2fab 654
<> 132:9baf128c2fab 655
<> 132:9baf128c2fab 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 132:9baf128c2fab 657 /* Cosmic specific functions */
<> 132:9baf128c2fab 658 #include <cmsis_csm.h>
<> 132:9baf128c2fab 659
<> 132:9baf128c2fab 660 #endif
<> 132:9baf128c2fab 661
<> 132:9baf128c2fab 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 132:9baf128c2fab 663
<> 132:9baf128c2fab 664 #endif /* __CORE_CMFUNC_H */