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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_THUNDERBOARD_SENSE/core_cm3.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
132:9baf128c2fab 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_cm3.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
<> 132:9baf128c2fab 4 * @version V4.10
<> 132:9baf128c2fab 5 * @date 18. March 2015
<> 132:9baf128c2fab 6 *
<> 132:9baf128c2fab 7 * @note
<> 132:9baf128c2fab 8 *
<> 132:9baf128c2fab 9 ******************************************************************************/
<> 132:9baf128c2fab 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 132:9baf128c2fab 11
<> 132:9baf128c2fab 12 All rights reserved.
<> 132:9baf128c2fab 13 Redistribution and use in source and binary forms, with or without
<> 132:9baf128c2fab 14 modification, are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 - Redistributions of source code must retain the above copyright
<> 132:9baf128c2fab 16 notice, this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 - Redistributions in binary form must reproduce the above copyright
<> 132:9baf128c2fab 18 notice, this list of conditions and the following disclaimer in the
<> 132:9baf128c2fab 19 documentation and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 - Neither the name of ARM nor the names of its contributors may be used
<> 132:9baf128c2fab 21 to endorse or promote products derived from this software without
<> 132:9baf128c2fab 22 specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 132:9baf128c2fab 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 132:9baf128c2fab 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 132:9baf128c2fab 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 132:9baf128c2fab 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 132:9baf128c2fab 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 132:9baf128c2fab 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 132:9baf128c2fab 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 132:9baf128c2fab 34 POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 35 ---------------------------------------------------------------------------*/
<> 132:9baf128c2fab 36
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 #if defined ( __ICCARM__ )
<> 132:9baf128c2fab 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 132:9baf128c2fab 40 #endif
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 #ifndef __CORE_CM3_H_GENERIC
<> 132:9baf128c2fab 43 #define __CORE_CM3_H_GENERIC
<> 132:9baf128c2fab 44
<> 132:9baf128c2fab 45 #ifdef __cplusplus
<> 132:9baf128c2fab 46 extern "C" {
<> 132:9baf128c2fab 47 #endif
<> 132:9baf128c2fab 48
<> 132:9baf128c2fab 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 132:9baf128c2fab 50 CMSIS violates the following MISRA-C:2004 rules:
<> 132:9baf128c2fab 51
<> 132:9baf128c2fab 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 132:9baf128c2fab 53 Function definitions in header files are used to allow 'inlining'.
<> 132:9baf128c2fab 54
<> 132:9baf128c2fab 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 132:9baf128c2fab 56 Unions are used for effective representation of core registers.
<> 132:9baf128c2fab 57
<> 132:9baf128c2fab 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 132:9baf128c2fab 59 Function-like macros are used to allow more efficient code.
<> 132:9baf128c2fab 60 */
<> 132:9baf128c2fab 61
<> 132:9baf128c2fab 62
<> 132:9baf128c2fab 63 /*******************************************************************************
<> 132:9baf128c2fab 64 * CMSIS definitions
<> 132:9baf128c2fab 65 ******************************************************************************/
<> 132:9baf128c2fab 66 /** \ingroup Cortex_M3
<> 132:9baf128c2fab 67 @{
<> 132:9baf128c2fab 68 */
<> 132:9baf128c2fab 69
<> 132:9baf128c2fab 70 /* CMSIS CM3 definitions */
<> 132:9baf128c2fab 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 132:9baf128c2fab 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 132:9baf128c2fab 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
<> 132:9baf128c2fab 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 132:9baf128c2fab 75
<> 132:9baf128c2fab 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
<> 132:9baf128c2fab 77
<> 132:9baf128c2fab 78
<> 132:9baf128c2fab 79 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 132:9baf128c2fab 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 132:9baf128c2fab 82 #define __STATIC_INLINE static __inline
<> 132:9baf128c2fab 83
<> 132:9baf128c2fab 84 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 132:9baf128c2fab 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 132:9baf128c2fab 87 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 88
<> 132:9baf128c2fab 89 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 132:9baf128c2fab 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 132:9baf128c2fab 92 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 93
<> 132:9baf128c2fab 94 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 132:9baf128c2fab 96 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 97
<> 132:9baf128c2fab 98 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 132:9baf128c2fab 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 132:9baf128c2fab 101 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 102
<> 132:9baf128c2fab 103 #elif defined ( __CSMC__ )
<> 132:9baf128c2fab 104 #define __packed
<> 132:9baf128c2fab 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 132:9baf128c2fab 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 132:9baf128c2fab 107 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 108
<> 132:9baf128c2fab 109 #endif
<> 132:9baf128c2fab 110
<> 132:9baf128c2fab 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 132:9baf128c2fab 112 This core does not support an FPU at all
<> 132:9baf128c2fab 113 */
<> 132:9baf128c2fab 114 #define __FPU_USED 0
<> 132:9baf128c2fab 115
<> 132:9baf128c2fab 116 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 117 #if defined __TARGET_FPU_VFP
<> 132:9baf128c2fab 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 119 #endif
<> 132:9baf128c2fab 120
<> 132:9baf128c2fab 121 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 132:9baf128c2fab 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 124 #endif
<> 132:9baf128c2fab 125
<> 132:9baf128c2fab 126 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 127 #if defined __ARMVFP__
<> 132:9baf128c2fab 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 129 #endif
<> 132:9baf128c2fab 130
<> 132:9baf128c2fab 131 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 132 #if defined __TI__VFP_SUPPORT____
<> 132:9baf128c2fab 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 134 #endif
<> 132:9baf128c2fab 135
<> 132:9baf128c2fab 136 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 137 #if defined __FPU_VFP__
<> 132:9baf128c2fab 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 139 #endif
<> 132:9baf128c2fab 140
<> 132:9baf128c2fab 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 132:9baf128c2fab 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 132:9baf128c2fab 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 144 #endif
<> 132:9baf128c2fab 145 #endif
<> 132:9baf128c2fab 146
<> 132:9baf128c2fab 147 #include <stdint.h> /* standard types definitions */
<> 132:9baf128c2fab 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 132:9baf128c2fab 149 #include <core_cmFunc.h> /* Core Function Access */
<> 132:9baf128c2fab 150
<> 132:9baf128c2fab 151 #ifdef __cplusplus
<> 132:9baf128c2fab 152 }
<> 132:9baf128c2fab 153 #endif
<> 132:9baf128c2fab 154
<> 132:9baf128c2fab 155 #endif /* __CORE_CM3_H_GENERIC */
<> 132:9baf128c2fab 156
<> 132:9baf128c2fab 157 #ifndef __CMSIS_GENERIC
<> 132:9baf128c2fab 158
<> 132:9baf128c2fab 159 #ifndef __CORE_CM3_H_DEPENDANT
<> 132:9baf128c2fab 160 #define __CORE_CM3_H_DEPENDANT
<> 132:9baf128c2fab 161
<> 132:9baf128c2fab 162 #ifdef __cplusplus
<> 132:9baf128c2fab 163 extern "C" {
<> 132:9baf128c2fab 164 #endif
<> 132:9baf128c2fab 165
<> 132:9baf128c2fab 166 /* check device defines and use defaults */
<> 132:9baf128c2fab 167 #if defined __CHECK_DEVICE_DEFINES
<> 132:9baf128c2fab 168 #ifndef __CM3_REV
<> 132:9baf128c2fab 169 #define __CM3_REV 0x0200
<> 132:9baf128c2fab 170 #warning "__CM3_REV not defined in device header file; using default!"
<> 132:9baf128c2fab 171 #endif
<> 132:9baf128c2fab 172
<> 132:9baf128c2fab 173 #ifndef __MPU_PRESENT
<> 132:9baf128c2fab 174 #define __MPU_PRESENT 0
<> 132:9baf128c2fab 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 132:9baf128c2fab 176 #endif
<> 132:9baf128c2fab 177
<> 132:9baf128c2fab 178 #ifndef __NVIC_PRIO_BITS
<> 132:9baf128c2fab 179 #define __NVIC_PRIO_BITS 4
<> 132:9baf128c2fab 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 132:9baf128c2fab 181 #endif
<> 132:9baf128c2fab 182
<> 132:9baf128c2fab 183 #ifndef __Vendor_SysTickConfig
<> 132:9baf128c2fab 184 #define __Vendor_SysTickConfig 0
<> 132:9baf128c2fab 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 132:9baf128c2fab 186 #endif
<> 132:9baf128c2fab 187 #endif
<> 132:9baf128c2fab 188
<> 132:9baf128c2fab 189 /* IO definitions (access restrictions to peripheral registers) */
<> 132:9baf128c2fab 190 /**
<> 132:9baf128c2fab 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 132:9baf128c2fab 192
<> 132:9baf128c2fab 193 <strong>IO Type Qualifiers</strong> are used
<> 132:9baf128c2fab 194 \li to specify the access to peripheral variables.
<> 132:9baf128c2fab 195 \li for automatic generation of peripheral register debug information.
<> 132:9baf128c2fab 196 */
<> 132:9baf128c2fab 197 #ifdef __cplusplus
<> 132:9baf128c2fab 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 199 #else
<> 132:9baf128c2fab 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 201 #endif
<> 132:9baf128c2fab 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 204
<> 132:9baf128c2fab 205 #ifdef __cplusplus
<> 132:9baf128c2fab 206 #define __IM volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 207 #else
<> 132:9baf128c2fab 208 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 209 #endif
<> 132:9baf128c2fab 210 #define __OM volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 212
<> 132:9baf128c2fab 213 /*@} end of group Cortex_M3 */
<> 132:9baf128c2fab 214
<> 132:9baf128c2fab 215
<> 132:9baf128c2fab 216
<> 132:9baf128c2fab 217 /*******************************************************************************
<> 132:9baf128c2fab 218 * Register Abstraction
<> 132:9baf128c2fab 219 Core Register contain:
<> 132:9baf128c2fab 220 - Core Register
<> 132:9baf128c2fab 221 - Core NVIC Register
<> 132:9baf128c2fab 222 - Core SCB Register
<> 132:9baf128c2fab 223 - Core SysTick Register
<> 132:9baf128c2fab 224 - Core Debug Register
<> 132:9baf128c2fab 225 - Core MPU Register
<> 132:9baf128c2fab 226 ******************************************************************************/
<> 132:9baf128c2fab 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 132:9baf128c2fab 228 \brief Type definitions and defines for Cortex-M processor based devices.
<> 132:9baf128c2fab 229 */
<> 132:9baf128c2fab 230
<> 132:9baf128c2fab 231 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 232 \defgroup CMSIS_CORE Status and Control Registers
<> 132:9baf128c2fab 233 \brief Core Register type definitions.
<> 132:9baf128c2fab 234 @{
<> 132:9baf128c2fab 235 */
<> 132:9baf128c2fab 236
<> 132:9baf128c2fab 237 /** \brief Union type to access the Application Program Status Register (APSR).
<> 132:9baf128c2fab 238 */
<> 132:9baf128c2fab 239 typedef union
<> 132:9baf128c2fab 240 {
<> 132:9baf128c2fab 241 struct
<> 132:9baf128c2fab 242 {
<> 132:9baf128c2fab 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
<> 132:9baf128c2fab 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 132:9baf128c2fab 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 249 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 250 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 251 } APSR_Type;
<> 132:9baf128c2fab 252
<> 132:9baf128c2fab 253 /* APSR Register Definitions */
<> 132:9baf128c2fab 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 132:9baf128c2fab 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 132:9baf128c2fab 256
<> 132:9baf128c2fab 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 132:9baf128c2fab 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 132:9baf128c2fab 259
<> 132:9baf128c2fab 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 132:9baf128c2fab 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 132:9baf128c2fab 262
<> 132:9baf128c2fab 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 132:9baf128c2fab 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 132:9baf128c2fab 265
<> 132:9baf128c2fab 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
<> 132:9baf128c2fab 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 132:9baf128c2fab 268
<> 132:9baf128c2fab 269
<> 132:9baf128c2fab 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 132:9baf128c2fab 271 */
<> 132:9baf128c2fab 272 typedef union
<> 132:9baf128c2fab 273 {
<> 132:9baf128c2fab 274 struct
<> 132:9baf128c2fab 275 {
<> 132:9baf128c2fab 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 132:9baf128c2fab 278 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 279 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 280 } IPSR_Type;
<> 132:9baf128c2fab 281
<> 132:9baf128c2fab 282 /* IPSR Register Definitions */
<> 132:9baf128c2fab 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 132:9baf128c2fab 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 132:9baf128c2fab 285
<> 132:9baf128c2fab 286
<> 132:9baf128c2fab 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 132:9baf128c2fab 288 */
<> 132:9baf128c2fab 289 typedef union
<> 132:9baf128c2fab 290 {
<> 132:9baf128c2fab 291 struct
<> 132:9baf128c2fab 292 {
<> 132:9baf128c2fab 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 132:9baf128c2fab 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 132:9baf128c2fab 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
<> 132:9baf128c2fab 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 132:9baf128c2fab 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 302 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 303 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 304 } xPSR_Type;
<> 132:9baf128c2fab 305
<> 132:9baf128c2fab 306 /* xPSR Register Definitions */
<> 132:9baf128c2fab 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 132:9baf128c2fab 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 132:9baf128c2fab 309
<> 132:9baf128c2fab 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 132:9baf128c2fab 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 132:9baf128c2fab 312
<> 132:9baf128c2fab 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 132:9baf128c2fab 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 132:9baf128c2fab 315
<> 132:9baf128c2fab 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 132:9baf128c2fab 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 132:9baf128c2fab 318
<> 132:9baf128c2fab 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
<> 132:9baf128c2fab 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 132:9baf128c2fab 321
<> 132:9baf128c2fab 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
<> 132:9baf128c2fab 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
<> 132:9baf128c2fab 324
<> 132:9baf128c2fab 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 132:9baf128c2fab 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 132:9baf128c2fab 327
<> 132:9baf128c2fab 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 132:9baf128c2fab 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 132:9baf128c2fab 330
<> 132:9baf128c2fab 331
<> 132:9baf128c2fab 332 /** \brief Union type to access the Control Registers (CONTROL).
<> 132:9baf128c2fab 333 */
<> 132:9baf128c2fab 334 typedef union
<> 132:9baf128c2fab 335 {
<> 132:9baf128c2fab 336 struct
<> 132:9baf128c2fab 337 {
<> 132:9baf128c2fab 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 132:9baf128c2fab 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 132:9baf128c2fab 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 132:9baf128c2fab 341 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 342 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 343 } CONTROL_Type;
<> 132:9baf128c2fab 344
<> 132:9baf128c2fab 345 /* CONTROL Register Definitions */
<> 132:9baf128c2fab 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 132:9baf128c2fab 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 132:9baf128c2fab 348
<> 132:9baf128c2fab 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 132:9baf128c2fab 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 132:9baf128c2fab 351
<> 132:9baf128c2fab 352 /*@} end of group CMSIS_CORE */
<> 132:9baf128c2fab 353
<> 132:9baf128c2fab 354
<> 132:9baf128c2fab 355 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 132:9baf128c2fab 357 \brief Type definitions for the NVIC Registers
<> 132:9baf128c2fab 358 @{
<> 132:9baf128c2fab 359 */
<> 132:9baf128c2fab 360
<> 132:9baf128c2fab 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 132:9baf128c2fab 362 */
<> 132:9baf128c2fab 363 typedef struct
<> 132:9baf128c2fab 364 {
<> 132:9baf128c2fab 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 132:9baf128c2fab 366 uint32_t RESERVED0[24];
<> 132:9baf128c2fab 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 132:9baf128c2fab 368 uint32_t RSERVED1[24];
<> 132:9baf128c2fab 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 132:9baf128c2fab 370 uint32_t RESERVED2[24];
<> 132:9baf128c2fab 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 132:9baf128c2fab 372 uint32_t RESERVED3[24];
<> 132:9baf128c2fab 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
<> 132:9baf128c2fab 374 uint32_t RESERVED4[56];
<> 132:9baf128c2fab 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
<> 132:9baf128c2fab 376 uint32_t RESERVED5[644];
<> 132:9baf128c2fab 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 132:9baf128c2fab 378 } NVIC_Type;
<> 132:9baf128c2fab 379
<> 132:9baf128c2fab 380 /* Software Triggered Interrupt Register Definitions */
<> 132:9baf128c2fab 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
<> 132:9baf128c2fab 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 132:9baf128c2fab 383
<> 132:9baf128c2fab 384 /*@} end of group CMSIS_NVIC */
<> 132:9baf128c2fab 385
<> 132:9baf128c2fab 386
<> 132:9baf128c2fab 387 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 388 \defgroup CMSIS_SCB System Control Block (SCB)
<> 132:9baf128c2fab 389 \brief Type definitions for the System Control Block Registers
<> 132:9baf128c2fab 390 @{
<> 132:9baf128c2fab 391 */
<> 132:9baf128c2fab 392
<> 132:9baf128c2fab 393 /** \brief Structure type to access the System Control Block (SCB).
<> 132:9baf128c2fab 394 */
<> 132:9baf128c2fab 395 typedef struct
<> 132:9baf128c2fab 396 {
<> 132:9baf128c2fab 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 132:9baf128c2fab 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 132:9baf128c2fab 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 132:9baf128c2fab 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 132:9baf128c2fab 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 132:9baf128c2fab 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 132:9baf128c2fab 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
<> 132:9baf128c2fab 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 132:9baf128c2fab 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
<> 132:9baf128c2fab 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
<> 132:9baf128c2fab 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
<> 132:9baf128c2fab 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
<> 132:9baf128c2fab 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
<> 132:9baf128c2fab 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
<> 132:9baf128c2fab 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
<> 132:9baf128c2fab 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
<> 132:9baf128c2fab 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
<> 132:9baf128c2fab 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
<> 132:9baf128c2fab 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
<> 132:9baf128c2fab 416 uint32_t RESERVED0[5];
<> 132:9baf128c2fab 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 132:9baf128c2fab 418 } SCB_Type;
<> 132:9baf128c2fab 419
<> 132:9baf128c2fab 420 /* SCB CPUID Register Definitions */
<> 132:9baf128c2fab 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 132:9baf128c2fab 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 132:9baf128c2fab 423
<> 132:9baf128c2fab 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 132:9baf128c2fab 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 132:9baf128c2fab 426
<> 132:9baf128c2fab 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 132:9baf128c2fab 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 132:9baf128c2fab 429
<> 132:9baf128c2fab 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 132:9baf128c2fab 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 132:9baf128c2fab 432
<> 132:9baf128c2fab 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 132:9baf128c2fab 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 132:9baf128c2fab 435
<> 132:9baf128c2fab 436 /* SCB Interrupt Control State Register Definitions */
<> 132:9baf128c2fab 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 132:9baf128c2fab 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 132:9baf128c2fab 439
<> 132:9baf128c2fab 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 132:9baf128c2fab 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 132:9baf128c2fab 442
<> 132:9baf128c2fab 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 132:9baf128c2fab 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 132:9baf128c2fab 445
<> 132:9baf128c2fab 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 132:9baf128c2fab 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 132:9baf128c2fab 448
<> 132:9baf128c2fab 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 132:9baf128c2fab 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 132:9baf128c2fab 451
<> 132:9baf128c2fab 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 132:9baf128c2fab 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 132:9baf128c2fab 454
<> 132:9baf128c2fab 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 132:9baf128c2fab 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 132:9baf128c2fab 457
<> 132:9baf128c2fab 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 132:9baf128c2fab 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 132:9baf128c2fab 460
<> 132:9baf128c2fab 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
<> 132:9baf128c2fab 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 132:9baf128c2fab 463
<> 132:9baf128c2fab 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 132:9baf128c2fab 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 132:9baf128c2fab 466
<> 132:9baf128c2fab 467 /* SCB Vector Table Offset Register Definitions */
<> 132:9baf128c2fab 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
<> 132:9baf128c2fab 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
<> 132:9baf128c2fab 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
<> 132:9baf128c2fab 471
<> 132:9baf128c2fab 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 132:9baf128c2fab 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 132:9baf128c2fab 474 #else
<> 132:9baf128c2fab 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 132:9baf128c2fab 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 132:9baf128c2fab 477 #endif
<> 132:9baf128c2fab 478
<> 132:9baf128c2fab 479 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 132:9baf128c2fab 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 132:9baf128c2fab 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 132:9baf128c2fab 482
<> 132:9baf128c2fab 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 132:9baf128c2fab 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 132:9baf128c2fab 485
<> 132:9baf128c2fab 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 132:9baf128c2fab 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 132:9baf128c2fab 488
<> 132:9baf128c2fab 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
<> 132:9baf128c2fab 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 132:9baf128c2fab 491
<> 132:9baf128c2fab 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 132:9baf128c2fab 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 132:9baf128c2fab 494
<> 132:9baf128c2fab 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 132:9baf128c2fab 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 132:9baf128c2fab 497
<> 132:9baf128c2fab 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
<> 132:9baf128c2fab 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 132:9baf128c2fab 500
<> 132:9baf128c2fab 501 /* SCB System Control Register Definitions */
<> 132:9baf128c2fab 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 132:9baf128c2fab 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 132:9baf128c2fab 504
<> 132:9baf128c2fab 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 132:9baf128c2fab 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 132:9baf128c2fab 507
<> 132:9baf128c2fab 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 132:9baf128c2fab 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 132:9baf128c2fab 510
<> 132:9baf128c2fab 511 /* SCB Configuration Control Register Definitions */
<> 132:9baf128c2fab 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 132:9baf128c2fab 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 132:9baf128c2fab 514
<> 132:9baf128c2fab 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
<> 132:9baf128c2fab 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 132:9baf128c2fab 517
<> 132:9baf128c2fab 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
<> 132:9baf128c2fab 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 132:9baf128c2fab 520
<> 132:9baf128c2fab 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 132:9baf128c2fab 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 132:9baf128c2fab 523
<> 132:9baf128c2fab 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
<> 132:9baf128c2fab 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 132:9baf128c2fab 526
<> 132:9baf128c2fab 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
<> 132:9baf128c2fab 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 132:9baf128c2fab 529
<> 132:9baf128c2fab 530 /* SCB System Handler Control and State Register Definitions */
<> 132:9baf128c2fab 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
<> 132:9baf128c2fab 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 132:9baf128c2fab 533
<> 132:9baf128c2fab 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
<> 132:9baf128c2fab 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 132:9baf128c2fab 536
<> 132:9baf128c2fab 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
<> 132:9baf128c2fab 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 132:9baf128c2fab 539
<> 132:9baf128c2fab 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 132:9baf128c2fab 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 132:9baf128c2fab 542
<> 132:9baf128c2fab 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 132:9baf128c2fab 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 132:9baf128c2fab 545
<> 132:9baf128c2fab 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 132:9baf128c2fab 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 132:9baf128c2fab 548
<> 132:9baf128c2fab 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 132:9baf128c2fab 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 132:9baf128c2fab 551
<> 132:9baf128c2fab 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
<> 132:9baf128c2fab 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 132:9baf128c2fab 554
<> 132:9baf128c2fab 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
<> 132:9baf128c2fab 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 132:9baf128c2fab 557
<> 132:9baf128c2fab 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
<> 132:9baf128c2fab 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 132:9baf128c2fab 560
<> 132:9baf128c2fab 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
<> 132:9baf128c2fab 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 132:9baf128c2fab 563
<> 132:9baf128c2fab 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
<> 132:9baf128c2fab 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 132:9baf128c2fab 566
<> 132:9baf128c2fab 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
<> 132:9baf128c2fab 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 132:9baf128c2fab 569
<> 132:9baf128c2fab 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
<> 132:9baf128c2fab 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 132:9baf128c2fab 572
<> 132:9baf128c2fab 573 /* SCB Configurable Fault Status Registers Definitions */
<> 132:9baf128c2fab 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
<> 132:9baf128c2fab 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 132:9baf128c2fab 576
<> 132:9baf128c2fab 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
<> 132:9baf128c2fab 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 132:9baf128c2fab 579
<> 132:9baf128c2fab 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 132:9baf128c2fab 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 132:9baf128c2fab 582
<> 132:9baf128c2fab 583 /* SCB Hard Fault Status Registers Definitions */
<> 132:9baf128c2fab 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
<> 132:9baf128c2fab 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 132:9baf128c2fab 586
<> 132:9baf128c2fab 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
<> 132:9baf128c2fab 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 132:9baf128c2fab 589
<> 132:9baf128c2fab 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
<> 132:9baf128c2fab 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 132:9baf128c2fab 592
<> 132:9baf128c2fab 593 /* SCB Debug Fault Status Register Definitions */
<> 132:9baf128c2fab 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
<> 132:9baf128c2fab 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 132:9baf128c2fab 596
<> 132:9baf128c2fab 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
<> 132:9baf128c2fab 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 132:9baf128c2fab 599
<> 132:9baf128c2fab 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
<> 132:9baf128c2fab 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 132:9baf128c2fab 602
<> 132:9baf128c2fab 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
<> 132:9baf128c2fab 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 132:9baf128c2fab 605
<> 132:9baf128c2fab 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
<> 132:9baf128c2fab 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 132:9baf128c2fab 608
<> 132:9baf128c2fab 609 /*@} end of group CMSIS_SCB */
<> 132:9baf128c2fab 610
<> 132:9baf128c2fab 611
<> 132:9baf128c2fab 612 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 132:9baf128c2fab 614 \brief Type definitions for the System Control and ID Register not in the SCB
<> 132:9baf128c2fab 615 @{
<> 132:9baf128c2fab 616 */
<> 132:9baf128c2fab 617
<> 132:9baf128c2fab 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 132:9baf128c2fab 619 */
<> 132:9baf128c2fab 620 typedef struct
<> 132:9baf128c2fab 621 {
<> 132:9baf128c2fab 622 uint32_t RESERVED0[1];
<> 132:9baf128c2fab 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
<> 132:9baf128c2fab 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
<> 132:9baf128c2fab 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 132:9baf128c2fab 626 #else
<> 132:9baf128c2fab 627 uint32_t RESERVED1[1];
<> 132:9baf128c2fab 628 #endif
<> 132:9baf128c2fab 629 } SCnSCB_Type;
<> 132:9baf128c2fab 630
<> 132:9baf128c2fab 631 /* Interrupt Controller Type Register Definitions */
<> 132:9baf128c2fab 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
<> 132:9baf128c2fab 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 132:9baf128c2fab 634
<> 132:9baf128c2fab 635 /* Auxiliary Control Register Definitions */
<> 132:9baf128c2fab 636
<> 132:9baf128c2fab 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
<> 132:9baf128c2fab 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
<> 132:9baf128c2fab 639
<> 132:9baf128c2fab 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
<> 132:9baf128c2fab 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
<> 132:9baf128c2fab 642
<> 132:9baf128c2fab 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
<> 132:9baf128c2fab 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 132:9baf128c2fab 645
<> 132:9baf128c2fab 646 /*@} end of group CMSIS_SCnotSCB */
<> 132:9baf128c2fab 647
<> 132:9baf128c2fab 648
<> 132:9baf128c2fab 649 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 132:9baf128c2fab 651 \brief Type definitions for the System Timer Registers.
<> 132:9baf128c2fab 652 @{
<> 132:9baf128c2fab 653 */
<> 132:9baf128c2fab 654
<> 132:9baf128c2fab 655 /** \brief Structure type to access the System Timer (SysTick).
<> 132:9baf128c2fab 656 */
<> 132:9baf128c2fab 657 typedef struct
<> 132:9baf128c2fab 658 {
<> 132:9baf128c2fab 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 132:9baf128c2fab 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 132:9baf128c2fab 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 132:9baf128c2fab 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 132:9baf128c2fab 663 } SysTick_Type;
<> 132:9baf128c2fab 664
<> 132:9baf128c2fab 665 /* SysTick Control / Status Register Definitions */
<> 132:9baf128c2fab 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 132:9baf128c2fab 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 132:9baf128c2fab 668
<> 132:9baf128c2fab 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 132:9baf128c2fab 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 132:9baf128c2fab 671
<> 132:9baf128c2fab 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 132:9baf128c2fab 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 132:9baf128c2fab 674
<> 132:9baf128c2fab 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 132:9baf128c2fab 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 132:9baf128c2fab 677
<> 132:9baf128c2fab 678 /* SysTick Reload Register Definitions */
<> 132:9baf128c2fab 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 132:9baf128c2fab 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 132:9baf128c2fab 681
<> 132:9baf128c2fab 682 /* SysTick Current Register Definitions */
<> 132:9baf128c2fab 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 132:9baf128c2fab 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 132:9baf128c2fab 685
<> 132:9baf128c2fab 686 /* SysTick Calibration Register Definitions */
<> 132:9baf128c2fab 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 132:9baf128c2fab 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 132:9baf128c2fab 689
<> 132:9baf128c2fab 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 132:9baf128c2fab 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 132:9baf128c2fab 692
<> 132:9baf128c2fab 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 132:9baf128c2fab 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 132:9baf128c2fab 695
<> 132:9baf128c2fab 696 /*@} end of group CMSIS_SysTick */
<> 132:9baf128c2fab 697
<> 132:9baf128c2fab 698
<> 132:9baf128c2fab 699 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<> 132:9baf128c2fab 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 132:9baf128c2fab 702 @{
<> 132:9baf128c2fab 703 */
<> 132:9baf128c2fab 704
<> 132:9baf128c2fab 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 132:9baf128c2fab 706 */
<> 132:9baf128c2fab 707 typedef struct
<> 132:9baf128c2fab 708 {
<> 132:9baf128c2fab 709 __O union
<> 132:9baf128c2fab 710 {
<> 132:9baf128c2fab 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
<> 132:9baf128c2fab 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
<> 132:9baf128c2fab 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
<> 132:9baf128c2fab 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
<> 132:9baf128c2fab 715 uint32_t RESERVED0[864];
<> 132:9baf128c2fab 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
<> 132:9baf128c2fab 717 uint32_t RESERVED1[15];
<> 132:9baf128c2fab 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
<> 132:9baf128c2fab 719 uint32_t RESERVED2[15];
<> 132:9baf128c2fab 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
<> 132:9baf128c2fab 721 uint32_t RESERVED3[29];
<> 132:9baf128c2fab 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
<> 132:9baf128c2fab 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
<> 132:9baf128c2fab 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
<> 132:9baf128c2fab 725 uint32_t RESERVED4[43];
<> 132:9baf128c2fab 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
<> 132:9baf128c2fab 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
<> 132:9baf128c2fab 728 uint32_t RESERVED5[6];
<> 132:9baf128c2fab 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
<> 132:9baf128c2fab 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
<> 132:9baf128c2fab 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
<> 132:9baf128c2fab 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
<> 132:9baf128c2fab 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
<> 132:9baf128c2fab 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
<> 132:9baf128c2fab 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
<> 132:9baf128c2fab 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
<> 132:9baf128c2fab 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
<> 132:9baf128c2fab 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
<> 132:9baf128c2fab 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
<> 132:9baf128c2fab 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 132:9baf128c2fab 741 } ITM_Type;
<> 132:9baf128c2fab 742
<> 132:9baf128c2fab 743 /* ITM Trace Privilege Register Definitions */
<> 132:9baf128c2fab 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
<> 132:9baf128c2fab 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 132:9baf128c2fab 746
<> 132:9baf128c2fab 747 /* ITM Trace Control Register Definitions */
<> 132:9baf128c2fab 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
<> 132:9baf128c2fab 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 132:9baf128c2fab 750
<> 132:9baf128c2fab 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
<> 132:9baf128c2fab 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 132:9baf128c2fab 753
<> 132:9baf128c2fab 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
<> 132:9baf128c2fab 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 132:9baf128c2fab 756
<> 132:9baf128c2fab 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
<> 132:9baf128c2fab 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 132:9baf128c2fab 759
<> 132:9baf128c2fab 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
<> 132:9baf128c2fab 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 132:9baf128c2fab 762
<> 132:9baf128c2fab 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
<> 132:9baf128c2fab 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 132:9baf128c2fab 765
<> 132:9baf128c2fab 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
<> 132:9baf128c2fab 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 132:9baf128c2fab 768
<> 132:9baf128c2fab 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
<> 132:9baf128c2fab 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 132:9baf128c2fab 771
<> 132:9baf128c2fab 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
<> 132:9baf128c2fab 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 132:9baf128c2fab 774
<> 132:9baf128c2fab 775 /* ITM Integration Write Register Definitions */
<> 132:9baf128c2fab 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
<> 132:9baf128c2fab 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 132:9baf128c2fab 778
<> 132:9baf128c2fab 779 /* ITM Integration Read Register Definitions */
<> 132:9baf128c2fab 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
<> 132:9baf128c2fab 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 132:9baf128c2fab 782
<> 132:9baf128c2fab 783 /* ITM Integration Mode Control Register Definitions */
<> 132:9baf128c2fab 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
<> 132:9baf128c2fab 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 132:9baf128c2fab 786
<> 132:9baf128c2fab 787 /* ITM Lock Status Register Definitions */
<> 132:9baf128c2fab 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
<> 132:9baf128c2fab 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 132:9baf128c2fab 790
<> 132:9baf128c2fab 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
<> 132:9baf128c2fab 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 132:9baf128c2fab 793
<> 132:9baf128c2fab 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
<> 132:9baf128c2fab 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 132:9baf128c2fab 796
<> 132:9baf128c2fab 797 /*@}*/ /* end of group CMSIS_ITM */
<> 132:9baf128c2fab 798
<> 132:9baf128c2fab 799
<> 132:9baf128c2fab 800 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<> 132:9baf128c2fab 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 132:9baf128c2fab 803 @{
<> 132:9baf128c2fab 804 */
<> 132:9baf128c2fab 805
<> 132:9baf128c2fab 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 132:9baf128c2fab 807 */
<> 132:9baf128c2fab 808 typedef struct
<> 132:9baf128c2fab 809 {
<> 132:9baf128c2fab 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
<> 132:9baf128c2fab 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
<> 132:9baf128c2fab 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
<> 132:9baf128c2fab 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
<> 132:9baf128c2fab 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
<> 132:9baf128c2fab 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
<> 132:9baf128c2fab 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
<> 132:9baf128c2fab 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
<> 132:9baf128c2fab 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
<> 132:9baf128c2fab 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
<> 132:9baf128c2fab 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
<> 132:9baf128c2fab 821 uint32_t RESERVED0[1];
<> 132:9baf128c2fab 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
<> 132:9baf128c2fab 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
<> 132:9baf128c2fab 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
<> 132:9baf128c2fab 825 uint32_t RESERVED1[1];
<> 132:9baf128c2fab 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
<> 132:9baf128c2fab 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
<> 132:9baf128c2fab 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
<> 132:9baf128c2fab 829 uint32_t RESERVED2[1];
<> 132:9baf128c2fab 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
<> 132:9baf128c2fab 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
<> 132:9baf128c2fab 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 132:9baf128c2fab 833 } DWT_Type;
<> 132:9baf128c2fab 834
<> 132:9baf128c2fab 835 /* DWT Control Register Definitions */
<> 132:9baf128c2fab 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
<> 132:9baf128c2fab 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 132:9baf128c2fab 838
<> 132:9baf128c2fab 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
<> 132:9baf128c2fab 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 132:9baf128c2fab 841
<> 132:9baf128c2fab 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
<> 132:9baf128c2fab 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 132:9baf128c2fab 844
<> 132:9baf128c2fab 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
<> 132:9baf128c2fab 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 132:9baf128c2fab 847
<> 132:9baf128c2fab 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
<> 132:9baf128c2fab 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 132:9baf128c2fab 850
<> 132:9baf128c2fab 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
<> 132:9baf128c2fab 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 132:9baf128c2fab 853
<> 132:9baf128c2fab 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
<> 132:9baf128c2fab 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 132:9baf128c2fab 856
<> 132:9baf128c2fab 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
<> 132:9baf128c2fab 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 132:9baf128c2fab 859
<> 132:9baf128c2fab 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
<> 132:9baf128c2fab 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 132:9baf128c2fab 862
<> 132:9baf128c2fab 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
<> 132:9baf128c2fab 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 132:9baf128c2fab 865
<> 132:9baf128c2fab 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
<> 132:9baf128c2fab 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 132:9baf128c2fab 868
<> 132:9baf128c2fab 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
<> 132:9baf128c2fab 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 132:9baf128c2fab 871
<> 132:9baf128c2fab 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
<> 132:9baf128c2fab 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 132:9baf128c2fab 874
<> 132:9baf128c2fab 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
<> 132:9baf128c2fab 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 132:9baf128c2fab 877
<> 132:9baf128c2fab 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
<> 132:9baf128c2fab 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 132:9baf128c2fab 880
<> 132:9baf128c2fab 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
<> 132:9baf128c2fab 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 132:9baf128c2fab 883
<> 132:9baf128c2fab 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
<> 132:9baf128c2fab 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 132:9baf128c2fab 886
<> 132:9baf128c2fab 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
<> 132:9baf128c2fab 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 132:9baf128c2fab 889
<> 132:9baf128c2fab 890 /* DWT CPI Count Register Definitions */
<> 132:9baf128c2fab 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
<> 132:9baf128c2fab 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 132:9baf128c2fab 893
<> 132:9baf128c2fab 894 /* DWT Exception Overhead Count Register Definitions */
<> 132:9baf128c2fab 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
<> 132:9baf128c2fab 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 132:9baf128c2fab 897
<> 132:9baf128c2fab 898 /* DWT Sleep Count Register Definitions */
<> 132:9baf128c2fab 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 132:9baf128c2fab 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 132:9baf128c2fab 901
<> 132:9baf128c2fab 902 /* DWT LSU Count Register Definitions */
<> 132:9baf128c2fab 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
<> 132:9baf128c2fab 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 132:9baf128c2fab 905
<> 132:9baf128c2fab 906 /* DWT Folded-instruction Count Register Definitions */
<> 132:9baf128c2fab 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
<> 132:9baf128c2fab 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 132:9baf128c2fab 909
<> 132:9baf128c2fab 910 /* DWT Comparator Mask Register Definitions */
<> 132:9baf128c2fab 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
<> 132:9baf128c2fab 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 132:9baf128c2fab 913
<> 132:9baf128c2fab 914 /* DWT Comparator Function Register Definitions */
<> 132:9baf128c2fab 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
<> 132:9baf128c2fab 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 132:9baf128c2fab 917
<> 132:9baf128c2fab 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 132:9baf128c2fab 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 132:9baf128c2fab 920
<> 132:9baf128c2fab 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 132:9baf128c2fab 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 132:9baf128c2fab 923
<> 132:9baf128c2fab 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
<> 132:9baf128c2fab 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 132:9baf128c2fab 926
<> 132:9baf128c2fab 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
<> 132:9baf128c2fab 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 132:9baf128c2fab 929
<> 132:9baf128c2fab 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
<> 132:9baf128c2fab 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 132:9baf128c2fab 932
<> 132:9baf128c2fab 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
<> 132:9baf128c2fab 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 132:9baf128c2fab 935
<> 132:9baf128c2fab 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
<> 132:9baf128c2fab 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 132:9baf128c2fab 938
<> 132:9baf128c2fab 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
<> 132:9baf128c2fab 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 132:9baf128c2fab 941
<> 132:9baf128c2fab 942 /*@}*/ /* end of group CMSIS_DWT */
<> 132:9baf128c2fab 943
<> 132:9baf128c2fab 944
<> 132:9baf128c2fab 945 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
<> 132:9baf128c2fab 947 \brief Type definitions for the Trace Port Interface (TPI)
<> 132:9baf128c2fab 948 @{
<> 132:9baf128c2fab 949 */
<> 132:9baf128c2fab 950
<> 132:9baf128c2fab 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
<> 132:9baf128c2fab 952 */
<> 132:9baf128c2fab 953 typedef struct
<> 132:9baf128c2fab 954 {
<> 132:9baf128c2fab 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
<> 132:9baf128c2fab 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
<> 132:9baf128c2fab 957 uint32_t RESERVED0[2];
<> 132:9baf128c2fab 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
<> 132:9baf128c2fab 959 uint32_t RESERVED1[55];
<> 132:9baf128c2fab 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
<> 132:9baf128c2fab 961 uint32_t RESERVED2[131];
<> 132:9baf128c2fab 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
<> 132:9baf128c2fab 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
<> 132:9baf128c2fab 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
<> 132:9baf128c2fab 965 uint32_t RESERVED3[759];
<> 132:9baf128c2fab 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
<> 132:9baf128c2fab 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
<> 132:9baf128c2fab 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
<> 132:9baf128c2fab 969 uint32_t RESERVED4[1];
<> 132:9baf128c2fab 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
<> 132:9baf128c2fab 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
<> 132:9baf128c2fab 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
<> 132:9baf128c2fab 973 uint32_t RESERVED5[39];
<> 132:9baf128c2fab 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
<> 132:9baf128c2fab 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
<> 132:9baf128c2fab 976 uint32_t RESERVED7[8];
<> 132:9baf128c2fab 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
<> 132:9baf128c2fab 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 132:9baf128c2fab 979 } TPI_Type;
<> 132:9baf128c2fab 980
<> 132:9baf128c2fab 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
<> 132:9baf128c2fab 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
<> 132:9baf128c2fab 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 132:9baf128c2fab 984
<> 132:9baf128c2fab 985 /* TPI Selected Pin Protocol Register Definitions */
<> 132:9baf128c2fab 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
<> 132:9baf128c2fab 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 132:9baf128c2fab 988
<> 132:9baf128c2fab 989 /* TPI Formatter and Flush Status Register Definitions */
<> 132:9baf128c2fab 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
<> 132:9baf128c2fab 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 132:9baf128c2fab 992
<> 132:9baf128c2fab 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
<> 132:9baf128c2fab 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 132:9baf128c2fab 995
<> 132:9baf128c2fab 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
<> 132:9baf128c2fab 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 132:9baf128c2fab 998
<> 132:9baf128c2fab 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
<> 132:9baf128c2fab 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 132:9baf128c2fab 1001
<> 132:9baf128c2fab 1002 /* TPI Formatter and Flush Control Register Definitions */
<> 132:9baf128c2fab 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
<> 132:9baf128c2fab 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 132:9baf128c2fab 1005
<> 132:9baf128c2fab 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
<> 132:9baf128c2fab 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 132:9baf128c2fab 1008
<> 132:9baf128c2fab 1009 /* TPI TRIGGER Register Definitions */
<> 132:9baf128c2fab 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
<> 132:9baf128c2fab 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 132:9baf128c2fab 1012
<> 132:9baf128c2fab 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
<> 132:9baf128c2fab 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
<> 132:9baf128c2fab 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 132:9baf128c2fab 1016
<> 132:9baf128c2fab 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
<> 132:9baf128c2fab 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 132:9baf128c2fab 1019
<> 132:9baf128c2fab 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
<> 132:9baf128c2fab 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 132:9baf128c2fab 1022
<> 132:9baf128c2fab 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
<> 132:9baf128c2fab 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 132:9baf128c2fab 1025
<> 132:9baf128c2fab 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
<> 132:9baf128c2fab 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 132:9baf128c2fab 1028
<> 132:9baf128c2fab 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
<> 132:9baf128c2fab 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 132:9baf128c2fab 1031
<> 132:9baf128c2fab 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
<> 132:9baf128c2fab 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 132:9baf128c2fab 1034
<> 132:9baf128c2fab 1035 /* TPI ITATBCTR2 Register Definitions */
<> 132:9baf128c2fab 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
<> 132:9baf128c2fab 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 132:9baf128c2fab 1038
<> 132:9baf128c2fab 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
<> 132:9baf128c2fab 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
<> 132:9baf128c2fab 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 132:9baf128c2fab 1042
<> 132:9baf128c2fab 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
<> 132:9baf128c2fab 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 132:9baf128c2fab 1045
<> 132:9baf128c2fab 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
<> 132:9baf128c2fab 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 132:9baf128c2fab 1048
<> 132:9baf128c2fab 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
<> 132:9baf128c2fab 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 132:9baf128c2fab 1051
<> 132:9baf128c2fab 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
<> 132:9baf128c2fab 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 132:9baf128c2fab 1054
<> 132:9baf128c2fab 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
<> 132:9baf128c2fab 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 132:9baf128c2fab 1057
<> 132:9baf128c2fab 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
<> 132:9baf128c2fab 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 132:9baf128c2fab 1060
<> 132:9baf128c2fab 1061 /* TPI ITATBCTR0 Register Definitions */
<> 132:9baf128c2fab 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
<> 132:9baf128c2fab 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 132:9baf128c2fab 1064
<> 132:9baf128c2fab 1065 /* TPI Integration Mode Control Register Definitions */
<> 132:9baf128c2fab 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
<> 132:9baf128c2fab 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 132:9baf128c2fab 1068
<> 132:9baf128c2fab 1069 /* TPI DEVID Register Definitions */
<> 132:9baf128c2fab 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
<> 132:9baf128c2fab 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 132:9baf128c2fab 1072
<> 132:9baf128c2fab 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
<> 132:9baf128c2fab 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 132:9baf128c2fab 1075
<> 132:9baf128c2fab 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
<> 132:9baf128c2fab 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 132:9baf128c2fab 1078
<> 132:9baf128c2fab 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
<> 132:9baf128c2fab 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 132:9baf128c2fab 1081
<> 132:9baf128c2fab 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
<> 132:9baf128c2fab 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 132:9baf128c2fab 1084
<> 132:9baf128c2fab 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
<> 132:9baf128c2fab 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 132:9baf128c2fab 1087
<> 132:9baf128c2fab 1088 /* TPI DEVTYPE Register Definitions */
<> 132:9baf128c2fab 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
<> 132:9baf128c2fab 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 132:9baf128c2fab 1091
<> 132:9baf128c2fab 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
<> 132:9baf128c2fab 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 132:9baf128c2fab 1094
<> 132:9baf128c2fab 1095 /*@}*/ /* end of group CMSIS_TPI */
<> 132:9baf128c2fab 1096
<> 132:9baf128c2fab 1097
<> 132:9baf128c2fab 1098 #if (__MPU_PRESENT == 1)
<> 132:9baf128c2fab 1099 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 132:9baf128c2fab 1101 \brief Type definitions for the Memory Protection Unit (MPU)
<> 132:9baf128c2fab 1102 @{
<> 132:9baf128c2fab 1103 */
<> 132:9baf128c2fab 1104
<> 132:9baf128c2fab 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 132:9baf128c2fab 1106 */
<> 132:9baf128c2fab 1107 typedef struct
<> 132:9baf128c2fab 1108 {
<> 132:9baf128c2fab 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 132:9baf128c2fab 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 132:9baf128c2fab 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 132:9baf128c2fab 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 132:9baf128c2fab 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 132:9baf128c2fab 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
<> 132:9baf128c2fab 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
<> 132:9baf128c2fab 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
<> 132:9baf128c2fab 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
<> 132:9baf128c2fab 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
<> 132:9baf128c2fab 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 132:9baf128c2fab 1120 } MPU_Type;
<> 132:9baf128c2fab 1121
<> 132:9baf128c2fab 1122 /* MPU Type Register */
<> 132:9baf128c2fab 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 132:9baf128c2fab 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 132:9baf128c2fab 1125
<> 132:9baf128c2fab 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 132:9baf128c2fab 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 132:9baf128c2fab 1128
<> 132:9baf128c2fab 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 132:9baf128c2fab 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 132:9baf128c2fab 1131
<> 132:9baf128c2fab 1132 /* MPU Control Register */
<> 132:9baf128c2fab 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 132:9baf128c2fab 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 132:9baf128c2fab 1135
<> 132:9baf128c2fab 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 132:9baf128c2fab 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 132:9baf128c2fab 1138
<> 132:9baf128c2fab 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 132:9baf128c2fab 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 132:9baf128c2fab 1141
<> 132:9baf128c2fab 1142 /* MPU Region Number Register */
<> 132:9baf128c2fab 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 132:9baf128c2fab 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 132:9baf128c2fab 1145
<> 132:9baf128c2fab 1146 /* MPU Region Base Address Register */
<> 132:9baf128c2fab 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
<> 132:9baf128c2fab 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 132:9baf128c2fab 1149
<> 132:9baf128c2fab 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 132:9baf128c2fab 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 132:9baf128c2fab 1152
<> 132:9baf128c2fab 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 132:9baf128c2fab 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 132:9baf128c2fab 1155
<> 132:9baf128c2fab 1156 /* MPU Region Attribute and Size Register */
<> 132:9baf128c2fab 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 132:9baf128c2fab 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 132:9baf128c2fab 1159
<> 132:9baf128c2fab 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 132:9baf128c2fab 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 132:9baf128c2fab 1162
<> 132:9baf128c2fab 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 132:9baf128c2fab 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 132:9baf128c2fab 1165
<> 132:9baf128c2fab 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 132:9baf128c2fab 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 132:9baf128c2fab 1168
<> 132:9baf128c2fab 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 132:9baf128c2fab 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 132:9baf128c2fab 1171
<> 132:9baf128c2fab 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 132:9baf128c2fab 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 132:9baf128c2fab 1174
<> 132:9baf128c2fab 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 132:9baf128c2fab 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 132:9baf128c2fab 1177
<> 132:9baf128c2fab 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 132:9baf128c2fab 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 132:9baf128c2fab 1180
<> 132:9baf128c2fab 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 132:9baf128c2fab 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 132:9baf128c2fab 1183
<> 132:9baf128c2fab 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 132:9baf128c2fab 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 132:9baf128c2fab 1186
<> 132:9baf128c2fab 1187 /*@} end of group CMSIS_MPU */
<> 132:9baf128c2fab 1188 #endif
<> 132:9baf128c2fab 1189
<> 132:9baf128c2fab 1190
<> 132:9baf128c2fab 1191 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 132:9baf128c2fab 1193 \brief Type definitions for the Core Debug Registers
<> 132:9baf128c2fab 1194 @{
<> 132:9baf128c2fab 1195 */
<> 132:9baf128c2fab 1196
<> 132:9baf128c2fab 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
<> 132:9baf128c2fab 1198 */
<> 132:9baf128c2fab 1199 typedef struct
<> 132:9baf128c2fab 1200 {
<> 132:9baf128c2fab 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
<> 132:9baf128c2fab 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
<> 132:9baf128c2fab 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
<> 132:9baf128c2fab 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 132:9baf128c2fab 1205 } CoreDebug_Type;
<> 132:9baf128c2fab 1206
<> 132:9baf128c2fab 1207 /* Debug Halting Control and Status Register */
<> 132:9baf128c2fab 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
<> 132:9baf128c2fab 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 132:9baf128c2fab 1210
<> 132:9baf128c2fab 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 132:9baf128c2fab 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 132:9baf128c2fab 1213
<> 132:9baf128c2fab 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 132:9baf128c2fab 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 132:9baf128c2fab 1216
<> 132:9baf128c2fab 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 132:9baf128c2fab 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 132:9baf128c2fab 1219
<> 132:9baf128c2fab 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 132:9baf128c2fab 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 132:9baf128c2fab 1222
<> 132:9baf128c2fab 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
<> 132:9baf128c2fab 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 132:9baf128c2fab 1225
<> 132:9baf128c2fab 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 132:9baf128c2fab 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 132:9baf128c2fab 1228
<> 132:9baf128c2fab 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 132:9baf128c2fab 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 132:9baf128c2fab 1231
<> 132:9baf128c2fab 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 132:9baf128c2fab 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 132:9baf128c2fab 1234
<> 132:9baf128c2fab 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
<> 132:9baf128c2fab 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 132:9baf128c2fab 1237
<> 132:9baf128c2fab 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
<> 132:9baf128c2fab 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 132:9baf128c2fab 1240
<> 132:9baf128c2fab 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 132:9baf128c2fab 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 132:9baf128c2fab 1243
<> 132:9baf128c2fab 1244 /* Debug Core Register Selector Register */
<> 132:9baf128c2fab 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
<> 132:9baf128c2fab 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 132:9baf128c2fab 1247
<> 132:9baf128c2fab 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
<> 132:9baf128c2fab 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 132:9baf128c2fab 1250
<> 132:9baf128c2fab 1251 /* Debug Exception and Monitor Control Register */
<> 132:9baf128c2fab 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
<> 132:9baf128c2fab 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 132:9baf128c2fab 1254
<> 132:9baf128c2fab 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
<> 132:9baf128c2fab 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 132:9baf128c2fab 1257
<> 132:9baf128c2fab 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
<> 132:9baf128c2fab 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 132:9baf128c2fab 1260
<> 132:9baf128c2fab 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
<> 132:9baf128c2fab 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 132:9baf128c2fab 1263
<> 132:9baf128c2fab 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
<> 132:9baf128c2fab 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 132:9baf128c2fab 1266
<> 132:9baf128c2fab 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 132:9baf128c2fab 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 132:9baf128c2fab 1269
<> 132:9baf128c2fab 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 132:9baf128c2fab 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 132:9baf128c2fab 1272
<> 132:9baf128c2fab 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 132:9baf128c2fab 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 132:9baf128c2fab 1275
<> 132:9baf128c2fab 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 132:9baf128c2fab 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 132:9baf128c2fab 1278
<> 132:9baf128c2fab 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 132:9baf128c2fab 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 132:9baf128c2fab 1281
<> 132:9baf128c2fab 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 132:9baf128c2fab 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 132:9baf128c2fab 1284
<> 132:9baf128c2fab 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 132:9baf128c2fab 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 132:9baf128c2fab 1287
<> 132:9baf128c2fab 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 132:9baf128c2fab 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 132:9baf128c2fab 1290
<> 132:9baf128c2fab 1291 /*@} end of group CMSIS_CoreDebug */
<> 132:9baf128c2fab 1292
<> 132:9baf128c2fab 1293
<> 132:9baf128c2fab 1294 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 1295 \defgroup CMSIS_core_base Core Definitions
<> 132:9baf128c2fab 1296 \brief Definitions for base addresses, unions, and structures.
<> 132:9baf128c2fab 1297 @{
<> 132:9baf128c2fab 1298 */
<> 132:9baf128c2fab 1299
<> 132:9baf128c2fab 1300 /* Memory mapping of Cortex-M3 Hardware */
<> 132:9baf128c2fab 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 132:9baf128c2fab 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
<> 132:9baf128c2fab 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
<> 132:9baf128c2fab 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
<> 132:9baf128c2fab 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
<> 132:9baf128c2fab 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 132:9baf128c2fab 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 132:9baf128c2fab 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 132:9baf128c2fab 1309
<> 132:9baf128c2fab 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 132:9baf128c2fab 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 132:9baf128c2fab 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 132:9baf128c2fab 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 132:9baf128c2fab 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
<> 132:9baf128c2fab 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
<> 132:9baf128c2fab 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
<> 132:9baf128c2fab 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 132:9baf128c2fab 1318
<> 132:9baf128c2fab 1319 #if (__MPU_PRESENT == 1)
<> 132:9baf128c2fab 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 132:9baf128c2fab 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 132:9baf128c2fab 1322 #endif
<> 132:9baf128c2fab 1323
<> 132:9baf128c2fab 1324 /*@} */
<> 132:9baf128c2fab 1325
<> 132:9baf128c2fab 1326
<> 132:9baf128c2fab 1327
<> 132:9baf128c2fab 1328 /*******************************************************************************
<> 132:9baf128c2fab 1329 * Hardware Abstraction Layer
<> 132:9baf128c2fab 1330 Core Function Interface contains:
<> 132:9baf128c2fab 1331 - Core NVIC Functions
<> 132:9baf128c2fab 1332 - Core SysTick Functions
<> 132:9baf128c2fab 1333 - Core Debug Functions
<> 132:9baf128c2fab 1334 - Core Register Access Functions
<> 132:9baf128c2fab 1335 ******************************************************************************/
<> 132:9baf128c2fab 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 132:9baf128c2fab 1337 */
<> 132:9baf128c2fab 1338
<> 132:9baf128c2fab 1339
<> 132:9baf128c2fab 1340
<> 132:9baf128c2fab 1341 /* ########################## NVIC functions #################################### */
<> 132:9baf128c2fab 1342 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 132:9baf128c2fab 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 132:9baf128c2fab 1345 @{
<> 132:9baf128c2fab 1346 */
<> 132:9baf128c2fab 1347
<> 132:9baf128c2fab 1348 #ifdef CMSIS_NVIC_VIRTUAL
<> 132:9baf128c2fab 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 132:9baf128c2fab 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 132:9baf128c2fab 1351 #endif
<> 132:9baf128c2fab 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 132:9baf128c2fab 1353 #else
<> 132:9baf128c2fab 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 132:9baf128c2fab 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 132:9baf128c2fab 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 132:9baf128c2fab 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 132:9baf128c2fab 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 132:9baf128c2fab 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 132:9baf128c2fab 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 132:9baf128c2fab 1361 #define NVIC_GetActive __NVIC_GetActive
<> 132:9baf128c2fab 1362 #define NVIC_SetPriority __NVIC_SetPriority
<> 132:9baf128c2fab 1363 #define NVIC_GetPriority __NVIC_GetPriority
<> 132:9baf128c2fab 1364 #define NVIC_SystemReset __NVIC_SystemReset
<> 132:9baf128c2fab 1365 #endif /* CMSIS_NVIC_VIRTUAL */
<> 132:9baf128c2fab 1366
<> 132:9baf128c2fab 1367 #ifdef CMSIS_VECTAB_VIRTUAL
<> 132:9baf128c2fab 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 132:9baf128c2fab 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 132:9baf128c2fab 1370 #endif
<> 132:9baf128c2fab 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 132:9baf128c2fab 1372 #else
<> 132:9baf128c2fab 1373 #define NVIC_SetVector __NVIC_SetVector
<> 132:9baf128c2fab 1374 #define NVIC_GetVector __NVIC_GetVector
<> 132:9baf128c2fab 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 132:9baf128c2fab 1376
<> 132:9baf128c2fab 1377 /** \brief Set Priority Grouping
<> 132:9baf128c2fab 1378
<> 132:9baf128c2fab 1379 The function sets the priority grouping field using the required unlock sequence.
<> 132:9baf128c2fab 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<> 132:9baf128c2fab 1381 Only values from 0..7 are used.
<> 132:9baf128c2fab 1382 In case of a conflict between priority grouping and available
<> 132:9baf128c2fab 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 132:9baf128c2fab 1384
<> 132:9baf128c2fab 1385 \param [in] PriorityGroup Priority grouping field.
<> 132:9baf128c2fab 1386 */
<> 132:9baf128c2fab 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 132:9baf128c2fab 1388 {
<> 132:9baf128c2fab 1389 uint32_t reg_value;
<> 132:9baf128c2fab 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 132:9baf128c2fab 1391
<> 132:9baf128c2fab 1392 reg_value = SCB->AIRCR; /* read old register configuration */
<> 132:9baf128c2fab 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 132:9baf128c2fab 1394 reg_value = (reg_value |
<> 132:9baf128c2fab 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 132:9baf128c2fab 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<> 132:9baf128c2fab 1397 SCB->AIRCR = reg_value;
<> 132:9baf128c2fab 1398 }
<> 132:9baf128c2fab 1399
<> 132:9baf128c2fab 1400
<> 132:9baf128c2fab 1401 /** \brief Get Priority Grouping
<> 132:9baf128c2fab 1402
<> 132:9baf128c2fab 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
<> 132:9baf128c2fab 1404
<> 132:9baf128c2fab 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 132:9baf128c2fab 1406 */
<> 132:9baf128c2fab 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<> 132:9baf128c2fab 1408 {
<> 132:9baf128c2fab 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 132:9baf128c2fab 1410 }
<> 132:9baf128c2fab 1411
<> 132:9baf128c2fab 1412
<> 132:9baf128c2fab 1413 /** \brief Enable External Interrupt
<> 132:9baf128c2fab 1414
<> 132:9baf128c2fab 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 1416
<> 132:9baf128c2fab 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 1418 */
<> 132:9baf128c2fab 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 1420 {
<> 132:9baf128c2fab 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 1422 }
<> 132:9baf128c2fab 1423
<> 132:9baf128c2fab 1424
<> 132:9baf128c2fab 1425 /** \brief Disable External Interrupt
<> 132:9baf128c2fab 1426
<> 132:9baf128c2fab 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 1428
<> 132:9baf128c2fab 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 1430 */
<> 132:9baf128c2fab 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 1432 {
<> 132:9baf128c2fab 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 1434 __DSB();
<> 132:9baf128c2fab 1435 __ISB();
<> 132:9baf128c2fab 1436 }
<> 132:9baf128c2fab 1437
<> 132:9baf128c2fab 1438
<> 132:9baf128c2fab 1439 /** \brief Get Pending Interrupt
<> 132:9baf128c2fab 1440
<> 132:9baf128c2fab 1441 The function reads the pending register in the NVIC and returns the pending bit
<> 132:9baf128c2fab 1442 for the specified interrupt.
<> 132:9baf128c2fab 1443
<> 132:9baf128c2fab 1444 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 1445
<> 132:9baf128c2fab 1446 \return 0 Interrupt status is not pending.
<> 132:9baf128c2fab 1447 \return 1 Interrupt status is pending.
<> 132:9baf128c2fab 1448 */
<> 132:9baf128c2fab 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 1450 {
<> 132:9baf128c2fab 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 132:9baf128c2fab 1452 }
<> 132:9baf128c2fab 1453
<> 132:9baf128c2fab 1454
<> 132:9baf128c2fab 1455 /** \brief Set Pending Interrupt
<> 132:9baf128c2fab 1456
<> 132:9baf128c2fab 1457 The function sets the pending bit of an external interrupt.
<> 132:9baf128c2fab 1458
<> 132:9baf128c2fab 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 1460 */
<> 132:9baf128c2fab 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 1462 {
<> 132:9baf128c2fab 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 1464 }
<> 132:9baf128c2fab 1465
<> 132:9baf128c2fab 1466
<> 132:9baf128c2fab 1467 /** \brief Clear Pending Interrupt
<> 132:9baf128c2fab 1468
<> 132:9baf128c2fab 1469 The function clears the pending bit of an external interrupt.
<> 132:9baf128c2fab 1470
<> 132:9baf128c2fab 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 1472 */
<> 132:9baf128c2fab 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 1474 {
<> 132:9baf128c2fab 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 1476 }
<> 132:9baf128c2fab 1477
<> 132:9baf128c2fab 1478
<> 132:9baf128c2fab 1479 /** \brief Get Active Interrupt
<> 132:9baf128c2fab 1480
<> 132:9baf128c2fab 1481 The function reads the active register in NVIC and returns the active bit.
<> 132:9baf128c2fab 1482
<> 132:9baf128c2fab 1483 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 1484
<> 132:9baf128c2fab 1485 \return 0 Interrupt status is not active.
<> 132:9baf128c2fab 1486 \return 1 Interrupt status is active.
<> 132:9baf128c2fab 1487 */
<> 132:9baf128c2fab 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
<> 132:9baf128c2fab 1489 {
<> 132:9baf128c2fab 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 132:9baf128c2fab 1491 }
<> 132:9baf128c2fab 1492
<> 132:9baf128c2fab 1493
<> 132:9baf128c2fab 1494 /** \brief Set Interrupt Priority
<> 132:9baf128c2fab 1495
<> 132:9baf128c2fab 1496 The function sets the priority of an interrupt.
<> 132:9baf128c2fab 1497
<> 132:9baf128c2fab 1498 \note The priority cannot be set for every core interrupt.
<> 132:9baf128c2fab 1499
<> 132:9baf128c2fab 1500 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 1501 \param [in] priority Priority to set.
<> 132:9baf128c2fab 1502 */
<> 132:9baf128c2fab 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 132:9baf128c2fab 1504 {
<> 132:9baf128c2fab 1505 if((int32_t)IRQn < 0) {
<> 132:9baf128c2fab 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 132:9baf128c2fab 1507 }
<> 132:9baf128c2fab 1508 else {
<> 132:9baf128c2fab 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 132:9baf128c2fab 1510 }
<> 132:9baf128c2fab 1511 }
<> 132:9baf128c2fab 1512
<> 132:9baf128c2fab 1513
<> 132:9baf128c2fab 1514 /** \brief Get Interrupt Priority
<> 132:9baf128c2fab 1515
<> 132:9baf128c2fab 1516 The function reads the priority of an interrupt. The interrupt
<> 132:9baf128c2fab 1517 number can be positive to specify an external (device specific)
<> 132:9baf128c2fab 1518 interrupt, or negative to specify an internal (core) interrupt.
<> 132:9baf128c2fab 1519
<> 132:9baf128c2fab 1520
<> 132:9baf128c2fab 1521 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 132:9baf128c2fab 1523 priority bits of the microcontroller.
<> 132:9baf128c2fab 1524 */
<> 132:9baf128c2fab 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<> 132:9baf128c2fab 1526 {
<> 132:9baf128c2fab 1527
<> 132:9baf128c2fab 1528 if((int32_t)IRQn < 0) {
<> 132:9baf128c2fab 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 1530 }
<> 132:9baf128c2fab 1531 else {
<> 132:9baf128c2fab 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 1533 }
<> 132:9baf128c2fab 1534 }
<> 132:9baf128c2fab 1535
<> 132:9baf128c2fab 1536
<> 132:9baf128c2fab 1537 /** \brief Encode Priority
<> 132:9baf128c2fab 1538
<> 132:9baf128c2fab 1539 The function encodes the priority for an interrupt with the given priority group,
<> 132:9baf128c2fab 1540 preemptive priority value, and subpriority value.
<> 132:9baf128c2fab 1541 In case of a conflict between priority grouping and available
<> 132:9baf128c2fab 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 132:9baf128c2fab 1543
<> 132:9baf128c2fab 1544 \param [in] PriorityGroup Used priority group.
<> 132:9baf128c2fab 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
<> 132:9baf128c2fab 1546 \param [in] SubPriority Subpriority value (starting from 0).
<> 132:9baf128c2fab 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 132:9baf128c2fab 1548 */
<> 132:9baf128c2fab 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 132:9baf128c2fab 1550 {
<> 132:9baf128c2fab 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 132:9baf128c2fab 1552 uint32_t PreemptPriorityBits;
<> 132:9baf128c2fab 1553 uint32_t SubPriorityBits;
<> 132:9baf128c2fab 1554
<> 132:9baf128c2fab 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 132:9baf128c2fab 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 132:9baf128c2fab 1557
<> 132:9baf128c2fab 1558 return (
<> 132:9baf128c2fab 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 132:9baf128c2fab 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 132:9baf128c2fab 1561 );
<> 132:9baf128c2fab 1562 }
<> 132:9baf128c2fab 1563
<> 132:9baf128c2fab 1564
<> 132:9baf128c2fab 1565 /** \brief Decode Priority
<> 132:9baf128c2fab 1566
<> 132:9baf128c2fab 1567 The function decodes an interrupt priority value with a given priority group to
<> 132:9baf128c2fab 1568 preemptive priority value and subpriority value.
<> 132:9baf128c2fab 1569 In case of a conflict between priority grouping and available
<> 132:9baf128c2fab 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<> 132:9baf128c2fab 1571
<> 132:9baf128c2fab 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<> 132:9baf128c2fab 1573 \param [in] PriorityGroup Used priority group.
<> 132:9baf128c2fab 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
<> 132:9baf128c2fab 1575 \param [out] pSubPriority Subpriority value (starting from 0).
<> 132:9baf128c2fab 1576 */
<> 132:9baf128c2fab 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 132:9baf128c2fab 1578 {
<> 132:9baf128c2fab 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 132:9baf128c2fab 1580 uint32_t PreemptPriorityBits;
<> 132:9baf128c2fab 1581 uint32_t SubPriorityBits;
<> 132:9baf128c2fab 1582
<> 132:9baf128c2fab 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 132:9baf128c2fab 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 132:9baf128c2fab 1585
<> 132:9baf128c2fab 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 132:9baf128c2fab 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 132:9baf128c2fab 1588 }
<> 132:9baf128c2fab 1589
<> 132:9baf128c2fab 1590
<> 132:9baf128c2fab 1591 /** \brief System Reset
<> 132:9baf128c2fab 1592
<> 132:9baf128c2fab 1593 The function initiates a system reset request to reset the MCU.
<> 132:9baf128c2fab 1594 */
<> 132:9baf128c2fab 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
<> 132:9baf128c2fab 1596 {
<> 132:9baf128c2fab 1597 __DSB(); /* Ensure all outstanding memory accesses included
<> 132:9baf128c2fab 1598 buffered write are completed before reset */
<> 132:9baf128c2fab 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 132:9baf128c2fab 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 132:9baf128c2fab 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 132:9baf128c2fab 1602 __DSB(); /* Ensure completion of memory access */
<> 132:9baf128c2fab 1603 while(1) { __NOP(); } /* wait until reset */
<> 132:9baf128c2fab 1604 }
<> 132:9baf128c2fab 1605
<> 132:9baf128c2fab 1606 /*@} end of CMSIS_Core_NVICFunctions */
<> 132:9baf128c2fab 1607
<> 132:9baf128c2fab 1608
<> 132:9baf128c2fab 1609
<> 132:9baf128c2fab 1610 /* ################################## SysTick function ############################################ */
<> 132:9baf128c2fab 1611 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 132:9baf128c2fab 1613 \brief Functions that configure the System.
<> 132:9baf128c2fab 1614 @{
<> 132:9baf128c2fab 1615 */
<> 132:9baf128c2fab 1616
<> 132:9baf128c2fab 1617 #if (__Vendor_SysTickConfig == 0)
<> 132:9baf128c2fab 1618
<> 132:9baf128c2fab 1619 /** \brief System Tick Configuration
<> 132:9baf128c2fab 1620
<> 132:9baf128c2fab 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 132:9baf128c2fab 1622 Counter is in free running mode to generate periodic interrupts.
<> 132:9baf128c2fab 1623
<> 132:9baf128c2fab 1624 \param [in] ticks Number of ticks between two interrupts.
<> 132:9baf128c2fab 1625
<> 132:9baf128c2fab 1626 \return 0 Function succeeded.
<> 132:9baf128c2fab 1627 \return 1 Function failed.
<> 132:9baf128c2fab 1628
<> 132:9baf128c2fab 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 132:9baf128c2fab 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 132:9baf128c2fab 1631 must contain a vendor-specific implementation of this function.
<> 132:9baf128c2fab 1632
<> 132:9baf128c2fab 1633 */
<> 132:9baf128c2fab 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 132:9baf128c2fab 1635 {
<> 132:9baf128c2fab 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 132:9baf128c2fab 1637
<> 132:9baf128c2fab 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 132:9baf128c2fab 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 132:9baf128c2fab 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 132:9baf128c2fab 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 132:9baf128c2fab 1642 SysTick_CTRL_TICKINT_Msk |
<> 132:9baf128c2fab 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 132:9baf128c2fab 1644 return (0UL); /* Function successful */
<> 132:9baf128c2fab 1645 }
<> 132:9baf128c2fab 1646
<> 132:9baf128c2fab 1647 #endif
<> 132:9baf128c2fab 1648
<> 132:9baf128c2fab 1649 /*@} end of CMSIS_Core_SysTickFunctions */
<> 132:9baf128c2fab 1650
<> 132:9baf128c2fab 1651
<> 132:9baf128c2fab 1652
<> 132:9baf128c2fab 1653 /* ##################################### Debug In/Output function ########################################### */
<> 132:9baf128c2fab 1654 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
<> 132:9baf128c2fab 1656 \brief Functions that access the ITM debug interface.
<> 132:9baf128c2fab 1657 @{
<> 132:9baf128c2fab 1658 */
<> 132:9baf128c2fab 1659
<> 132:9baf128c2fab 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
<> 132:9baf128c2fab 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 132:9baf128c2fab 1662
<> 132:9baf128c2fab 1663
<> 132:9baf128c2fab 1664 /** \brief ITM Send Character
<> 132:9baf128c2fab 1665
<> 132:9baf128c2fab 1666 The function transmits a character via the ITM channel 0, and
<> 132:9baf128c2fab 1667 \li Just returns when no debugger is connected that has booked the output.
<> 132:9baf128c2fab 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<> 132:9baf128c2fab 1669
<> 132:9baf128c2fab 1670 \param [in] ch Character to transmit.
<> 132:9baf128c2fab 1671
<> 132:9baf128c2fab 1672 \returns Character to transmit.
<> 132:9baf128c2fab 1673 */
<> 132:9baf128c2fab 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 132:9baf128c2fab 1675 {
<> 132:9baf128c2fab 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 132:9baf128c2fab 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 132:9baf128c2fab 1678 {
<> 132:9baf128c2fab 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<> 132:9baf128c2fab 1680 ITM->PORT[0].u8 = (uint8_t)ch;
<> 132:9baf128c2fab 1681 }
<> 132:9baf128c2fab 1682 return (ch);
<> 132:9baf128c2fab 1683 }
<> 132:9baf128c2fab 1684
<> 132:9baf128c2fab 1685
<> 132:9baf128c2fab 1686 /** \brief ITM Receive Character
<> 132:9baf128c2fab 1687
<> 132:9baf128c2fab 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
<> 132:9baf128c2fab 1689
<> 132:9baf128c2fab 1690 \return Received character.
<> 132:9baf128c2fab 1691 \return -1 No character pending.
<> 132:9baf128c2fab 1692 */
<> 132:9baf128c2fab 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<> 132:9baf128c2fab 1694 int32_t ch = -1; /* no character available */
<> 132:9baf128c2fab 1695
<> 132:9baf128c2fab 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<> 132:9baf128c2fab 1697 ch = ITM_RxBuffer;
<> 132:9baf128c2fab 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 132:9baf128c2fab 1699 }
<> 132:9baf128c2fab 1700
<> 132:9baf128c2fab 1701 return (ch);
<> 132:9baf128c2fab 1702 }
<> 132:9baf128c2fab 1703
<> 132:9baf128c2fab 1704
<> 132:9baf128c2fab 1705 /** \brief ITM Check Character
<> 132:9baf128c2fab 1706
<> 132:9baf128c2fab 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<> 132:9baf128c2fab 1708
<> 132:9baf128c2fab 1709 \return 0 No character available.
<> 132:9baf128c2fab 1710 \return 1 Character available.
<> 132:9baf128c2fab 1711 */
<> 132:9baf128c2fab 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
<> 132:9baf128c2fab 1713
<> 132:9baf128c2fab 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<> 132:9baf128c2fab 1715 return (0); /* no character available */
<> 132:9baf128c2fab 1716 } else {
<> 132:9baf128c2fab 1717 return (1); /* character available */
<> 132:9baf128c2fab 1718 }
<> 132:9baf128c2fab 1719 }
<> 132:9baf128c2fab 1720
<> 132:9baf128c2fab 1721 /*@} end of CMSIS_core_DebugFunctions */
<> 132:9baf128c2fab 1722
<> 132:9baf128c2fab 1723
<> 132:9baf128c2fab 1724
<> 132:9baf128c2fab 1725
<> 132:9baf128c2fab 1726 #ifdef __cplusplus
<> 132:9baf128c2fab 1727 }
<> 132:9baf128c2fab 1728 #endif
<> 132:9baf128c2fab 1729
<> 132:9baf128c2fab 1730 #endif /* __CORE_CM3_H_DEPENDANT */
<> 132:9baf128c2fab 1731
<> 132:9baf128c2fab 1732 #endif /* __CMSIS_GENERIC */