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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_THUNDERBOARD_SENSE/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
132:9baf128c2fab 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_cm0plus.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
<> 132:9baf128c2fab 4 * @version V4.10
<> 132:9baf128c2fab 5 * @date 18. March 2015
<> 132:9baf128c2fab 6 *
<> 132:9baf128c2fab 7 * @note
<> 132:9baf128c2fab 8 *
<> 132:9baf128c2fab 9 ******************************************************************************/
<> 132:9baf128c2fab 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 132:9baf128c2fab 11
<> 132:9baf128c2fab 12 All rights reserved.
<> 132:9baf128c2fab 13 Redistribution and use in source and binary forms, with or without
<> 132:9baf128c2fab 14 modification, are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 - Redistributions of source code must retain the above copyright
<> 132:9baf128c2fab 16 notice, this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 - Redistributions in binary form must reproduce the above copyright
<> 132:9baf128c2fab 18 notice, this list of conditions and the following disclaimer in the
<> 132:9baf128c2fab 19 documentation and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 - Neither the name of ARM nor the names of its contributors may be used
<> 132:9baf128c2fab 21 to endorse or promote products derived from this software without
<> 132:9baf128c2fab 22 specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 132:9baf128c2fab 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 132:9baf128c2fab 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 132:9baf128c2fab 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 132:9baf128c2fab 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 132:9baf128c2fab 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 132:9baf128c2fab 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 132:9baf128c2fab 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 132:9baf128c2fab 34 POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 35 ---------------------------------------------------------------------------*/
<> 132:9baf128c2fab 36
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 #if defined ( __ICCARM__ )
<> 132:9baf128c2fab 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 132:9baf128c2fab 40 #endif
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 132:9baf128c2fab 43 #define __CORE_CM0PLUS_H_GENERIC
<> 132:9baf128c2fab 44
<> 132:9baf128c2fab 45 #ifdef __cplusplus
<> 132:9baf128c2fab 46 extern "C" {
<> 132:9baf128c2fab 47 #endif
<> 132:9baf128c2fab 48
<> 132:9baf128c2fab 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 132:9baf128c2fab 50 CMSIS violates the following MISRA-C:2004 rules:
<> 132:9baf128c2fab 51
<> 132:9baf128c2fab 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 132:9baf128c2fab 53 Function definitions in header files are used to allow 'inlining'.
<> 132:9baf128c2fab 54
<> 132:9baf128c2fab 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 132:9baf128c2fab 56 Unions are used for effective representation of core registers.
<> 132:9baf128c2fab 57
<> 132:9baf128c2fab 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 132:9baf128c2fab 59 Function-like macros are used to allow more efficient code.
<> 132:9baf128c2fab 60 */
<> 132:9baf128c2fab 61
<> 132:9baf128c2fab 62
<> 132:9baf128c2fab 63 /*******************************************************************************
<> 132:9baf128c2fab 64 * CMSIS definitions
<> 132:9baf128c2fab 65 ******************************************************************************/
<> 132:9baf128c2fab 66 /** \ingroup Cortex-M0+
<> 132:9baf128c2fab 67 @{
<> 132:9baf128c2fab 68 */
<> 132:9baf128c2fab 69
<> 132:9baf128c2fab 70 /* CMSIS CM0P definitions */
<> 132:9baf128c2fab 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 132:9baf128c2fab 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 132:9baf128c2fab 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
<> 132:9baf128c2fab 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 132:9baf128c2fab 75
<> 132:9baf128c2fab 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 132:9baf128c2fab 77
<> 132:9baf128c2fab 78
<> 132:9baf128c2fab 79 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 132:9baf128c2fab 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 132:9baf128c2fab 82 #define __STATIC_INLINE static __inline
<> 132:9baf128c2fab 83
<> 132:9baf128c2fab 84 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 132:9baf128c2fab 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 132:9baf128c2fab 87 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 88
<> 132:9baf128c2fab 89 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 132:9baf128c2fab 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 132:9baf128c2fab 92 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 93
<> 132:9baf128c2fab 94 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 132:9baf128c2fab 96 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 97
<> 132:9baf128c2fab 98 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 132:9baf128c2fab 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 132:9baf128c2fab 101 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 102
<> 132:9baf128c2fab 103 #elif defined ( __CSMC__ )
<> 132:9baf128c2fab 104 #define __packed
<> 132:9baf128c2fab 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 132:9baf128c2fab 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 132:9baf128c2fab 107 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 108
<> 132:9baf128c2fab 109 #endif
<> 132:9baf128c2fab 110
<> 132:9baf128c2fab 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 132:9baf128c2fab 112 This core does not support an FPU at all
<> 132:9baf128c2fab 113 */
<> 132:9baf128c2fab 114 #define __FPU_USED 0
<> 132:9baf128c2fab 115
<> 132:9baf128c2fab 116 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 117 #if defined __TARGET_FPU_VFP
<> 132:9baf128c2fab 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 119 #endif
<> 132:9baf128c2fab 120
<> 132:9baf128c2fab 121 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 132:9baf128c2fab 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 124 #endif
<> 132:9baf128c2fab 125
<> 132:9baf128c2fab 126 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 127 #if defined __ARMVFP__
<> 132:9baf128c2fab 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 129 #endif
<> 132:9baf128c2fab 130
<> 132:9baf128c2fab 131 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 132 #if defined __TI__VFP_SUPPORT____
<> 132:9baf128c2fab 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 134 #endif
<> 132:9baf128c2fab 135
<> 132:9baf128c2fab 136 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 137 #if defined __FPU_VFP__
<> 132:9baf128c2fab 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 139 #endif
<> 132:9baf128c2fab 140
<> 132:9baf128c2fab 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 132:9baf128c2fab 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 132:9baf128c2fab 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 144 #endif
<> 132:9baf128c2fab 145 #endif
<> 132:9baf128c2fab 146
<> 132:9baf128c2fab 147 #include <stdint.h> /* standard types definitions */
<> 132:9baf128c2fab 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 132:9baf128c2fab 149 #include <core_cmFunc.h> /* Core Function Access */
<> 132:9baf128c2fab 150
<> 132:9baf128c2fab 151 #ifdef __cplusplus
<> 132:9baf128c2fab 152 }
<> 132:9baf128c2fab 153 #endif
<> 132:9baf128c2fab 154
<> 132:9baf128c2fab 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 132:9baf128c2fab 156
<> 132:9baf128c2fab 157 #ifndef __CMSIS_GENERIC
<> 132:9baf128c2fab 158
<> 132:9baf128c2fab 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 132:9baf128c2fab 160 #define __CORE_CM0PLUS_H_DEPENDANT
<> 132:9baf128c2fab 161
<> 132:9baf128c2fab 162 #ifdef __cplusplus
<> 132:9baf128c2fab 163 extern "C" {
<> 132:9baf128c2fab 164 #endif
<> 132:9baf128c2fab 165
<> 132:9baf128c2fab 166 /* check device defines and use defaults */
<> 132:9baf128c2fab 167 #if defined __CHECK_DEVICE_DEFINES
<> 132:9baf128c2fab 168 #ifndef __CM0PLUS_REV
<> 132:9baf128c2fab 169 #define __CM0PLUS_REV 0x0000
<> 132:9baf128c2fab 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 132:9baf128c2fab 171 #endif
<> 132:9baf128c2fab 172
<> 132:9baf128c2fab 173 #ifndef __MPU_PRESENT
<> 132:9baf128c2fab 174 #define __MPU_PRESENT 0
<> 132:9baf128c2fab 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 132:9baf128c2fab 176 #endif
<> 132:9baf128c2fab 177
<> 132:9baf128c2fab 178 #ifndef __VTOR_PRESENT
<> 132:9baf128c2fab 179 #define __VTOR_PRESENT 0
<> 132:9baf128c2fab 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 132:9baf128c2fab 181 #endif
<> 132:9baf128c2fab 182
<> 132:9baf128c2fab 183 #ifndef __NVIC_PRIO_BITS
<> 132:9baf128c2fab 184 #define __NVIC_PRIO_BITS 2
<> 132:9baf128c2fab 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 132:9baf128c2fab 186 #endif
<> 132:9baf128c2fab 187
<> 132:9baf128c2fab 188 #ifndef __Vendor_SysTickConfig
<> 132:9baf128c2fab 189 #define __Vendor_SysTickConfig 0
<> 132:9baf128c2fab 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 132:9baf128c2fab 191 #endif
<> 132:9baf128c2fab 192 #endif
<> 132:9baf128c2fab 193
<> 132:9baf128c2fab 194 /* IO definitions (access restrictions to peripheral registers) */
<> 132:9baf128c2fab 195 /**
<> 132:9baf128c2fab 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 132:9baf128c2fab 197
<> 132:9baf128c2fab 198 <strong>IO Type Qualifiers</strong> are used
<> 132:9baf128c2fab 199 \li to specify the access to peripheral variables.
<> 132:9baf128c2fab 200 \li for automatic generation of peripheral register debug information.
<> 132:9baf128c2fab 201 */
<> 132:9baf128c2fab 202 #ifdef __cplusplus
<> 132:9baf128c2fab 203 #define __I volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 204 #else
<> 132:9baf128c2fab 205 #define __I volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 206 #endif
<> 132:9baf128c2fab 207 #define __O volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 208 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 209
<> 132:9baf128c2fab 210 #ifdef __cplusplus
<> 132:9baf128c2fab 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 212 #else
<> 132:9baf128c2fab 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 214 #endif
<> 132:9baf128c2fab 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 217
<> 132:9baf128c2fab 218 /*@} end of group Cortex-M0+ */
<> 132:9baf128c2fab 219
<> 132:9baf128c2fab 220
<> 132:9baf128c2fab 221
<> 132:9baf128c2fab 222 /*******************************************************************************
<> 132:9baf128c2fab 223 * Register Abstraction
<> 132:9baf128c2fab 224 Core Register contain:
<> 132:9baf128c2fab 225 - Core Register
<> 132:9baf128c2fab 226 - Core NVIC Register
<> 132:9baf128c2fab 227 - Core SCB Register
<> 132:9baf128c2fab 228 - Core SysTick Register
<> 132:9baf128c2fab 229 - Core MPU Register
<> 132:9baf128c2fab 230 ******************************************************************************/
<> 132:9baf128c2fab 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 132:9baf128c2fab 232 \brief Type definitions and defines for Cortex-M processor based devices.
<> 132:9baf128c2fab 233 */
<> 132:9baf128c2fab 234
<> 132:9baf128c2fab 235 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 236 \defgroup CMSIS_CORE Status and Control Registers
<> 132:9baf128c2fab 237 \brief Core Register type definitions.
<> 132:9baf128c2fab 238 @{
<> 132:9baf128c2fab 239 */
<> 132:9baf128c2fab 240
<> 132:9baf128c2fab 241 /** \brief Union type to access the Application Program Status Register (APSR).
<> 132:9baf128c2fab 242 */
<> 132:9baf128c2fab 243 typedef union
<> 132:9baf128c2fab 244 {
<> 132:9baf128c2fab 245 struct
<> 132:9baf128c2fab 246 {
<> 132:9baf128c2fab 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 132:9baf128c2fab 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 252 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 253 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 254 } APSR_Type;
<> 132:9baf128c2fab 255
<> 132:9baf128c2fab 256 /* APSR Register Definitions */
<> 132:9baf128c2fab 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 132:9baf128c2fab 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 132:9baf128c2fab 259
<> 132:9baf128c2fab 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 132:9baf128c2fab 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 132:9baf128c2fab 262
<> 132:9baf128c2fab 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 132:9baf128c2fab 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 132:9baf128c2fab 265
<> 132:9baf128c2fab 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 132:9baf128c2fab 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 132:9baf128c2fab 268
<> 132:9baf128c2fab 269
<> 132:9baf128c2fab 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 132:9baf128c2fab 271 */
<> 132:9baf128c2fab 272 typedef union
<> 132:9baf128c2fab 273 {
<> 132:9baf128c2fab 274 struct
<> 132:9baf128c2fab 275 {
<> 132:9baf128c2fab 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 132:9baf128c2fab 278 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 279 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 280 } IPSR_Type;
<> 132:9baf128c2fab 281
<> 132:9baf128c2fab 282 /* IPSR Register Definitions */
<> 132:9baf128c2fab 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 132:9baf128c2fab 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 132:9baf128c2fab 285
<> 132:9baf128c2fab 286
<> 132:9baf128c2fab 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 132:9baf128c2fab 288 */
<> 132:9baf128c2fab 289 typedef union
<> 132:9baf128c2fab 290 {
<> 132:9baf128c2fab 291 struct
<> 132:9baf128c2fab 292 {
<> 132:9baf128c2fab 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 132:9baf128c2fab 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 132:9baf128c2fab 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 132:9baf128c2fab 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 301 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 302 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 303 } xPSR_Type;
<> 132:9baf128c2fab 304
<> 132:9baf128c2fab 305 /* xPSR Register Definitions */
<> 132:9baf128c2fab 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 132:9baf128c2fab 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 132:9baf128c2fab 308
<> 132:9baf128c2fab 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 132:9baf128c2fab 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 132:9baf128c2fab 311
<> 132:9baf128c2fab 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 132:9baf128c2fab 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 132:9baf128c2fab 314
<> 132:9baf128c2fab 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 132:9baf128c2fab 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 132:9baf128c2fab 317
<> 132:9baf128c2fab 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 132:9baf128c2fab 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 132:9baf128c2fab 320
<> 132:9baf128c2fab 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 132:9baf128c2fab 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 132:9baf128c2fab 323
<> 132:9baf128c2fab 324
<> 132:9baf128c2fab 325 /** \brief Union type to access the Control Registers (CONTROL).
<> 132:9baf128c2fab 326 */
<> 132:9baf128c2fab 327 typedef union
<> 132:9baf128c2fab 328 {
<> 132:9baf128c2fab 329 struct
<> 132:9baf128c2fab 330 {
<> 132:9baf128c2fab 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 132:9baf128c2fab 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 132:9baf128c2fab 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 132:9baf128c2fab 334 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 335 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 336 } CONTROL_Type;
<> 132:9baf128c2fab 337
<> 132:9baf128c2fab 338 /* CONTROL Register Definitions */
<> 132:9baf128c2fab 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 132:9baf128c2fab 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 132:9baf128c2fab 341
<> 132:9baf128c2fab 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 132:9baf128c2fab 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 132:9baf128c2fab 344
<> 132:9baf128c2fab 345 /*@} end of group CMSIS_CORE */
<> 132:9baf128c2fab 346
<> 132:9baf128c2fab 347
<> 132:9baf128c2fab 348 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 132:9baf128c2fab 350 \brief Type definitions for the NVIC Registers
<> 132:9baf128c2fab 351 @{
<> 132:9baf128c2fab 352 */
<> 132:9baf128c2fab 353
<> 132:9baf128c2fab 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 132:9baf128c2fab 355 */
<> 132:9baf128c2fab 356 typedef struct
<> 132:9baf128c2fab 357 {
<> 132:9baf128c2fab 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 132:9baf128c2fab 359 uint32_t RESERVED0[31];
<> 132:9baf128c2fab 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 132:9baf128c2fab 361 uint32_t RSERVED1[31];
<> 132:9baf128c2fab 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 132:9baf128c2fab 363 uint32_t RESERVED2[31];
<> 132:9baf128c2fab 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 132:9baf128c2fab 365 uint32_t RESERVED3[31];
<> 132:9baf128c2fab 366 uint32_t RESERVED4[64];
<> 132:9baf128c2fab 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 132:9baf128c2fab 368 } NVIC_Type;
<> 132:9baf128c2fab 369
<> 132:9baf128c2fab 370 /*@} end of group CMSIS_NVIC */
<> 132:9baf128c2fab 371
<> 132:9baf128c2fab 372
<> 132:9baf128c2fab 373 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 374 \defgroup CMSIS_SCB System Control Block (SCB)
<> 132:9baf128c2fab 375 \brief Type definitions for the System Control Block Registers
<> 132:9baf128c2fab 376 @{
<> 132:9baf128c2fab 377 */
<> 132:9baf128c2fab 378
<> 132:9baf128c2fab 379 /** \brief Structure type to access the System Control Block (SCB).
<> 132:9baf128c2fab 380 */
<> 132:9baf128c2fab 381 typedef struct
<> 132:9baf128c2fab 382 {
<> 132:9baf128c2fab 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 132:9baf128c2fab 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 132:9baf128c2fab 385 #if (__VTOR_PRESENT == 1)
<> 132:9baf128c2fab 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 132:9baf128c2fab 387 #else
<> 132:9baf128c2fab 388 uint32_t RESERVED0;
<> 132:9baf128c2fab 389 #endif
<> 132:9baf128c2fab 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 132:9baf128c2fab 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 132:9baf128c2fab 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 132:9baf128c2fab 393 uint32_t RESERVED1;
<> 132:9baf128c2fab 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 132:9baf128c2fab 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 132:9baf128c2fab 396 } SCB_Type;
<> 132:9baf128c2fab 397
<> 132:9baf128c2fab 398 /* SCB CPUID Register Definitions */
<> 132:9baf128c2fab 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 132:9baf128c2fab 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 132:9baf128c2fab 401
<> 132:9baf128c2fab 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 132:9baf128c2fab 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 132:9baf128c2fab 404
<> 132:9baf128c2fab 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 132:9baf128c2fab 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 132:9baf128c2fab 407
<> 132:9baf128c2fab 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 132:9baf128c2fab 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 132:9baf128c2fab 410
<> 132:9baf128c2fab 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 132:9baf128c2fab 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 132:9baf128c2fab 413
<> 132:9baf128c2fab 414 /* SCB Interrupt Control State Register Definitions */
<> 132:9baf128c2fab 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 132:9baf128c2fab 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 132:9baf128c2fab 417
<> 132:9baf128c2fab 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 132:9baf128c2fab 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 132:9baf128c2fab 420
<> 132:9baf128c2fab 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 132:9baf128c2fab 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 132:9baf128c2fab 423
<> 132:9baf128c2fab 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 132:9baf128c2fab 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 132:9baf128c2fab 426
<> 132:9baf128c2fab 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 132:9baf128c2fab 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 132:9baf128c2fab 429
<> 132:9baf128c2fab 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 132:9baf128c2fab 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 132:9baf128c2fab 432
<> 132:9baf128c2fab 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 132:9baf128c2fab 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 132:9baf128c2fab 435
<> 132:9baf128c2fab 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 132:9baf128c2fab 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 132:9baf128c2fab 438
<> 132:9baf128c2fab 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 132:9baf128c2fab 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 132:9baf128c2fab 441
<> 132:9baf128c2fab 442 #if (__VTOR_PRESENT == 1)
<> 132:9baf128c2fab 443 /* SCB Interrupt Control State Register Definitions */
<> 132:9baf128c2fab 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
<> 132:9baf128c2fab 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 132:9baf128c2fab 446 #endif
<> 132:9baf128c2fab 447
<> 132:9baf128c2fab 448 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 132:9baf128c2fab 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 132:9baf128c2fab 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 132:9baf128c2fab 451
<> 132:9baf128c2fab 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 132:9baf128c2fab 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 132:9baf128c2fab 454
<> 132:9baf128c2fab 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 132:9baf128c2fab 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 132:9baf128c2fab 457
<> 132:9baf128c2fab 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 132:9baf128c2fab 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 132:9baf128c2fab 460
<> 132:9baf128c2fab 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 132:9baf128c2fab 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 132:9baf128c2fab 463
<> 132:9baf128c2fab 464 /* SCB System Control Register Definitions */
<> 132:9baf128c2fab 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 132:9baf128c2fab 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 132:9baf128c2fab 467
<> 132:9baf128c2fab 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 132:9baf128c2fab 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 132:9baf128c2fab 470
<> 132:9baf128c2fab 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 132:9baf128c2fab 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 132:9baf128c2fab 473
<> 132:9baf128c2fab 474 /* SCB Configuration Control Register Definitions */
<> 132:9baf128c2fab 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 132:9baf128c2fab 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 132:9baf128c2fab 477
<> 132:9baf128c2fab 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 132:9baf128c2fab 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 132:9baf128c2fab 480
<> 132:9baf128c2fab 481 /* SCB System Handler Control and State Register Definitions */
<> 132:9baf128c2fab 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 132:9baf128c2fab 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 132:9baf128c2fab 484
<> 132:9baf128c2fab 485 /*@} end of group CMSIS_SCB */
<> 132:9baf128c2fab 486
<> 132:9baf128c2fab 487
<> 132:9baf128c2fab 488 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 132:9baf128c2fab 490 \brief Type definitions for the System Timer Registers.
<> 132:9baf128c2fab 491 @{
<> 132:9baf128c2fab 492 */
<> 132:9baf128c2fab 493
<> 132:9baf128c2fab 494 /** \brief Structure type to access the System Timer (SysTick).
<> 132:9baf128c2fab 495 */
<> 132:9baf128c2fab 496 typedef struct
<> 132:9baf128c2fab 497 {
<> 132:9baf128c2fab 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 132:9baf128c2fab 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 132:9baf128c2fab 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 132:9baf128c2fab 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 132:9baf128c2fab 502 } SysTick_Type;
<> 132:9baf128c2fab 503
<> 132:9baf128c2fab 504 /* SysTick Control / Status Register Definitions */
<> 132:9baf128c2fab 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 132:9baf128c2fab 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 132:9baf128c2fab 507
<> 132:9baf128c2fab 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 132:9baf128c2fab 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 132:9baf128c2fab 510
<> 132:9baf128c2fab 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 132:9baf128c2fab 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 132:9baf128c2fab 513
<> 132:9baf128c2fab 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 132:9baf128c2fab 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 132:9baf128c2fab 516
<> 132:9baf128c2fab 517 /* SysTick Reload Register Definitions */
<> 132:9baf128c2fab 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 132:9baf128c2fab 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 132:9baf128c2fab 520
<> 132:9baf128c2fab 521 /* SysTick Current Register Definitions */
<> 132:9baf128c2fab 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 132:9baf128c2fab 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 132:9baf128c2fab 524
<> 132:9baf128c2fab 525 /* SysTick Calibration Register Definitions */
<> 132:9baf128c2fab 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 132:9baf128c2fab 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 132:9baf128c2fab 528
<> 132:9baf128c2fab 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 132:9baf128c2fab 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 132:9baf128c2fab 531
<> 132:9baf128c2fab 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 132:9baf128c2fab 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 132:9baf128c2fab 534
<> 132:9baf128c2fab 535 /*@} end of group CMSIS_SysTick */
<> 132:9baf128c2fab 536
<> 132:9baf128c2fab 537 #if (__MPU_PRESENT == 1)
<> 132:9baf128c2fab 538 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 132:9baf128c2fab 540 \brief Type definitions for the Memory Protection Unit (MPU)
<> 132:9baf128c2fab 541 @{
<> 132:9baf128c2fab 542 */
<> 132:9baf128c2fab 543
<> 132:9baf128c2fab 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 132:9baf128c2fab 545 */
<> 132:9baf128c2fab 546 typedef struct
<> 132:9baf128c2fab 547 {
<> 132:9baf128c2fab 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 132:9baf128c2fab 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 132:9baf128c2fab 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 132:9baf128c2fab 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 132:9baf128c2fab 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 132:9baf128c2fab 553 } MPU_Type;
<> 132:9baf128c2fab 554
<> 132:9baf128c2fab 555 /* MPU Type Register */
<> 132:9baf128c2fab 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 132:9baf128c2fab 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 132:9baf128c2fab 558
<> 132:9baf128c2fab 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 132:9baf128c2fab 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 132:9baf128c2fab 561
<> 132:9baf128c2fab 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 132:9baf128c2fab 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 132:9baf128c2fab 564
<> 132:9baf128c2fab 565 /* MPU Control Register */
<> 132:9baf128c2fab 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 132:9baf128c2fab 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 132:9baf128c2fab 568
<> 132:9baf128c2fab 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 132:9baf128c2fab 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 132:9baf128c2fab 571
<> 132:9baf128c2fab 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 132:9baf128c2fab 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 132:9baf128c2fab 574
<> 132:9baf128c2fab 575 /* MPU Region Number Register */
<> 132:9baf128c2fab 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 132:9baf128c2fab 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 132:9baf128c2fab 578
<> 132:9baf128c2fab 579 /* MPU Region Base Address Register */
<> 132:9baf128c2fab 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 132:9baf128c2fab 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 132:9baf128c2fab 582
<> 132:9baf128c2fab 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 132:9baf128c2fab 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 132:9baf128c2fab 585
<> 132:9baf128c2fab 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 132:9baf128c2fab 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 132:9baf128c2fab 588
<> 132:9baf128c2fab 589 /* MPU Region Attribute and Size Register */
<> 132:9baf128c2fab 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 132:9baf128c2fab 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 132:9baf128c2fab 592
<> 132:9baf128c2fab 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 132:9baf128c2fab 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 132:9baf128c2fab 595
<> 132:9baf128c2fab 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 132:9baf128c2fab 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 132:9baf128c2fab 598
<> 132:9baf128c2fab 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 132:9baf128c2fab 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 132:9baf128c2fab 601
<> 132:9baf128c2fab 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 132:9baf128c2fab 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 132:9baf128c2fab 604
<> 132:9baf128c2fab 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 132:9baf128c2fab 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 132:9baf128c2fab 607
<> 132:9baf128c2fab 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 132:9baf128c2fab 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 132:9baf128c2fab 610
<> 132:9baf128c2fab 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 132:9baf128c2fab 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 132:9baf128c2fab 613
<> 132:9baf128c2fab 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 132:9baf128c2fab 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 132:9baf128c2fab 616
<> 132:9baf128c2fab 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 132:9baf128c2fab 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 132:9baf128c2fab 619
<> 132:9baf128c2fab 620 /*@} end of group CMSIS_MPU */
<> 132:9baf128c2fab 621 #endif
<> 132:9baf128c2fab 622
<> 132:9baf128c2fab 623
<> 132:9baf128c2fab 624 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 132:9baf128c2fab 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 132:9baf128c2fab 627 are only accessible over DAP and not via processor. Therefore
<> 132:9baf128c2fab 628 they are not covered by the Cortex-M0 header file.
<> 132:9baf128c2fab 629 @{
<> 132:9baf128c2fab 630 */
<> 132:9baf128c2fab 631 /*@} end of group CMSIS_CoreDebug */
<> 132:9baf128c2fab 632
<> 132:9baf128c2fab 633
<> 132:9baf128c2fab 634 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 635 \defgroup CMSIS_core_base Core Definitions
<> 132:9baf128c2fab 636 \brief Definitions for base addresses, unions, and structures.
<> 132:9baf128c2fab 637 @{
<> 132:9baf128c2fab 638 */
<> 132:9baf128c2fab 639
<> 132:9baf128c2fab 640 /* Memory mapping of Cortex-M0+ Hardware */
<> 132:9baf128c2fab 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 132:9baf128c2fab 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 132:9baf128c2fab 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 132:9baf128c2fab 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 132:9baf128c2fab 645
<> 132:9baf128c2fab 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 132:9baf128c2fab 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 132:9baf128c2fab 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 132:9baf128c2fab 649
<> 132:9baf128c2fab 650 #if (__MPU_PRESENT == 1)
<> 132:9baf128c2fab 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 132:9baf128c2fab 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 132:9baf128c2fab 653 #endif
<> 132:9baf128c2fab 654
<> 132:9baf128c2fab 655 /*@} */
<> 132:9baf128c2fab 656
<> 132:9baf128c2fab 657
<> 132:9baf128c2fab 658
<> 132:9baf128c2fab 659 /*******************************************************************************
<> 132:9baf128c2fab 660 * Hardware Abstraction Layer
<> 132:9baf128c2fab 661 Core Function Interface contains:
<> 132:9baf128c2fab 662 - Core NVIC Functions
<> 132:9baf128c2fab 663 - Core SysTick Functions
<> 132:9baf128c2fab 664 - Core Register Access Functions
<> 132:9baf128c2fab 665 ******************************************************************************/
<> 132:9baf128c2fab 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 132:9baf128c2fab 667 */
<> 132:9baf128c2fab 668
<> 132:9baf128c2fab 669
<> 132:9baf128c2fab 670
<> 132:9baf128c2fab 671 /* ########################## NVIC functions #################################### */
<> 132:9baf128c2fab 672 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 132:9baf128c2fab 674 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 132:9baf128c2fab 675 @{
<> 132:9baf128c2fab 676 */
<> 132:9baf128c2fab 677
<> 132:9baf128c2fab 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 132:9baf128c2fab 679 /* The following MACROS handle generation of the register offset and byte masks */
<> 132:9baf128c2fab 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 132:9baf128c2fab 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 132:9baf128c2fab 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 132:9baf128c2fab 683
<> 132:9baf128c2fab 684
<> 132:9baf128c2fab 685 /** \brief Enable External Interrupt
<> 132:9baf128c2fab 686
<> 132:9baf128c2fab 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 688
<> 132:9baf128c2fab 689 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 690 */
<> 132:9baf128c2fab 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 692 {
<> 132:9baf128c2fab 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 694 }
<> 132:9baf128c2fab 695
<> 132:9baf128c2fab 696
<> 132:9baf128c2fab 697 /** \brief Disable External Interrupt
<> 132:9baf128c2fab 698
<> 132:9baf128c2fab 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 700
<> 132:9baf128c2fab 701 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 702 */
<> 132:9baf128c2fab 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 704 {
<> 132:9baf128c2fab 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 706 __DSB();
<> 132:9baf128c2fab 707 __ISB();
<> 132:9baf128c2fab 708 }
<> 132:9baf128c2fab 709
<> 132:9baf128c2fab 710
<> 132:9baf128c2fab 711 /** \brief Get Pending Interrupt
<> 132:9baf128c2fab 712
<> 132:9baf128c2fab 713 The function reads the pending register in the NVIC and returns the pending bit
<> 132:9baf128c2fab 714 for the specified interrupt.
<> 132:9baf128c2fab 715
<> 132:9baf128c2fab 716 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 717
<> 132:9baf128c2fab 718 \return 0 Interrupt status is not pending.
<> 132:9baf128c2fab 719 \return 1 Interrupt status is pending.
<> 132:9baf128c2fab 720 */
<> 132:9baf128c2fab 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 722 {
<> 132:9baf128c2fab 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 132:9baf128c2fab 724 }
<> 132:9baf128c2fab 725
<> 132:9baf128c2fab 726
<> 132:9baf128c2fab 727 /** \brief Set Pending Interrupt
<> 132:9baf128c2fab 728
<> 132:9baf128c2fab 729 The function sets the pending bit of an external interrupt.
<> 132:9baf128c2fab 730
<> 132:9baf128c2fab 731 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 732 */
<> 132:9baf128c2fab 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 734 {
<> 132:9baf128c2fab 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 736 }
<> 132:9baf128c2fab 737
<> 132:9baf128c2fab 738
<> 132:9baf128c2fab 739 /** \brief Clear Pending Interrupt
<> 132:9baf128c2fab 740
<> 132:9baf128c2fab 741 The function clears the pending bit of an external interrupt.
<> 132:9baf128c2fab 742
<> 132:9baf128c2fab 743 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 744 */
<> 132:9baf128c2fab 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 746 {
<> 132:9baf128c2fab 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 748 }
<> 132:9baf128c2fab 749
<> 132:9baf128c2fab 750
<> 132:9baf128c2fab 751 /** \brief Set Interrupt Priority
<> 132:9baf128c2fab 752
<> 132:9baf128c2fab 753 The function sets the priority of an interrupt.
<> 132:9baf128c2fab 754
<> 132:9baf128c2fab 755 \note The priority cannot be set for every core interrupt.
<> 132:9baf128c2fab 756
<> 132:9baf128c2fab 757 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 758 \param [in] priority Priority to set.
<> 132:9baf128c2fab 759 */
<> 132:9baf128c2fab 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 132:9baf128c2fab 761 {
<> 132:9baf128c2fab 762 if((int32_t)(IRQn) < 0) {
<> 132:9baf128c2fab 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 132:9baf128c2fab 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 765 }
<> 132:9baf128c2fab 766 else {
<> 132:9baf128c2fab 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 132:9baf128c2fab 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 769 }
<> 132:9baf128c2fab 770 }
<> 132:9baf128c2fab 771
<> 132:9baf128c2fab 772
<> 132:9baf128c2fab 773 /** \brief Get Interrupt Priority
<> 132:9baf128c2fab 774
<> 132:9baf128c2fab 775 The function reads the priority of an interrupt. The interrupt
<> 132:9baf128c2fab 776 number can be positive to specify an external (device specific)
<> 132:9baf128c2fab 777 interrupt, or negative to specify an internal (core) interrupt.
<> 132:9baf128c2fab 778
<> 132:9baf128c2fab 779
<> 132:9baf128c2fab 780 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 781 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 132:9baf128c2fab 782 priority bits of the microcontroller.
<> 132:9baf128c2fab 783 */
<> 132:9baf128c2fab 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 132:9baf128c2fab 785 {
<> 132:9baf128c2fab 786
<> 132:9baf128c2fab 787 if((int32_t)(IRQn) < 0) {
<> 132:9baf128c2fab 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 789 }
<> 132:9baf128c2fab 790 else {
<> 132:9baf128c2fab 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 792 }
<> 132:9baf128c2fab 793 }
<> 132:9baf128c2fab 794
<> 132:9baf128c2fab 795
<> 132:9baf128c2fab 796 /** \brief System Reset
<> 132:9baf128c2fab 797
<> 132:9baf128c2fab 798 The function initiates a system reset request to reset the MCU.
<> 132:9baf128c2fab 799 */
<> 132:9baf128c2fab 800 __STATIC_INLINE void NVIC_SystemReset(void)
<> 132:9baf128c2fab 801 {
<> 132:9baf128c2fab 802 __DSB(); /* Ensure all outstanding memory accesses included
<> 132:9baf128c2fab 803 buffered write are completed before reset */
<> 132:9baf128c2fab 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 132:9baf128c2fab 805 SCB_AIRCR_SYSRESETREQ_Msk);
<> 132:9baf128c2fab 806 __DSB(); /* Ensure completion of memory access */
<> 132:9baf128c2fab 807 while(1) { __NOP(); } /* wait until reset */
<> 132:9baf128c2fab 808 }
<> 132:9baf128c2fab 809
<> 132:9baf128c2fab 810 /*@} end of CMSIS_Core_NVICFunctions */
<> 132:9baf128c2fab 811
<> 132:9baf128c2fab 812
<> 132:9baf128c2fab 813
<> 132:9baf128c2fab 814 /* ################################## SysTick function ############################################ */
<> 132:9baf128c2fab 815 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 132:9baf128c2fab 817 \brief Functions that configure the System.
<> 132:9baf128c2fab 818 @{
<> 132:9baf128c2fab 819 */
<> 132:9baf128c2fab 820
<> 132:9baf128c2fab 821 #if (__Vendor_SysTickConfig == 0)
<> 132:9baf128c2fab 822
<> 132:9baf128c2fab 823 /** \brief System Tick Configuration
<> 132:9baf128c2fab 824
<> 132:9baf128c2fab 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 132:9baf128c2fab 826 Counter is in free running mode to generate periodic interrupts.
<> 132:9baf128c2fab 827
<> 132:9baf128c2fab 828 \param [in] ticks Number of ticks between two interrupts.
<> 132:9baf128c2fab 829
<> 132:9baf128c2fab 830 \return 0 Function succeeded.
<> 132:9baf128c2fab 831 \return 1 Function failed.
<> 132:9baf128c2fab 832
<> 132:9baf128c2fab 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 132:9baf128c2fab 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 132:9baf128c2fab 835 must contain a vendor-specific implementation of this function.
<> 132:9baf128c2fab 836
<> 132:9baf128c2fab 837 */
<> 132:9baf128c2fab 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 132:9baf128c2fab 839 {
<> 132:9baf128c2fab 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 132:9baf128c2fab 841
<> 132:9baf128c2fab 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 132:9baf128c2fab 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 132:9baf128c2fab 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 132:9baf128c2fab 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 132:9baf128c2fab 846 SysTick_CTRL_TICKINT_Msk |
<> 132:9baf128c2fab 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 132:9baf128c2fab 848 return (0UL); /* Function successful */
<> 132:9baf128c2fab 849 }
<> 132:9baf128c2fab 850
<> 132:9baf128c2fab 851 #endif
<> 132:9baf128c2fab 852
<> 132:9baf128c2fab 853 /*@} end of CMSIS_Core_SysTickFunctions */
<> 132:9baf128c2fab 854
<> 132:9baf128c2fab 855
<> 132:9baf128c2fab 856
<> 132:9baf128c2fab 857
<> 132:9baf128c2fab 858 #ifdef __cplusplus
<> 132:9baf128c2fab 859 }
<> 132:9baf128c2fab 860 #endif
<> 132:9baf128c2fab 861
<> 132:9baf128c2fab 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 132:9baf128c2fab 863
<> 132:9baf128c2fab 864 #endif /* __CMSIS_GENERIC */