mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_THUNDERBOARD_SENSE/core_cm0.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
132:9baf128c2fab 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_cm0.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
<> 132:9baf128c2fab 4 * @version V4.10
<> 132:9baf128c2fab 5 * @date 18. March 2015
<> 132:9baf128c2fab 6 *
<> 132:9baf128c2fab 7 * @note
<> 132:9baf128c2fab 8 *
<> 132:9baf128c2fab 9 ******************************************************************************/
<> 132:9baf128c2fab 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 132:9baf128c2fab 11
<> 132:9baf128c2fab 12 All rights reserved.
<> 132:9baf128c2fab 13 Redistribution and use in source and binary forms, with or without
<> 132:9baf128c2fab 14 modification, are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 - Redistributions of source code must retain the above copyright
<> 132:9baf128c2fab 16 notice, this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 - Redistributions in binary form must reproduce the above copyright
<> 132:9baf128c2fab 18 notice, this list of conditions and the following disclaimer in the
<> 132:9baf128c2fab 19 documentation and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 - Neither the name of ARM nor the names of its contributors may be used
<> 132:9baf128c2fab 21 to endorse or promote products derived from this software without
<> 132:9baf128c2fab 22 specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 132:9baf128c2fab 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 132:9baf128c2fab 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 132:9baf128c2fab 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 132:9baf128c2fab 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 132:9baf128c2fab 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 132:9baf128c2fab 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 132:9baf128c2fab 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 132:9baf128c2fab 34 POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 35 ---------------------------------------------------------------------------*/
<> 132:9baf128c2fab 36
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 #if defined ( __ICCARM__ )
<> 132:9baf128c2fab 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 132:9baf128c2fab 40 #endif
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 #ifndef __CORE_CM0_H_GENERIC
<> 132:9baf128c2fab 43 #define __CORE_CM0_H_GENERIC
<> 132:9baf128c2fab 44
<> 132:9baf128c2fab 45 #ifdef __cplusplus
<> 132:9baf128c2fab 46 extern "C" {
<> 132:9baf128c2fab 47 #endif
<> 132:9baf128c2fab 48
<> 132:9baf128c2fab 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 132:9baf128c2fab 50 CMSIS violates the following MISRA-C:2004 rules:
<> 132:9baf128c2fab 51
<> 132:9baf128c2fab 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 132:9baf128c2fab 53 Function definitions in header files are used to allow 'inlining'.
<> 132:9baf128c2fab 54
<> 132:9baf128c2fab 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 132:9baf128c2fab 56 Unions are used for effective representation of core registers.
<> 132:9baf128c2fab 57
<> 132:9baf128c2fab 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 132:9baf128c2fab 59 Function-like macros are used to allow more efficient code.
<> 132:9baf128c2fab 60 */
<> 132:9baf128c2fab 61
<> 132:9baf128c2fab 62
<> 132:9baf128c2fab 63 /*******************************************************************************
<> 132:9baf128c2fab 64 * CMSIS definitions
<> 132:9baf128c2fab 65 ******************************************************************************/
<> 132:9baf128c2fab 66 /** \ingroup Cortex_M0
<> 132:9baf128c2fab 67 @{
<> 132:9baf128c2fab 68 */
<> 132:9baf128c2fab 69
<> 132:9baf128c2fab 70 /* CMSIS CM0 definitions */
<> 132:9baf128c2fab 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 132:9baf128c2fab 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 132:9baf128c2fab 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
<> 132:9baf128c2fab 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 132:9baf128c2fab 75
<> 132:9baf128c2fab 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 132:9baf128c2fab 77
<> 132:9baf128c2fab 78
<> 132:9baf128c2fab 79 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 132:9baf128c2fab 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 132:9baf128c2fab 82 #define __STATIC_INLINE static __inline
<> 132:9baf128c2fab 83
<> 132:9baf128c2fab 84 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 132:9baf128c2fab 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 132:9baf128c2fab 87 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 88
<> 132:9baf128c2fab 89 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 132:9baf128c2fab 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 132:9baf128c2fab 92 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 93
<> 132:9baf128c2fab 94 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 132:9baf128c2fab 96 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 97
<> 132:9baf128c2fab 98 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 132:9baf128c2fab 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 132:9baf128c2fab 101 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 102
<> 132:9baf128c2fab 103 #elif defined ( __CSMC__ )
<> 132:9baf128c2fab 104 #define __packed
<> 132:9baf128c2fab 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 132:9baf128c2fab 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 132:9baf128c2fab 107 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 108
<> 132:9baf128c2fab 109 #endif
<> 132:9baf128c2fab 110
<> 132:9baf128c2fab 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 132:9baf128c2fab 112 This core does not support an FPU at all
<> 132:9baf128c2fab 113 */
<> 132:9baf128c2fab 114 #define __FPU_USED 0
<> 132:9baf128c2fab 115
<> 132:9baf128c2fab 116 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 117 #if defined __TARGET_FPU_VFP
<> 132:9baf128c2fab 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 119 #endif
<> 132:9baf128c2fab 120
<> 132:9baf128c2fab 121 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 132:9baf128c2fab 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 124 #endif
<> 132:9baf128c2fab 125
<> 132:9baf128c2fab 126 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 127 #if defined __ARMVFP__
<> 132:9baf128c2fab 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 129 #endif
<> 132:9baf128c2fab 130
<> 132:9baf128c2fab 131 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 132 #if defined __TI__VFP_SUPPORT____
<> 132:9baf128c2fab 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 134 #endif
<> 132:9baf128c2fab 135
<> 132:9baf128c2fab 136 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 137 #if defined __FPU_VFP__
<> 132:9baf128c2fab 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 139 #endif
<> 132:9baf128c2fab 140
<> 132:9baf128c2fab 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 132:9baf128c2fab 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 132:9baf128c2fab 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 144 #endif
<> 132:9baf128c2fab 145 #endif
<> 132:9baf128c2fab 146
<> 132:9baf128c2fab 147 #include <stdint.h> /* standard types definitions */
<> 132:9baf128c2fab 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 132:9baf128c2fab 149 #include <core_cmFunc.h> /* Core Function Access */
<> 132:9baf128c2fab 150
<> 132:9baf128c2fab 151 #ifdef __cplusplus
<> 132:9baf128c2fab 152 }
<> 132:9baf128c2fab 153 #endif
<> 132:9baf128c2fab 154
<> 132:9baf128c2fab 155 #endif /* __CORE_CM0_H_GENERIC */
<> 132:9baf128c2fab 156
<> 132:9baf128c2fab 157 #ifndef __CMSIS_GENERIC
<> 132:9baf128c2fab 158
<> 132:9baf128c2fab 159 #ifndef __CORE_CM0_H_DEPENDANT
<> 132:9baf128c2fab 160 #define __CORE_CM0_H_DEPENDANT
<> 132:9baf128c2fab 161
<> 132:9baf128c2fab 162 #ifdef __cplusplus
<> 132:9baf128c2fab 163 extern "C" {
<> 132:9baf128c2fab 164 #endif
<> 132:9baf128c2fab 165
<> 132:9baf128c2fab 166 /* check device defines and use defaults */
<> 132:9baf128c2fab 167 #if defined __CHECK_DEVICE_DEFINES
<> 132:9baf128c2fab 168 #ifndef __CM0_REV
<> 132:9baf128c2fab 169 #define __CM0_REV 0x0000
<> 132:9baf128c2fab 170 #warning "__CM0_REV not defined in device header file; using default!"
<> 132:9baf128c2fab 171 #endif
<> 132:9baf128c2fab 172
<> 132:9baf128c2fab 173 #ifndef __NVIC_PRIO_BITS
<> 132:9baf128c2fab 174 #define __NVIC_PRIO_BITS 2
<> 132:9baf128c2fab 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 132:9baf128c2fab 176 #endif
<> 132:9baf128c2fab 177
<> 132:9baf128c2fab 178 #ifndef __Vendor_SysTickConfig
<> 132:9baf128c2fab 179 #define __Vendor_SysTickConfig 0
<> 132:9baf128c2fab 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 132:9baf128c2fab 181 #endif
<> 132:9baf128c2fab 182 #endif
<> 132:9baf128c2fab 183
<> 132:9baf128c2fab 184 /* IO definitions (access restrictions to peripheral registers) */
<> 132:9baf128c2fab 185 /**
<> 132:9baf128c2fab 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 132:9baf128c2fab 187
<> 132:9baf128c2fab 188 <strong>IO Type Qualifiers</strong> are used
<> 132:9baf128c2fab 189 \li to specify the access to peripheral variables.
<> 132:9baf128c2fab 190 \li for automatic generation of peripheral register debug information.
<> 132:9baf128c2fab 191 */
<> 132:9baf128c2fab 192 #ifdef __cplusplus
<> 132:9baf128c2fab 193 #define __I volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 194 #else
<> 132:9baf128c2fab 195 #define __I volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 196 #endif
<> 132:9baf128c2fab 197 #define __O volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 198 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 199
<> 132:9baf128c2fab 200 #ifdef __cplusplus
<> 132:9baf128c2fab 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 202 #else
<> 132:9baf128c2fab 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 204 #endif
<> 132:9baf128c2fab 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 207
<> 132:9baf128c2fab 208 /*@} end of group Cortex_M0 */
<> 132:9baf128c2fab 209
<> 132:9baf128c2fab 210
<> 132:9baf128c2fab 211
<> 132:9baf128c2fab 212 /*******************************************************************************
<> 132:9baf128c2fab 213 * Register Abstraction
<> 132:9baf128c2fab 214 Core Register contain:
<> 132:9baf128c2fab 215 - Core Register
<> 132:9baf128c2fab 216 - Core NVIC Register
<> 132:9baf128c2fab 217 - Core SCB Register
<> 132:9baf128c2fab 218 - Core SysTick Register
<> 132:9baf128c2fab 219 ******************************************************************************/
<> 132:9baf128c2fab 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 132:9baf128c2fab 221 \brief Type definitions and defines for Cortex-M processor based devices.
<> 132:9baf128c2fab 222 */
<> 132:9baf128c2fab 223
<> 132:9baf128c2fab 224 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 225 \defgroup CMSIS_CORE Status and Control Registers
<> 132:9baf128c2fab 226 \brief Core Register type definitions.
<> 132:9baf128c2fab 227 @{
<> 132:9baf128c2fab 228 */
<> 132:9baf128c2fab 229
<> 132:9baf128c2fab 230 /** \brief Union type to access the Application Program Status Register (APSR).
<> 132:9baf128c2fab 231 */
<> 132:9baf128c2fab 232 typedef union
<> 132:9baf128c2fab 233 {
<> 132:9baf128c2fab 234 struct
<> 132:9baf128c2fab 235 {
<> 132:9baf128c2fab 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 132:9baf128c2fab 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 241 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 242 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 243 } APSR_Type;
<> 132:9baf128c2fab 244
<> 132:9baf128c2fab 245 /* APSR Register Definitions */
<> 132:9baf128c2fab 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 132:9baf128c2fab 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 132:9baf128c2fab 248
<> 132:9baf128c2fab 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 132:9baf128c2fab 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 132:9baf128c2fab 251
<> 132:9baf128c2fab 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 132:9baf128c2fab 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 132:9baf128c2fab 254
<> 132:9baf128c2fab 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 132:9baf128c2fab 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 132:9baf128c2fab 257
<> 132:9baf128c2fab 258
<> 132:9baf128c2fab 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 132:9baf128c2fab 260 */
<> 132:9baf128c2fab 261 typedef union
<> 132:9baf128c2fab 262 {
<> 132:9baf128c2fab 263 struct
<> 132:9baf128c2fab 264 {
<> 132:9baf128c2fab 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 132:9baf128c2fab 267 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 268 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 269 } IPSR_Type;
<> 132:9baf128c2fab 270
<> 132:9baf128c2fab 271 /* IPSR Register Definitions */
<> 132:9baf128c2fab 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 132:9baf128c2fab 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 132:9baf128c2fab 274
<> 132:9baf128c2fab 275
<> 132:9baf128c2fab 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 132:9baf128c2fab 277 */
<> 132:9baf128c2fab 278 typedef union
<> 132:9baf128c2fab 279 {
<> 132:9baf128c2fab 280 struct
<> 132:9baf128c2fab 281 {
<> 132:9baf128c2fab 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 132:9baf128c2fab 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 132:9baf128c2fab 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 132:9baf128c2fab 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 132:9baf128c2fab 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 290 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 291 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 292 } xPSR_Type;
<> 132:9baf128c2fab 293
<> 132:9baf128c2fab 294 /* xPSR Register Definitions */
<> 132:9baf128c2fab 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 132:9baf128c2fab 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 132:9baf128c2fab 297
<> 132:9baf128c2fab 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 132:9baf128c2fab 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 132:9baf128c2fab 300
<> 132:9baf128c2fab 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 132:9baf128c2fab 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 132:9baf128c2fab 303
<> 132:9baf128c2fab 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 132:9baf128c2fab 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 132:9baf128c2fab 306
<> 132:9baf128c2fab 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 132:9baf128c2fab 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 132:9baf128c2fab 309
<> 132:9baf128c2fab 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 132:9baf128c2fab 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 132:9baf128c2fab 312
<> 132:9baf128c2fab 313
<> 132:9baf128c2fab 314 /** \brief Union type to access the Control Registers (CONTROL).
<> 132:9baf128c2fab 315 */
<> 132:9baf128c2fab 316 typedef union
<> 132:9baf128c2fab 317 {
<> 132:9baf128c2fab 318 struct
<> 132:9baf128c2fab 319 {
<> 132:9baf128c2fab 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
<> 132:9baf128c2fab 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 132:9baf128c2fab 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 132:9baf128c2fab 323 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 324 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 325 } CONTROL_Type;
<> 132:9baf128c2fab 326
<> 132:9baf128c2fab 327 /* CONTROL Register Definitions */
<> 132:9baf128c2fab 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 132:9baf128c2fab 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 132:9baf128c2fab 330
<> 132:9baf128c2fab 331 /*@} end of group CMSIS_CORE */
<> 132:9baf128c2fab 332
<> 132:9baf128c2fab 333
<> 132:9baf128c2fab 334 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 132:9baf128c2fab 336 \brief Type definitions for the NVIC Registers
<> 132:9baf128c2fab 337 @{
<> 132:9baf128c2fab 338 */
<> 132:9baf128c2fab 339
<> 132:9baf128c2fab 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 132:9baf128c2fab 341 */
<> 132:9baf128c2fab 342 typedef struct
<> 132:9baf128c2fab 343 {
<> 132:9baf128c2fab 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 132:9baf128c2fab 345 uint32_t RESERVED0[31];
<> 132:9baf128c2fab 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 132:9baf128c2fab 347 uint32_t RSERVED1[31];
<> 132:9baf128c2fab 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 132:9baf128c2fab 349 uint32_t RESERVED2[31];
<> 132:9baf128c2fab 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 132:9baf128c2fab 351 uint32_t RESERVED3[31];
<> 132:9baf128c2fab 352 uint32_t RESERVED4[64];
<> 132:9baf128c2fab 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 132:9baf128c2fab 354 } NVIC_Type;
<> 132:9baf128c2fab 355
<> 132:9baf128c2fab 356 /*@} end of group CMSIS_NVIC */
<> 132:9baf128c2fab 357
<> 132:9baf128c2fab 358
<> 132:9baf128c2fab 359 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 360 \defgroup CMSIS_SCB System Control Block (SCB)
<> 132:9baf128c2fab 361 \brief Type definitions for the System Control Block Registers
<> 132:9baf128c2fab 362 @{
<> 132:9baf128c2fab 363 */
<> 132:9baf128c2fab 364
<> 132:9baf128c2fab 365 /** \brief Structure type to access the System Control Block (SCB).
<> 132:9baf128c2fab 366 */
<> 132:9baf128c2fab 367 typedef struct
<> 132:9baf128c2fab 368 {
<> 132:9baf128c2fab 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 132:9baf128c2fab 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 132:9baf128c2fab 371 uint32_t RESERVED0;
<> 132:9baf128c2fab 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 132:9baf128c2fab 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 132:9baf128c2fab 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 132:9baf128c2fab 375 uint32_t RESERVED1;
<> 132:9baf128c2fab 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 132:9baf128c2fab 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 132:9baf128c2fab 378 } SCB_Type;
<> 132:9baf128c2fab 379
<> 132:9baf128c2fab 380 /* SCB CPUID Register Definitions */
<> 132:9baf128c2fab 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 132:9baf128c2fab 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 132:9baf128c2fab 383
<> 132:9baf128c2fab 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 132:9baf128c2fab 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 132:9baf128c2fab 386
<> 132:9baf128c2fab 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 132:9baf128c2fab 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 132:9baf128c2fab 389
<> 132:9baf128c2fab 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 132:9baf128c2fab 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 132:9baf128c2fab 392
<> 132:9baf128c2fab 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 132:9baf128c2fab 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 132:9baf128c2fab 395
<> 132:9baf128c2fab 396 /* SCB Interrupt Control State Register Definitions */
<> 132:9baf128c2fab 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 132:9baf128c2fab 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 132:9baf128c2fab 399
<> 132:9baf128c2fab 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 132:9baf128c2fab 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 132:9baf128c2fab 402
<> 132:9baf128c2fab 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 132:9baf128c2fab 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 132:9baf128c2fab 405
<> 132:9baf128c2fab 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 132:9baf128c2fab 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 132:9baf128c2fab 408
<> 132:9baf128c2fab 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 132:9baf128c2fab 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 132:9baf128c2fab 411
<> 132:9baf128c2fab 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 132:9baf128c2fab 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 132:9baf128c2fab 414
<> 132:9baf128c2fab 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 132:9baf128c2fab 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 132:9baf128c2fab 417
<> 132:9baf128c2fab 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 132:9baf128c2fab 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 132:9baf128c2fab 420
<> 132:9baf128c2fab 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 132:9baf128c2fab 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 132:9baf128c2fab 423
<> 132:9baf128c2fab 424 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 132:9baf128c2fab 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 132:9baf128c2fab 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 132:9baf128c2fab 427
<> 132:9baf128c2fab 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 132:9baf128c2fab 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 132:9baf128c2fab 430
<> 132:9baf128c2fab 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 132:9baf128c2fab 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 132:9baf128c2fab 433
<> 132:9baf128c2fab 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 132:9baf128c2fab 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 132:9baf128c2fab 436
<> 132:9baf128c2fab 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 132:9baf128c2fab 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 132:9baf128c2fab 439
<> 132:9baf128c2fab 440 /* SCB System Control Register Definitions */
<> 132:9baf128c2fab 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 132:9baf128c2fab 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 132:9baf128c2fab 443
<> 132:9baf128c2fab 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 132:9baf128c2fab 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 132:9baf128c2fab 446
<> 132:9baf128c2fab 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 132:9baf128c2fab 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 132:9baf128c2fab 449
<> 132:9baf128c2fab 450 /* SCB Configuration Control Register Definitions */
<> 132:9baf128c2fab 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 132:9baf128c2fab 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 132:9baf128c2fab 453
<> 132:9baf128c2fab 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 132:9baf128c2fab 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 132:9baf128c2fab 456
<> 132:9baf128c2fab 457 /* SCB System Handler Control and State Register Definitions */
<> 132:9baf128c2fab 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 132:9baf128c2fab 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 132:9baf128c2fab 460
<> 132:9baf128c2fab 461 /*@} end of group CMSIS_SCB */
<> 132:9baf128c2fab 462
<> 132:9baf128c2fab 463
<> 132:9baf128c2fab 464 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 132:9baf128c2fab 466 \brief Type definitions for the System Timer Registers.
<> 132:9baf128c2fab 467 @{
<> 132:9baf128c2fab 468 */
<> 132:9baf128c2fab 469
<> 132:9baf128c2fab 470 /** \brief Structure type to access the System Timer (SysTick).
<> 132:9baf128c2fab 471 */
<> 132:9baf128c2fab 472 typedef struct
<> 132:9baf128c2fab 473 {
<> 132:9baf128c2fab 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 132:9baf128c2fab 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 132:9baf128c2fab 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 132:9baf128c2fab 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 132:9baf128c2fab 478 } SysTick_Type;
<> 132:9baf128c2fab 479
<> 132:9baf128c2fab 480 /* SysTick Control / Status Register Definitions */
<> 132:9baf128c2fab 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 132:9baf128c2fab 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 132:9baf128c2fab 483
<> 132:9baf128c2fab 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 132:9baf128c2fab 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 132:9baf128c2fab 486
<> 132:9baf128c2fab 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 132:9baf128c2fab 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 132:9baf128c2fab 489
<> 132:9baf128c2fab 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 132:9baf128c2fab 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 132:9baf128c2fab 492
<> 132:9baf128c2fab 493 /* SysTick Reload Register Definitions */
<> 132:9baf128c2fab 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 132:9baf128c2fab 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 132:9baf128c2fab 496
<> 132:9baf128c2fab 497 /* SysTick Current Register Definitions */
<> 132:9baf128c2fab 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 132:9baf128c2fab 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 132:9baf128c2fab 500
<> 132:9baf128c2fab 501 /* SysTick Calibration Register Definitions */
<> 132:9baf128c2fab 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 132:9baf128c2fab 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 132:9baf128c2fab 504
<> 132:9baf128c2fab 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 132:9baf128c2fab 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 132:9baf128c2fab 507
<> 132:9baf128c2fab 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 132:9baf128c2fab 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 132:9baf128c2fab 510
<> 132:9baf128c2fab 511 /*@} end of group CMSIS_SysTick */
<> 132:9baf128c2fab 512
<> 132:9baf128c2fab 513
<> 132:9baf128c2fab 514 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 132:9baf128c2fab 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 132:9baf128c2fab 517 are only accessible over DAP and not via processor. Therefore
<> 132:9baf128c2fab 518 they are not covered by the Cortex-M0 header file.
<> 132:9baf128c2fab 519 @{
<> 132:9baf128c2fab 520 */
<> 132:9baf128c2fab 521 /*@} end of group CMSIS_CoreDebug */
<> 132:9baf128c2fab 522
<> 132:9baf128c2fab 523
<> 132:9baf128c2fab 524 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 525 \defgroup CMSIS_core_base Core Definitions
<> 132:9baf128c2fab 526 \brief Definitions for base addresses, unions, and structures.
<> 132:9baf128c2fab 527 @{
<> 132:9baf128c2fab 528 */
<> 132:9baf128c2fab 529
<> 132:9baf128c2fab 530 /* Memory mapping of Cortex-M0 Hardware */
<> 132:9baf128c2fab 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 132:9baf128c2fab 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 132:9baf128c2fab 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 132:9baf128c2fab 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 132:9baf128c2fab 535
<> 132:9baf128c2fab 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 132:9baf128c2fab 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 132:9baf128c2fab 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 132:9baf128c2fab 539
<> 132:9baf128c2fab 540
<> 132:9baf128c2fab 541 /*@} */
<> 132:9baf128c2fab 542
<> 132:9baf128c2fab 543
<> 132:9baf128c2fab 544
<> 132:9baf128c2fab 545 /*******************************************************************************
<> 132:9baf128c2fab 546 * Hardware Abstraction Layer
<> 132:9baf128c2fab 547 Core Function Interface contains:
<> 132:9baf128c2fab 548 - Core NVIC Functions
<> 132:9baf128c2fab 549 - Core SysTick Functions
<> 132:9baf128c2fab 550 - Core Register Access Functions
<> 132:9baf128c2fab 551 ******************************************************************************/
<> 132:9baf128c2fab 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 132:9baf128c2fab 553 */
<> 132:9baf128c2fab 554
<> 132:9baf128c2fab 555
<> 132:9baf128c2fab 556
<> 132:9baf128c2fab 557 /* ########################## NVIC functions #################################### */
<> 132:9baf128c2fab 558 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 132:9baf128c2fab 560 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 132:9baf128c2fab 561 @{
<> 132:9baf128c2fab 562 */
<> 132:9baf128c2fab 563
<> 132:9baf128c2fab 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 132:9baf128c2fab 565 /* The following MACROS handle generation of the register offset and byte masks */
<> 132:9baf128c2fab 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 132:9baf128c2fab 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 132:9baf128c2fab 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 132:9baf128c2fab 569
<> 132:9baf128c2fab 570
<> 132:9baf128c2fab 571 /** \brief Enable External Interrupt
<> 132:9baf128c2fab 572
<> 132:9baf128c2fab 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 574
<> 132:9baf128c2fab 575 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 576 */
<> 132:9baf128c2fab 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 578 {
<> 132:9baf128c2fab 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 580 }
<> 132:9baf128c2fab 581
<> 132:9baf128c2fab 582
<> 132:9baf128c2fab 583 /** \brief Disable External Interrupt
<> 132:9baf128c2fab 584
<> 132:9baf128c2fab 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 132:9baf128c2fab 586
<> 132:9baf128c2fab 587 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 588 */
<> 132:9baf128c2fab 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 590 {
<> 132:9baf128c2fab 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 592 __DSB();
<> 132:9baf128c2fab 593 __ISB();
<> 132:9baf128c2fab 594 }
<> 132:9baf128c2fab 595
<> 132:9baf128c2fab 596
<> 132:9baf128c2fab 597 /** \brief Get Pending Interrupt
<> 132:9baf128c2fab 598
<> 132:9baf128c2fab 599 The function reads the pending register in the NVIC and returns the pending bit
<> 132:9baf128c2fab 600 for the specified interrupt.
<> 132:9baf128c2fab 601
<> 132:9baf128c2fab 602 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 603
<> 132:9baf128c2fab 604 \return 0 Interrupt status is not pending.
<> 132:9baf128c2fab 605 \return 1 Interrupt status is pending.
<> 132:9baf128c2fab 606 */
<> 132:9baf128c2fab 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 608 {
<> 132:9baf128c2fab 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 132:9baf128c2fab 610 }
<> 132:9baf128c2fab 611
<> 132:9baf128c2fab 612
<> 132:9baf128c2fab 613 /** \brief Set Pending Interrupt
<> 132:9baf128c2fab 614
<> 132:9baf128c2fab 615 The function sets the pending bit of an external interrupt.
<> 132:9baf128c2fab 616
<> 132:9baf128c2fab 617 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 618 */
<> 132:9baf128c2fab 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 620 {
<> 132:9baf128c2fab 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 622 }
<> 132:9baf128c2fab 623
<> 132:9baf128c2fab 624
<> 132:9baf128c2fab 625 /** \brief Clear Pending Interrupt
<> 132:9baf128c2fab 626
<> 132:9baf128c2fab 627 The function clears the pending bit of an external interrupt.
<> 132:9baf128c2fab 628
<> 132:9baf128c2fab 629 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 132:9baf128c2fab 630 */
<> 132:9baf128c2fab 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 632 {
<> 132:9baf128c2fab 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 634 }
<> 132:9baf128c2fab 635
<> 132:9baf128c2fab 636
<> 132:9baf128c2fab 637 /** \brief Set Interrupt Priority
<> 132:9baf128c2fab 638
<> 132:9baf128c2fab 639 The function sets the priority of an interrupt.
<> 132:9baf128c2fab 640
<> 132:9baf128c2fab 641 \note The priority cannot be set for every core interrupt.
<> 132:9baf128c2fab 642
<> 132:9baf128c2fab 643 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 644 \param [in] priority Priority to set.
<> 132:9baf128c2fab 645 */
<> 132:9baf128c2fab 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 132:9baf128c2fab 647 {
<> 132:9baf128c2fab 648 if((int32_t)(IRQn) < 0) {
<> 132:9baf128c2fab 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 132:9baf128c2fab 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 651 }
<> 132:9baf128c2fab 652 else {
<> 132:9baf128c2fab 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 132:9baf128c2fab 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 655 }
<> 132:9baf128c2fab 656 }
<> 132:9baf128c2fab 657
<> 132:9baf128c2fab 658
<> 132:9baf128c2fab 659 /** \brief Get Interrupt Priority
<> 132:9baf128c2fab 660
<> 132:9baf128c2fab 661 The function reads the priority of an interrupt. The interrupt
<> 132:9baf128c2fab 662 number can be positive to specify an external (device specific)
<> 132:9baf128c2fab 663 interrupt, or negative to specify an internal (core) interrupt.
<> 132:9baf128c2fab 664
<> 132:9baf128c2fab 665
<> 132:9baf128c2fab 666 \param [in] IRQn Interrupt number.
<> 132:9baf128c2fab 667 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 132:9baf128c2fab 668 priority bits of the microcontroller.
<> 132:9baf128c2fab 669 */
<> 132:9baf128c2fab 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 132:9baf128c2fab 671 {
<> 132:9baf128c2fab 672
<> 132:9baf128c2fab 673 if((int32_t)(IRQn) < 0) {
<> 132:9baf128c2fab 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 675 }
<> 132:9baf128c2fab 676 else {
<> 132:9baf128c2fab 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 132:9baf128c2fab 678 }
<> 132:9baf128c2fab 679 }
<> 132:9baf128c2fab 680
<> 132:9baf128c2fab 681
<> 132:9baf128c2fab 682 /** \brief System Reset
<> 132:9baf128c2fab 683
<> 132:9baf128c2fab 684 The function initiates a system reset request to reset the MCU.
<> 132:9baf128c2fab 685 */
<> 132:9baf128c2fab 686 __STATIC_INLINE void NVIC_SystemReset(void)
<> 132:9baf128c2fab 687 {
<> 132:9baf128c2fab 688 __DSB(); /* Ensure all outstanding memory accesses included
<> 132:9baf128c2fab 689 buffered write are completed before reset */
<> 132:9baf128c2fab 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 132:9baf128c2fab 691 SCB_AIRCR_SYSRESETREQ_Msk);
<> 132:9baf128c2fab 692 __DSB(); /* Ensure completion of memory access */
<> 132:9baf128c2fab 693 while(1) { __NOP(); } /* wait until reset */
<> 132:9baf128c2fab 694 }
<> 132:9baf128c2fab 695
<> 132:9baf128c2fab 696 /*@} end of CMSIS_Core_NVICFunctions */
<> 132:9baf128c2fab 697
<> 132:9baf128c2fab 698
<> 132:9baf128c2fab 699
<> 132:9baf128c2fab 700 /* ################################## SysTick function ############################################ */
<> 132:9baf128c2fab 701 /** \ingroup CMSIS_Core_FunctionInterface
<> 132:9baf128c2fab 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 132:9baf128c2fab 703 \brief Functions that configure the System.
<> 132:9baf128c2fab 704 @{
<> 132:9baf128c2fab 705 */
<> 132:9baf128c2fab 706
<> 132:9baf128c2fab 707 #if (__Vendor_SysTickConfig == 0)
<> 132:9baf128c2fab 708
<> 132:9baf128c2fab 709 /** \brief System Tick Configuration
<> 132:9baf128c2fab 710
<> 132:9baf128c2fab 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 132:9baf128c2fab 712 Counter is in free running mode to generate periodic interrupts.
<> 132:9baf128c2fab 713
<> 132:9baf128c2fab 714 \param [in] ticks Number of ticks between two interrupts.
<> 132:9baf128c2fab 715
<> 132:9baf128c2fab 716 \return 0 Function succeeded.
<> 132:9baf128c2fab 717 \return 1 Function failed.
<> 132:9baf128c2fab 718
<> 132:9baf128c2fab 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 132:9baf128c2fab 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 132:9baf128c2fab 721 must contain a vendor-specific implementation of this function.
<> 132:9baf128c2fab 722
<> 132:9baf128c2fab 723 */
<> 132:9baf128c2fab 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 132:9baf128c2fab 725 {
<> 132:9baf128c2fab 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 132:9baf128c2fab 727
<> 132:9baf128c2fab 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 132:9baf128c2fab 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 132:9baf128c2fab 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 132:9baf128c2fab 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 132:9baf128c2fab 732 SysTick_CTRL_TICKINT_Msk |
<> 132:9baf128c2fab 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 132:9baf128c2fab 734 return (0UL); /* Function successful */
<> 132:9baf128c2fab 735 }
<> 132:9baf128c2fab 736
<> 132:9baf128c2fab 737 #endif
<> 132:9baf128c2fab 738
<> 132:9baf128c2fab 739 /*@} end of CMSIS_Core_SysTickFunctions */
<> 132:9baf128c2fab 740
<> 132:9baf128c2fab 741
<> 132:9baf128c2fab 742
<> 132:9baf128c2fab 743
<> 132:9baf128c2fab 744 #ifdef __cplusplus
<> 132:9baf128c2fab 745 }
<> 132:9baf128c2fab 746 #endif
<> 132:9baf128c2fab 747
<> 132:9baf128c2fab 748 #endif /* __CORE_CM0_H_DEPENDANT */
<> 132:9baf128c2fab 749
<> 132:9baf128c2fab 750 #endif /* __CMSIS_GENERIC */