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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_THUNDERBOARD_SENSE/core_ca9.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
132:9baf128c2fab 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_ca9.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 132:9baf128c2fab 4 * @version
<> 132:9baf128c2fab 5 * @date 25 March 2013
<> 132:9baf128c2fab 6 *
<> 132:9baf128c2fab 7 * @note
<> 132:9baf128c2fab 8 *
<> 132:9baf128c2fab 9 ******************************************************************************/
<> 132:9baf128c2fab 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 132:9baf128c2fab 11
<> 132:9baf128c2fab 12 All rights reserved.
<> 132:9baf128c2fab 13 Redistribution and use in source and binary forms, with or without
<> 132:9baf128c2fab 14 modification, are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 - Redistributions of source code must retain the above copyright
<> 132:9baf128c2fab 16 notice, this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 - Redistributions in binary form must reproduce the above copyright
<> 132:9baf128c2fab 18 notice, this list of conditions and the following disclaimer in the
<> 132:9baf128c2fab 19 documentation and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 - Neither the name of ARM nor the names of its contributors may be used
<> 132:9baf128c2fab 21 to endorse or promote products derived from this software without
<> 132:9baf128c2fab 22 specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 132:9baf128c2fab 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 132:9baf128c2fab 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 132:9baf128c2fab 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 132:9baf128c2fab 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 132:9baf128c2fab 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 132:9baf128c2fab 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 132:9baf128c2fab 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 132:9baf128c2fab 34 POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 35 ---------------------------------------------------------------------------*/
<> 132:9baf128c2fab 36
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 #if defined ( __ICCARM__ )
<> 132:9baf128c2fab 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 132:9baf128c2fab 40 #endif
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 #ifdef __cplusplus
<> 132:9baf128c2fab 43 extern "C" {
<> 132:9baf128c2fab 44 #endif
<> 132:9baf128c2fab 45
<> 132:9baf128c2fab 46 #ifndef __CORE_CA9_H_GENERIC
<> 132:9baf128c2fab 47 #define __CORE_CA9_H_GENERIC
<> 132:9baf128c2fab 48
<> 132:9baf128c2fab 49
<> 132:9baf128c2fab 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 132:9baf128c2fab 51 CMSIS violates the following MISRA-C:2004 rules:
<> 132:9baf128c2fab 52
<> 132:9baf128c2fab 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 132:9baf128c2fab 54 Function definitions in header files are used to allow 'inlining'.
<> 132:9baf128c2fab 55
<> 132:9baf128c2fab 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 132:9baf128c2fab 57 Unions are used for effective representation of core registers.
<> 132:9baf128c2fab 58
<> 132:9baf128c2fab 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 132:9baf128c2fab 60 Function-like macros are used to allow more efficient code.
<> 132:9baf128c2fab 61 */
<> 132:9baf128c2fab 62
<> 132:9baf128c2fab 63
<> 132:9baf128c2fab 64 /*******************************************************************************
<> 132:9baf128c2fab 65 * CMSIS definitions
<> 132:9baf128c2fab 66 ******************************************************************************/
<> 132:9baf128c2fab 67 /** \ingroup Cortex_A9
<> 132:9baf128c2fab 68 @{
<> 132:9baf128c2fab 69 */
<> 132:9baf128c2fab 70
<> 132:9baf128c2fab 71 /* CMSIS CA9 definitions */
<> 132:9baf128c2fab 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 132:9baf128c2fab 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 132:9baf128c2fab 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 132:9baf128c2fab 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 132:9baf128c2fab 76
<> 132:9baf128c2fab 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 132:9baf128c2fab 78
<> 132:9baf128c2fab 79
<> 132:9baf128c2fab 80 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 132:9baf128c2fab 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 132:9baf128c2fab 83 #define __STATIC_INLINE static __inline
<> 132:9baf128c2fab 84 #define __STATIC_ASM static __asm
<> 132:9baf128c2fab 85
<> 132:9baf128c2fab 86 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 132:9baf128c2fab 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 132:9baf128c2fab 89 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 90 #define __STATIC_ASM static __asm
<> 132:9baf128c2fab 91
<> 132:9baf128c2fab 92 #include <stdint.h>
<> 132:9baf128c2fab 93 inline uint32_t __get_PSR(void) {
<> 132:9baf128c2fab 94 __ASM("mrs r0, cpsr");
<> 132:9baf128c2fab 95 }
<> 132:9baf128c2fab 96
<> 132:9baf128c2fab 97 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 132:9baf128c2fab 99 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 100 #define __STATIC_ASM static __asm
<> 132:9baf128c2fab 101
<> 132:9baf128c2fab 102 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 132:9baf128c2fab 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 132:9baf128c2fab 105 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 106 #define __STATIC_ASM static __asm
<> 132:9baf128c2fab 107
<> 132:9baf128c2fab 108 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 132:9baf128c2fab 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 132:9baf128c2fab 111 #define __STATIC_INLINE static inline
<> 132:9baf128c2fab 112 #define __STATIC_ASM static __asm
<> 132:9baf128c2fab 113
<> 132:9baf128c2fab 114 #endif
<> 132:9baf128c2fab 115
<> 132:9baf128c2fab 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 132:9baf128c2fab 117 */
<> 132:9baf128c2fab 118 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 119 #if defined __TARGET_FPU_VFP
<> 132:9baf128c2fab 120 #if (__FPU_PRESENT == 1)
<> 132:9baf128c2fab 121 #define __FPU_USED 1
<> 132:9baf128c2fab 122 #else
<> 132:9baf128c2fab 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 124 #define __FPU_USED 0
<> 132:9baf128c2fab 125 #endif
<> 132:9baf128c2fab 126 #else
<> 132:9baf128c2fab 127 #define __FPU_USED 0
<> 132:9baf128c2fab 128 #endif
<> 132:9baf128c2fab 129
<> 132:9baf128c2fab 130 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 131 #if defined __ARMVFP__
<> 132:9baf128c2fab 132 #if (__FPU_PRESENT == 1)
<> 132:9baf128c2fab 133 #define __FPU_USED 1
<> 132:9baf128c2fab 134 #else
<> 132:9baf128c2fab 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 136 #define __FPU_USED 0
<> 132:9baf128c2fab 137 #endif
<> 132:9baf128c2fab 138 #else
<> 132:9baf128c2fab 139 #define __FPU_USED 0
<> 132:9baf128c2fab 140 #endif
<> 132:9baf128c2fab 141
<> 132:9baf128c2fab 142 #elif defined ( __TMS470__ )
<> 132:9baf128c2fab 143 #if defined __TI_VFP_SUPPORT__
<> 132:9baf128c2fab 144 #if (__FPU_PRESENT == 1)
<> 132:9baf128c2fab 145 #define __FPU_USED 1
<> 132:9baf128c2fab 146 #else
<> 132:9baf128c2fab 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 148 #define __FPU_USED 0
<> 132:9baf128c2fab 149 #endif
<> 132:9baf128c2fab 150 #else
<> 132:9baf128c2fab 151 #define __FPU_USED 0
<> 132:9baf128c2fab 152 #endif
<> 132:9baf128c2fab 153
<> 132:9baf128c2fab 154 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 132:9baf128c2fab 156 #if (__FPU_PRESENT == 1)
<> 132:9baf128c2fab 157 #define __FPU_USED 1
<> 132:9baf128c2fab 158 #else
<> 132:9baf128c2fab 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 160 #define __FPU_USED 0
<> 132:9baf128c2fab 161 #endif
<> 132:9baf128c2fab 162 #else
<> 132:9baf128c2fab 163 #define __FPU_USED 0
<> 132:9baf128c2fab 164 #endif
<> 132:9baf128c2fab 165
<> 132:9baf128c2fab 166 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 167 #if defined __FPU_VFP__
<> 132:9baf128c2fab 168 #if (__FPU_PRESENT == 1)
<> 132:9baf128c2fab 169 #define __FPU_USED 1
<> 132:9baf128c2fab 170 #else
<> 132:9baf128c2fab 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 172 #define __FPU_USED 0
<> 132:9baf128c2fab 173 #endif
<> 132:9baf128c2fab 174 #else
<> 132:9baf128c2fab 175 #define __FPU_USED 0
<> 132:9baf128c2fab 176 #endif
<> 132:9baf128c2fab 177 #endif
<> 132:9baf128c2fab 178
<> 132:9baf128c2fab 179 #include <stdint.h> /*!< standard types definitions */
<> 132:9baf128c2fab 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 132:9baf128c2fab 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 132:9baf128c2fab 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 132:9baf128c2fab 183
<> 132:9baf128c2fab 184 #endif /* __CORE_CA9_H_GENERIC */
<> 132:9baf128c2fab 185
<> 132:9baf128c2fab 186 #ifndef __CMSIS_GENERIC
<> 132:9baf128c2fab 187
<> 132:9baf128c2fab 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 132:9baf128c2fab 189 #define __CORE_CA9_H_DEPENDANT
<> 132:9baf128c2fab 190
<> 132:9baf128c2fab 191 /* check device defines and use defaults */
<> 132:9baf128c2fab 192 #if defined __CHECK_DEVICE_DEFINES
<> 132:9baf128c2fab 193 #ifndef __CA9_REV
<> 132:9baf128c2fab 194 #define __CA9_REV 0x0000
<> 132:9baf128c2fab 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 132:9baf128c2fab 196 #endif
<> 132:9baf128c2fab 197
<> 132:9baf128c2fab 198 #ifndef __FPU_PRESENT
<> 132:9baf128c2fab 199 #define __FPU_PRESENT 1
<> 132:9baf128c2fab 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 132:9baf128c2fab 201 #endif
<> 132:9baf128c2fab 202
<> 132:9baf128c2fab 203 #ifndef __Vendor_SysTickConfig
<> 132:9baf128c2fab 204 #define __Vendor_SysTickConfig 1
<> 132:9baf128c2fab 205 #endif
<> 132:9baf128c2fab 206
<> 132:9baf128c2fab 207 #if __Vendor_SysTickConfig == 0
<> 132:9baf128c2fab 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 132:9baf128c2fab 209 #endif
<> 132:9baf128c2fab 210 #endif
<> 132:9baf128c2fab 211
<> 132:9baf128c2fab 212 /* IO definitions (access restrictions to peripheral registers) */
<> 132:9baf128c2fab 213 /**
<> 132:9baf128c2fab 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 132:9baf128c2fab 215
<> 132:9baf128c2fab 216 <strong>IO Type Qualifiers</strong> are used
<> 132:9baf128c2fab 217 \li to specify the access to peripheral variables.
<> 132:9baf128c2fab 218 \li for automatic generation of peripheral register debug information.
<> 132:9baf128c2fab 219 */
<> 132:9baf128c2fab 220 #ifdef __cplusplus
<> 132:9baf128c2fab 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 222 #else
<> 132:9baf128c2fab 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 224 #endif
<> 132:9baf128c2fab 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 132:9baf128c2fab 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 227
<> 132:9baf128c2fab 228 /*@} end of group Cortex_A9 */
<> 132:9baf128c2fab 229
<> 132:9baf128c2fab 230
<> 132:9baf128c2fab 231 /*******************************************************************************
<> 132:9baf128c2fab 232 * Register Abstraction
<> 132:9baf128c2fab 233 ******************************************************************************/
<> 132:9baf128c2fab 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 132:9baf128c2fab 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 132:9baf128c2fab 236 */
<> 132:9baf128c2fab 237
<> 132:9baf128c2fab 238 /** \ingroup CMSIS_core_register
<> 132:9baf128c2fab 239 \defgroup CMSIS_CORE Status and Control Registers
<> 132:9baf128c2fab 240 \brief Core Register type definitions.
<> 132:9baf128c2fab 241 @{
<> 132:9baf128c2fab 242 */
<> 132:9baf128c2fab 243
<> 132:9baf128c2fab 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 132:9baf128c2fab 245 */
<> 132:9baf128c2fab 246 typedef union
<> 132:9baf128c2fab 247 {
<> 132:9baf128c2fab 248 struct
<> 132:9baf128c2fab 249 {
<> 132:9baf128c2fab 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 132:9baf128c2fab 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 132:9baf128c2fab 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 132:9baf128c2fab 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 132:9baf128c2fab 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 132:9baf128c2fab 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 132:9baf128c2fab 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 132:9baf128c2fab 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 132:9baf128c2fab 258 } b; /*!< Structure used for bit access */
<> 132:9baf128c2fab 259 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 260 } APSR_Type;
<> 132:9baf128c2fab 261
<> 132:9baf128c2fab 262
<> 132:9baf128c2fab 263 /*@} end of group CMSIS_CORE */
<> 132:9baf128c2fab 264
<> 132:9baf128c2fab 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 132:9baf128c2fab 266
<> 132:9baf128c2fab 267
<> 132:9baf128c2fab 268 #endif /* __CORE_CA9_H_GENERIC */
<> 132:9baf128c2fab 269
<> 132:9baf128c2fab 270 #endif /* __CMSIS_GENERIC */
<> 132:9baf128c2fab 271
<> 132:9baf128c2fab 272 #ifdef __cplusplus
<> 132:9baf128c2fab 273 }
<> 132:9baf128c2fab 274
<> 132:9baf128c2fab 275
<> 132:9baf128c2fab 276 #endif