mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/core_cm3.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_cm3.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #if defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 92:4fc01daae5a5 40 #endif
bogdanm 92:4fc01daae5a5 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 92:4fc01daae5a5 45 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 46 extern "C" {
bogdanm 92:4fc01daae5a5 47 #endif
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 92:4fc01daae5a5 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 92:4fc01daae5a5 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 92:4fc01daae5a5 56 Unions are used for effective representation of core registers.
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 92:4fc01daae5a5 59 Function-like macros are used to allow more efficient code.
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 /*******************************************************************************
bogdanm 92:4fc01daae5a5 64 * CMSIS definitions
bogdanm 92:4fc01daae5a5 65 ******************************************************************************/
bogdanm 92:4fc01daae5a5 66 /** \ingroup Cortex_M3
bogdanm 92:4fc01daae5a5 67 @{
bogdanm 92:4fc01daae5a5 68 */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 /* CMSIS CM3 definitions */
Kojto 110:165afa46840b 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 92:4fc01daae5a5 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
bogdanm 92:4fc01daae5a5 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 82 #define __STATIC_INLINE static __inline
bogdanm 92:4fc01daae5a5 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 92:4fc01daae5a5 89 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 92:4fc01daae5a5 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 92:4fc01daae5a5 92 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 #elif defined ( __TMS470__ )
bogdanm 92:4fc01daae5a5 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 92:4fc01daae5a5 96 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 101 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 92:4fc01daae5a5 109 #endif
bogdanm 92:4fc01daae5a5 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 92:4fc01daae5a5 113 */
bogdanm 92:4fc01daae5a5 114 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 117 #if defined __TARGET_FPU_VFP
bogdanm 92:4fc01daae5a5 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 119 #endif
bogdanm 92:4fc01daae5a5 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 92:4fc01daae5a5 126 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 127 #if defined __ARMVFP__
bogdanm 92:4fc01daae5a5 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 129 #endif
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 #elif defined ( __TMS470__ )
bogdanm 92:4fc01daae5a5 132 #if defined __TI__VFP_SUPPORT____
bogdanm 92:4fc01daae5a5 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 134 #endif
bogdanm 92:4fc01daae5a5 135
Kojto 110:165afa46840b 136 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 137 #if defined __FPU_VFP__
Kojto 110:165afa46840b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 139 #endif
bogdanm 92:4fc01daae5a5 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
bogdanm 92:4fc01daae5a5 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 144 #endif
bogdanm 92:4fc01daae5a5 145 #endif
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 #include <stdint.h> /* standard types definitions */
bogdanm 92:4fc01daae5a5 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 92:4fc01daae5a5 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 92:4fc01daae5a5 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 92:4fc01daae5a5 155 #endif /* __CORE_CM3_H_GENERIC */
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 #ifndef __CMSIS_GENERIC
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 #ifndef __CORE_CM3_H_DEPENDANT
bogdanm 92:4fc01daae5a5 160 #define __CORE_CM3_H_DEPENDANT
bogdanm 92:4fc01daae5a5 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 92:4fc01daae5a5 166 /* check device defines and use defaults */
bogdanm 92:4fc01daae5a5 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 92:4fc01daae5a5 168 #ifndef __CM3_REV
bogdanm 92:4fc01daae5a5 169 #define __CM3_REV 0x0200
bogdanm 92:4fc01daae5a5 170 #warning "__CM3_REV not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 171 #endif
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 #ifndef __MPU_PRESENT
bogdanm 92:4fc01daae5a5 174 #define __MPU_PRESENT 0
bogdanm 92:4fc01daae5a5 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 176 #endif
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 #ifndef __NVIC_PRIO_BITS
bogdanm 92:4fc01daae5a5 179 #define __NVIC_PRIO_BITS 4
bogdanm 92:4fc01daae5a5 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 181 #endif
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 #ifndef __Vendor_SysTickConfig
bogdanm 92:4fc01daae5a5 184 #define __Vendor_SysTickConfig 0
bogdanm 92:4fc01daae5a5 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 186 #endif
bogdanm 92:4fc01daae5a5 187 #endif
bogdanm 92:4fc01daae5a5 188
bogdanm 92:4fc01daae5a5 189 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 92:4fc01daae5a5 190 /**
bogdanm 92:4fc01daae5a5 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 92:4fc01daae5a5 192
bogdanm 92:4fc01daae5a5 193 <strong>IO Type Qualifiers</strong> are used
bogdanm 92:4fc01daae5a5 194 \li to specify the access to peripheral variables.
bogdanm 92:4fc01daae5a5 195 \li for automatic generation of peripheral register debug information.
bogdanm 92:4fc01daae5a5 196 */
bogdanm 92:4fc01daae5a5 197 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 198 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 199 #else
bogdanm 92:4fc01daae5a5 200 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 201 #endif
bogdanm 92:4fc01daae5a5 202 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 92:4fc01daae5a5 203 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 92:4fc01daae5a5 204
<> 128:9bcdf88f62b0 205 #ifdef __cplusplus
<> 128:9bcdf88f62b0 206 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 207 #else
<> 128:9bcdf88f62b0 208 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 209 #endif
<> 128:9bcdf88f62b0 210 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 212
bogdanm 92:4fc01daae5a5 213 /*@} end of group Cortex_M3 */
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216
bogdanm 92:4fc01daae5a5 217 /*******************************************************************************
bogdanm 92:4fc01daae5a5 218 * Register Abstraction
bogdanm 92:4fc01daae5a5 219 Core Register contain:
bogdanm 92:4fc01daae5a5 220 - Core Register
bogdanm 92:4fc01daae5a5 221 - Core NVIC Register
bogdanm 92:4fc01daae5a5 222 - Core SCB Register
bogdanm 92:4fc01daae5a5 223 - Core SysTick Register
bogdanm 92:4fc01daae5a5 224 - Core Debug Register
bogdanm 92:4fc01daae5a5 225 - Core MPU Register
bogdanm 92:4fc01daae5a5 226 ******************************************************************************/
bogdanm 92:4fc01daae5a5 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 92:4fc01daae5a5 228 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 92:4fc01daae5a5 229 */
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 232 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 92:4fc01daae5a5 233 \brief Core Register type definitions.
bogdanm 92:4fc01daae5a5 234 @{
bogdanm 92:4fc01daae5a5 235 */
bogdanm 92:4fc01daae5a5 236
bogdanm 92:4fc01daae5a5 237 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 92:4fc01daae5a5 238 */
bogdanm 92:4fc01daae5a5 239 typedef union
bogdanm 92:4fc01daae5a5 240 {
bogdanm 92:4fc01daae5a5 241 struct
bogdanm 92:4fc01daae5a5 242 {
bogdanm 92:4fc01daae5a5 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 92:4fc01daae5a5 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 92:4fc01daae5a5 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 249 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 250 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 251 } APSR_Type;
bogdanm 92:4fc01daae5a5 252
Kojto 110:165afa46840b 253 /* APSR Register Definitions */
Kojto 110:165afa46840b 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 256
Kojto 110:165afa46840b 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 110:165afa46840b 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 110:165afa46840b 268
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 92:4fc01daae5a5 271 */
bogdanm 92:4fc01daae5a5 272 typedef union
bogdanm 92:4fc01daae5a5 273 {
bogdanm 92:4fc01daae5a5 274 struct
bogdanm 92:4fc01daae5a5 275 {
bogdanm 92:4fc01daae5a5 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 92:4fc01daae5a5 278 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 279 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 280 } IPSR_Type;
bogdanm 92:4fc01daae5a5 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
bogdanm 92:4fc01daae5a5 286
bogdanm 92:4fc01daae5a5 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 typedef union
bogdanm 92:4fc01daae5a5 290 {
bogdanm 92:4fc01daae5a5 291 struct
bogdanm 92:4fc01daae5a5 292 {
bogdanm 92:4fc01daae5a5 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 92:4fc01daae5a5 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 92:4fc01daae5a5 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 92:4fc01daae5a5 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 92:4fc01daae5a5 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 302 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 303 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 304 } xPSR_Type;
bogdanm 92:4fc01daae5a5 305
Kojto 110:165afa46840b 306 /* xPSR Register Definitions */
Kojto 110:165afa46840b 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 315
Kojto 110:165afa46840b 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 318
Kojto 110:165afa46840b 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 110:165afa46840b 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 110:165afa46840b 321
Kojto 110:165afa46840b 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 110:165afa46840b 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 110:165afa46840b 324
Kojto 110:165afa46840b 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 327
Kojto 110:165afa46840b 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 330
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 92:4fc01daae5a5 333 */
bogdanm 92:4fc01daae5a5 334 typedef union
bogdanm 92:4fc01daae5a5 335 {
bogdanm 92:4fc01daae5a5 336 struct
bogdanm 92:4fc01daae5a5 337 {
bogdanm 92:4fc01daae5a5 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 92:4fc01daae5a5 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 92:4fc01daae5a5 341 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 342 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 343 } CONTROL_Type;
bogdanm 92:4fc01daae5a5 344
Kojto 110:165afa46840b 345 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 348
Kojto 110:165afa46840b 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 351
bogdanm 92:4fc01daae5a5 352 /*@} end of group CMSIS_CORE */
bogdanm 92:4fc01daae5a5 353
bogdanm 92:4fc01daae5a5 354
bogdanm 92:4fc01daae5a5 355 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 92:4fc01daae5a5 357 \brief Type definitions for the NVIC Registers
bogdanm 92:4fc01daae5a5 358 @{
bogdanm 92:4fc01daae5a5 359 */
bogdanm 92:4fc01daae5a5 360
bogdanm 92:4fc01daae5a5 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 92:4fc01daae5a5 362 */
bogdanm 92:4fc01daae5a5 363 typedef struct
bogdanm 92:4fc01daae5a5 364 {
bogdanm 92:4fc01daae5a5 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 92:4fc01daae5a5 366 uint32_t RESERVED0[24];
bogdanm 92:4fc01daae5a5 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 92:4fc01daae5a5 368 uint32_t RSERVED1[24];
bogdanm 92:4fc01daae5a5 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 92:4fc01daae5a5 370 uint32_t RESERVED2[24];
bogdanm 92:4fc01daae5a5 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 92:4fc01daae5a5 372 uint32_t RESERVED3[24];
bogdanm 92:4fc01daae5a5 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 92:4fc01daae5a5 374 uint32_t RESERVED4[56];
bogdanm 92:4fc01daae5a5 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 92:4fc01daae5a5 376 uint32_t RESERVED5[644];
bogdanm 92:4fc01daae5a5 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 92:4fc01daae5a5 378 } NVIC_Type;
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 /* Software Triggered Interrupt Register Definitions */
bogdanm 92:4fc01daae5a5 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 110:165afa46840b 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
bogdanm 92:4fc01daae5a5 383
bogdanm 92:4fc01daae5a5 384 /*@} end of group CMSIS_NVIC */
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386
bogdanm 92:4fc01daae5a5 387 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 388 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 92:4fc01daae5a5 389 \brief Type definitions for the System Control Block Registers
bogdanm 92:4fc01daae5a5 390 @{
bogdanm 92:4fc01daae5a5 391 */
bogdanm 92:4fc01daae5a5 392
bogdanm 92:4fc01daae5a5 393 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 92:4fc01daae5a5 394 */
bogdanm 92:4fc01daae5a5 395 typedef struct
bogdanm 92:4fc01daae5a5 396 {
bogdanm 92:4fc01daae5a5 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 92:4fc01daae5a5 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 92:4fc01daae5a5 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 92:4fc01daae5a5 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 92:4fc01daae5a5 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 92:4fc01daae5a5 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 92:4fc01daae5a5 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 92:4fc01daae5a5 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 92:4fc01daae5a5 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 92:4fc01daae5a5 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 92:4fc01daae5a5 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 92:4fc01daae5a5 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 92:4fc01daae5a5 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 92:4fc01daae5a5 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 92:4fc01daae5a5 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 92:4fc01daae5a5 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 92:4fc01daae5a5 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 92:4fc01daae5a5 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 92:4fc01daae5a5 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 92:4fc01daae5a5 416 uint32_t RESERVED0[5];
bogdanm 92:4fc01daae5a5 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 92:4fc01daae5a5 418 } SCB_Type;
bogdanm 92:4fc01daae5a5 419
bogdanm 92:4fc01daae5a5 420 /* SCB CPUID Register Definitions */
bogdanm 92:4fc01daae5a5 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 92:4fc01daae5a5 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 92:4fc01daae5a5 423
bogdanm 92:4fc01daae5a5 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 92:4fc01daae5a5 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 92:4fc01daae5a5 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 92:4fc01daae5a5 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 92:4fc01daae5a5 432
bogdanm 92:4fc01daae5a5 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436 /* SCB Interrupt Control State Register Definitions */
bogdanm 92:4fc01daae5a5 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 92:4fc01daae5a5 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 92:4fc01daae5a5 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 92:4fc01daae5a5 442
bogdanm 92:4fc01daae5a5 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 92:4fc01daae5a5 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 92:4fc01daae5a5 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 92:4fc01daae5a5 448
bogdanm 92:4fc01daae5a5 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 92:4fc01daae5a5 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 92:4fc01daae5a5 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 92:4fc01daae5a5 454
bogdanm 92:4fc01daae5a5 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 92:4fc01daae5a5 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 92:4fc01daae5a5 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 92:4fc01daae5a5 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 /* SCB Vector Table Offset Register Definitions */
bogdanm 92:4fc01daae5a5 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
bogdanm 92:4fc01daae5a5 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
bogdanm 92:4fc01daae5a5 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
bogdanm 92:4fc01daae5a5 471
bogdanm 92:4fc01daae5a5 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 92:4fc01daae5a5 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 92:4fc01daae5a5 474 #else
bogdanm 92:4fc01daae5a5 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 92:4fc01daae5a5 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 92:4fc01daae5a5 477 #endif
bogdanm 92:4fc01daae5a5 478
bogdanm 92:4fc01daae5a5 479 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 92:4fc01daae5a5 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 92:4fc01daae5a5 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 92:4fc01daae5a5 482
bogdanm 92:4fc01daae5a5 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 92:4fc01daae5a5 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 92:4fc01daae5a5 485
bogdanm 92:4fc01daae5a5 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 92:4fc01daae5a5 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 92:4fc01daae5a5 488
bogdanm 92:4fc01daae5a5 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 92:4fc01daae5a5 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 92:4fc01daae5a5 491
bogdanm 92:4fc01daae5a5 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 92:4fc01daae5a5 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 92:4fc01daae5a5 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 92:4fc01daae5a5 497
bogdanm 92:4fc01daae5a5 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 110:165afa46840b 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 92:4fc01daae5a5 500
bogdanm 92:4fc01daae5a5 501 /* SCB System Control Register Definitions */
bogdanm 92:4fc01daae5a5 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 92:4fc01daae5a5 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 92:4fc01daae5a5 504
bogdanm 92:4fc01daae5a5 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 92:4fc01daae5a5 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 92:4fc01daae5a5 507
bogdanm 92:4fc01daae5a5 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 92:4fc01daae5a5 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 92:4fc01daae5a5 510
bogdanm 92:4fc01daae5a5 511 /* SCB Configuration Control Register Definitions */
bogdanm 92:4fc01daae5a5 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 92:4fc01daae5a5 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 92:4fc01daae5a5 514
bogdanm 92:4fc01daae5a5 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 92:4fc01daae5a5 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 92:4fc01daae5a5 517
bogdanm 92:4fc01daae5a5 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 92:4fc01daae5a5 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 92:4fc01daae5a5 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 92:4fc01daae5a5 523
bogdanm 92:4fc01daae5a5 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 92:4fc01daae5a5 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 92:4fc01daae5a5 526
bogdanm 92:4fc01daae5a5 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 110:165afa46840b 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 92:4fc01daae5a5 529
bogdanm 92:4fc01daae5a5 530 /* SCB System Handler Control and State Register Definitions */
bogdanm 92:4fc01daae5a5 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 92:4fc01daae5a5 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 92:4fc01daae5a5 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 92:4fc01daae5a5 536
bogdanm 92:4fc01daae5a5 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 92:4fc01daae5a5 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 92:4fc01daae5a5 539
bogdanm 92:4fc01daae5a5 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 92:4fc01daae5a5 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 92:4fc01daae5a5 542
bogdanm 92:4fc01daae5a5 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 92:4fc01daae5a5 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 92:4fc01daae5a5 545
bogdanm 92:4fc01daae5a5 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 92:4fc01daae5a5 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 92:4fc01daae5a5 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 92:4fc01daae5a5 551
bogdanm 92:4fc01daae5a5 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 92:4fc01daae5a5 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 92:4fc01daae5a5 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 92:4fc01daae5a5 557
bogdanm 92:4fc01daae5a5 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 92:4fc01daae5a5 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 92:4fc01daae5a5 560
bogdanm 92:4fc01daae5a5 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 92:4fc01daae5a5 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 92:4fc01daae5a5 563
bogdanm 92:4fc01daae5a5 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 92:4fc01daae5a5 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 92:4fc01daae5a5 566
bogdanm 92:4fc01daae5a5 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 92:4fc01daae5a5 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 92:4fc01daae5a5 569
bogdanm 92:4fc01daae5a5 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 110:165afa46840b 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 92:4fc01daae5a5 572
bogdanm 92:4fc01daae5a5 573 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 92:4fc01daae5a5 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 92:4fc01daae5a5 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 92:4fc01daae5a5 576
bogdanm 92:4fc01daae5a5 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 92:4fc01daae5a5 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 92:4fc01daae5a5 579
bogdanm 92:4fc01daae5a5 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 110:165afa46840b 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 92:4fc01daae5a5 582
bogdanm 92:4fc01daae5a5 583 /* SCB Hard Fault Status Registers Definitions */
bogdanm 92:4fc01daae5a5 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 92:4fc01daae5a5 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 92:4fc01daae5a5 586
bogdanm 92:4fc01daae5a5 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 92:4fc01daae5a5 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 92:4fc01daae5a5 589
bogdanm 92:4fc01daae5a5 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 92:4fc01daae5a5 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 /* SCB Debug Fault Status Register Definitions */
bogdanm 92:4fc01daae5a5 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 92:4fc01daae5a5 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 92:4fc01daae5a5 596
bogdanm 92:4fc01daae5a5 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 92:4fc01daae5a5 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 92:4fc01daae5a5 599
bogdanm 92:4fc01daae5a5 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 92:4fc01daae5a5 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 92:4fc01daae5a5 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 92:4fc01daae5a5 605
bogdanm 92:4fc01daae5a5 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 110:165afa46840b 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
bogdanm 92:4fc01daae5a5 608
bogdanm 92:4fc01daae5a5 609 /*@} end of group CMSIS_SCB */
bogdanm 92:4fc01daae5a5 610
bogdanm 92:4fc01daae5a5 611
bogdanm 92:4fc01daae5a5 612 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 92:4fc01daae5a5 614 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 92:4fc01daae5a5 615 @{
bogdanm 92:4fc01daae5a5 616 */
bogdanm 92:4fc01daae5a5 617
bogdanm 92:4fc01daae5a5 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 92:4fc01daae5a5 619 */
bogdanm 92:4fc01daae5a5 620 typedef struct
bogdanm 92:4fc01daae5a5 621 {
bogdanm 92:4fc01daae5a5 622 uint32_t RESERVED0[1];
bogdanm 92:4fc01daae5a5 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 92:4fc01daae5a5 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
bogdanm 92:4fc01daae5a5 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 92:4fc01daae5a5 626 #else
bogdanm 92:4fc01daae5a5 627 uint32_t RESERVED1[1];
bogdanm 92:4fc01daae5a5 628 #endif
bogdanm 92:4fc01daae5a5 629 } SCnSCB_Type;
bogdanm 92:4fc01daae5a5 630
bogdanm 92:4fc01daae5a5 631 /* Interrupt Controller Type Register Definitions */
bogdanm 92:4fc01daae5a5 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 110:165afa46840b 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 /* Auxiliary Control Register Definitions */
bogdanm 92:4fc01daae5a5 636
bogdanm 92:4fc01daae5a5 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 92:4fc01daae5a5 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 92:4fc01daae5a5 639
bogdanm 92:4fc01daae5a5 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 92:4fc01daae5a5 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 110:165afa46840b 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 92:4fc01daae5a5 645
bogdanm 92:4fc01daae5a5 646 /*@} end of group CMSIS_SCnotSCB */
bogdanm 92:4fc01daae5a5 647
bogdanm 92:4fc01daae5a5 648
bogdanm 92:4fc01daae5a5 649 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 92:4fc01daae5a5 651 \brief Type definitions for the System Timer Registers.
bogdanm 92:4fc01daae5a5 652 @{
bogdanm 92:4fc01daae5a5 653 */
bogdanm 92:4fc01daae5a5 654
bogdanm 92:4fc01daae5a5 655 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 92:4fc01daae5a5 656 */
bogdanm 92:4fc01daae5a5 657 typedef struct
bogdanm 92:4fc01daae5a5 658 {
bogdanm 92:4fc01daae5a5 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 92:4fc01daae5a5 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 92:4fc01daae5a5 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 92:4fc01daae5a5 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 92:4fc01daae5a5 663 } SysTick_Type;
bogdanm 92:4fc01daae5a5 664
bogdanm 92:4fc01daae5a5 665 /* SysTick Control / Status Register Definitions */
bogdanm 92:4fc01daae5a5 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 92:4fc01daae5a5 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 92:4fc01daae5a5 668
bogdanm 92:4fc01daae5a5 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 92:4fc01daae5a5 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 92:4fc01daae5a5 671
bogdanm 92:4fc01daae5a5 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 92:4fc01daae5a5 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 92:4fc01daae5a5 674
bogdanm 92:4fc01daae5a5 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678 /* SysTick Reload Register Definitions */
bogdanm 92:4fc01daae5a5 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 92:4fc01daae5a5 681
bogdanm 92:4fc01daae5a5 682 /* SysTick Current Register Definitions */
bogdanm 92:4fc01daae5a5 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 /* SysTick Calibration Register Definitions */
bogdanm 92:4fc01daae5a5 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 92:4fc01daae5a5 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 92:4fc01daae5a5 689
bogdanm 92:4fc01daae5a5 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 92:4fc01daae5a5 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 92:4fc01daae5a5 692
bogdanm 92:4fc01daae5a5 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 92:4fc01daae5a5 695
bogdanm 92:4fc01daae5a5 696 /*@} end of group CMSIS_SysTick */
bogdanm 92:4fc01daae5a5 697
bogdanm 92:4fc01daae5a5 698
bogdanm 92:4fc01daae5a5 699 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 92:4fc01daae5a5 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 92:4fc01daae5a5 702 @{
bogdanm 92:4fc01daae5a5 703 */
bogdanm 92:4fc01daae5a5 704
bogdanm 92:4fc01daae5a5 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 92:4fc01daae5a5 706 */
bogdanm 92:4fc01daae5a5 707 typedef struct
bogdanm 92:4fc01daae5a5 708 {
bogdanm 92:4fc01daae5a5 709 __O union
bogdanm 92:4fc01daae5a5 710 {
bogdanm 92:4fc01daae5a5 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 92:4fc01daae5a5 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 92:4fc01daae5a5 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 92:4fc01daae5a5 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 92:4fc01daae5a5 715 uint32_t RESERVED0[864];
bogdanm 92:4fc01daae5a5 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 92:4fc01daae5a5 717 uint32_t RESERVED1[15];
bogdanm 92:4fc01daae5a5 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 92:4fc01daae5a5 719 uint32_t RESERVED2[15];
bogdanm 92:4fc01daae5a5 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 92:4fc01daae5a5 721 uint32_t RESERVED3[29];
bogdanm 92:4fc01daae5a5 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 92:4fc01daae5a5 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 92:4fc01daae5a5 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 92:4fc01daae5a5 725 uint32_t RESERVED4[43];
bogdanm 92:4fc01daae5a5 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 92:4fc01daae5a5 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 92:4fc01daae5a5 728 uint32_t RESERVED5[6];
bogdanm 92:4fc01daae5a5 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 92:4fc01daae5a5 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 92:4fc01daae5a5 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 92:4fc01daae5a5 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 92:4fc01daae5a5 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 92:4fc01daae5a5 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 92:4fc01daae5a5 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 92:4fc01daae5a5 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 92:4fc01daae5a5 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 92:4fc01daae5a5 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 92:4fc01daae5a5 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 92:4fc01daae5a5 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 92:4fc01daae5a5 741 } ITM_Type;
bogdanm 92:4fc01daae5a5 742
bogdanm 92:4fc01daae5a5 743 /* ITM Trace Privilege Register Definitions */
bogdanm 92:4fc01daae5a5 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 110:165afa46840b 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 92:4fc01daae5a5 746
bogdanm 92:4fc01daae5a5 747 /* ITM Trace Control Register Definitions */
bogdanm 92:4fc01daae5a5 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 92:4fc01daae5a5 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 92:4fc01daae5a5 750
bogdanm 92:4fc01daae5a5 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 92:4fc01daae5a5 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 92:4fc01daae5a5 753
bogdanm 92:4fc01daae5a5 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 92:4fc01daae5a5 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 92:4fc01daae5a5 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 92:4fc01daae5a5 759
bogdanm 92:4fc01daae5a5 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 92:4fc01daae5a5 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 92:4fc01daae5a5 762
bogdanm 92:4fc01daae5a5 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 92:4fc01daae5a5 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 92:4fc01daae5a5 765
bogdanm 92:4fc01daae5a5 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 92:4fc01daae5a5 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 92:4fc01daae5a5 768
bogdanm 92:4fc01daae5a5 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 92:4fc01daae5a5 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 92:4fc01daae5a5 771
bogdanm 92:4fc01daae5a5 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 110:165afa46840b 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 92:4fc01daae5a5 774
bogdanm 92:4fc01daae5a5 775 /* ITM Integration Write Register Definitions */
bogdanm 92:4fc01daae5a5 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 110:165afa46840b 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 92:4fc01daae5a5 778
bogdanm 92:4fc01daae5a5 779 /* ITM Integration Read Register Definitions */
bogdanm 92:4fc01daae5a5 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 110:165afa46840b 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783 /* ITM Integration Mode Control Register Definitions */
bogdanm 92:4fc01daae5a5 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 110:165afa46840b 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787 /* ITM Lock Status Register Definitions */
bogdanm 92:4fc01daae5a5 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 92:4fc01daae5a5 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 92:4fc01daae5a5 790
bogdanm 92:4fc01daae5a5 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 92:4fc01daae5a5 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 92:4fc01daae5a5 793
bogdanm 92:4fc01daae5a5 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 110:165afa46840b 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
bogdanm 92:4fc01daae5a5 796
bogdanm 92:4fc01daae5a5 797 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 92:4fc01daae5a5 798
bogdanm 92:4fc01daae5a5 799
bogdanm 92:4fc01daae5a5 800 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 92:4fc01daae5a5 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 92:4fc01daae5a5 803 @{
bogdanm 92:4fc01daae5a5 804 */
bogdanm 92:4fc01daae5a5 805
bogdanm 92:4fc01daae5a5 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 92:4fc01daae5a5 807 */
bogdanm 92:4fc01daae5a5 808 typedef struct
bogdanm 92:4fc01daae5a5 809 {
bogdanm 92:4fc01daae5a5 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 92:4fc01daae5a5 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 92:4fc01daae5a5 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 92:4fc01daae5a5 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 92:4fc01daae5a5 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 92:4fc01daae5a5 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 92:4fc01daae5a5 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 92:4fc01daae5a5 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 92:4fc01daae5a5 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 92:4fc01daae5a5 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 92:4fc01daae5a5 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 92:4fc01daae5a5 821 uint32_t RESERVED0[1];
bogdanm 92:4fc01daae5a5 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 92:4fc01daae5a5 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 92:4fc01daae5a5 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 92:4fc01daae5a5 825 uint32_t RESERVED1[1];
bogdanm 92:4fc01daae5a5 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 92:4fc01daae5a5 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 92:4fc01daae5a5 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 92:4fc01daae5a5 829 uint32_t RESERVED2[1];
bogdanm 92:4fc01daae5a5 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 92:4fc01daae5a5 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 92:4fc01daae5a5 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 92:4fc01daae5a5 833 } DWT_Type;
bogdanm 92:4fc01daae5a5 834
bogdanm 92:4fc01daae5a5 835 /* DWT Control Register Definitions */
bogdanm 92:4fc01daae5a5 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 92:4fc01daae5a5 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 92:4fc01daae5a5 838
bogdanm 92:4fc01daae5a5 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 92:4fc01daae5a5 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 92:4fc01daae5a5 841
bogdanm 92:4fc01daae5a5 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 92:4fc01daae5a5 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 92:4fc01daae5a5 844
bogdanm 92:4fc01daae5a5 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 92:4fc01daae5a5 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 92:4fc01daae5a5 847
bogdanm 92:4fc01daae5a5 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 92:4fc01daae5a5 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 92:4fc01daae5a5 850
bogdanm 92:4fc01daae5a5 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 92:4fc01daae5a5 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 92:4fc01daae5a5 853
bogdanm 92:4fc01daae5a5 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 92:4fc01daae5a5 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 92:4fc01daae5a5 856
bogdanm 92:4fc01daae5a5 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 92:4fc01daae5a5 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 92:4fc01daae5a5 859
bogdanm 92:4fc01daae5a5 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 92:4fc01daae5a5 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 92:4fc01daae5a5 862
bogdanm 92:4fc01daae5a5 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 92:4fc01daae5a5 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 92:4fc01daae5a5 865
bogdanm 92:4fc01daae5a5 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 92:4fc01daae5a5 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 92:4fc01daae5a5 868
bogdanm 92:4fc01daae5a5 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 92:4fc01daae5a5 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 92:4fc01daae5a5 871
bogdanm 92:4fc01daae5a5 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 92:4fc01daae5a5 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 92:4fc01daae5a5 874
bogdanm 92:4fc01daae5a5 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 92:4fc01daae5a5 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 92:4fc01daae5a5 877
bogdanm 92:4fc01daae5a5 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 92:4fc01daae5a5 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 92:4fc01daae5a5 880
bogdanm 92:4fc01daae5a5 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 92:4fc01daae5a5 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 92:4fc01daae5a5 883
bogdanm 92:4fc01daae5a5 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 92:4fc01daae5a5 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 92:4fc01daae5a5 886
bogdanm 92:4fc01daae5a5 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 110:165afa46840b 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 92:4fc01daae5a5 889
bogdanm 92:4fc01daae5a5 890 /* DWT CPI Count Register Definitions */
bogdanm 92:4fc01daae5a5 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 110:165afa46840b 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 92:4fc01daae5a5 893
bogdanm 92:4fc01daae5a5 894 /* DWT Exception Overhead Count Register Definitions */
bogdanm 92:4fc01daae5a5 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 110:165afa46840b 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898 /* DWT Sleep Count Register Definitions */
bogdanm 92:4fc01daae5a5 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 110:165afa46840b 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 92:4fc01daae5a5 901
bogdanm 92:4fc01daae5a5 902 /* DWT LSU Count Register Definitions */
bogdanm 92:4fc01daae5a5 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 110:165afa46840b 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 92:4fc01daae5a5 905
bogdanm 92:4fc01daae5a5 906 /* DWT Folded-instruction Count Register Definitions */
bogdanm 92:4fc01daae5a5 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 110:165afa46840b 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 92:4fc01daae5a5 909
bogdanm 92:4fc01daae5a5 910 /* DWT Comparator Mask Register Definitions */
bogdanm 92:4fc01daae5a5 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 110:165afa46840b 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
bogdanm 92:4fc01daae5a5 913
bogdanm 92:4fc01daae5a5 914 /* DWT Comparator Function Register Definitions */
bogdanm 92:4fc01daae5a5 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 92:4fc01daae5a5 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 92:4fc01daae5a5 917
bogdanm 92:4fc01daae5a5 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 92:4fc01daae5a5 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 92:4fc01daae5a5 920
bogdanm 92:4fc01daae5a5 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 92:4fc01daae5a5 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 92:4fc01daae5a5 923
bogdanm 92:4fc01daae5a5 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 92:4fc01daae5a5 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 92:4fc01daae5a5 926
bogdanm 92:4fc01daae5a5 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 92:4fc01daae5a5 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 92:4fc01daae5a5 929
bogdanm 92:4fc01daae5a5 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 92:4fc01daae5a5 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 92:4fc01daae5a5 932
bogdanm 92:4fc01daae5a5 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 92:4fc01daae5a5 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 92:4fc01daae5a5 935
bogdanm 92:4fc01daae5a5 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 92:4fc01daae5a5 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 92:4fc01daae5a5 938
bogdanm 92:4fc01daae5a5 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 110:165afa46840b 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 92:4fc01daae5a5 941
bogdanm 92:4fc01daae5a5 942 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 92:4fc01daae5a5 943
bogdanm 92:4fc01daae5a5 944
bogdanm 92:4fc01daae5a5 945 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 92:4fc01daae5a5 947 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 92:4fc01daae5a5 948 @{
bogdanm 92:4fc01daae5a5 949 */
bogdanm 92:4fc01daae5a5 950
bogdanm 92:4fc01daae5a5 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 92:4fc01daae5a5 952 */
bogdanm 92:4fc01daae5a5 953 typedef struct
bogdanm 92:4fc01daae5a5 954 {
bogdanm 92:4fc01daae5a5 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 92:4fc01daae5a5 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 92:4fc01daae5a5 957 uint32_t RESERVED0[2];
bogdanm 92:4fc01daae5a5 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 92:4fc01daae5a5 959 uint32_t RESERVED1[55];
bogdanm 92:4fc01daae5a5 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 92:4fc01daae5a5 961 uint32_t RESERVED2[131];
bogdanm 92:4fc01daae5a5 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 92:4fc01daae5a5 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 92:4fc01daae5a5 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 92:4fc01daae5a5 965 uint32_t RESERVED3[759];
bogdanm 92:4fc01daae5a5 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 92:4fc01daae5a5 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 92:4fc01daae5a5 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 92:4fc01daae5a5 969 uint32_t RESERVED4[1];
bogdanm 92:4fc01daae5a5 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 92:4fc01daae5a5 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 92:4fc01daae5a5 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 92:4fc01daae5a5 973 uint32_t RESERVED5[39];
bogdanm 92:4fc01daae5a5 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 92:4fc01daae5a5 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 92:4fc01daae5a5 976 uint32_t RESERVED7[8];
bogdanm 92:4fc01daae5a5 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 92:4fc01daae5a5 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 92:4fc01daae5a5 979 } TPI_Type;
bogdanm 92:4fc01daae5a5 980
bogdanm 92:4fc01daae5a5 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 92:4fc01daae5a5 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 110:165afa46840b 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 92:4fc01daae5a5 984
bogdanm 92:4fc01daae5a5 985 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 92:4fc01daae5a5 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 110:165afa46840b 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
bogdanm 92:4fc01daae5a5 988
bogdanm 92:4fc01daae5a5 989 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 92:4fc01daae5a5 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 92:4fc01daae5a5 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 92:4fc01daae5a5 992
bogdanm 92:4fc01daae5a5 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 92:4fc01daae5a5 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 92:4fc01daae5a5 995
bogdanm 92:4fc01daae5a5 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 92:4fc01daae5a5 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 92:4fc01daae5a5 998
bogdanm 92:4fc01daae5a5 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 110:165afa46840b 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
bogdanm 92:4fc01daae5a5 1001
bogdanm 92:4fc01daae5a5 1002 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 92:4fc01daae5a5 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 92:4fc01daae5a5 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 92:4fc01daae5a5 1005
bogdanm 92:4fc01daae5a5 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 92:4fc01daae5a5 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 92:4fc01daae5a5 1008
bogdanm 92:4fc01daae5a5 1009 /* TPI TRIGGER Register Definitions */
bogdanm 92:4fc01daae5a5 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 110:165afa46840b 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 92:4fc01daae5a5 1012
bogdanm 92:4fc01daae5a5 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 92:4fc01daae5a5 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 92:4fc01daae5a5 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 92:4fc01daae5a5 1016
bogdanm 92:4fc01daae5a5 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 92:4fc01daae5a5 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 92:4fc01daae5a5 1019
bogdanm 92:4fc01daae5a5 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 92:4fc01daae5a5 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 92:4fc01daae5a5 1022
bogdanm 92:4fc01daae5a5 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 92:4fc01daae5a5 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 92:4fc01daae5a5 1025
bogdanm 92:4fc01daae5a5 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 92:4fc01daae5a5 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 92:4fc01daae5a5 1028
bogdanm 92:4fc01daae5a5 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 92:4fc01daae5a5 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 92:4fc01daae5a5 1031
bogdanm 92:4fc01daae5a5 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 110:165afa46840b 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 92:4fc01daae5a5 1034
bogdanm 92:4fc01daae5a5 1035 /* TPI ITATBCTR2 Register Definitions */
bogdanm 92:4fc01daae5a5 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 110:165afa46840b 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 92:4fc01daae5a5 1038
bogdanm 92:4fc01daae5a5 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 92:4fc01daae5a5 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 92:4fc01daae5a5 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 92:4fc01daae5a5 1042
bogdanm 92:4fc01daae5a5 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 92:4fc01daae5a5 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 92:4fc01daae5a5 1045
bogdanm 92:4fc01daae5a5 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 92:4fc01daae5a5 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 92:4fc01daae5a5 1048
bogdanm 92:4fc01daae5a5 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 92:4fc01daae5a5 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 92:4fc01daae5a5 1051
bogdanm 92:4fc01daae5a5 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 92:4fc01daae5a5 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 92:4fc01daae5a5 1054
bogdanm 92:4fc01daae5a5 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 92:4fc01daae5a5 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 92:4fc01daae5a5 1057
bogdanm 92:4fc01daae5a5 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 110:165afa46840b 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 92:4fc01daae5a5 1060
bogdanm 92:4fc01daae5a5 1061 /* TPI ITATBCTR0 Register Definitions */
bogdanm 92:4fc01daae5a5 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 110:165afa46840b 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 92:4fc01daae5a5 1064
bogdanm 92:4fc01daae5a5 1065 /* TPI Integration Mode Control Register Definitions */
bogdanm 92:4fc01daae5a5 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 110:165afa46840b 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
bogdanm 92:4fc01daae5a5 1068
bogdanm 92:4fc01daae5a5 1069 /* TPI DEVID Register Definitions */
bogdanm 92:4fc01daae5a5 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 92:4fc01daae5a5 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 92:4fc01daae5a5 1072
bogdanm 92:4fc01daae5a5 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 92:4fc01daae5a5 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 92:4fc01daae5a5 1075
bogdanm 92:4fc01daae5a5 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 92:4fc01daae5a5 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 92:4fc01daae5a5 1078
bogdanm 92:4fc01daae5a5 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 92:4fc01daae5a5 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 92:4fc01daae5a5 1081
bogdanm 92:4fc01daae5a5 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 92:4fc01daae5a5 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 92:4fc01daae5a5 1084
bogdanm 92:4fc01daae5a5 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 110:165afa46840b 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 92:4fc01daae5a5 1087
bogdanm 92:4fc01daae5a5 1088 /* TPI DEVTYPE Register Definitions */
bogdanm 92:4fc01daae5a5 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 92:4fc01daae5a5 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 92:4fc01daae5a5 1091
Kojto 110:165afa46840b 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 110:165afa46840b 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 110:165afa46840b 1094
bogdanm 92:4fc01daae5a5 1095 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 92:4fc01daae5a5 1096
bogdanm 92:4fc01daae5a5 1097
bogdanm 92:4fc01daae5a5 1098 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 1099 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 1101 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 1102 @{
bogdanm 92:4fc01daae5a5 1103 */
bogdanm 92:4fc01daae5a5 1104
bogdanm 92:4fc01daae5a5 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 92:4fc01daae5a5 1106 */
bogdanm 92:4fc01daae5a5 1107 typedef struct
bogdanm 92:4fc01daae5a5 1108 {
bogdanm 92:4fc01daae5a5 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 92:4fc01daae5a5 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 92:4fc01daae5a5 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 92:4fc01daae5a5 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 92:4fc01daae5a5 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 92:4fc01daae5a5 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 92:4fc01daae5a5 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 1120 } MPU_Type;
bogdanm 92:4fc01daae5a5 1121
bogdanm 92:4fc01daae5a5 1122 /* MPU Type Register */
bogdanm 92:4fc01daae5a5 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 92:4fc01daae5a5 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 92:4fc01daae5a5 1125
bogdanm 92:4fc01daae5a5 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 92:4fc01daae5a5 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 92:4fc01daae5a5 1128
bogdanm 92:4fc01daae5a5 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 92:4fc01daae5a5 1131
bogdanm 92:4fc01daae5a5 1132 /* MPU Control Register */
bogdanm 92:4fc01daae5a5 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 92:4fc01daae5a5 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 92:4fc01daae5a5 1135
bogdanm 92:4fc01daae5a5 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 92:4fc01daae5a5 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 92:4fc01daae5a5 1138
bogdanm 92:4fc01daae5a5 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 1141
bogdanm 92:4fc01daae5a5 1142 /* MPU Region Number Register */
bogdanm 92:4fc01daae5a5 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 92:4fc01daae5a5 1145
bogdanm 92:4fc01daae5a5 1146 /* MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 92:4fc01daae5a5 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 92:4fc01daae5a5 1149
bogdanm 92:4fc01daae5a5 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 92:4fc01daae5a5 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 92:4fc01daae5a5 1152
bogdanm 92:4fc01daae5a5 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 92:4fc01daae5a5 1155
bogdanm 92:4fc01daae5a5 1156 /* MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 92:4fc01daae5a5 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 92:4fc01daae5a5 1159
bogdanm 92:4fc01daae5a5 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 92:4fc01daae5a5 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 92:4fc01daae5a5 1162
bogdanm 92:4fc01daae5a5 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 92:4fc01daae5a5 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 92:4fc01daae5a5 1165
bogdanm 92:4fc01daae5a5 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 92:4fc01daae5a5 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 92:4fc01daae5a5 1168
bogdanm 92:4fc01daae5a5 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 92:4fc01daae5a5 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 92:4fc01daae5a5 1171
bogdanm 92:4fc01daae5a5 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 92:4fc01daae5a5 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 92:4fc01daae5a5 1174
bogdanm 92:4fc01daae5a5 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 92:4fc01daae5a5 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 92:4fc01daae5a5 1177
bogdanm 92:4fc01daae5a5 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 92:4fc01daae5a5 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 92:4fc01daae5a5 1180
bogdanm 92:4fc01daae5a5 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 92:4fc01daae5a5 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 92:4fc01daae5a5 1183
bogdanm 92:4fc01daae5a5 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 92:4fc01daae5a5 1186
bogdanm 92:4fc01daae5a5 1187 /*@} end of group CMSIS_MPU */
bogdanm 92:4fc01daae5a5 1188 #endif
bogdanm 92:4fc01daae5a5 1189
bogdanm 92:4fc01daae5a5 1190
bogdanm 92:4fc01daae5a5 1191 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 92:4fc01daae5a5 1193 \brief Type definitions for the Core Debug Registers
bogdanm 92:4fc01daae5a5 1194 @{
bogdanm 92:4fc01daae5a5 1195 */
bogdanm 92:4fc01daae5a5 1196
bogdanm 92:4fc01daae5a5 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 92:4fc01daae5a5 1198 */
bogdanm 92:4fc01daae5a5 1199 typedef struct
bogdanm 92:4fc01daae5a5 1200 {
bogdanm 92:4fc01daae5a5 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 92:4fc01daae5a5 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 92:4fc01daae5a5 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 92:4fc01daae5a5 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 92:4fc01daae5a5 1205 } CoreDebug_Type;
bogdanm 92:4fc01daae5a5 1206
bogdanm 92:4fc01daae5a5 1207 /* Debug Halting Control and Status Register */
bogdanm 92:4fc01daae5a5 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 92:4fc01daae5a5 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 92:4fc01daae5a5 1210
bogdanm 92:4fc01daae5a5 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 92:4fc01daae5a5 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 92:4fc01daae5a5 1213
bogdanm 92:4fc01daae5a5 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 92:4fc01daae5a5 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 92:4fc01daae5a5 1216
bogdanm 92:4fc01daae5a5 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 92:4fc01daae5a5 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 92:4fc01daae5a5 1219
bogdanm 92:4fc01daae5a5 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 92:4fc01daae5a5 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 92:4fc01daae5a5 1222
bogdanm 92:4fc01daae5a5 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 92:4fc01daae5a5 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 92:4fc01daae5a5 1225
bogdanm 92:4fc01daae5a5 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 92:4fc01daae5a5 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 92:4fc01daae5a5 1228
bogdanm 92:4fc01daae5a5 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 92:4fc01daae5a5 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 92:4fc01daae5a5 1231
bogdanm 92:4fc01daae5a5 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 92:4fc01daae5a5 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 92:4fc01daae5a5 1234
bogdanm 92:4fc01daae5a5 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 92:4fc01daae5a5 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 92:4fc01daae5a5 1237
bogdanm 92:4fc01daae5a5 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 92:4fc01daae5a5 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 92:4fc01daae5a5 1240
bogdanm 92:4fc01daae5a5 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 110:165afa46840b 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 92:4fc01daae5a5 1243
bogdanm 92:4fc01daae5a5 1244 /* Debug Core Register Selector Register */
bogdanm 92:4fc01daae5a5 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 92:4fc01daae5a5 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 92:4fc01daae5a5 1247
bogdanm 92:4fc01daae5a5 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 110:165afa46840b 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 92:4fc01daae5a5 1250
bogdanm 92:4fc01daae5a5 1251 /* Debug Exception and Monitor Control Register */
bogdanm 92:4fc01daae5a5 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 92:4fc01daae5a5 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 92:4fc01daae5a5 1254
bogdanm 92:4fc01daae5a5 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 92:4fc01daae5a5 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 92:4fc01daae5a5 1257
bogdanm 92:4fc01daae5a5 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 92:4fc01daae5a5 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 92:4fc01daae5a5 1260
bogdanm 92:4fc01daae5a5 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 92:4fc01daae5a5 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 92:4fc01daae5a5 1263
bogdanm 92:4fc01daae5a5 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 92:4fc01daae5a5 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 92:4fc01daae5a5 1266
bogdanm 92:4fc01daae5a5 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 92:4fc01daae5a5 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 92:4fc01daae5a5 1269
bogdanm 92:4fc01daae5a5 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 92:4fc01daae5a5 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 92:4fc01daae5a5 1272
bogdanm 92:4fc01daae5a5 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 92:4fc01daae5a5 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 92:4fc01daae5a5 1275
bogdanm 92:4fc01daae5a5 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 92:4fc01daae5a5 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 92:4fc01daae5a5 1278
bogdanm 92:4fc01daae5a5 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 92:4fc01daae5a5 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 92:4fc01daae5a5 1281
bogdanm 92:4fc01daae5a5 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 92:4fc01daae5a5 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 92:4fc01daae5a5 1284
bogdanm 92:4fc01daae5a5 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 92:4fc01daae5a5 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 92:4fc01daae5a5 1287
bogdanm 92:4fc01daae5a5 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 110:165afa46840b 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 92:4fc01daae5a5 1290
bogdanm 92:4fc01daae5a5 1291 /*@} end of group CMSIS_CoreDebug */
bogdanm 92:4fc01daae5a5 1292
bogdanm 92:4fc01daae5a5 1293
bogdanm 92:4fc01daae5a5 1294 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 1295 \defgroup CMSIS_core_base Core Definitions
bogdanm 92:4fc01daae5a5 1296 \brief Definitions for base addresses, unions, and structures.
bogdanm 92:4fc01daae5a5 1297 @{
bogdanm 92:4fc01daae5a5 1298 */
bogdanm 92:4fc01daae5a5 1299
bogdanm 92:4fc01daae5a5 1300 /* Memory mapping of Cortex-M3 Hardware */
bogdanm 92:4fc01daae5a5 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 92:4fc01daae5a5 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 92:4fc01daae5a5 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 92:4fc01daae5a5 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 92:4fc01daae5a5 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 92:4fc01daae5a5 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 92:4fc01daae5a5 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 92:4fc01daae5a5 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 92:4fc01daae5a5 1309
bogdanm 92:4fc01daae5a5 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 92:4fc01daae5a5 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 92:4fc01daae5a5 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 92:4fc01daae5a5 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 92:4fc01daae5a5 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 92:4fc01daae5a5 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 92:4fc01daae5a5 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 92:4fc01daae5a5 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 92:4fc01daae5a5 1318
bogdanm 92:4fc01daae5a5 1319 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 1322 #endif
bogdanm 92:4fc01daae5a5 1323
bogdanm 92:4fc01daae5a5 1324 /*@} */
bogdanm 92:4fc01daae5a5 1325
bogdanm 92:4fc01daae5a5 1326
bogdanm 92:4fc01daae5a5 1327
bogdanm 92:4fc01daae5a5 1328 /*******************************************************************************
bogdanm 92:4fc01daae5a5 1329 * Hardware Abstraction Layer
bogdanm 92:4fc01daae5a5 1330 Core Function Interface contains:
bogdanm 92:4fc01daae5a5 1331 - Core NVIC Functions
bogdanm 92:4fc01daae5a5 1332 - Core SysTick Functions
bogdanm 92:4fc01daae5a5 1333 - Core Debug Functions
bogdanm 92:4fc01daae5a5 1334 - Core Register Access Functions
bogdanm 92:4fc01daae5a5 1335 ******************************************************************************/
bogdanm 92:4fc01daae5a5 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 92:4fc01daae5a5 1337 */
bogdanm 92:4fc01daae5a5 1338
bogdanm 92:4fc01daae5a5 1339
bogdanm 92:4fc01daae5a5 1340
bogdanm 92:4fc01daae5a5 1341 /* ########################## NVIC functions #################################### */
bogdanm 92:4fc01daae5a5 1342 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 92:4fc01daae5a5 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 92:4fc01daae5a5 1345 @{
bogdanm 92:4fc01daae5a5 1346 */
bogdanm 92:4fc01daae5a5 1347
<> 127:25aea2a3f4e3 1348 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1351 #endif
<> 127:25aea2a3f4e3 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1353 #else
<> 127:25aea2a3f4e3 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 127:25aea2a3f4e3 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1361 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1362 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1363 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1364 #define NVIC_SystemReset __NVIC_SystemReset
<> 127:25aea2a3f4e3 1365 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1366
<> 127:25aea2a3f4e3 1367 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1370 #endif
<> 127:25aea2a3f4e3 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1372 #else
<> 127:25aea2a3f4e3 1373 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1374 #define NVIC_GetVector __NVIC_GetVector
<> 127:25aea2a3f4e3 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 127:25aea2a3f4e3 1376
bogdanm 92:4fc01daae5a5 1377 /** \brief Set Priority Grouping
bogdanm 92:4fc01daae5a5 1378
bogdanm 92:4fc01daae5a5 1379 The function sets the priority grouping field using the required unlock sequence.
bogdanm 92:4fc01daae5a5 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 92:4fc01daae5a5 1381 Only values from 0..7 are used.
bogdanm 92:4fc01daae5a5 1382 In case of a conflict between priority grouping and available
bogdanm 92:4fc01daae5a5 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 92:4fc01daae5a5 1384
bogdanm 92:4fc01daae5a5 1385 \param [in] PriorityGroup Priority grouping field.
bogdanm 92:4fc01daae5a5 1386 */
<> 127:25aea2a3f4e3 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 92:4fc01daae5a5 1388 {
bogdanm 92:4fc01daae5a5 1389 uint32_t reg_value;
Kojto 110:165afa46840b 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 92:4fc01daae5a5 1391
bogdanm 92:4fc01daae5a5 1392 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 110:165afa46840b 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 110:165afa46840b 1394 reg_value = (reg_value |
Kojto 110:165afa46840b 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
bogdanm 92:4fc01daae5a5 1397 SCB->AIRCR = reg_value;
bogdanm 92:4fc01daae5a5 1398 }
bogdanm 92:4fc01daae5a5 1399
bogdanm 92:4fc01daae5a5 1400
bogdanm 92:4fc01daae5a5 1401 /** \brief Get Priority Grouping
bogdanm 92:4fc01daae5a5 1402
bogdanm 92:4fc01daae5a5 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 92:4fc01daae5a5 1404
bogdanm 92:4fc01daae5a5 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 92:4fc01daae5a5 1406 */
<> 127:25aea2a3f4e3 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
bogdanm 92:4fc01daae5a5 1408 {
Kojto 110:165afa46840b 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
bogdanm 92:4fc01daae5a5 1410 }
bogdanm 92:4fc01daae5a5 1411
bogdanm 92:4fc01daae5a5 1412
bogdanm 92:4fc01daae5a5 1413 /** \brief Enable External Interrupt
bogdanm 92:4fc01daae5a5 1414
bogdanm 92:4fc01daae5a5 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 1416
bogdanm 92:4fc01daae5a5 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 1418 */
<> 127:25aea2a3f4e3 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1420 {
Kojto 110:165afa46840b 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 1422 }
bogdanm 92:4fc01daae5a5 1423
bogdanm 92:4fc01daae5a5 1424
bogdanm 92:4fc01daae5a5 1425 /** \brief Disable External Interrupt
bogdanm 92:4fc01daae5a5 1426
bogdanm 92:4fc01daae5a5 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 1428
bogdanm 92:4fc01daae5a5 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 1430 */
<> 127:25aea2a3f4e3 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1432 {
Kojto 110:165afa46840b 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1434 __DSB();
<> 131:faff56e089b2 1435 __ISB();
bogdanm 92:4fc01daae5a5 1436 }
bogdanm 92:4fc01daae5a5 1437
bogdanm 92:4fc01daae5a5 1438
bogdanm 92:4fc01daae5a5 1439 /** \brief Get Pending Interrupt
bogdanm 92:4fc01daae5a5 1440
bogdanm 92:4fc01daae5a5 1441 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 92:4fc01daae5a5 1442 for the specified interrupt.
bogdanm 92:4fc01daae5a5 1443
bogdanm 92:4fc01daae5a5 1444 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 1445
bogdanm 92:4fc01daae5a5 1446 \return 0 Interrupt status is not pending.
bogdanm 92:4fc01daae5a5 1447 \return 1 Interrupt status is pending.
bogdanm 92:4fc01daae5a5 1448 */
<> 127:25aea2a3f4e3 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1450 {
Kojto 110:165afa46840b 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 92:4fc01daae5a5 1452 }
bogdanm 92:4fc01daae5a5 1453
bogdanm 92:4fc01daae5a5 1454
bogdanm 92:4fc01daae5a5 1455 /** \brief Set Pending Interrupt
bogdanm 92:4fc01daae5a5 1456
bogdanm 92:4fc01daae5a5 1457 The function sets the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 1458
bogdanm 92:4fc01daae5a5 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 1460 */
<> 127:25aea2a3f4e3 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1462 {
Kojto 110:165afa46840b 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 1464 }
bogdanm 92:4fc01daae5a5 1465
bogdanm 92:4fc01daae5a5 1466
bogdanm 92:4fc01daae5a5 1467 /** \brief Clear Pending Interrupt
bogdanm 92:4fc01daae5a5 1468
bogdanm 92:4fc01daae5a5 1469 The function clears the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 1470
bogdanm 92:4fc01daae5a5 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 1472 */
<> 127:25aea2a3f4e3 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1474 {
Kojto 110:165afa46840b 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 1476 }
bogdanm 92:4fc01daae5a5 1477
bogdanm 92:4fc01daae5a5 1478
bogdanm 92:4fc01daae5a5 1479 /** \brief Get Active Interrupt
bogdanm 92:4fc01daae5a5 1480
bogdanm 92:4fc01daae5a5 1481 The function reads the active register in NVIC and returns the active bit.
bogdanm 92:4fc01daae5a5 1482
bogdanm 92:4fc01daae5a5 1483 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 1484
bogdanm 92:4fc01daae5a5 1485 \return 0 Interrupt status is not active.
bogdanm 92:4fc01daae5a5 1486 \return 1 Interrupt status is active.
bogdanm 92:4fc01daae5a5 1487 */
<> 127:25aea2a3f4e3 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1489 {
Kojto 110:165afa46840b 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 92:4fc01daae5a5 1491 }
bogdanm 92:4fc01daae5a5 1492
bogdanm 92:4fc01daae5a5 1493
bogdanm 92:4fc01daae5a5 1494 /** \brief Set Interrupt Priority
bogdanm 92:4fc01daae5a5 1495
bogdanm 92:4fc01daae5a5 1496 The function sets the priority of an interrupt.
bogdanm 92:4fc01daae5a5 1497
bogdanm 92:4fc01daae5a5 1498 \note The priority cannot be set for every core interrupt.
bogdanm 92:4fc01daae5a5 1499
bogdanm 92:4fc01daae5a5 1500 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 1501 \param [in] priority Priority to set.
bogdanm 92:4fc01daae5a5 1502 */
<> 127:25aea2a3f4e3 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 92:4fc01daae5a5 1504 {
Kojto 110:165afa46840b 1505 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1507 }
bogdanm 92:4fc01daae5a5 1508 else {
Kojto 110:165afa46840b 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1510 }
bogdanm 92:4fc01daae5a5 1511 }
bogdanm 92:4fc01daae5a5 1512
bogdanm 92:4fc01daae5a5 1513
bogdanm 92:4fc01daae5a5 1514 /** \brief Get Interrupt Priority
bogdanm 92:4fc01daae5a5 1515
bogdanm 92:4fc01daae5a5 1516 The function reads the priority of an interrupt. The interrupt
bogdanm 92:4fc01daae5a5 1517 number can be positive to specify an external (device specific)
bogdanm 92:4fc01daae5a5 1518 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 92:4fc01daae5a5 1519
bogdanm 92:4fc01daae5a5 1520
bogdanm 92:4fc01daae5a5 1521 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 92:4fc01daae5a5 1523 priority bits of the microcontroller.
bogdanm 92:4fc01daae5a5 1524 */
<> 127:25aea2a3f4e3 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 1526 {
bogdanm 92:4fc01daae5a5 1527
Kojto 110:165afa46840b 1528 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1530 }
bogdanm 92:4fc01daae5a5 1531 else {
Kojto 110:165afa46840b 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1533 }
bogdanm 92:4fc01daae5a5 1534 }
bogdanm 92:4fc01daae5a5 1535
bogdanm 92:4fc01daae5a5 1536
bogdanm 92:4fc01daae5a5 1537 /** \brief Encode Priority
bogdanm 92:4fc01daae5a5 1538
bogdanm 92:4fc01daae5a5 1539 The function encodes the priority for an interrupt with the given priority group,
bogdanm 92:4fc01daae5a5 1540 preemptive priority value, and subpriority value.
bogdanm 92:4fc01daae5a5 1541 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 92:4fc01daae5a5 1543
bogdanm 92:4fc01daae5a5 1544 \param [in] PriorityGroup Used priority group.
bogdanm 92:4fc01daae5a5 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 92:4fc01daae5a5 1546 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 92:4fc01daae5a5 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 92:4fc01daae5a5 1548 */
bogdanm 92:4fc01daae5a5 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 92:4fc01daae5a5 1550 {
Kojto 110:165afa46840b 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 92:4fc01daae5a5 1552 uint32_t PreemptPriorityBits;
bogdanm 92:4fc01daae5a5 1553 uint32_t SubPriorityBits;
bogdanm 92:4fc01daae5a5 1554
Kojto 110:165afa46840b 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 92:4fc01daae5a5 1557
bogdanm 92:4fc01daae5a5 1558 return (
Kojto 110:165afa46840b 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 110:165afa46840b 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
bogdanm 92:4fc01daae5a5 1561 );
bogdanm 92:4fc01daae5a5 1562 }
bogdanm 92:4fc01daae5a5 1563
bogdanm 92:4fc01daae5a5 1564
bogdanm 92:4fc01daae5a5 1565 /** \brief Decode Priority
bogdanm 92:4fc01daae5a5 1566
bogdanm 92:4fc01daae5a5 1567 The function decodes an interrupt priority value with a given priority group to
bogdanm 92:4fc01daae5a5 1568 preemptive priority value and subpriority value.
bogdanm 92:4fc01daae5a5 1569 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
bogdanm 92:4fc01daae5a5 1571
bogdanm 92:4fc01daae5a5 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 92:4fc01daae5a5 1573 \param [in] PriorityGroup Used priority group.
bogdanm 92:4fc01daae5a5 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 92:4fc01daae5a5 1575 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 92:4fc01daae5a5 1576 */
bogdanm 92:4fc01daae5a5 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 92:4fc01daae5a5 1578 {
Kojto 110:165afa46840b 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 92:4fc01daae5a5 1580 uint32_t PreemptPriorityBits;
bogdanm 92:4fc01daae5a5 1581 uint32_t SubPriorityBits;
bogdanm 92:4fc01daae5a5 1582
Kojto 110:165afa46840b 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 92:4fc01daae5a5 1585
Kojto 110:165afa46840b 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 110:165afa46840b 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
bogdanm 92:4fc01daae5a5 1588 }
bogdanm 92:4fc01daae5a5 1589
bogdanm 92:4fc01daae5a5 1590
bogdanm 92:4fc01daae5a5 1591 /** \brief System Reset
bogdanm 92:4fc01daae5a5 1592
bogdanm 92:4fc01daae5a5 1593 The function initiates a system reset request to reset the MCU.
bogdanm 92:4fc01daae5a5 1594 */
<> 128:9bcdf88f62b0 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
bogdanm 92:4fc01daae5a5 1596 {
Kojto 110:165afa46840b 1597 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 110:165afa46840b 1598 buffered write are completed before reset */
Kojto 110:165afa46840b 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 110:165afa46840b 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 110:165afa46840b 1602 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 1603 while(1) { __NOP(); } /* wait until reset */
bogdanm 92:4fc01daae5a5 1604 }
bogdanm 92:4fc01daae5a5 1605
bogdanm 92:4fc01daae5a5 1606 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 92:4fc01daae5a5 1607
bogdanm 92:4fc01daae5a5 1608
bogdanm 92:4fc01daae5a5 1609
bogdanm 92:4fc01daae5a5 1610 /* ################################## SysTick function ############################################ */
bogdanm 92:4fc01daae5a5 1611 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 92:4fc01daae5a5 1613 \brief Functions that configure the System.
bogdanm 92:4fc01daae5a5 1614 @{
bogdanm 92:4fc01daae5a5 1615 */
bogdanm 92:4fc01daae5a5 1616
bogdanm 92:4fc01daae5a5 1617 #if (__Vendor_SysTickConfig == 0)
bogdanm 92:4fc01daae5a5 1618
bogdanm 92:4fc01daae5a5 1619 /** \brief System Tick Configuration
bogdanm 92:4fc01daae5a5 1620
bogdanm 92:4fc01daae5a5 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 92:4fc01daae5a5 1622 Counter is in free running mode to generate periodic interrupts.
bogdanm 92:4fc01daae5a5 1623
bogdanm 92:4fc01daae5a5 1624 \param [in] ticks Number of ticks between two interrupts.
bogdanm 92:4fc01daae5a5 1625
bogdanm 92:4fc01daae5a5 1626 \return 0 Function succeeded.
bogdanm 92:4fc01daae5a5 1627 \return 1 Function failed.
bogdanm 92:4fc01daae5a5 1628
bogdanm 92:4fc01daae5a5 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 92:4fc01daae5a5 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 92:4fc01daae5a5 1631 must contain a vendor-specific implementation of this function.
bogdanm 92:4fc01daae5a5 1632
bogdanm 92:4fc01daae5a5 1633 */
bogdanm 92:4fc01daae5a5 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 92:4fc01daae5a5 1635 {
Kojto 110:165afa46840b 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 92:4fc01daae5a5 1637
Kojto 110:165afa46840b 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 92:4fc01daae5a5 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 92:4fc01daae5a5 1642 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 1644 return (0UL); /* Function successful */
bogdanm 92:4fc01daae5a5 1645 }
bogdanm 92:4fc01daae5a5 1646
bogdanm 92:4fc01daae5a5 1647 #endif
bogdanm 92:4fc01daae5a5 1648
bogdanm 92:4fc01daae5a5 1649 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 92:4fc01daae5a5 1650
bogdanm 92:4fc01daae5a5 1651
bogdanm 92:4fc01daae5a5 1652
bogdanm 92:4fc01daae5a5 1653 /* ##################################### Debug In/Output function ########################################### */
bogdanm 92:4fc01daae5a5 1654 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 92:4fc01daae5a5 1656 \brief Functions that access the ITM debug interface.
bogdanm 92:4fc01daae5a5 1657 @{
bogdanm 92:4fc01daae5a5 1658 */
bogdanm 92:4fc01daae5a5 1659
bogdanm 92:4fc01daae5a5 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 92:4fc01daae5a5 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 92:4fc01daae5a5 1662
bogdanm 92:4fc01daae5a5 1663
bogdanm 92:4fc01daae5a5 1664 /** \brief ITM Send Character
bogdanm 92:4fc01daae5a5 1665
bogdanm 92:4fc01daae5a5 1666 The function transmits a character via the ITM channel 0, and
bogdanm 92:4fc01daae5a5 1667 \li Just returns when no debugger is connected that has booked the output.
bogdanm 92:4fc01daae5a5 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 92:4fc01daae5a5 1669
bogdanm 92:4fc01daae5a5 1670 \param [in] ch Character to transmit.
bogdanm 92:4fc01daae5a5 1671
bogdanm 92:4fc01daae5a5 1672 \returns Character to transmit.
bogdanm 92:4fc01daae5a5 1673 */
bogdanm 92:4fc01daae5a5 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 92:4fc01daae5a5 1675 {
Kojto 110:165afa46840b 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 110:165afa46840b 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
bogdanm 92:4fc01daae5a5 1678 {
Kojto 110:165afa46840b 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 110:165afa46840b 1680 ITM->PORT[0].u8 = (uint8_t)ch;
bogdanm 92:4fc01daae5a5 1681 }
bogdanm 92:4fc01daae5a5 1682 return (ch);
bogdanm 92:4fc01daae5a5 1683 }
bogdanm 92:4fc01daae5a5 1684
bogdanm 92:4fc01daae5a5 1685
bogdanm 92:4fc01daae5a5 1686 /** \brief ITM Receive Character
bogdanm 92:4fc01daae5a5 1687
bogdanm 92:4fc01daae5a5 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 92:4fc01daae5a5 1689
bogdanm 92:4fc01daae5a5 1690 \return Received character.
bogdanm 92:4fc01daae5a5 1691 \return -1 No character pending.
bogdanm 92:4fc01daae5a5 1692 */
bogdanm 92:4fc01daae5a5 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 92:4fc01daae5a5 1694 int32_t ch = -1; /* no character available */
bogdanm 92:4fc01daae5a5 1695
bogdanm 92:4fc01daae5a5 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 92:4fc01daae5a5 1697 ch = ITM_RxBuffer;
bogdanm 92:4fc01daae5a5 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 92:4fc01daae5a5 1699 }
bogdanm 92:4fc01daae5a5 1700
bogdanm 92:4fc01daae5a5 1701 return (ch);
bogdanm 92:4fc01daae5a5 1702 }
bogdanm 92:4fc01daae5a5 1703
bogdanm 92:4fc01daae5a5 1704
bogdanm 92:4fc01daae5a5 1705 /** \brief ITM Check Character
bogdanm 92:4fc01daae5a5 1706
bogdanm 92:4fc01daae5a5 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 92:4fc01daae5a5 1708
bogdanm 92:4fc01daae5a5 1709 \return 0 No character available.
bogdanm 92:4fc01daae5a5 1710 \return 1 Character available.
bogdanm 92:4fc01daae5a5 1711 */
bogdanm 92:4fc01daae5a5 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 92:4fc01daae5a5 1713
bogdanm 92:4fc01daae5a5 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 92:4fc01daae5a5 1715 return (0); /* no character available */
bogdanm 92:4fc01daae5a5 1716 } else {
bogdanm 92:4fc01daae5a5 1717 return (1); /* character available */
bogdanm 92:4fc01daae5a5 1718 }
bogdanm 92:4fc01daae5a5 1719 }
bogdanm 92:4fc01daae5a5 1720
bogdanm 92:4fc01daae5a5 1721 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 92:4fc01daae5a5 1722
bogdanm 92:4fc01daae5a5 1723
Kojto 110:165afa46840b 1724
bogdanm 92:4fc01daae5a5 1725
bogdanm 92:4fc01daae5a5 1726 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1727 }
bogdanm 92:4fc01daae5a5 1728 #endif
Kojto 110:165afa46840b 1729
Kojto 110:165afa46840b 1730 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 110:165afa46840b 1731
Kojto 110:165afa46840b 1732 #endif /* __CMSIS_GENERIC */