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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L031K6/core_cm3.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 119:aae6fcc7d9bb 1 /**************************************************************************//**
Kojto 119:aae6fcc7d9bb 2 * @file core_cm3.h
Kojto 119:aae6fcc7d9bb 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto 119:aae6fcc7d9bb 4 * @version V4.10
Kojto 119:aae6fcc7d9bb 5 * @date 18. March 2015
Kojto 119:aae6fcc7d9bb 6 *
Kojto 119:aae6fcc7d9bb 7 * @note
Kojto 119:aae6fcc7d9bb 8 *
Kojto 119:aae6fcc7d9bb 9 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 119:aae6fcc7d9bb 11
Kojto 119:aae6fcc7d9bb 12 All rights reserved.
Kojto 119:aae6fcc7d9bb 13 Redistribution and use in source and binary forms, with or without
Kojto 119:aae6fcc7d9bb 14 modification, are permitted provided that the following conditions are met:
Kojto 119:aae6fcc7d9bb 15 - Redistributions of source code must retain the above copyright
Kojto 119:aae6fcc7d9bb 16 notice, this list of conditions and the following disclaimer.
Kojto 119:aae6fcc7d9bb 17 - Redistributions in binary form must reproduce the above copyright
Kojto 119:aae6fcc7d9bb 18 notice, this list of conditions and the following disclaimer in the
Kojto 119:aae6fcc7d9bb 19 documentation and/or other materials provided with the distribution.
Kojto 119:aae6fcc7d9bb 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 119:aae6fcc7d9bb 21 to endorse or promote products derived from this software without
Kojto 119:aae6fcc7d9bb 22 specific prior written permission.
Kojto 119:aae6fcc7d9bb 23 *
Kojto 119:aae6fcc7d9bb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 119:aae6fcc7d9bb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 119:aae6fcc7d9bb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 119:aae6fcc7d9bb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 119:aae6fcc7d9bb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 119:aae6fcc7d9bb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 119:aae6fcc7d9bb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 119:aae6fcc7d9bb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 119:aae6fcc7d9bb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 119:aae6fcc7d9bb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 119:aae6fcc7d9bb 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 119:aae6fcc7d9bb 35 ---------------------------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 36
Kojto 119:aae6fcc7d9bb 37
Kojto 119:aae6fcc7d9bb 38 #if defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 119:aae6fcc7d9bb 40 #endif
Kojto 119:aae6fcc7d9bb 41
Kojto 119:aae6fcc7d9bb 42 #ifndef __CORE_CM3_H_GENERIC
Kojto 119:aae6fcc7d9bb 43 #define __CORE_CM3_H_GENERIC
Kojto 119:aae6fcc7d9bb 44
Kojto 119:aae6fcc7d9bb 45 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 46 extern "C" {
Kojto 119:aae6fcc7d9bb 47 #endif
Kojto 119:aae6fcc7d9bb 48
Kojto 119:aae6fcc7d9bb 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 119:aae6fcc7d9bb 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 119:aae6fcc7d9bb 51
Kojto 119:aae6fcc7d9bb 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 119:aae6fcc7d9bb 53 Function definitions in header files are used to allow 'inlining'.
Kojto 119:aae6fcc7d9bb 54
Kojto 119:aae6fcc7d9bb 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 119:aae6fcc7d9bb 56 Unions are used for effective representation of core registers.
Kojto 119:aae6fcc7d9bb 57
Kojto 119:aae6fcc7d9bb 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 119:aae6fcc7d9bb 59 Function-like macros are used to allow more efficient code.
Kojto 119:aae6fcc7d9bb 60 */
Kojto 119:aae6fcc7d9bb 61
Kojto 119:aae6fcc7d9bb 62
Kojto 119:aae6fcc7d9bb 63 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 64 * CMSIS definitions
Kojto 119:aae6fcc7d9bb 65 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 66 /** \ingroup Cortex_M3
Kojto 119:aae6fcc7d9bb 67 @{
Kojto 119:aae6fcc7d9bb 68 */
Kojto 119:aae6fcc7d9bb 69
Kojto 119:aae6fcc7d9bb 70 /* CMSIS CM3 definitions */
Kojto 119:aae6fcc7d9bb 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 119:aae6fcc7d9bb 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 119:aae6fcc7d9bb 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
Kojto 119:aae6fcc7d9bb 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 119:aae6fcc7d9bb 75
Kojto 119:aae6fcc7d9bb 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
Kojto 119:aae6fcc7d9bb 77
Kojto 119:aae6fcc7d9bb 78
Kojto 119:aae6fcc7d9bb 79 #if defined ( __CC_ARM )
Kojto 119:aae6fcc7d9bb 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 119:aae6fcc7d9bb 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 119:aae6fcc7d9bb 82 #define __STATIC_INLINE static __inline
Kojto 119:aae6fcc7d9bb 83
Kojto 119:aae6fcc7d9bb 84 #elif defined ( __GNUC__ )
Kojto 119:aae6fcc7d9bb 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 119:aae6fcc7d9bb 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 119:aae6fcc7d9bb 87 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 88
Kojto 119:aae6fcc7d9bb 89 #elif defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 119:aae6fcc7d9bb 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 119:aae6fcc7d9bb 92 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 93
Kojto 119:aae6fcc7d9bb 94 #elif defined ( __TMS470__ )
Kojto 119:aae6fcc7d9bb 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 119:aae6fcc7d9bb 96 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 97
Kojto 119:aae6fcc7d9bb 98 #elif defined ( __TASKING__ )
Kojto 119:aae6fcc7d9bb 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 119:aae6fcc7d9bb 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 119:aae6fcc7d9bb 101 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 102
Kojto 119:aae6fcc7d9bb 103 #elif defined ( __CSMC__ )
Kojto 119:aae6fcc7d9bb 104 #define __packed
Kojto 119:aae6fcc7d9bb 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 119:aae6fcc7d9bb 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 119:aae6fcc7d9bb 107 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 108
Kojto 119:aae6fcc7d9bb 109 #endif
Kojto 119:aae6fcc7d9bb 110
Kojto 119:aae6fcc7d9bb 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 119:aae6fcc7d9bb 112 This core does not support an FPU at all
Kojto 119:aae6fcc7d9bb 113 */
Kojto 119:aae6fcc7d9bb 114 #define __FPU_USED 0
Kojto 119:aae6fcc7d9bb 115
Kojto 119:aae6fcc7d9bb 116 #if defined ( __CC_ARM )
Kojto 119:aae6fcc7d9bb 117 #if defined __TARGET_FPU_VFP
Kojto 119:aae6fcc7d9bb 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 119 #endif
Kojto 119:aae6fcc7d9bb 120
Kojto 119:aae6fcc7d9bb 121 #elif defined ( __GNUC__ )
Kojto 119:aae6fcc7d9bb 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 119:aae6fcc7d9bb 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 124 #endif
Kojto 119:aae6fcc7d9bb 125
Kojto 119:aae6fcc7d9bb 126 #elif defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 127 #if defined __ARMVFP__
Kojto 119:aae6fcc7d9bb 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 129 #endif
Kojto 119:aae6fcc7d9bb 130
Kojto 119:aae6fcc7d9bb 131 #elif defined ( __TMS470__ )
Kojto 119:aae6fcc7d9bb 132 #if defined __TI__VFP_SUPPORT____
Kojto 119:aae6fcc7d9bb 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 134 #endif
Kojto 119:aae6fcc7d9bb 135
Kojto 119:aae6fcc7d9bb 136 #elif defined ( __TASKING__ )
Kojto 119:aae6fcc7d9bb 137 #if defined __FPU_VFP__
Kojto 119:aae6fcc7d9bb 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 139 #endif
Kojto 119:aae6fcc7d9bb 140
Kojto 119:aae6fcc7d9bb 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 119:aae6fcc7d9bb 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 119:aae6fcc7d9bb 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 144 #endif
Kojto 119:aae6fcc7d9bb 145 #endif
Kojto 119:aae6fcc7d9bb 146
Kojto 119:aae6fcc7d9bb 147 #include <stdint.h> /* standard types definitions */
Kojto 119:aae6fcc7d9bb 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 119:aae6fcc7d9bb 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 119:aae6fcc7d9bb 150
Kojto 119:aae6fcc7d9bb 151 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 152 }
Kojto 119:aae6fcc7d9bb 153 #endif
Kojto 119:aae6fcc7d9bb 154
Kojto 119:aae6fcc7d9bb 155 #endif /* __CORE_CM3_H_GENERIC */
Kojto 119:aae6fcc7d9bb 156
Kojto 119:aae6fcc7d9bb 157 #ifndef __CMSIS_GENERIC
Kojto 119:aae6fcc7d9bb 158
Kojto 119:aae6fcc7d9bb 159 #ifndef __CORE_CM3_H_DEPENDANT
Kojto 119:aae6fcc7d9bb 160 #define __CORE_CM3_H_DEPENDANT
Kojto 119:aae6fcc7d9bb 161
Kojto 119:aae6fcc7d9bb 162 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 163 extern "C" {
Kojto 119:aae6fcc7d9bb 164 #endif
Kojto 119:aae6fcc7d9bb 165
Kojto 119:aae6fcc7d9bb 166 /* check device defines and use defaults */
Kojto 119:aae6fcc7d9bb 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 119:aae6fcc7d9bb 168 #ifndef __CM3_REV
Kojto 119:aae6fcc7d9bb 169 #define __CM3_REV 0x0200
Kojto 119:aae6fcc7d9bb 170 #warning "__CM3_REV not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 171 #endif
Kojto 119:aae6fcc7d9bb 172
Kojto 119:aae6fcc7d9bb 173 #ifndef __MPU_PRESENT
Kojto 119:aae6fcc7d9bb 174 #define __MPU_PRESENT 0
Kojto 119:aae6fcc7d9bb 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 176 #endif
Kojto 119:aae6fcc7d9bb 177
Kojto 119:aae6fcc7d9bb 178 #ifndef __NVIC_PRIO_BITS
Kojto 119:aae6fcc7d9bb 179 #define __NVIC_PRIO_BITS 4
Kojto 119:aae6fcc7d9bb 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 181 #endif
Kojto 119:aae6fcc7d9bb 182
Kojto 119:aae6fcc7d9bb 183 #ifndef __Vendor_SysTickConfig
Kojto 119:aae6fcc7d9bb 184 #define __Vendor_SysTickConfig 0
Kojto 119:aae6fcc7d9bb 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 186 #endif
Kojto 119:aae6fcc7d9bb 187 #endif
Kojto 119:aae6fcc7d9bb 188
Kojto 119:aae6fcc7d9bb 189 /* IO definitions (access restrictions to peripheral registers) */
Kojto 119:aae6fcc7d9bb 190 /**
Kojto 119:aae6fcc7d9bb 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 119:aae6fcc7d9bb 192
Kojto 119:aae6fcc7d9bb 193 <strong>IO Type Qualifiers</strong> are used
Kojto 119:aae6fcc7d9bb 194 \li to specify the access to peripheral variables.
Kojto 119:aae6fcc7d9bb 195 \li for automatic generation of peripheral register debug information.
Kojto 119:aae6fcc7d9bb 196 */
Kojto 119:aae6fcc7d9bb 197 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 198 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 119:aae6fcc7d9bb 199 #else
Kojto 119:aae6fcc7d9bb 200 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 119:aae6fcc7d9bb 201 #endif
Kojto 119:aae6fcc7d9bb 202 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 119:aae6fcc7d9bb 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 119:aae6fcc7d9bb 204
<> 128:9bcdf88f62b0 205 #ifdef __cplusplus
<> 128:9bcdf88f62b0 206 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 207 #else
<> 128:9bcdf88f62b0 208 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 209 #endif
<> 128:9bcdf88f62b0 210 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 212
Kojto 119:aae6fcc7d9bb 213 /*@} end of group Cortex_M3 */
Kojto 119:aae6fcc7d9bb 214
Kojto 119:aae6fcc7d9bb 215
Kojto 119:aae6fcc7d9bb 216
Kojto 119:aae6fcc7d9bb 217 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 218 * Register Abstraction
Kojto 119:aae6fcc7d9bb 219 Core Register contain:
Kojto 119:aae6fcc7d9bb 220 - Core Register
Kojto 119:aae6fcc7d9bb 221 - Core NVIC Register
Kojto 119:aae6fcc7d9bb 222 - Core SCB Register
Kojto 119:aae6fcc7d9bb 223 - Core SysTick Register
Kojto 119:aae6fcc7d9bb 224 - Core Debug Register
Kojto 119:aae6fcc7d9bb 225 - Core MPU Register
Kojto 119:aae6fcc7d9bb 226 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 119:aae6fcc7d9bb 228 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 119:aae6fcc7d9bb 229 */
Kojto 119:aae6fcc7d9bb 230
Kojto 119:aae6fcc7d9bb 231 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 232 \defgroup CMSIS_CORE Status and Control Registers
Kojto 119:aae6fcc7d9bb 233 \brief Core Register type definitions.
Kojto 119:aae6fcc7d9bb 234 @{
Kojto 119:aae6fcc7d9bb 235 */
Kojto 119:aae6fcc7d9bb 236
Kojto 119:aae6fcc7d9bb 237 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 119:aae6fcc7d9bb 238 */
Kojto 119:aae6fcc7d9bb 239 typedef union
Kojto 119:aae6fcc7d9bb 240 {
Kojto 119:aae6fcc7d9bb 241 struct
Kojto 119:aae6fcc7d9bb 242 {
Kojto 119:aae6fcc7d9bb 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 119:aae6fcc7d9bb 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 119:aae6fcc7d9bb 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 119:aae6fcc7d9bb 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 119:aae6fcc7d9bb 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 119:aae6fcc7d9bb 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 119:aae6fcc7d9bb 249 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 250 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 251 } APSR_Type;
Kojto 119:aae6fcc7d9bb 252
Kojto 119:aae6fcc7d9bb 253 /* APSR Register Definitions */
Kojto 119:aae6fcc7d9bb 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 119:aae6fcc7d9bb 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 119:aae6fcc7d9bb 256
Kojto 119:aae6fcc7d9bb 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 119:aae6fcc7d9bb 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 119:aae6fcc7d9bb 259
Kojto 119:aae6fcc7d9bb 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 119:aae6fcc7d9bb 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 119:aae6fcc7d9bb 262
Kojto 119:aae6fcc7d9bb 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 119:aae6fcc7d9bb 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 119:aae6fcc7d9bb 265
Kojto 119:aae6fcc7d9bb 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 119:aae6fcc7d9bb 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 119:aae6fcc7d9bb 268
Kojto 119:aae6fcc7d9bb 269
Kojto 119:aae6fcc7d9bb 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 119:aae6fcc7d9bb 271 */
Kojto 119:aae6fcc7d9bb 272 typedef union
Kojto 119:aae6fcc7d9bb 273 {
Kojto 119:aae6fcc7d9bb 274 struct
Kojto 119:aae6fcc7d9bb 275 {
Kojto 119:aae6fcc7d9bb 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 119:aae6fcc7d9bb 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 119:aae6fcc7d9bb 278 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 279 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 280 } IPSR_Type;
Kojto 119:aae6fcc7d9bb 281
Kojto 119:aae6fcc7d9bb 282 /* IPSR Register Definitions */
Kojto 119:aae6fcc7d9bb 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 119:aae6fcc7d9bb 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 119:aae6fcc7d9bb 285
Kojto 119:aae6fcc7d9bb 286
Kojto 119:aae6fcc7d9bb 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 119:aae6fcc7d9bb 288 */
Kojto 119:aae6fcc7d9bb 289 typedef union
Kojto 119:aae6fcc7d9bb 290 {
Kojto 119:aae6fcc7d9bb 291 struct
Kojto 119:aae6fcc7d9bb 292 {
Kojto 119:aae6fcc7d9bb 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 119:aae6fcc7d9bb 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 119:aae6fcc7d9bb 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 119:aae6fcc7d9bb 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 119:aae6fcc7d9bb 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 119:aae6fcc7d9bb 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 119:aae6fcc7d9bb 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 119:aae6fcc7d9bb 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 119:aae6fcc7d9bb 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 119:aae6fcc7d9bb 302 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 303 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 304 } xPSR_Type;
Kojto 119:aae6fcc7d9bb 305
Kojto 119:aae6fcc7d9bb 306 /* xPSR Register Definitions */
Kojto 119:aae6fcc7d9bb 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 119:aae6fcc7d9bb 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 119:aae6fcc7d9bb 309
Kojto 119:aae6fcc7d9bb 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 119:aae6fcc7d9bb 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 119:aae6fcc7d9bb 312
Kojto 119:aae6fcc7d9bb 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 119:aae6fcc7d9bb 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 119:aae6fcc7d9bb 315
Kojto 119:aae6fcc7d9bb 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 119:aae6fcc7d9bb 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 119:aae6fcc7d9bb 318
Kojto 119:aae6fcc7d9bb 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 119:aae6fcc7d9bb 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 119:aae6fcc7d9bb 321
Kojto 119:aae6fcc7d9bb 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 119:aae6fcc7d9bb 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 119:aae6fcc7d9bb 324
Kojto 119:aae6fcc7d9bb 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 119:aae6fcc7d9bb 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 119:aae6fcc7d9bb 327
Kojto 119:aae6fcc7d9bb 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 119:aae6fcc7d9bb 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 119:aae6fcc7d9bb 330
Kojto 119:aae6fcc7d9bb 331
Kojto 119:aae6fcc7d9bb 332 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 119:aae6fcc7d9bb 333 */
Kojto 119:aae6fcc7d9bb 334 typedef union
Kojto 119:aae6fcc7d9bb 335 {
Kojto 119:aae6fcc7d9bb 336 struct
Kojto 119:aae6fcc7d9bb 337 {
Kojto 119:aae6fcc7d9bb 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 119:aae6fcc7d9bb 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 119:aae6fcc7d9bb 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 119:aae6fcc7d9bb 341 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 342 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 343 } CONTROL_Type;
Kojto 119:aae6fcc7d9bb 344
Kojto 119:aae6fcc7d9bb 345 /* CONTROL Register Definitions */
Kojto 119:aae6fcc7d9bb 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 119:aae6fcc7d9bb 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 119:aae6fcc7d9bb 348
Kojto 119:aae6fcc7d9bb 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 119:aae6fcc7d9bb 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 119:aae6fcc7d9bb 351
Kojto 119:aae6fcc7d9bb 352 /*@} end of group CMSIS_CORE */
Kojto 119:aae6fcc7d9bb 353
Kojto 119:aae6fcc7d9bb 354
Kojto 119:aae6fcc7d9bb 355 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 119:aae6fcc7d9bb 357 \brief Type definitions for the NVIC Registers
Kojto 119:aae6fcc7d9bb 358 @{
Kojto 119:aae6fcc7d9bb 359 */
Kojto 119:aae6fcc7d9bb 360
Kojto 119:aae6fcc7d9bb 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 119:aae6fcc7d9bb 362 */
Kojto 119:aae6fcc7d9bb 363 typedef struct
Kojto 119:aae6fcc7d9bb 364 {
Kojto 119:aae6fcc7d9bb 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 119:aae6fcc7d9bb 366 uint32_t RESERVED0[24];
Kojto 119:aae6fcc7d9bb 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 119:aae6fcc7d9bb 368 uint32_t RSERVED1[24];
Kojto 119:aae6fcc7d9bb 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 119:aae6fcc7d9bb 370 uint32_t RESERVED2[24];
Kojto 119:aae6fcc7d9bb 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 119:aae6fcc7d9bb 372 uint32_t RESERVED3[24];
Kojto 119:aae6fcc7d9bb 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 119:aae6fcc7d9bb 374 uint32_t RESERVED4[56];
Kojto 119:aae6fcc7d9bb 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 119:aae6fcc7d9bb 376 uint32_t RESERVED5[644];
Kojto 119:aae6fcc7d9bb 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 119:aae6fcc7d9bb 378 } NVIC_Type;
Kojto 119:aae6fcc7d9bb 379
Kojto 119:aae6fcc7d9bb 380 /* Software Triggered Interrupt Register Definitions */
Kojto 119:aae6fcc7d9bb 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 119:aae6fcc7d9bb 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 119:aae6fcc7d9bb 383
Kojto 119:aae6fcc7d9bb 384 /*@} end of group CMSIS_NVIC */
Kojto 119:aae6fcc7d9bb 385
Kojto 119:aae6fcc7d9bb 386
Kojto 119:aae6fcc7d9bb 387 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 388 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 119:aae6fcc7d9bb 389 \brief Type definitions for the System Control Block Registers
Kojto 119:aae6fcc7d9bb 390 @{
Kojto 119:aae6fcc7d9bb 391 */
Kojto 119:aae6fcc7d9bb 392
Kojto 119:aae6fcc7d9bb 393 /** \brief Structure type to access the System Control Block (SCB).
Kojto 119:aae6fcc7d9bb 394 */
Kojto 119:aae6fcc7d9bb 395 typedef struct
Kojto 119:aae6fcc7d9bb 396 {
Kojto 119:aae6fcc7d9bb 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 119:aae6fcc7d9bb 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 119:aae6fcc7d9bb 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 119:aae6fcc7d9bb 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 119:aae6fcc7d9bb 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 119:aae6fcc7d9bb 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 119:aae6fcc7d9bb 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 119:aae6fcc7d9bb 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 119:aae6fcc7d9bb 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 119:aae6fcc7d9bb 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 119:aae6fcc7d9bb 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 119:aae6fcc7d9bb 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 119:aae6fcc7d9bb 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 119:aae6fcc7d9bb 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 119:aae6fcc7d9bb 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 119:aae6fcc7d9bb 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 119:aae6fcc7d9bb 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 119:aae6fcc7d9bb 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 119:aae6fcc7d9bb 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 119:aae6fcc7d9bb 416 uint32_t RESERVED0[5];
Kojto 119:aae6fcc7d9bb 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 119:aae6fcc7d9bb 418 } SCB_Type;
Kojto 119:aae6fcc7d9bb 419
Kojto 119:aae6fcc7d9bb 420 /* SCB CPUID Register Definitions */
Kojto 119:aae6fcc7d9bb 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 119:aae6fcc7d9bb 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 119:aae6fcc7d9bb 423
Kojto 119:aae6fcc7d9bb 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 119:aae6fcc7d9bb 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 119:aae6fcc7d9bb 426
Kojto 119:aae6fcc7d9bb 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 119:aae6fcc7d9bb 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 119:aae6fcc7d9bb 429
Kojto 119:aae6fcc7d9bb 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 119:aae6fcc7d9bb 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 119:aae6fcc7d9bb 432
Kojto 119:aae6fcc7d9bb 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 119:aae6fcc7d9bb 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 119:aae6fcc7d9bb 435
Kojto 119:aae6fcc7d9bb 436 /* SCB Interrupt Control State Register Definitions */
Kojto 119:aae6fcc7d9bb 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 119:aae6fcc7d9bb 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 119:aae6fcc7d9bb 439
Kojto 119:aae6fcc7d9bb 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 119:aae6fcc7d9bb 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 119:aae6fcc7d9bb 442
Kojto 119:aae6fcc7d9bb 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 119:aae6fcc7d9bb 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 119:aae6fcc7d9bb 445
Kojto 119:aae6fcc7d9bb 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 119:aae6fcc7d9bb 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 119:aae6fcc7d9bb 448
Kojto 119:aae6fcc7d9bb 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 119:aae6fcc7d9bb 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 119:aae6fcc7d9bb 451
Kojto 119:aae6fcc7d9bb 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 119:aae6fcc7d9bb 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 119:aae6fcc7d9bb 454
Kojto 119:aae6fcc7d9bb 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 119:aae6fcc7d9bb 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 119:aae6fcc7d9bb 457
Kojto 119:aae6fcc7d9bb 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 119:aae6fcc7d9bb 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 119:aae6fcc7d9bb 460
Kojto 119:aae6fcc7d9bb 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 119:aae6fcc7d9bb 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 119:aae6fcc7d9bb 463
Kojto 119:aae6fcc7d9bb 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 119:aae6fcc7d9bb 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 119:aae6fcc7d9bb 466
Kojto 119:aae6fcc7d9bb 467 /* SCB Vector Table Offset Register Definitions */
Kojto 119:aae6fcc7d9bb 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
Kojto 119:aae6fcc7d9bb 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kojto 119:aae6fcc7d9bb 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 119:aae6fcc7d9bb 471
Kojto 119:aae6fcc7d9bb 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 119:aae6fcc7d9bb 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 119:aae6fcc7d9bb 474 #else
Kojto 119:aae6fcc7d9bb 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 119:aae6fcc7d9bb 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 119:aae6fcc7d9bb 477 #endif
Kojto 119:aae6fcc7d9bb 478
Kojto 119:aae6fcc7d9bb 479 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 119:aae6fcc7d9bb 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 119:aae6fcc7d9bb 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 119:aae6fcc7d9bb 482
Kojto 119:aae6fcc7d9bb 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 119:aae6fcc7d9bb 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 119:aae6fcc7d9bb 485
Kojto 119:aae6fcc7d9bb 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 119:aae6fcc7d9bb 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 119:aae6fcc7d9bb 488
Kojto 119:aae6fcc7d9bb 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 119:aae6fcc7d9bb 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 119:aae6fcc7d9bb 491
Kojto 119:aae6fcc7d9bb 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 119:aae6fcc7d9bb 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 119:aae6fcc7d9bb 494
Kojto 119:aae6fcc7d9bb 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 119:aae6fcc7d9bb 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 119:aae6fcc7d9bb 497
Kojto 119:aae6fcc7d9bb 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 119:aae6fcc7d9bb 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 119:aae6fcc7d9bb 500
Kojto 119:aae6fcc7d9bb 501 /* SCB System Control Register Definitions */
Kojto 119:aae6fcc7d9bb 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 119:aae6fcc7d9bb 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 119:aae6fcc7d9bb 504
Kojto 119:aae6fcc7d9bb 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 119:aae6fcc7d9bb 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 119:aae6fcc7d9bb 507
Kojto 119:aae6fcc7d9bb 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 119:aae6fcc7d9bb 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 119:aae6fcc7d9bb 510
Kojto 119:aae6fcc7d9bb 511 /* SCB Configuration Control Register Definitions */
Kojto 119:aae6fcc7d9bb 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 119:aae6fcc7d9bb 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 119:aae6fcc7d9bb 514
Kojto 119:aae6fcc7d9bb 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 119:aae6fcc7d9bb 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 119:aae6fcc7d9bb 517
Kojto 119:aae6fcc7d9bb 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 119:aae6fcc7d9bb 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 119:aae6fcc7d9bb 520
Kojto 119:aae6fcc7d9bb 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 119:aae6fcc7d9bb 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 119:aae6fcc7d9bb 523
Kojto 119:aae6fcc7d9bb 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 119:aae6fcc7d9bb 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 119:aae6fcc7d9bb 526
Kojto 119:aae6fcc7d9bb 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 119:aae6fcc7d9bb 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 119:aae6fcc7d9bb 529
Kojto 119:aae6fcc7d9bb 530 /* SCB System Handler Control and State Register Definitions */
Kojto 119:aae6fcc7d9bb 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 119:aae6fcc7d9bb 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 119:aae6fcc7d9bb 533
Kojto 119:aae6fcc7d9bb 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 119:aae6fcc7d9bb 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 119:aae6fcc7d9bb 536
Kojto 119:aae6fcc7d9bb 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 119:aae6fcc7d9bb 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 119:aae6fcc7d9bb 539
Kojto 119:aae6fcc7d9bb 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 119:aae6fcc7d9bb 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 119:aae6fcc7d9bb 542
Kojto 119:aae6fcc7d9bb 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 119:aae6fcc7d9bb 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 119:aae6fcc7d9bb 545
Kojto 119:aae6fcc7d9bb 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 119:aae6fcc7d9bb 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 119:aae6fcc7d9bb 548
Kojto 119:aae6fcc7d9bb 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 119:aae6fcc7d9bb 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 119:aae6fcc7d9bb 551
Kojto 119:aae6fcc7d9bb 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 119:aae6fcc7d9bb 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 119:aae6fcc7d9bb 554
Kojto 119:aae6fcc7d9bb 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 119:aae6fcc7d9bb 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 119:aae6fcc7d9bb 557
Kojto 119:aae6fcc7d9bb 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 119:aae6fcc7d9bb 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 119:aae6fcc7d9bb 560
Kojto 119:aae6fcc7d9bb 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 119:aae6fcc7d9bb 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 119:aae6fcc7d9bb 563
Kojto 119:aae6fcc7d9bb 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 119:aae6fcc7d9bb 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 119:aae6fcc7d9bb 566
Kojto 119:aae6fcc7d9bb 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 119:aae6fcc7d9bb 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 119:aae6fcc7d9bb 569
Kojto 119:aae6fcc7d9bb 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 119:aae6fcc7d9bb 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 119:aae6fcc7d9bb 572
Kojto 119:aae6fcc7d9bb 573 /* SCB Configurable Fault Status Registers Definitions */
Kojto 119:aae6fcc7d9bb 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 119:aae6fcc7d9bb 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 119:aae6fcc7d9bb 576
Kojto 119:aae6fcc7d9bb 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 119:aae6fcc7d9bb 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 119:aae6fcc7d9bb 579
Kojto 119:aae6fcc7d9bb 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 119:aae6fcc7d9bb 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 119:aae6fcc7d9bb 582
Kojto 119:aae6fcc7d9bb 583 /* SCB Hard Fault Status Registers Definitions */
Kojto 119:aae6fcc7d9bb 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 119:aae6fcc7d9bb 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 119:aae6fcc7d9bb 586
Kojto 119:aae6fcc7d9bb 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 119:aae6fcc7d9bb 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 119:aae6fcc7d9bb 589
Kojto 119:aae6fcc7d9bb 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 119:aae6fcc7d9bb 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 119:aae6fcc7d9bb 592
Kojto 119:aae6fcc7d9bb 593 /* SCB Debug Fault Status Register Definitions */
Kojto 119:aae6fcc7d9bb 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 119:aae6fcc7d9bb 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 119:aae6fcc7d9bb 596
Kojto 119:aae6fcc7d9bb 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 119:aae6fcc7d9bb 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 119:aae6fcc7d9bb 599
Kojto 119:aae6fcc7d9bb 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 119:aae6fcc7d9bb 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 119:aae6fcc7d9bb 602
Kojto 119:aae6fcc7d9bb 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 119:aae6fcc7d9bb 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 119:aae6fcc7d9bb 605
Kojto 119:aae6fcc7d9bb 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 119:aae6fcc7d9bb 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 119:aae6fcc7d9bb 608
Kojto 119:aae6fcc7d9bb 609 /*@} end of group CMSIS_SCB */
Kojto 119:aae6fcc7d9bb 610
Kojto 119:aae6fcc7d9bb 611
Kojto 119:aae6fcc7d9bb 612 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 119:aae6fcc7d9bb 614 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 119:aae6fcc7d9bb 615 @{
Kojto 119:aae6fcc7d9bb 616 */
Kojto 119:aae6fcc7d9bb 617
Kojto 119:aae6fcc7d9bb 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 119:aae6fcc7d9bb 619 */
Kojto 119:aae6fcc7d9bb 620 typedef struct
Kojto 119:aae6fcc7d9bb 621 {
Kojto 119:aae6fcc7d9bb 622 uint32_t RESERVED0[1];
Kojto 119:aae6fcc7d9bb 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 119:aae6fcc7d9bb 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kojto 119:aae6fcc7d9bb 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 119:aae6fcc7d9bb 626 #else
Kojto 119:aae6fcc7d9bb 627 uint32_t RESERVED1[1];
Kojto 119:aae6fcc7d9bb 628 #endif
Kojto 119:aae6fcc7d9bb 629 } SCnSCB_Type;
Kojto 119:aae6fcc7d9bb 630
Kojto 119:aae6fcc7d9bb 631 /* Interrupt Controller Type Register Definitions */
Kojto 119:aae6fcc7d9bb 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 119:aae6fcc7d9bb 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 119:aae6fcc7d9bb 634
Kojto 119:aae6fcc7d9bb 635 /* Auxiliary Control Register Definitions */
Kojto 119:aae6fcc7d9bb 636
Kojto 119:aae6fcc7d9bb 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 119:aae6fcc7d9bb 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 119:aae6fcc7d9bb 639
Kojto 119:aae6fcc7d9bb 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
Kojto 119:aae6fcc7d9bb 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Kojto 119:aae6fcc7d9bb 642
Kojto 119:aae6fcc7d9bb 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 119:aae6fcc7d9bb 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 119:aae6fcc7d9bb 645
Kojto 119:aae6fcc7d9bb 646 /*@} end of group CMSIS_SCnotSCB */
Kojto 119:aae6fcc7d9bb 647
Kojto 119:aae6fcc7d9bb 648
Kojto 119:aae6fcc7d9bb 649 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 119:aae6fcc7d9bb 651 \brief Type definitions for the System Timer Registers.
Kojto 119:aae6fcc7d9bb 652 @{
Kojto 119:aae6fcc7d9bb 653 */
Kojto 119:aae6fcc7d9bb 654
Kojto 119:aae6fcc7d9bb 655 /** \brief Structure type to access the System Timer (SysTick).
Kojto 119:aae6fcc7d9bb 656 */
Kojto 119:aae6fcc7d9bb 657 typedef struct
Kojto 119:aae6fcc7d9bb 658 {
Kojto 119:aae6fcc7d9bb 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 119:aae6fcc7d9bb 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 119:aae6fcc7d9bb 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 119:aae6fcc7d9bb 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 119:aae6fcc7d9bb 663 } SysTick_Type;
Kojto 119:aae6fcc7d9bb 664
Kojto 119:aae6fcc7d9bb 665 /* SysTick Control / Status Register Definitions */
Kojto 119:aae6fcc7d9bb 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 119:aae6fcc7d9bb 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 119:aae6fcc7d9bb 668
Kojto 119:aae6fcc7d9bb 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 119:aae6fcc7d9bb 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 119:aae6fcc7d9bb 671
Kojto 119:aae6fcc7d9bb 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 119:aae6fcc7d9bb 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 119:aae6fcc7d9bb 674
Kojto 119:aae6fcc7d9bb 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 119:aae6fcc7d9bb 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 119:aae6fcc7d9bb 677
Kojto 119:aae6fcc7d9bb 678 /* SysTick Reload Register Definitions */
Kojto 119:aae6fcc7d9bb 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 119:aae6fcc7d9bb 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 119:aae6fcc7d9bb 681
Kojto 119:aae6fcc7d9bb 682 /* SysTick Current Register Definitions */
Kojto 119:aae6fcc7d9bb 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 119:aae6fcc7d9bb 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 119:aae6fcc7d9bb 685
Kojto 119:aae6fcc7d9bb 686 /* SysTick Calibration Register Definitions */
Kojto 119:aae6fcc7d9bb 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 119:aae6fcc7d9bb 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 119:aae6fcc7d9bb 689
Kojto 119:aae6fcc7d9bb 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 119:aae6fcc7d9bb 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 119:aae6fcc7d9bb 692
Kojto 119:aae6fcc7d9bb 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 119:aae6fcc7d9bb 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 119:aae6fcc7d9bb 695
Kojto 119:aae6fcc7d9bb 696 /*@} end of group CMSIS_SysTick */
Kojto 119:aae6fcc7d9bb 697
Kojto 119:aae6fcc7d9bb 698
Kojto 119:aae6fcc7d9bb 699 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 119:aae6fcc7d9bb 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 119:aae6fcc7d9bb 702 @{
Kojto 119:aae6fcc7d9bb 703 */
Kojto 119:aae6fcc7d9bb 704
Kojto 119:aae6fcc7d9bb 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 119:aae6fcc7d9bb 706 */
Kojto 119:aae6fcc7d9bb 707 typedef struct
Kojto 119:aae6fcc7d9bb 708 {
Kojto 119:aae6fcc7d9bb 709 __O union
Kojto 119:aae6fcc7d9bb 710 {
Kojto 119:aae6fcc7d9bb 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 119:aae6fcc7d9bb 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 119:aae6fcc7d9bb 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 119:aae6fcc7d9bb 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 119:aae6fcc7d9bb 715 uint32_t RESERVED0[864];
Kojto 119:aae6fcc7d9bb 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 119:aae6fcc7d9bb 717 uint32_t RESERVED1[15];
Kojto 119:aae6fcc7d9bb 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 119:aae6fcc7d9bb 719 uint32_t RESERVED2[15];
Kojto 119:aae6fcc7d9bb 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 119:aae6fcc7d9bb 721 uint32_t RESERVED3[29];
Kojto 119:aae6fcc7d9bb 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 119:aae6fcc7d9bb 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 119:aae6fcc7d9bb 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 119:aae6fcc7d9bb 725 uint32_t RESERVED4[43];
Kojto 119:aae6fcc7d9bb 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 119:aae6fcc7d9bb 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 119:aae6fcc7d9bb 728 uint32_t RESERVED5[6];
Kojto 119:aae6fcc7d9bb 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 119:aae6fcc7d9bb 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 119:aae6fcc7d9bb 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 119:aae6fcc7d9bb 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 119:aae6fcc7d9bb 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 119:aae6fcc7d9bb 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 119:aae6fcc7d9bb 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 119:aae6fcc7d9bb 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 119:aae6fcc7d9bb 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 119:aae6fcc7d9bb 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 119:aae6fcc7d9bb 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 119:aae6fcc7d9bb 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 119:aae6fcc7d9bb 741 } ITM_Type;
Kojto 119:aae6fcc7d9bb 742
Kojto 119:aae6fcc7d9bb 743 /* ITM Trace Privilege Register Definitions */
Kojto 119:aae6fcc7d9bb 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 119:aae6fcc7d9bb 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 119:aae6fcc7d9bb 746
Kojto 119:aae6fcc7d9bb 747 /* ITM Trace Control Register Definitions */
Kojto 119:aae6fcc7d9bb 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 119:aae6fcc7d9bb 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 119:aae6fcc7d9bb 750
Kojto 119:aae6fcc7d9bb 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 119:aae6fcc7d9bb 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 119:aae6fcc7d9bb 753
Kojto 119:aae6fcc7d9bb 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 119:aae6fcc7d9bb 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 119:aae6fcc7d9bb 756
Kojto 119:aae6fcc7d9bb 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 119:aae6fcc7d9bb 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 119:aae6fcc7d9bb 759
Kojto 119:aae6fcc7d9bb 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 119:aae6fcc7d9bb 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 119:aae6fcc7d9bb 762
Kojto 119:aae6fcc7d9bb 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 119:aae6fcc7d9bb 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 119:aae6fcc7d9bb 765
Kojto 119:aae6fcc7d9bb 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 119:aae6fcc7d9bb 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 119:aae6fcc7d9bb 768
Kojto 119:aae6fcc7d9bb 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 119:aae6fcc7d9bb 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 119:aae6fcc7d9bb 771
Kojto 119:aae6fcc7d9bb 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 119:aae6fcc7d9bb 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 119:aae6fcc7d9bb 774
Kojto 119:aae6fcc7d9bb 775 /* ITM Integration Write Register Definitions */
Kojto 119:aae6fcc7d9bb 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 119:aae6fcc7d9bb 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 119:aae6fcc7d9bb 778
Kojto 119:aae6fcc7d9bb 779 /* ITM Integration Read Register Definitions */
Kojto 119:aae6fcc7d9bb 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 119:aae6fcc7d9bb 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 119:aae6fcc7d9bb 782
Kojto 119:aae6fcc7d9bb 783 /* ITM Integration Mode Control Register Definitions */
Kojto 119:aae6fcc7d9bb 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 119:aae6fcc7d9bb 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 119:aae6fcc7d9bb 786
Kojto 119:aae6fcc7d9bb 787 /* ITM Lock Status Register Definitions */
Kojto 119:aae6fcc7d9bb 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 119:aae6fcc7d9bb 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 119:aae6fcc7d9bb 790
Kojto 119:aae6fcc7d9bb 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 119:aae6fcc7d9bb 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 119:aae6fcc7d9bb 793
Kojto 119:aae6fcc7d9bb 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 119:aae6fcc7d9bb 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 119:aae6fcc7d9bb 796
Kojto 119:aae6fcc7d9bb 797 /*@}*/ /* end of group CMSIS_ITM */
Kojto 119:aae6fcc7d9bb 798
Kojto 119:aae6fcc7d9bb 799
Kojto 119:aae6fcc7d9bb 800 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 119:aae6fcc7d9bb 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 119:aae6fcc7d9bb 803 @{
Kojto 119:aae6fcc7d9bb 804 */
Kojto 119:aae6fcc7d9bb 805
Kojto 119:aae6fcc7d9bb 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 119:aae6fcc7d9bb 807 */
Kojto 119:aae6fcc7d9bb 808 typedef struct
Kojto 119:aae6fcc7d9bb 809 {
Kojto 119:aae6fcc7d9bb 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 119:aae6fcc7d9bb 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 119:aae6fcc7d9bb 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 119:aae6fcc7d9bb 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 119:aae6fcc7d9bb 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 119:aae6fcc7d9bb 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 119:aae6fcc7d9bb 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 119:aae6fcc7d9bb 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 119:aae6fcc7d9bb 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 119:aae6fcc7d9bb 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 119:aae6fcc7d9bb 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 119:aae6fcc7d9bb 821 uint32_t RESERVED0[1];
Kojto 119:aae6fcc7d9bb 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 119:aae6fcc7d9bb 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 119:aae6fcc7d9bb 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 119:aae6fcc7d9bb 825 uint32_t RESERVED1[1];
Kojto 119:aae6fcc7d9bb 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 119:aae6fcc7d9bb 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 119:aae6fcc7d9bb 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 119:aae6fcc7d9bb 829 uint32_t RESERVED2[1];
Kojto 119:aae6fcc7d9bb 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 119:aae6fcc7d9bb 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 119:aae6fcc7d9bb 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 119:aae6fcc7d9bb 833 } DWT_Type;
Kojto 119:aae6fcc7d9bb 834
Kojto 119:aae6fcc7d9bb 835 /* DWT Control Register Definitions */
Kojto 119:aae6fcc7d9bb 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 119:aae6fcc7d9bb 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 119:aae6fcc7d9bb 838
Kojto 119:aae6fcc7d9bb 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 119:aae6fcc7d9bb 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 119:aae6fcc7d9bb 841
Kojto 119:aae6fcc7d9bb 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 119:aae6fcc7d9bb 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 119:aae6fcc7d9bb 844
Kojto 119:aae6fcc7d9bb 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 119:aae6fcc7d9bb 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 119:aae6fcc7d9bb 847
Kojto 119:aae6fcc7d9bb 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 119:aae6fcc7d9bb 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 119:aae6fcc7d9bb 850
Kojto 119:aae6fcc7d9bb 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 119:aae6fcc7d9bb 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 119:aae6fcc7d9bb 853
Kojto 119:aae6fcc7d9bb 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 119:aae6fcc7d9bb 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 119:aae6fcc7d9bb 856
Kojto 119:aae6fcc7d9bb 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 119:aae6fcc7d9bb 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 119:aae6fcc7d9bb 859
Kojto 119:aae6fcc7d9bb 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 119:aae6fcc7d9bb 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 119:aae6fcc7d9bb 862
Kojto 119:aae6fcc7d9bb 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 119:aae6fcc7d9bb 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 119:aae6fcc7d9bb 865
Kojto 119:aae6fcc7d9bb 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 119:aae6fcc7d9bb 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 119:aae6fcc7d9bb 868
Kojto 119:aae6fcc7d9bb 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 119:aae6fcc7d9bb 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 119:aae6fcc7d9bb 871
Kojto 119:aae6fcc7d9bb 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 119:aae6fcc7d9bb 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 119:aae6fcc7d9bb 874
Kojto 119:aae6fcc7d9bb 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 119:aae6fcc7d9bb 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 119:aae6fcc7d9bb 877
Kojto 119:aae6fcc7d9bb 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 119:aae6fcc7d9bb 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 119:aae6fcc7d9bb 880
Kojto 119:aae6fcc7d9bb 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 119:aae6fcc7d9bb 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 119:aae6fcc7d9bb 883
Kojto 119:aae6fcc7d9bb 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 119:aae6fcc7d9bb 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 119:aae6fcc7d9bb 886
Kojto 119:aae6fcc7d9bb 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 119:aae6fcc7d9bb 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 119:aae6fcc7d9bb 889
Kojto 119:aae6fcc7d9bb 890 /* DWT CPI Count Register Definitions */
Kojto 119:aae6fcc7d9bb 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 119:aae6fcc7d9bb 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 119:aae6fcc7d9bb 893
Kojto 119:aae6fcc7d9bb 894 /* DWT Exception Overhead Count Register Definitions */
Kojto 119:aae6fcc7d9bb 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 119:aae6fcc7d9bb 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 119:aae6fcc7d9bb 897
Kojto 119:aae6fcc7d9bb 898 /* DWT Sleep Count Register Definitions */
Kojto 119:aae6fcc7d9bb 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 119:aae6fcc7d9bb 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 119:aae6fcc7d9bb 901
Kojto 119:aae6fcc7d9bb 902 /* DWT LSU Count Register Definitions */
Kojto 119:aae6fcc7d9bb 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 119:aae6fcc7d9bb 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 119:aae6fcc7d9bb 905
Kojto 119:aae6fcc7d9bb 906 /* DWT Folded-instruction Count Register Definitions */
Kojto 119:aae6fcc7d9bb 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 119:aae6fcc7d9bb 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 119:aae6fcc7d9bb 909
Kojto 119:aae6fcc7d9bb 910 /* DWT Comparator Mask Register Definitions */
Kojto 119:aae6fcc7d9bb 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 119:aae6fcc7d9bb 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 119:aae6fcc7d9bb 913
Kojto 119:aae6fcc7d9bb 914 /* DWT Comparator Function Register Definitions */
Kojto 119:aae6fcc7d9bb 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 119:aae6fcc7d9bb 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 119:aae6fcc7d9bb 917
Kojto 119:aae6fcc7d9bb 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 119:aae6fcc7d9bb 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 119:aae6fcc7d9bb 920
Kojto 119:aae6fcc7d9bb 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 119:aae6fcc7d9bb 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 119:aae6fcc7d9bb 923
Kojto 119:aae6fcc7d9bb 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 119:aae6fcc7d9bb 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 119:aae6fcc7d9bb 926
Kojto 119:aae6fcc7d9bb 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 119:aae6fcc7d9bb 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 119:aae6fcc7d9bb 929
Kojto 119:aae6fcc7d9bb 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 119:aae6fcc7d9bb 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 119:aae6fcc7d9bb 932
Kojto 119:aae6fcc7d9bb 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 119:aae6fcc7d9bb 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 119:aae6fcc7d9bb 935
Kojto 119:aae6fcc7d9bb 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 119:aae6fcc7d9bb 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 119:aae6fcc7d9bb 938
Kojto 119:aae6fcc7d9bb 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 119:aae6fcc7d9bb 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 119:aae6fcc7d9bb 941
Kojto 119:aae6fcc7d9bb 942 /*@}*/ /* end of group CMSIS_DWT */
Kojto 119:aae6fcc7d9bb 943
Kojto 119:aae6fcc7d9bb 944
Kojto 119:aae6fcc7d9bb 945 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 119:aae6fcc7d9bb 947 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 119:aae6fcc7d9bb 948 @{
Kojto 119:aae6fcc7d9bb 949 */
Kojto 119:aae6fcc7d9bb 950
Kojto 119:aae6fcc7d9bb 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 119:aae6fcc7d9bb 952 */
Kojto 119:aae6fcc7d9bb 953 typedef struct
Kojto 119:aae6fcc7d9bb 954 {
Kojto 119:aae6fcc7d9bb 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 119:aae6fcc7d9bb 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 119:aae6fcc7d9bb 957 uint32_t RESERVED0[2];
Kojto 119:aae6fcc7d9bb 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 119:aae6fcc7d9bb 959 uint32_t RESERVED1[55];
Kojto 119:aae6fcc7d9bb 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 119:aae6fcc7d9bb 961 uint32_t RESERVED2[131];
Kojto 119:aae6fcc7d9bb 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 119:aae6fcc7d9bb 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 119:aae6fcc7d9bb 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 119:aae6fcc7d9bb 965 uint32_t RESERVED3[759];
Kojto 119:aae6fcc7d9bb 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 119:aae6fcc7d9bb 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 119:aae6fcc7d9bb 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 119:aae6fcc7d9bb 969 uint32_t RESERVED4[1];
Kojto 119:aae6fcc7d9bb 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 119:aae6fcc7d9bb 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 119:aae6fcc7d9bb 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 119:aae6fcc7d9bb 973 uint32_t RESERVED5[39];
Kojto 119:aae6fcc7d9bb 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 119:aae6fcc7d9bb 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 119:aae6fcc7d9bb 976 uint32_t RESERVED7[8];
Kojto 119:aae6fcc7d9bb 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 119:aae6fcc7d9bb 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 119:aae6fcc7d9bb 979 } TPI_Type;
Kojto 119:aae6fcc7d9bb 980
Kojto 119:aae6fcc7d9bb 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 119:aae6fcc7d9bb 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 119:aae6fcc7d9bb 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 119:aae6fcc7d9bb 984
Kojto 119:aae6fcc7d9bb 985 /* TPI Selected Pin Protocol Register Definitions */
Kojto 119:aae6fcc7d9bb 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 119:aae6fcc7d9bb 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 119:aae6fcc7d9bb 988
Kojto 119:aae6fcc7d9bb 989 /* TPI Formatter and Flush Status Register Definitions */
Kojto 119:aae6fcc7d9bb 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 119:aae6fcc7d9bb 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 119:aae6fcc7d9bb 992
Kojto 119:aae6fcc7d9bb 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 119:aae6fcc7d9bb 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 119:aae6fcc7d9bb 995
Kojto 119:aae6fcc7d9bb 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 119:aae6fcc7d9bb 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 119:aae6fcc7d9bb 998
Kojto 119:aae6fcc7d9bb 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 119:aae6fcc7d9bb 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 119:aae6fcc7d9bb 1001
Kojto 119:aae6fcc7d9bb 1002 /* TPI Formatter and Flush Control Register Definitions */
Kojto 119:aae6fcc7d9bb 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 119:aae6fcc7d9bb 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 119:aae6fcc7d9bb 1005
Kojto 119:aae6fcc7d9bb 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 119:aae6fcc7d9bb 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 119:aae6fcc7d9bb 1008
Kojto 119:aae6fcc7d9bb 1009 /* TPI TRIGGER Register Definitions */
Kojto 119:aae6fcc7d9bb 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 119:aae6fcc7d9bb 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 119:aae6fcc7d9bb 1012
Kojto 119:aae6fcc7d9bb 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 119:aae6fcc7d9bb 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 119:aae6fcc7d9bb 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 119:aae6fcc7d9bb 1016
Kojto 119:aae6fcc7d9bb 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 119:aae6fcc7d9bb 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 119:aae6fcc7d9bb 1019
Kojto 119:aae6fcc7d9bb 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 119:aae6fcc7d9bb 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 119:aae6fcc7d9bb 1022
Kojto 119:aae6fcc7d9bb 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 119:aae6fcc7d9bb 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 119:aae6fcc7d9bb 1025
Kojto 119:aae6fcc7d9bb 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 119:aae6fcc7d9bb 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 119:aae6fcc7d9bb 1028
Kojto 119:aae6fcc7d9bb 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 119:aae6fcc7d9bb 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 119:aae6fcc7d9bb 1031
Kojto 119:aae6fcc7d9bb 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 119:aae6fcc7d9bb 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 119:aae6fcc7d9bb 1034
Kojto 119:aae6fcc7d9bb 1035 /* TPI ITATBCTR2 Register Definitions */
Kojto 119:aae6fcc7d9bb 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 119:aae6fcc7d9bb 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 119:aae6fcc7d9bb 1038
Kojto 119:aae6fcc7d9bb 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 119:aae6fcc7d9bb 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 119:aae6fcc7d9bb 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 119:aae6fcc7d9bb 1042
Kojto 119:aae6fcc7d9bb 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 119:aae6fcc7d9bb 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 119:aae6fcc7d9bb 1045
Kojto 119:aae6fcc7d9bb 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 119:aae6fcc7d9bb 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 119:aae6fcc7d9bb 1048
Kojto 119:aae6fcc7d9bb 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 119:aae6fcc7d9bb 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 119:aae6fcc7d9bb 1051
Kojto 119:aae6fcc7d9bb 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 119:aae6fcc7d9bb 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 119:aae6fcc7d9bb 1054
Kojto 119:aae6fcc7d9bb 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 119:aae6fcc7d9bb 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 119:aae6fcc7d9bb 1057
Kojto 119:aae6fcc7d9bb 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 119:aae6fcc7d9bb 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 119:aae6fcc7d9bb 1060
Kojto 119:aae6fcc7d9bb 1061 /* TPI ITATBCTR0 Register Definitions */
Kojto 119:aae6fcc7d9bb 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 119:aae6fcc7d9bb 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 119:aae6fcc7d9bb 1064
Kojto 119:aae6fcc7d9bb 1065 /* TPI Integration Mode Control Register Definitions */
Kojto 119:aae6fcc7d9bb 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 119:aae6fcc7d9bb 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 119:aae6fcc7d9bb 1068
Kojto 119:aae6fcc7d9bb 1069 /* TPI DEVID Register Definitions */
Kojto 119:aae6fcc7d9bb 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 119:aae6fcc7d9bb 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 119:aae6fcc7d9bb 1072
Kojto 119:aae6fcc7d9bb 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 119:aae6fcc7d9bb 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 119:aae6fcc7d9bb 1075
Kojto 119:aae6fcc7d9bb 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 119:aae6fcc7d9bb 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 119:aae6fcc7d9bb 1078
Kojto 119:aae6fcc7d9bb 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 119:aae6fcc7d9bb 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 119:aae6fcc7d9bb 1081
Kojto 119:aae6fcc7d9bb 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 119:aae6fcc7d9bb 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 119:aae6fcc7d9bb 1084
Kojto 119:aae6fcc7d9bb 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 119:aae6fcc7d9bb 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 119:aae6fcc7d9bb 1087
Kojto 119:aae6fcc7d9bb 1088 /* TPI DEVTYPE Register Definitions */
Kojto 119:aae6fcc7d9bb 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 119:aae6fcc7d9bb 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 119:aae6fcc7d9bb 1091
Kojto 119:aae6fcc7d9bb 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 119:aae6fcc7d9bb 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 119:aae6fcc7d9bb 1094
Kojto 119:aae6fcc7d9bb 1095 /*@}*/ /* end of group CMSIS_TPI */
Kojto 119:aae6fcc7d9bb 1096
Kojto 119:aae6fcc7d9bb 1097
Kojto 119:aae6fcc7d9bb 1098 #if (__MPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 1099 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 119:aae6fcc7d9bb 1101 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 119:aae6fcc7d9bb 1102 @{
Kojto 119:aae6fcc7d9bb 1103 */
Kojto 119:aae6fcc7d9bb 1104
Kojto 119:aae6fcc7d9bb 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 119:aae6fcc7d9bb 1106 */
Kojto 119:aae6fcc7d9bb 1107 typedef struct
Kojto 119:aae6fcc7d9bb 1108 {
Kojto 119:aae6fcc7d9bb 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 119:aae6fcc7d9bb 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 119:aae6fcc7d9bb 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 119:aae6fcc7d9bb 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 119:aae6fcc7d9bb 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 119:aae6fcc7d9bb 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 119:aae6fcc7d9bb 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 119:aae6fcc7d9bb 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 1120 } MPU_Type;
Kojto 119:aae6fcc7d9bb 1121
Kojto 119:aae6fcc7d9bb 1122 /* MPU Type Register */
Kojto 119:aae6fcc7d9bb 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 119:aae6fcc7d9bb 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 119:aae6fcc7d9bb 1125
Kojto 119:aae6fcc7d9bb 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 119:aae6fcc7d9bb 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 119:aae6fcc7d9bb 1128
Kojto 119:aae6fcc7d9bb 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 119:aae6fcc7d9bb 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 119:aae6fcc7d9bb 1131
Kojto 119:aae6fcc7d9bb 1132 /* MPU Control Register */
Kojto 119:aae6fcc7d9bb 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 119:aae6fcc7d9bb 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 119:aae6fcc7d9bb 1135
Kojto 119:aae6fcc7d9bb 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 119:aae6fcc7d9bb 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 119:aae6fcc7d9bb 1138
Kojto 119:aae6fcc7d9bb 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 119:aae6fcc7d9bb 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 119:aae6fcc7d9bb 1141
Kojto 119:aae6fcc7d9bb 1142 /* MPU Region Number Register */
Kojto 119:aae6fcc7d9bb 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 119:aae6fcc7d9bb 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 119:aae6fcc7d9bb 1145
Kojto 119:aae6fcc7d9bb 1146 /* MPU Region Base Address Register */
Kojto 119:aae6fcc7d9bb 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 119:aae6fcc7d9bb 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 119:aae6fcc7d9bb 1149
Kojto 119:aae6fcc7d9bb 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 119:aae6fcc7d9bb 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 119:aae6fcc7d9bb 1152
Kojto 119:aae6fcc7d9bb 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 119:aae6fcc7d9bb 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 119:aae6fcc7d9bb 1155
Kojto 119:aae6fcc7d9bb 1156 /* MPU Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 119:aae6fcc7d9bb 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 119:aae6fcc7d9bb 1159
Kojto 119:aae6fcc7d9bb 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 119:aae6fcc7d9bb 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 119:aae6fcc7d9bb 1162
Kojto 119:aae6fcc7d9bb 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 119:aae6fcc7d9bb 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 119:aae6fcc7d9bb 1165
Kojto 119:aae6fcc7d9bb 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 119:aae6fcc7d9bb 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 119:aae6fcc7d9bb 1168
Kojto 119:aae6fcc7d9bb 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 119:aae6fcc7d9bb 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 119:aae6fcc7d9bb 1171
Kojto 119:aae6fcc7d9bb 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 119:aae6fcc7d9bb 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 119:aae6fcc7d9bb 1174
Kojto 119:aae6fcc7d9bb 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 119:aae6fcc7d9bb 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 119:aae6fcc7d9bb 1177
Kojto 119:aae6fcc7d9bb 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 119:aae6fcc7d9bb 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 119:aae6fcc7d9bb 1180
Kojto 119:aae6fcc7d9bb 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 119:aae6fcc7d9bb 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 119:aae6fcc7d9bb 1183
Kojto 119:aae6fcc7d9bb 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 119:aae6fcc7d9bb 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 119:aae6fcc7d9bb 1186
Kojto 119:aae6fcc7d9bb 1187 /*@} end of group CMSIS_MPU */
Kojto 119:aae6fcc7d9bb 1188 #endif
Kojto 119:aae6fcc7d9bb 1189
Kojto 119:aae6fcc7d9bb 1190
Kojto 119:aae6fcc7d9bb 1191 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 119:aae6fcc7d9bb 1193 \brief Type definitions for the Core Debug Registers
Kojto 119:aae6fcc7d9bb 1194 @{
Kojto 119:aae6fcc7d9bb 1195 */
Kojto 119:aae6fcc7d9bb 1196
Kojto 119:aae6fcc7d9bb 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 119:aae6fcc7d9bb 1198 */
Kojto 119:aae6fcc7d9bb 1199 typedef struct
Kojto 119:aae6fcc7d9bb 1200 {
Kojto 119:aae6fcc7d9bb 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 119:aae6fcc7d9bb 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 119:aae6fcc7d9bb 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 119:aae6fcc7d9bb 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 119:aae6fcc7d9bb 1205 } CoreDebug_Type;
Kojto 119:aae6fcc7d9bb 1206
Kojto 119:aae6fcc7d9bb 1207 /* Debug Halting Control and Status Register */
Kojto 119:aae6fcc7d9bb 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 119:aae6fcc7d9bb 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 119:aae6fcc7d9bb 1210
Kojto 119:aae6fcc7d9bb 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 119:aae6fcc7d9bb 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 119:aae6fcc7d9bb 1213
Kojto 119:aae6fcc7d9bb 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 119:aae6fcc7d9bb 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 119:aae6fcc7d9bb 1216
Kojto 119:aae6fcc7d9bb 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 119:aae6fcc7d9bb 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 119:aae6fcc7d9bb 1219
Kojto 119:aae6fcc7d9bb 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 119:aae6fcc7d9bb 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 119:aae6fcc7d9bb 1222
Kojto 119:aae6fcc7d9bb 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 119:aae6fcc7d9bb 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 119:aae6fcc7d9bb 1225
Kojto 119:aae6fcc7d9bb 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 119:aae6fcc7d9bb 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 119:aae6fcc7d9bb 1228
Kojto 119:aae6fcc7d9bb 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 119:aae6fcc7d9bb 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 119:aae6fcc7d9bb 1231
Kojto 119:aae6fcc7d9bb 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 119:aae6fcc7d9bb 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 119:aae6fcc7d9bb 1234
Kojto 119:aae6fcc7d9bb 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 119:aae6fcc7d9bb 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 119:aae6fcc7d9bb 1237
Kojto 119:aae6fcc7d9bb 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 119:aae6fcc7d9bb 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 119:aae6fcc7d9bb 1240
Kojto 119:aae6fcc7d9bb 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 119:aae6fcc7d9bb 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 119:aae6fcc7d9bb 1243
Kojto 119:aae6fcc7d9bb 1244 /* Debug Core Register Selector Register */
Kojto 119:aae6fcc7d9bb 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 119:aae6fcc7d9bb 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 119:aae6fcc7d9bb 1247
Kojto 119:aae6fcc7d9bb 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 119:aae6fcc7d9bb 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 119:aae6fcc7d9bb 1250
Kojto 119:aae6fcc7d9bb 1251 /* Debug Exception and Monitor Control Register */
Kojto 119:aae6fcc7d9bb 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 119:aae6fcc7d9bb 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 119:aae6fcc7d9bb 1254
Kojto 119:aae6fcc7d9bb 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 119:aae6fcc7d9bb 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 119:aae6fcc7d9bb 1257
Kojto 119:aae6fcc7d9bb 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 119:aae6fcc7d9bb 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 119:aae6fcc7d9bb 1260
Kojto 119:aae6fcc7d9bb 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 119:aae6fcc7d9bb 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 119:aae6fcc7d9bb 1263
Kojto 119:aae6fcc7d9bb 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 119:aae6fcc7d9bb 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 119:aae6fcc7d9bb 1266
Kojto 119:aae6fcc7d9bb 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 119:aae6fcc7d9bb 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 119:aae6fcc7d9bb 1269
Kojto 119:aae6fcc7d9bb 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 119:aae6fcc7d9bb 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 119:aae6fcc7d9bb 1272
Kojto 119:aae6fcc7d9bb 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 119:aae6fcc7d9bb 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 119:aae6fcc7d9bb 1275
Kojto 119:aae6fcc7d9bb 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 119:aae6fcc7d9bb 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 119:aae6fcc7d9bb 1278
Kojto 119:aae6fcc7d9bb 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 119:aae6fcc7d9bb 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 119:aae6fcc7d9bb 1281
Kojto 119:aae6fcc7d9bb 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 119:aae6fcc7d9bb 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 119:aae6fcc7d9bb 1284
Kojto 119:aae6fcc7d9bb 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 119:aae6fcc7d9bb 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 119:aae6fcc7d9bb 1287
Kojto 119:aae6fcc7d9bb 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 119:aae6fcc7d9bb 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 119:aae6fcc7d9bb 1290
Kojto 119:aae6fcc7d9bb 1291 /*@} end of group CMSIS_CoreDebug */
Kojto 119:aae6fcc7d9bb 1292
Kojto 119:aae6fcc7d9bb 1293
Kojto 119:aae6fcc7d9bb 1294 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 1295 \defgroup CMSIS_core_base Core Definitions
Kojto 119:aae6fcc7d9bb 1296 \brief Definitions for base addresses, unions, and structures.
Kojto 119:aae6fcc7d9bb 1297 @{
Kojto 119:aae6fcc7d9bb 1298 */
Kojto 119:aae6fcc7d9bb 1299
Kojto 119:aae6fcc7d9bb 1300 /* Memory mapping of Cortex-M3 Hardware */
Kojto 119:aae6fcc7d9bb 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 119:aae6fcc7d9bb 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 119:aae6fcc7d9bb 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 119:aae6fcc7d9bb 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 119:aae6fcc7d9bb 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 119:aae6fcc7d9bb 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 119:aae6fcc7d9bb 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 119:aae6fcc7d9bb 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 119:aae6fcc7d9bb 1309
Kojto 119:aae6fcc7d9bb 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 119:aae6fcc7d9bb 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 119:aae6fcc7d9bb 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 119:aae6fcc7d9bb 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 119:aae6fcc7d9bb 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 119:aae6fcc7d9bb 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 119:aae6fcc7d9bb 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 119:aae6fcc7d9bb 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 119:aae6fcc7d9bb 1318
Kojto 119:aae6fcc7d9bb 1319 #if (__MPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 119:aae6fcc7d9bb 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 119:aae6fcc7d9bb 1322 #endif
Kojto 119:aae6fcc7d9bb 1323
Kojto 119:aae6fcc7d9bb 1324 /*@} */
Kojto 119:aae6fcc7d9bb 1325
Kojto 119:aae6fcc7d9bb 1326
Kojto 119:aae6fcc7d9bb 1327
Kojto 119:aae6fcc7d9bb 1328 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 1329 * Hardware Abstraction Layer
Kojto 119:aae6fcc7d9bb 1330 Core Function Interface contains:
Kojto 119:aae6fcc7d9bb 1331 - Core NVIC Functions
Kojto 119:aae6fcc7d9bb 1332 - Core SysTick Functions
Kojto 119:aae6fcc7d9bb 1333 - Core Debug Functions
Kojto 119:aae6fcc7d9bb 1334 - Core Register Access Functions
Kojto 119:aae6fcc7d9bb 1335 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 119:aae6fcc7d9bb 1337 */
Kojto 119:aae6fcc7d9bb 1338
Kojto 119:aae6fcc7d9bb 1339
Kojto 119:aae6fcc7d9bb 1340
Kojto 119:aae6fcc7d9bb 1341 /* ########################## NVIC functions #################################### */
Kojto 119:aae6fcc7d9bb 1342 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 119:aae6fcc7d9bb 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 119:aae6fcc7d9bb 1345 @{
Kojto 119:aae6fcc7d9bb 1346 */
Kojto 119:aae6fcc7d9bb 1347
<> 127:25aea2a3f4e3 1348 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1351 #endif
<> 127:25aea2a3f4e3 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1353 #else
<> 127:25aea2a3f4e3 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 127:25aea2a3f4e3 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1361 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1362 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1363 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1364 #define NVIC_SystemReset __NVIC_SystemReset
<> 127:25aea2a3f4e3 1365 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1366
<> 127:25aea2a3f4e3 1367 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1370 #endif
<> 127:25aea2a3f4e3 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1372 #else
<> 127:25aea2a3f4e3 1373 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1374 #define NVIC_GetVector __NVIC_GetVector
<> 127:25aea2a3f4e3 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 127:25aea2a3f4e3 1376
Kojto 119:aae6fcc7d9bb 1377 /** \brief Set Priority Grouping
Kojto 119:aae6fcc7d9bb 1378
Kojto 119:aae6fcc7d9bb 1379 The function sets the priority grouping field using the required unlock sequence.
Kojto 119:aae6fcc7d9bb 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 119:aae6fcc7d9bb 1381 Only values from 0..7 are used.
Kojto 119:aae6fcc7d9bb 1382 In case of a conflict between priority grouping and available
Kojto 119:aae6fcc7d9bb 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 119:aae6fcc7d9bb 1384
Kojto 119:aae6fcc7d9bb 1385 \param [in] PriorityGroup Priority grouping field.
Kojto 119:aae6fcc7d9bb 1386 */
<> 127:25aea2a3f4e3 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 119:aae6fcc7d9bb 1388 {
Kojto 119:aae6fcc7d9bb 1389 uint32_t reg_value;
Kojto 119:aae6fcc7d9bb 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 119:aae6fcc7d9bb 1391
Kojto 119:aae6fcc7d9bb 1392 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 119:aae6fcc7d9bb 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 119:aae6fcc7d9bb 1394 reg_value = (reg_value |
Kojto 119:aae6fcc7d9bb 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 119:aae6fcc7d9bb 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 119:aae6fcc7d9bb 1397 SCB->AIRCR = reg_value;
Kojto 119:aae6fcc7d9bb 1398 }
Kojto 119:aae6fcc7d9bb 1399
Kojto 119:aae6fcc7d9bb 1400
Kojto 119:aae6fcc7d9bb 1401 /** \brief Get Priority Grouping
Kojto 119:aae6fcc7d9bb 1402
Kojto 119:aae6fcc7d9bb 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 119:aae6fcc7d9bb 1404
Kojto 119:aae6fcc7d9bb 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 119:aae6fcc7d9bb 1406 */
<> 127:25aea2a3f4e3 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Kojto 119:aae6fcc7d9bb 1408 {
Kojto 119:aae6fcc7d9bb 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 119:aae6fcc7d9bb 1410 }
Kojto 119:aae6fcc7d9bb 1411
Kojto 119:aae6fcc7d9bb 1412
Kojto 119:aae6fcc7d9bb 1413 /** \brief Enable External Interrupt
Kojto 119:aae6fcc7d9bb 1414
Kojto 119:aae6fcc7d9bb 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 119:aae6fcc7d9bb 1416
Kojto 119:aae6fcc7d9bb 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 1418 */
<> 127:25aea2a3f4e3 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1420 {
Kojto 119:aae6fcc7d9bb 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 1422 }
Kojto 119:aae6fcc7d9bb 1423
Kojto 119:aae6fcc7d9bb 1424
Kojto 119:aae6fcc7d9bb 1425 /** \brief Disable External Interrupt
Kojto 119:aae6fcc7d9bb 1426
Kojto 119:aae6fcc7d9bb 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 119:aae6fcc7d9bb 1428
Kojto 119:aae6fcc7d9bb 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 1430 */
<> 127:25aea2a3f4e3 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1432 {
Kojto 119:aae6fcc7d9bb 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1434 __DSB();
<> 131:faff56e089b2 1435 __ISB();
Kojto 119:aae6fcc7d9bb 1436 }
Kojto 119:aae6fcc7d9bb 1437
Kojto 119:aae6fcc7d9bb 1438
Kojto 119:aae6fcc7d9bb 1439 /** \brief Get Pending Interrupt
Kojto 119:aae6fcc7d9bb 1440
Kojto 119:aae6fcc7d9bb 1441 The function reads the pending register in the NVIC and returns the pending bit
Kojto 119:aae6fcc7d9bb 1442 for the specified interrupt.
Kojto 119:aae6fcc7d9bb 1443
Kojto 119:aae6fcc7d9bb 1444 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 1445
Kojto 119:aae6fcc7d9bb 1446 \return 0 Interrupt status is not pending.
Kojto 119:aae6fcc7d9bb 1447 \return 1 Interrupt status is pending.
Kojto 119:aae6fcc7d9bb 1448 */
<> 127:25aea2a3f4e3 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1450 {
Kojto 119:aae6fcc7d9bb 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 119:aae6fcc7d9bb 1452 }
Kojto 119:aae6fcc7d9bb 1453
Kojto 119:aae6fcc7d9bb 1454
Kojto 119:aae6fcc7d9bb 1455 /** \brief Set Pending Interrupt
Kojto 119:aae6fcc7d9bb 1456
Kojto 119:aae6fcc7d9bb 1457 The function sets the pending bit of an external interrupt.
Kojto 119:aae6fcc7d9bb 1458
Kojto 119:aae6fcc7d9bb 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 1460 */
<> 127:25aea2a3f4e3 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1462 {
Kojto 119:aae6fcc7d9bb 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 1464 }
Kojto 119:aae6fcc7d9bb 1465
Kojto 119:aae6fcc7d9bb 1466
Kojto 119:aae6fcc7d9bb 1467 /** \brief Clear Pending Interrupt
Kojto 119:aae6fcc7d9bb 1468
Kojto 119:aae6fcc7d9bb 1469 The function clears the pending bit of an external interrupt.
Kojto 119:aae6fcc7d9bb 1470
Kojto 119:aae6fcc7d9bb 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 1472 */
<> 127:25aea2a3f4e3 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1474 {
Kojto 119:aae6fcc7d9bb 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 1476 }
Kojto 119:aae6fcc7d9bb 1477
Kojto 119:aae6fcc7d9bb 1478
Kojto 119:aae6fcc7d9bb 1479 /** \brief Get Active Interrupt
Kojto 119:aae6fcc7d9bb 1480
Kojto 119:aae6fcc7d9bb 1481 The function reads the active register in NVIC and returns the active bit.
Kojto 119:aae6fcc7d9bb 1482
Kojto 119:aae6fcc7d9bb 1483 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 1484
Kojto 119:aae6fcc7d9bb 1485 \return 0 Interrupt status is not active.
Kojto 119:aae6fcc7d9bb 1486 \return 1 Interrupt status is active.
Kojto 119:aae6fcc7d9bb 1487 */
<> 127:25aea2a3f4e3 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1489 {
Kojto 119:aae6fcc7d9bb 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 119:aae6fcc7d9bb 1491 }
Kojto 119:aae6fcc7d9bb 1492
Kojto 119:aae6fcc7d9bb 1493
Kojto 119:aae6fcc7d9bb 1494 /** \brief Set Interrupt Priority
Kojto 119:aae6fcc7d9bb 1495
Kojto 119:aae6fcc7d9bb 1496 The function sets the priority of an interrupt.
Kojto 119:aae6fcc7d9bb 1497
Kojto 119:aae6fcc7d9bb 1498 \note The priority cannot be set for every core interrupt.
Kojto 119:aae6fcc7d9bb 1499
Kojto 119:aae6fcc7d9bb 1500 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 1501 \param [in] priority Priority to set.
Kojto 119:aae6fcc7d9bb 1502 */
<> 127:25aea2a3f4e3 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 119:aae6fcc7d9bb 1504 {
Kojto 119:aae6fcc7d9bb 1505 if((int32_t)IRQn < 0) {
Kojto 119:aae6fcc7d9bb 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 119:aae6fcc7d9bb 1507 }
Kojto 119:aae6fcc7d9bb 1508 else {
Kojto 119:aae6fcc7d9bb 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 119:aae6fcc7d9bb 1510 }
Kojto 119:aae6fcc7d9bb 1511 }
Kojto 119:aae6fcc7d9bb 1512
Kojto 119:aae6fcc7d9bb 1513
Kojto 119:aae6fcc7d9bb 1514 /** \brief Get Interrupt Priority
Kojto 119:aae6fcc7d9bb 1515
Kojto 119:aae6fcc7d9bb 1516 The function reads the priority of an interrupt. The interrupt
Kojto 119:aae6fcc7d9bb 1517 number can be positive to specify an external (device specific)
Kojto 119:aae6fcc7d9bb 1518 interrupt, or negative to specify an internal (core) interrupt.
Kojto 119:aae6fcc7d9bb 1519
Kojto 119:aae6fcc7d9bb 1520
Kojto 119:aae6fcc7d9bb 1521 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 119:aae6fcc7d9bb 1523 priority bits of the microcontroller.
Kojto 119:aae6fcc7d9bb 1524 */
<> 127:25aea2a3f4e3 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 1526 {
Kojto 119:aae6fcc7d9bb 1527
Kojto 119:aae6fcc7d9bb 1528 if((int32_t)IRQn < 0) {
Kojto 119:aae6fcc7d9bb 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 119:aae6fcc7d9bb 1530 }
Kojto 119:aae6fcc7d9bb 1531 else {
Kojto 119:aae6fcc7d9bb 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 119:aae6fcc7d9bb 1533 }
Kojto 119:aae6fcc7d9bb 1534 }
Kojto 119:aae6fcc7d9bb 1535
Kojto 119:aae6fcc7d9bb 1536
Kojto 119:aae6fcc7d9bb 1537 /** \brief Encode Priority
Kojto 119:aae6fcc7d9bb 1538
Kojto 119:aae6fcc7d9bb 1539 The function encodes the priority for an interrupt with the given priority group,
Kojto 119:aae6fcc7d9bb 1540 preemptive priority value, and subpriority value.
Kojto 119:aae6fcc7d9bb 1541 In case of a conflict between priority grouping and available
Kojto 119:aae6fcc7d9bb 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 119:aae6fcc7d9bb 1543
Kojto 119:aae6fcc7d9bb 1544 \param [in] PriorityGroup Used priority group.
Kojto 119:aae6fcc7d9bb 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 119:aae6fcc7d9bb 1546 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 119:aae6fcc7d9bb 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 119:aae6fcc7d9bb 1548 */
Kojto 119:aae6fcc7d9bb 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 119:aae6fcc7d9bb 1550 {
Kojto 119:aae6fcc7d9bb 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 119:aae6fcc7d9bb 1552 uint32_t PreemptPriorityBits;
Kojto 119:aae6fcc7d9bb 1553 uint32_t SubPriorityBits;
Kojto 119:aae6fcc7d9bb 1554
Kojto 119:aae6fcc7d9bb 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 119:aae6fcc7d9bb 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 119:aae6fcc7d9bb 1557
Kojto 119:aae6fcc7d9bb 1558 return (
Kojto 119:aae6fcc7d9bb 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 119:aae6fcc7d9bb 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 119:aae6fcc7d9bb 1561 );
Kojto 119:aae6fcc7d9bb 1562 }
Kojto 119:aae6fcc7d9bb 1563
Kojto 119:aae6fcc7d9bb 1564
Kojto 119:aae6fcc7d9bb 1565 /** \brief Decode Priority
Kojto 119:aae6fcc7d9bb 1566
Kojto 119:aae6fcc7d9bb 1567 The function decodes an interrupt priority value with a given priority group to
Kojto 119:aae6fcc7d9bb 1568 preemptive priority value and subpriority value.
Kojto 119:aae6fcc7d9bb 1569 In case of a conflict between priority grouping and available
Kojto 119:aae6fcc7d9bb 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 119:aae6fcc7d9bb 1571
Kojto 119:aae6fcc7d9bb 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 119:aae6fcc7d9bb 1573 \param [in] PriorityGroup Used priority group.
Kojto 119:aae6fcc7d9bb 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 119:aae6fcc7d9bb 1575 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 119:aae6fcc7d9bb 1576 */
Kojto 119:aae6fcc7d9bb 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 119:aae6fcc7d9bb 1578 {
Kojto 119:aae6fcc7d9bb 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 119:aae6fcc7d9bb 1580 uint32_t PreemptPriorityBits;
Kojto 119:aae6fcc7d9bb 1581 uint32_t SubPriorityBits;
Kojto 119:aae6fcc7d9bb 1582
Kojto 119:aae6fcc7d9bb 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 119:aae6fcc7d9bb 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 119:aae6fcc7d9bb 1585
Kojto 119:aae6fcc7d9bb 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 119:aae6fcc7d9bb 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 119:aae6fcc7d9bb 1588 }
Kojto 119:aae6fcc7d9bb 1589
Kojto 119:aae6fcc7d9bb 1590
Kojto 119:aae6fcc7d9bb 1591 /** \brief System Reset
Kojto 119:aae6fcc7d9bb 1592
Kojto 119:aae6fcc7d9bb 1593 The function initiates a system reset request to reset the MCU.
Kojto 119:aae6fcc7d9bb 1594 */
<> 128:9bcdf88f62b0 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
Kojto 119:aae6fcc7d9bb 1596 {
Kojto 119:aae6fcc7d9bb 1597 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 119:aae6fcc7d9bb 1598 buffered write are completed before reset */
Kojto 119:aae6fcc7d9bb 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 119:aae6fcc7d9bb 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 119:aae6fcc7d9bb 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 119:aae6fcc7d9bb 1602 __DSB(); /* Ensure completion of memory access */
Kojto 119:aae6fcc7d9bb 1603 while(1) { __NOP(); } /* wait until reset */
Kojto 119:aae6fcc7d9bb 1604 }
Kojto 119:aae6fcc7d9bb 1605
Kojto 119:aae6fcc7d9bb 1606 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 119:aae6fcc7d9bb 1607
Kojto 119:aae6fcc7d9bb 1608
Kojto 119:aae6fcc7d9bb 1609
Kojto 119:aae6fcc7d9bb 1610 /* ################################## SysTick function ############################################ */
Kojto 119:aae6fcc7d9bb 1611 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 119:aae6fcc7d9bb 1613 \brief Functions that configure the System.
Kojto 119:aae6fcc7d9bb 1614 @{
Kojto 119:aae6fcc7d9bb 1615 */
Kojto 119:aae6fcc7d9bb 1616
Kojto 119:aae6fcc7d9bb 1617 #if (__Vendor_SysTickConfig == 0)
Kojto 119:aae6fcc7d9bb 1618
Kojto 119:aae6fcc7d9bb 1619 /** \brief System Tick Configuration
Kojto 119:aae6fcc7d9bb 1620
Kojto 119:aae6fcc7d9bb 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 119:aae6fcc7d9bb 1622 Counter is in free running mode to generate periodic interrupts.
Kojto 119:aae6fcc7d9bb 1623
Kojto 119:aae6fcc7d9bb 1624 \param [in] ticks Number of ticks between two interrupts.
Kojto 119:aae6fcc7d9bb 1625
Kojto 119:aae6fcc7d9bb 1626 \return 0 Function succeeded.
Kojto 119:aae6fcc7d9bb 1627 \return 1 Function failed.
Kojto 119:aae6fcc7d9bb 1628
Kojto 119:aae6fcc7d9bb 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 119:aae6fcc7d9bb 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 119:aae6fcc7d9bb 1631 must contain a vendor-specific implementation of this function.
Kojto 119:aae6fcc7d9bb 1632
Kojto 119:aae6fcc7d9bb 1633 */
Kojto 119:aae6fcc7d9bb 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 119:aae6fcc7d9bb 1635 {
Kojto 119:aae6fcc7d9bb 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 119:aae6fcc7d9bb 1637
Kojto 119:aae6fcc7d9bb 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 119:aae6fcc7d9bb 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 119:aae6fcc7d9bb 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 119:aae6fcc7d9bb 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 119:aae6fcc7d9bb 1642 SysTick_CTRL_TICKINT_Msk |
Kojto 119:aae6fcc7d9bb 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 119:aae6fcc7d9bb 1644 return (0UL); /* Function successful */
Kojto 119:aae6fcc7d9bb 1645 }
Kojto 119:aae6fcc7d9bb 1646
Kojto 119:aae6fcc7d9bb 1647 #endif
Kojto 119:aae6fcc7d9bb 1648
Kojto 119:aae6fcc7d9bb 1649 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 119:aae6fcc7d9bb 1650
Kojto 119:aae6fcc7d9bb 1651
Kojto 119:aae6fcc7d9bb 1652
Kojto 119:aae6fcc7d9bb 1653 /* ##################################### Debug In/Output function ########################################### */
Kojto 119:aae6fcc7d9bb 1654 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 119:aae6fcc7d9bb 1656 \brief Functions that access the ITM debug interface.
Kojto 119:aae6fcc7d9bb 1657 @{
Kojto 119:aae6fcc7d9bb 1658 */
Kojto 119:aae6fcc7d9bb 1659
Kojto 119:aae6fcc7d9bb 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 119:aae6fcc7d9bb 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 119:aae6fcc7d9bb 1662
Kojto 119:aae6fcc7d9bb 1663
Kojto 119:aae6fcc7d9bb 1664 /** \brief ITM Send Character
Kojto 119:aae6fcc7d9bb 1665
Kojto 119:aae6fcc7d9bb 1666 The function transmits a character via the ITM channel 0, and
Kojto 119:aae6fcc7d9bb 1667 \li Just returns when no debugger is connected that has booked the output.
Kojto 119:aae6fcc7d9bb 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 119:aae6fcc7d9bb 1669
Kojto 119:aae6fcc7d9bb 1670 \param [in] ch Character to transmit.
Kojto 119:aae6fcc7d9bb 1671
Kojto 119:aae6fcc7d9bb 1672 \returns Character to transmit.
Kojto 119:aae6fcc7d9bb 1673 */
Kojto 119:aae6fcc7d9bb 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 119:aae6fcc7d9bb 1675 {
Kojto 119:aae6fcc7d9bb 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 119:aae6fcc7d9bb 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 119:aae6fcc7d9bb 1678 {
Kojto 119:aae6fcc7d9bb 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 119:aae6fcc7d9bb 1680 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 119:aae6fcc7d9bb 1681 }
Kojto 119:aae6fcc7d9bb 1682 return (ch);
Kojto 119:aae6fcc7d9bb 1683 }
Kojto 119:aae6fcc7d9bb 1684
Kojto 119:aae6fcc7d9bb 1685
Kojto 119:aae6fcc7d9bb 1686 /** \brief ITM Receive Character
Kojto 119:aae6fcc7d9bb 1687
Kojto 119:aae6fcc7d9bb 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 119:aae6fcc7d9bb 1689
Kojto 119:aae6fcc7d9bb 1690 \return Received character.
Kojto 119:aae6fcc7d9bb 1691 \return -1 No character pending.
Kojto 119:aae6fcc7d9bb 1692 */
Kojto 119:aae6fcc7d9bb 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 119:aae6fcc7d9bb 1694 int32_t ch = -1; /* no character available */
Kojto 119:aae6fcc7d9bb 1695
Kojto 119:aae6fcc7d9bb 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 119:aae6fcc7d9bb 1697 ch = ITM_RxBuffer;
Kojto 119:aae6fcc7d9bb 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 119:aae6fcc7d9bb 1699 }
Kojto 119:aae6fcc7d9bb 1700
Kojto 119:aae6fcc7d9bb 1701 return (ch);
Kojto 119:aae6fcc7d9bb 1702 }
Kojto 119:aae6fcc7d9bb 1703
Kojto 119:aae6fcc7d9bb 1704
Kojto 119:aae6fcc7d9bb 1705 /** \brief ITM Check Character
Kojto 119:aae6fcc7d9bb 1706
Kojto 119:aae6fcc7d9bb 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 119:aae6fcc7d9bb 1708
Kojto 119:aae6fcc7d9bb 1709 \return 0 No character available.
Kojto 119:aae6fcc7d9bb 1710 \return 1 Character available.
Kojto 119:aae6fcc7d9bb 1711 */
Kojto 119:aae6fcc7d9bb 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 119:aae6fcc7d9bb 1713
Kojto 119:aae6fcc7d9bb 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 119:aae6fcc7d9bb 1715 return (0); /* no character available */
Kojto 119:aae6fcc7d9bb 1716 } else {
Kojto 119:aae6fcc7d9bb 1717 return (1); /* character available */
Kojto 119:aae6fcc7d9bb 1718 }
Kojto 119:aae6fcc7d9bb 1719 }
Kojto 119:aae6fcc7d9bb 1720
Kojto 119:aae6fcc7d9bb 1721 /*@} end of CMSIS_core_DebugFunctions */
Kojto 119:aae6fcc7d9bb 1722
Kojto 119:aae6fcc7d9bb 1723
Kojto 119:aae6fcc7d9bb 1724
Kojto 119:aae6fcc7d9bb 1725
Kojto 119:aae6fcc7d9bb 1726 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 1727 }
Kojto 119:aae6fcc7d9bb 1728 #endif
Kojto 119:aae6fcc7d9bb 1729
Kojto 119:aae6fcc7d9bb 1730 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 119:aae6fcc7d9bb 1731
Kojto 119:aae6fcc7d9bb 1732 #endif /* __CMSIS_GENERIC */