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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L031K6/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 119:aae6fcc7d9bb 1 /**************************************************************************//**
Kojto 119:aae6fcc7d9bb 2 * @file core_cm0plus.h
Kojto 119:aae6fcc7d9bb 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 119:aae6fcc7d9bb 4 * @version V4.10
Kojto 119:aae6fcc7d9bb 5 * @date 18. March 2015
Kojto 119:aae6fcc7d9bb 6 *
Kojto 119:aae6fcc7d9bb 7 * @note
Kojto 119:aae6fcc7d9bb 8 *
Kojto 119:aae6fcc7d9bb 9 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 119:aae6fcc7d9bb 11
Kojto 119:aae6fcc7d9bb 12 All rights reserved.
Kojto 119:aae6fcc7d9bb 13 Redistribution and use in source and binary forms, with or without
Kojto 119:aae6fcc7d9bb 14 modification, are permitted provided that the following conditions are met:
Kojto 119:aae6fcc7d9bb 15 - Redistributions of source code must retain the above copyright
Kojto 119:aae6fcc7d9bb 16 notice, this list of conditions and the following disclaimer.
Kojto 119:aae6fcc7d9bb 17 - Redistributions in binary form must reproduce the above copyright
Kojto 119:aae6fcc7d9bb 18 notice, this list of conditions and the following disclaimer in the
Kojto 119:aae6fcc7d9bb 19 documentation and/or other materials provided with the distribution.
Kojto 119:aae6fcc7d9bb 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 119:aae6fcc7d9bb 21 to endorse or promote products derived from this software without
Kojto 119:aae6fcc7d9bb 22 specific prior written permission.
Kojto 119:aae6fcc7d9bb 23 *
Kojto 119:aae6fcc7d9bb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 119:aae6fcc7d9bb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 119:aae6fcc7d9bb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 119:aae6fcc7d9bb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 119:aae6fcc7d9bb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 119:aae6fcc7d9bb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 119:aae6fcc7d9bb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 119:aae6fcc7d9bb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 119:aae6fcc7d9bb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 119:aae6fcc7d9bb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 119:aae6fcc7d9bb 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 119:aae6fcc7d9bb 35 ---------------------------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 36
Kojto 119:aae6fcc7d9bb 37
Kojto 119:aae6fcc7d9bb 38 #if defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 119:aae6fcc7d9bb 40 #endif
Kojto 119:aae6fcc7d9bb 41
Kojto 119:aae6fcc7d9bb 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 119:aae6fcc7d9bb 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 119:aae6fcc7d9bb 44
Kojto 119:aae6fcc7d9bb 45 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 46 extern "C" {
Kojto 119:aae6fcc7d9bb 47 #endif
Kojto 119:aae6fcc7d9bb 48
Kojto 119:aae6fcc7d9bb 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 119:aae6fcc7d9bb 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 119:aae6fcc7d9bb 51
Kojto 119:aae6fcc7d9bb 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 119:aae6fcc7d9bb 53 Function definitions in header files are used to allow 'inlining'.
Kojto 119:aae6fcc7d9bb 54
Kojto 119:aae6fcc7d9bb 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 119:aae6fcc7d9bb 56 Unions are used for effective representation of core registers.
Kojto 119:aae6fcc7d9bb 57
Kojto 119:aae6fcc7d9bb 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 119:aae6fcc7d9bb 59 Function-like macros are used to allow more efficient code.
Kojto 119:aae6fcc7d9bb 60 */
Kojto 119:aae6fcc7d9bb 61
Kojto 119:aae6fcc7d9bb 62
Kojto 119:aae6fcc7d9bb 63 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 64 * CMSIS definitions
Kojto 119:aae6fcc7d9bb 65 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 66 /** \ingroup Cortex-M0+
Kojto 119:aae6fcc7d9bb 67 @{
Kojto 119:aae6fcc7d9bb 68 */
Kojto 119:aae6fcc7d9bb 69
Kojto 119:aae6fcc7d9bb 70 /* CMSIS CM0P definitions */
Kojto 119:aae6fcc7d9bb 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 119:aae6fcc7d9bb 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 119:aae6fcc7d9bb 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 119:aae6fcc7d9bb 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 119:aae6fcc7d9bb 75
Kojto 119:aae6fcc7d9bb 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 119:aae6fcc7d9bb 77
Kojto 119:aae6fcc7d9bb 78
Kojto 119:aae6fcc7d9bb 79 #if defined ( __CC_ARM )
Kojto 119:aae6fcc7d9bb 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 119:aae6fcc7d9bb 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 119:aae6fcc7d9bb 82 #define __STATIC_INLINE static __inline
Kojto 119:aae6fcc7d9bb 83
Kojto 119:aae6fcc7d9bb 84 #elif defined ( __GNUC__ )
Kojto 119:aae6fcc7d9bb 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 119:aae6fcc7d9bb 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 119:aae6fcc7d9bb 87 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 88
Kojto 119:aae6fcc7d9bb 89 #elif defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 119:aae6fcc7d9bb 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 119:aae6fcc7d9bb 92 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 93
Kojto 119:aae6fcc7d9bb 94 #elif defined ( __TMS470__ )
Kojto 119:aae6fcc7d9bb 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 119:aae6fcc7d9bb 96 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 97
Kojto 119:aae6fcc7d9bb 98 #elif defined ( __TASKING__ )
Kojto 119:aae6fcc7d9bb 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 119:aae6fcc7d9bb 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 119:aae6fcc7d9bb 101 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 102
Kojto 119:aae6fcc7d9bb 103 #elif defined ( __CSMC__ )
Kojto 119:aae6fcc7d9bb 104 #define __packed
Kojto 119:aae6fcc7d9bb 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 119:aae6fcc7d9bb 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 119:aae6fcc7d9bb 107 #define __STATIC_INLINE static inline
Kojto 119:aae6fcc7d9bb 108
Kojto 119:aae6fcc7d9bb 109 #endif
Kojto 119:aae6fcc7d9bb 110
Kojto 119:aae6fcc7d9bb 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 119:aae6fcc7d9bb 112 This core does not support an FPU at all
Kojto 119:aae6fcc7d9bb 113 */
Kojto 119:aae6fcc7d9bb 114 #define __FPU_USED 0
Kojto 119:aae6fcc7d9bb 115
Kojto 119:aae6fcc7d9bb 116 #if defined ( __CC_ARM )
Kojto 119:aae6fcc7d9bb 117 #if defined __TARGET_FPU_VFP
Kojto 119:aae6fcc7d9bb 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 119 #endif
Kojto 119:aae6fcc7d9bb 120
Kojto 119:aae6fcc7d9bb 121 #elif defined ( __GNUC__ )
Kojto 119:aae6fcc7d9bb 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 119:aae6fcc7d9bb 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 124 #endif
Kojto 119:aae6fcc7d9bb 125
Kojto 119:aae6fcc7d9bb 126 #elif defined ( __ICCARM__ )
Kojto 119:aae6fcc7d9bb 127 #if defined __ARMVFP__
Kojto 119:aae6fcc7d9bb 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 129 #endif
Kojto 119:aae6fcc7d9bb 130
Kojto 119:aae6fcc7d9bb 131 #elif defined ( __TMS470__ )
Kojto 119:aae6fcc7d9bb 132 #if defined __TI__VFP_SUPPORT____
Kojto 119:aae6fcc7d9bb 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 134 #endif
Kojto 119:aae6fcc7d9bb 135
Kojto 119:aae6fcc7d9bb 136 #elif defined ( __TASKING__ )
Kojto 119:aae6fcc7d9bb 137 #if defined __FPU_VFP__
Kojto 119:aae6fcc7d9bb 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 139 #endif
Kojto 119:aae6fcc7d9bb 140
Kojto 119:aae6fcc7d9bb 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 119:aae6fcc7d9bb 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 119:aae6fcc7d9bb 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 119:aae6fcc7d9bb 144 #endif
Kojto 119:aae6fcc7d9bb 145 #endif
Kojto 119:aae6fcc7d9bb 146
Kojto 119:aae6fcc7d9bb 147 #include <stdint.h> /* standard types definitions */
Kojto 119:aae6fcc7d9bb 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 119:aae6fcc7d9bb 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 119:aae6fcc7d9bb 150
Kojto 119:aae6fcc7d9bb 151 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 152 }
Kojto 119:aae6fcc7d9bb 153 #endif
Kojto 119:aae6fcc7d9bb 154
Kojto 119:aae6fcc7d9bb 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 119:aae6fcc7d9bb 156
Kojto 119:aae6fcc7d9bb 157 #ifndef __CMSIS_GENERIC
Kojto 119:aae6fcc7d9bb 158
Kojto 119:aae6fcc7d9bb 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 119:aae6fcc7d9bb 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 119:aae6fcc7d9bb 161
Kojto 119:aae6fcc7d9bb 162 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 163 extern "C" {
Kojto 119:aae6fcc7d9bb 164 #endif
Kojto 119:aae6fcc7d9bb 165
Kojto 119:aae6fcc7d9bb 166 /* check device defines and use defaults */
Kojto 119:aae6fcc7d9bb 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 119:aae6fcc7d9bb 168 #ifndef __CM0PLUS_REV
Kojto 119:aae6fcc7d9bb 169 #define __CM0PLUS_REV 0x0000
Kojto 119:aae6fcc7d9bb 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 171 #endif
Kojto 119:aae6fcc7d9bb 172
Kojto 119:aae6fcc7d9bb 173 #ifndef __MPU_PRESENT
Kojto 119:aae6fcc7d9bb 174 #define __MPU_PRESENT 0
Kojto 119:aae6fcc7d9bb 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 176 #endif
Kojto 119:aae6fcc7d9bb 177
Kojto 119:aae6fcc7d9bb 178 #ifndef __VTOR_PRESENT
Kojto 119:aae6fcc7d9bb 179 #define __VTOR_PRESENT 0
Kojto 119:aae6fcc7d9bb 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 181 #endif
Kojto 119:aae6fcc7d9bb 182
Kojto 119:aae6fcc7d9bb 183 #ifndef __NVIC_PRIO_BITS
Kojto 119:aae6fcc7d9bb 184 #define __NVIC_PRIO_BITS 2
Kojto 119:aae6fcc7d9bb 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 186 #endif
Kojto 119:aae6fcc7d9bb 187
Kojto 119:aae6fcc7d9bb 188 #ifndef __Vendor_SysTickConfig
Kojto 119:aae6fcc7d9bb 189 #define __Vendor_SysTickConfig 0
Kojto 119:aae6fcc7d9bb 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 119:aae6fcc7d9bb 191 #endif
Kojto 119:aae6fcc7d9bb 192 #endif
Kojto 119:aae6fcc7d9bb 193
Kojto 119:aae6fcc7d9bb 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 119:aae6fcc7d9bb 195 /**
Kojto 119:aae6fcc7d9bb 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 119:aae6fcc7d9bb 197
Kojto 119:aae6fcc7d9bb 198 <strong>IO Type Qualifiers</strong> are used
Kojto 119:aae6fcc7d9bb 199 \li to specify the access to peripheral variables.
Kojto 119:aae6fcc7d9bb 200 \li for automatic generation of peripheral register debug information.
Kojto 119:aae6fcc7d9bb 201 */
Kojto 119:aae6fcc7d9bb 202 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 119:aae6fcc7d9bb 204 #else
Kojto 119:aae6fcc7d9bb 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 119:aae6fcc7d9bb 206 #endif
Kojto 119:aae6fcc7d9bb 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 119:aae6fcc7d9bb 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 119:aae6fcc7d9bb 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 119:aae6fcc7d9bb 218 /*@} end of group Cortex-M0+ */
Kojto 119:aae6fcc7d9bb 219
Kojto 119:aae6fcc7d9bb 220
Kojto 119:aae6fcc7d9bb 221
Kojto 119:aae6fcc7d9bb 222 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 223 * Register Abstraction
Kojto 119:aae6fcc7d9bb 224 Core Register contain:
Kojto 119:aae6fcc7d9bb 225 - Core Register
Kojto 119:aae6fcc7d9bb 226 - Core NVIC Register
Kojto 119:aae6fcc7d9bb 227 - Core SCB Register
Kojto 119:aae6fcc7d9bb 228 - Core SysTick Register
Kojto 119:aae6fcc7d9bb 229 - Core MPU Register
Kojto 119:aae6fcc7d9bb 230 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 119:aae6fcc7d9bb 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 119:aae6fcc7d9bb 233 */
Kojto 119:aae6fcc7d9bb 234
Kojto 119:aae6fcc7d9bb 235 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 119:aae6fcc7d9bb 237 \brief Core Register type definitions.
Kojto 119:aae6fcc7d9bb 238 @{
Kojto 119:aae6fcc7d9bb 239 */
Kojto 119:aae6fcc7d9bb 240
Kojto 119:aae6fcc7d9bb 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 119:aae6fcc7d9bb 242 */
Kojto 119:aae6fcc7d9bb 243 typedef union
Kojto 119:aae6fcc7d9bb 244 {
Kojto 119:aae6fcc7d9bb 245 struct
Kojto 119:aae6fcc7d9bb 246 {
Kojto 119:aae6fcc7d9bb 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 119:aae6fcc7d9bb 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 119:aae6fcc7d9bb 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 119:aae6fcc7d9bb 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 119:aae6fcc7d9bb 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 119:aae6fcc7d9bb 252 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 253 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 254 } APSR_Type;
Kojto 119:aae6fcc7d9bb 255
Kojto 119:aae6fcc7d9bb 256 /* APSR Register Definitions */
Kojto 119:aae6fcc7d9bb 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 119:aae6fcc7d9bb 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 119:aae6fcc7d9bb 259
Kojto 119:aae6fcc7d9bb 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 119:aae6fcc7d9bb 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 119:aae6fcc7d9bb 262
Kojto 119:aae6fcc7d9bb 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 119:aae6fcc7d9bb 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 119:aae6fcc7d9bb 265
Kojto 119:aae6fcc7d9bb 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 119:aae6fcc7d9bb 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 119:aae6fcc7d9bb 268
Kojto 119:aae6fcc7d9bb 269
Kojto 119:aae6fcc7d9bb 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 119:aae6fcc7d9bb 271 */
Kojto 119:aae6fcc7d9bb 272 typedef union
Kojto 119:aae6fcc7d9bb 273 {
Kojto 119:aae6fcc7d9bb 274 struct
Kojto 119:aae6fcc7d9bb 275 {
Kojto 119:aae6fcc7d9bb 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 119:aae6fcc7d9bb 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 119:aae6fcc7d9bb 278 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 279 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 280 } IPSR_Type;
Kojto 119:aae6fcc7d9bb 281
Kojto 119:aae6fcc7d9bb 282 /* IPSR Register Definitions */
Kojto 119:aae6fcc7d9bb 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 119:aae6fcc7d9bb 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 119:aae6fcc7d9bb 285
Kojto 119:aae6fcc7d9bb 286
Kojto 119:aae6fcc7d9bb 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 119:aae6fcc7d9bb 288 */
Kojto 119:aae6fcc7d9bb 289 typedef union
Kojto 119:aae6fcc7d9bb 290 {
Kojto 119:aae6fcc7d9bb 291 struct
Kojto 119:aae6fcc7d9bb 292 {
Kojto 119:aae6fcc7d9bb 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 119:aae6fcc7d9bb 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 119:aae6fcc7d9bb 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 119:aae6fcc7d9bb 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 119:aae6fcc7d9bb 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 119:aae6fcc7d9bb 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 119:aae6fcc7d9bb 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 119:aae6fcc7d9bb 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 119:aae6fcc7d9bb 301 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 302 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 303 } xPSR_Type;
Kojto 119:aae6fcc7d9bb 304
Kojto 119:aae6fcc7d9bb 305 /* xPSR Register Definitions */
Kojto 119:aae6fcc7d9bb 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 119:aae6fcc7d9bb 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 119:aae6fcc7d9bb 308
Kojto 119:aae6fcc7d9bb 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 119:aae6fcc7d9bb 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 119:aae6fcc7d9bb 311
Kojto 119:aae6fcc7d9bb 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 119:aae6fcc7d9bb 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 119:aae6fcc7d9bb 314
Kojto 119:aae6fcc7d9bb 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 119:aae6fcc7d9bb 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 119:aae6fcc7d9bb 317
Kojto 119:aae6fcc7d9bb 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 119:aae6fcc7d9bb 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 119:aae6fcc7d9bb 320
Kojto 119:aae6fcc7d9bb 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 119:aae6fcc7d9bb 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 119:aae6fcc7d9bb 323
Kojto 119:aae6fcc7d9bb 324
Kojto 119:aae6fcc7d9bb 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 119:aae6fcc7d9bb 326 */
Kojto 119:aae6fcc7d9bb 327 typedef union
Kojto 119:aae6fcc7d9bb 328 {
Kojto 119:aae6fcc7d9bb 329 struct
Kojto 119:aae6fcc7d9bb 330 {
Kojto 119:aae6fcc7d9bb 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 119:aae6fcc7d9bb 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 119:aae6fcc7d9bb 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 119:aae6fcc7d9bb 334 } b; /*!< Structure used for bit access */
Kojto 119:aae6fcc7d9bb 335 uint32_t w; /*!< Type used for word access */
Kojto 119:aae6fcc7d9bb 336 } CONTROL_Type;
Kojto 119:aae6fcc7d9bb 337
Kojto 119:aae6fcc7d9bb 338 /* CONTROL Register Definitions */
Kojto 119:aae6fcc7d9bb 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 119:aae6fcc7d9bb 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 119:aae6fcc7d9bb 341
Kojto 119:aae6fcc7d9bb 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 119:aae6fcc7d9bb 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 119:aae6fcc7d9bb 344
Kojto 119:aae6fcc7d9bb 345 /*@} end of group CMSIS_CORE */
Kojto 119:aae6fcc7d9bb 346
Kojto 119:aae6fcc7d9bb 347
Kojto 119:aae6fcc7d9bb 348 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 119:aae6fcc7d9bb 350 \brief Type definitions for the NVIC Registers
Kojto 119:aae6fcc7d9bb 351 @{
Kojto 119:aae6fcc7d9bb 352 */
Kojto 119:aae6fcc7d9bb 353
Kojto 119:aae6fcc7d9bb 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 119:aae6fcc7d9bb 355 */
Kojto 119:aae6fcc7d9bb 356 typedef struct
Kojto 119:aae6fcc7d9bb 357 {
Kojto 119:aae6fcc7d9bb 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 119:aae6fcc7d9bb 359 uint32_t RESERVED0[31];
Kojto 119:aae6fcc7d9bb 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 119:aae6fcc7d9bb 361 uint32_t RSERVED1[31];
Kojto 119:aae6fcc7d9bb 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 119:aae6fcc7d9bb 363 uint32_t RESERVED2[31];
Kojto 119:aae6fcc7d9bb 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 119:aae6fcc7d9bb 365 uint32_t RESERVED3[31];
Kojto 119:aae6fcc7d9bb 366 uint32_t RESERVED4[64];
Kojto 119:aae6fcc7d9bb 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 119:aae6fcc7d9bb 368 } NVIC_Type;
Kojto 119:aae6fcc7d9bb 369
Kojto 119:aae6fcc7d9bb 370 /*@} end of group CMSIS_NVIC */
Kojto 119:aae6fcc7d9bb 371
Kojto 119:aae6fcc7d9bb 372
Kojto 119:aae6fcc7d9bb 373 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 119:aae6fcc7d9bb 375 \brief Type definitions for the System Control Block Registers
Kojto 119:aae6fcc7d9bb 376 @{
Kojto 119:aae6fcc7d9bb 377 */
Kojto 119:aae6fcc7d9bb 378
Kojto 119:aae6fcc7d9bb 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 119:aae6fcc7d9bb 380 */
Kojto 119:aae6fcc7d9bb 381 typedef struct
Kojto 119:aae6fcc7d9bb 382 {
Kojto 119:aae6fcc7d9bb 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 119:aae6fcc7d9bb 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 119:aae6fcc7d9bb 385 #if (__VTOR_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 119:aae6fcc7d9bb 387 #else
Kojto 119:aae6fcc7d9bb 388 uint32_t RESERVED0;
Kojto 119:aae6fcc7d9bb 389 #endif
Kojto 119:aae6fcc7d9bb 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 119:aae6fcc7d9bb 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 119:aae6fcc7d9bb 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 119:aae6fcc7d9bb 393 uint32_t RESERVED1;
Kojto 119:aae6fcc7d9bb 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 119:aae6fcc7d9bb 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 119:aae6fcc7d9bb 396 } SCB_Type;
Kojto 119:aae6fcc7d9bb 397
Kojto 119:aae6fcc7d9bb 398 /* SCB CPUID Register Definitions */
Kojto 119:aae6fcc7d9bb 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 119:aae6fcc7d9bb 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 119:aae6fcc7d9bb 401
Kojto 119:aae6fcc7d9bb 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 119:aae6fcc7d9bb 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 119:aae6fcc7d9bb 404
Kojto 119:aae6fcc7d9bb 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 119:aae6fcc7d9bb 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 119:aae6fcc7d9bb 407
Kojto 119:aae6fcc7d9bb 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 119:aae6fcc7d9bb 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 119:aae6fcc7d9bb 410
Kojto 119:aae6fcc7d9bb 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 119:aae6fcc7d9bb 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 119:aae6fcc7d9bb 413
Kojto 119:aae6fcc7d9bb 414 /* SCB Interrupt Control State Register Definitions */
Kojto 119:aae6fcc7d9bb 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 119:aae6fcc7d9bb 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 119:aae6fcc7d9bb 417
Kojto 119:aae6fcc7d9bb 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 119:aae6fcc7d9bb 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 119:aae6fcc7d9bb 420
Kojto 119:aae6fcc7d9bb 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 119:aae6fcc7d9bb 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 119:aae6fcc7d9bb 423
Kojto 119:aae6fcc7d9bb 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 119:aae6fcc7d9bb 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 119:aae6fcc7d9bb 426
Kojto 119:aae6fcc7d9bb 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 119:aae6fcc7d9bb 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 119:aae6fcc7d9bb 429
Kojto 119:aae6fcc7d9bb 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 119:aae6fcc7d9bb 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 119:aae6fcc7d9bb 432
Kojto 119:aae6fcc7d9bb 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 119:aae6fcc7d9bb 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 119:aae6fcc7d9bb 435
Kojto 119:aae6fcc7d9bb 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 119:aae6fcc7d9bb 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 119:aae6fcc7d9bb 438
Kojto 119:aae6fcc7d9bb 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 119:aae6fcc7d9bb 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 119:aae6fcc7d9bb 441
Kojto 119:aae6fcc7d9bb 442 #if (__VTOR_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 443 /* SCB Interrupt Control State Register Definitions */
Kojto 119:aae6fcc7d9bb 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 119:aae6fcc7d9bb 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 119:aae6fcc7d9bb 446 #endif
Kojto 119:aae6fcc7d9bb 447
Kojto 119:aae6fcc7d9bb 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 119:aae6fcc7d9bb 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 119:aae6fcc7d9bb 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 119:aae6fcc7d9bb 451
Kojto 119:aae6fcc7d9bb 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 119:aae6fcc7d9bb 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 119:aae6fcc7d9bb 454
Kojto 119:aae6fcc7d9bb 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 119:aae6fcc7d9bb 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 119:aae6fcc7d9bb 457
Kojto 119:aae6fcc7d9bb 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 119:aae6fcc7d9bb 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 119:aae6fcc7d9bb 460
Kojto 119:aae6fcc7d9bb 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 119:aae6fcc7d9bb 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 119:aae6fcc7d9bb 463
Kojto 119:aae6fcc7d9bb 464 /* SCB System Control Register Definitions */
Kojto 119:aae6fcc7d9bb 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 119:aae6fcc7d9bb 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 119:aae6fcc7d9bb 467
Kojto 119:aae6fcc7d9bb 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 119:aae6fcc7d9bb 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 119:aae6fcc7d9bb 470
Kojto 119:aae6fcc7d9bb 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 119:aae6fcc7d9bb 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 119:aae6fcc7d9bb 473
Kojto 119:aae6fcc7d9bb 474 /* SCB Configuration Control Register Definitions */
Kojto 119:aae6fcc7d9bb 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 119:aae6fcc7d9bb 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 119:aae6fcc7d9bb 477
Kojto 119:aae6fcc7d9bb 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 119:aae6fcc7d9bb 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 119:aae6fcc7d9bb 480
Kojto 119:aae6fcc7d9bb 481 /* SCB System Handler Control and State Register Definitions */
Kojto 119:aae6fcc7d9bb 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 119:aae6fcc7d9bb 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 119:aae6fcc7d9bb 484
Kojto 119:aae6fcc7d9bb 485 /*@} end of group CMSIS_SCB */
Kojto 119:aae6fcc7d9bb 486
Kojto 119:aae6fcc7d9bb 487
Kojto 119:aae6fcc7d9bb 488 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 119:aae6fcc7d9bb 490 \brief Type definitions for the System Timer Registers.
Kojto 119:aae6fcc7d9bb 491 @{
Kojto 119:aae6fcc7d9bb 492 */
Kojto 119:aae6fcc7d9bb 493
Kojto 119:aae6fcc7d9bb 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 119:aae6fcc7d9bb 495 */
Kojto 119:aae6fcc7d9bb 496 typedef struct
Kojto 119:aae6fcc7d9bb 497 {
Kojto 119:aae6fcc7d9bb 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 119:aae6fcc7d9bb 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 119:aae6fcc7d9bb 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 119:aae6fcc7d9bb 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 119:aae6fcc7d9bb 502 } SysTick_Type;
Kojto 119:aae6fcc7d9bb 503
Kojto 119:aae6fcc7d9bb 504 /* SysTick Control / Status Register Definitions */
Kojto 119:aae6fcc7d9bb 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 119:aae6fcc7d9bb 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 119:aae6fcc7d9bb 507
Kojto 119:aae6fcc7d9bb 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 119:aae6fcc7d9bb 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 119:aae6fcc7d9bb 510
Kojto 119:aae6fcc7d9bb 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 119:aae6fcc7d9bb 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 119:aae6fcc7d9bb 513
Kojto 119:aae6fcc7d9bb 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 119:aae6fcc7d9bb 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 119:aae6fcc7d9bb 516
Kojto 119:aae6fcc7d9bb 517 /* SysTick Reload Register Definitions */
Kojto 119:aae6fcc7d9bb 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 119:aae6fcc7d9bb 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 119:aae6fcc7d9bb 520
Kojto 119:aae6fcc7d9bb 521 /* SysTick Current Register Definitions */
Kojto 119:aae6fcc7d9bb 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 119:aae6fcc7d9bb 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 119:aae6fcc7d9bb 524
Kojto 119:aae6fcc7d9bb 525 /* SysTick Calibration Register Definitions */
Kojto 119:aae6fcc7d9bb 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 119:aae6fcc7d9bb 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 119:aae6fcc7d9bb 528
Kojto 119:aae6fcc7d9bb 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 119:aae6fcc7d9bb 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 119:aae6fcc7d9bb 531
Kojto 119:aae6fcc7d9bb 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 119:aae6fcc7d9bb 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 119:aae6fcc7d9bb 534
Kojto 119:aae6fcc7d9bb 535 /*@} end of group CMSIS_SysTick */
Kojto 119:aae6fcc7d9bb 536
Kojto 119:aae6fcc7d9bb 537 #if (__MPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 538 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 119:aae6fcc7d9bb 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 119:aae6fcc7d9bb 541 @{
Kojto 119:aae6fcc7d9bb 542 */
Kojto 119:aae6fcc7d9bb 543
Kojto 119:aae6fcc7d9bb 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 119:aae6fcc7d9bb 545 */
Kojto 119:aae6fcc7d9bb 546 typedef struct
Kojto 119:aae6fcc7d9bb 547 {
Kojto 119:aae6fcc7d9bb 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 119:aae6fcc7d9bb 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 119:aae6fcc7d9bb 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 119:aae6fcc7d9bb 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 119:aae6fcc7d9bb 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 553 } MPU_Type;
Kojto 119:aae6fcc7d9bb 554
Kojto 119:aae6fcc7d9bb 555 /* MPU Type Register */
Kojto 119:aae6fcc7d9bb 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 119:aae6fcc7d9bb 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 119:aae6fcc7d9bb 558
Kojto 119:aae6fcc7d9bb 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 119:aae6fcc7d9bb 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 119:aae6fcc7d9bb 561
Kojto 119:aae6fcc7d9bb 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 119:aae6fcc7d9bb 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 119:aae6fcc7d9bb 564
Kojto 119:aae6fcc7d9bb 565 /* MPU Control Register */
Kojto 119:aae6fcc7d9bb 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 119:aae6fcc7d9bb 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 119:aae6fcc7d9bb 568
Kojto 119:aae6fcc7d9bb 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 119:aae6fcc7d9bb 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 119:aae6fcc7d9bb 571
Kojto 119:aae6fcc7d9bb 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 119:aae6fcc7d9bb 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 119:aae6fcc7d9bb 574
Kojto 119:aae6fcc7d9bb 575 /* MPU Region Number Register */
Kojto 119:aae6fcc7d9bb 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 119:aae6fcc7d9bb 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 119:aae6fcc7d9bb 578
Kojto 119:aae6fcc7d9bb 579 /* MPU Region Base Address Register */
Kojto 119:aae6fcc7d9bb 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 119:aae6fcc7d9bb 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 119:aae6fcc7d9bb 582
Kojto 119:aae6fcc7d9bb 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 119:aae6fcc7d9bb 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 119:aae6fcc7d9bb 585
Kojto 119:aae6fcc7d9bb 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 119:aae6fcc7d9bb 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 119:aae6fcc7d9bb 588
Kojto 119:aae6fcc7d9bb 589 /* MPU Region Attribute and Size Register */
Kojto 119:aae6fcc7d9bb 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 119:aae6fcc7d9bb 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 119:aae6fcc7d9bb 592
Kojto 119:aae6fcc7d9bb 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 119:aae6fcc7d9bb 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 119:aae6fcc7d9bb 595
Kojto 119:aae6fcc7d9bb 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 119:aae6fcc7d9bb 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 119:aae6fcc7d9bb 598
Kojto 119:aae6fcc7d9bb 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 119:aae6fcc7d9bb 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 119:aae6fcc7d9bb 601
Kojto 119:aae6fcc7d9bb 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 119:aae6fcc7d9bb 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 119:aae6fcc7d9bb 604
Kojto 119:aae6fcc7d9bb 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 119:aae6fcc7d9bb 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 119:aae6fcc7d9bb 607
Kojto 119:aae6fcc7d9bb 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 119:aae6fcc7d9bb 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 119:aae6fcc7d9bb 610
Kojto 119:aae6fcc7d9bb 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 119:aae6fcc7d9bb 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 119:aae6fcc7d9bb 613
Kojto 119:aae6fcc7d9bb 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 119:aae6fcc7d9bb 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 119:aae6fcc7d9bb 616
Kojto 119:aae6fcc7d9bb 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 119:aae6fcc7d9bb 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 119:aae6fcc7d9bb 619
Kojto 119:aae6fcc7d9bb 620 /*@} end of group CMSIS_MPU */
Kojto 119:aae6fcc7d9bb 621 #endif
Kojto 119:aae6fcc7d9bb 622
Kojto 119:aae6fcc7d9bb 623
Kojto 119:aae6fcc7d9bb 624 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 119:aae6fcc7d9bb 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 119:aae6fcc7d9bb 627 are only accessible over DAP and not via processor. Therefore
Kojto 119:aae6fcc7d9bb 628 they are not covered by the Cortex-M0 header file.
Kojto 119:aae6fcc7d9bb 629 @{
Kojto 119:aae6fcc7d9bb 630 */
Kojto 119:aae6fcc7d9bb 631 /*@} end of group CMSIS_CoreDebug */
Kojto 119:aae6fcc7d9bb 632
Kojto 119:aae6fcc7d9bb 633
Kojto 119:aae6fcc7d9bb 634 /** \ingroup CMSIS_core_register
Kojto 119:aae6fcc7d9bb 635 \defgroup CMSIS_core_base Core Definitions
Kojto 119:aae6fcc7d9bb 636 \brief Definitions for base addresses, unions, and structures.
Kojto 119:aae6fcc7d9bb 637 @{
Kojto 119:aae6fcc7d9bb 638 */
Kojto 119:aae6fcc7d9bb 639
Kojto 119:aae6fcc7d9bb 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 119:aae6fcc7d9bb 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 119:aae6fcc7d9bb 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 119:aae6fcc7d9bb 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 119:aae6fcc7d9bb 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 119:aae6fcc7d9bb 645
Kojto 119:aae6fcc7d9bb 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 119:aae6fcc7d9bb 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 119:aae6fcc7d9bb 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 119:aae6fcc7d9bb 649
Kojto 119:aae6fcc7d9bb 650 #if (__MPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 119:aae6fcc7d9bb 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 119:aae6fcc7d9bb 653 #endif
Kojto 119:aae6fcc7d9bb 654
Kojto 119:aae6fcc7d9bb 655 /*@} */
Kojto 119:aae6fcc7d9bb 656
Kojto 119:aae6fcc7d9bb 657
Kojto 119:aae6fcc7d9bb 658
Kojto 119:aae6fcc7d9bb 659 /*******************************************************************************
Kojto 119:aae6fcc7d9bb 660 * Hardware Abstraction Layer
Kojto 119:aae6fcc7d9bb 661 Core Function Interface contains:
Kojto 119:aae6fcc7d9bb 662 - Core NVIC Functions
Kojto 119:aae6fcc7d9bb 663 - Core SysTick Functions
Kojto 119:aae6fcc7d9bb 664 - Core Register Access Functions
Kojto 119:aae6fcc7d9bb 665 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 119:aae6fcc7d9bb 667 */
Kojto 119:aae6fcc7d9bb 668
Kojto 119:aae6fcc7d9bb 669
Kojto 119:aae6fcc7d9bb 670
Kojto 119:aae6fcc7d9bb 671 /* ########################## NVIC functions #################################### */
Kojto 119:aae6fcc7d9bb 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 119:aae6fcc7d9bb 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 119:aae6fcc7d9bb 675 @{
Kojto 119:aae6fcc7d9bb 676 */
Kojto 119:aae6fcc7d9bb 677
Kojto 119:aae6fcc7d9bb 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 119:aae6fcc7d9bb 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 119:aae6fcc7d9bb 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 119:aae6fcc7d9bb 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 119:aae6fcc7d9bb 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 119:aae6fcc7d9bb 683
Kojto 119:aae6fcc7d9bb 684
Kojto 119:aae6fcc7d9bb 685 /** \brief Enable External Interrupt
Kojto 119:aae6fcc7d9bb 686
Kojto 119:aae6fcc7d9bb 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 119:aae6fcc7d9bb 688
Kojto 119:aae6fcc7d9bb 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 690 */
Kojto 119:aae6fcc7d9bb 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 692 {
Kojto 119:aae6fcc7d9bb 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 694 }
Kojto 119:aae6fcc7d9bb 695
Kojto 119:aae6fcc7d9bb 696
Kojto 119:aae6fcc7d9bb 697 /** \brief Disable External Interrupt
Kojto 119:aae6fcc7d9bb 698
Kojto 119:aae6fcc7d9bb 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 119:aae6fcc7d9bb 700
Kojto 119:aae6fcc7d9bb 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 702 */
Kojto 119:aae6fcc7d9bb 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 704 {
Kojto 119:aae6fcc7d9bb 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 119:aae6fcc7d9bb 708 }
Kojto 119:aae6fcc7d9bb 709
Kojto 119:aae6fcc7d9bb 710
Kojto 119:aae6fcc7d9bb 711 /** \brief Get Pending Interrupt
Kojto 119:aae6fcc7d9bb 712
Kojto 119:aae6fcc7d9bb 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 119:aae6fcc7d9bb 714 for the specified interrupt.
Kojto 119:aae6fcc7d9bb 715
Kojto 119:aae6fcc7d9bb 716 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 717
Kojto 119:aae6fcc7d9bb 718 \return 0 Interrupt status is not pending.
Kojto 119:aae6fcc7d9bb 719 \return 1 Interrupt status is pending.
Kojto 119:aae6fcc7d9bb 720 */
Kojto 119:aae6fcc7d9bb 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 722 {
Kojto 119:aae6fcc7d9bb 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 119:aae6fcc7d9bb 724 }
Kojto 119:aae6fcc7d9bb 725
Kojto 119:aae6fcc7d9bb 726
Kojto 119:aae6fcc7d9bb 727 /** \brief Set Pending Interrupt
Kojto 119:aae6fcc7d9bb 728
Kojto 119:aae6fcc7d9bb 729 The function sets the pending bit of an external interrupt.
Kojto 119:aae6fcc7d9bb 730
Kojto 119:aae6fcc7d9bb 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 732 */
Kojto 119:aae6fcc7d9bb 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 734 {
Kojto 119:aae6fcc7d9bb 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 736 }
Kojto 119:aae6fcc7d9bb 737
Kojto 119:aae6fcc7d9bb 738
Kojto 119:aae6fcc7d9bb 739 /** \brief Clear Pending Interrupt
Kojto 119:aae6fcc7d9bb 740
Kojto 119:aae6fcc7d9bb 741 The function clears the pending bit of an external interrupt.
Kojto 119:aae6fcc7d9bb 742
Kojto 119:aae6fcc7d9bb 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 119:aae6fcc7d9bb 744 */
Kojto 119:aae6fcc7d9bb 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 746 {
Kojto 119:aae6fcc7d9bb 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 119:aae6fcc7d9bb 748 }
Kojto 119:aae6fcc7d9bb 749
Kojto 119:aae6fcc7d9bb 750
Kojto 119:aae6fcc7d9bb 751 /** \brief Set Interrupt Priority
Kojto 119:aae6fcc7d9bb 752
Kojto 119:aae6fcc7d9bb 753 The function sets the priority of an interrupt.
Kojto 119:aae6fcc7d9bb 754
Kojto 119:aae6fcc7d9bb 755 \note The priority cannot be set for every core interrupt.
Kojto 119:aae6fcc7d9bb 756
Kojto 119:aae6fcc7d9bb 757 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 758 \param [in] priority Priority to set.
Kojto 119:aae6fcc7d9bb 759 */
Kojto 119:aae6fcc7d9bb 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 119:aae6fcc7d9bb 761 {
Kojto 119:aae6fcc7d9bb 762 if((int32_t)(IRQn) < 0) {
Kojto 119:aae6fcc7d9bb 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 119:aae6fcc7d9bb 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 119:aae6fcc7d9bb 765 }
Kojto 119:aae6fcc7d9bb 766 else {
Kojto 119:aae6fcc7d9bb 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 119:aae6fcc7d9bb 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 119:aae6fcc7d9bb 769 }
Kojto 119:aae6fcc7d9bb 770 }
Kojto 119:aae6fcc7d9bb 771
Kojto 119:aae6fcc7d9bb 772
Kojto 119:aae6fcc7d9bb 773 /** \brief Get Interrupt Priority
Kojto 119:aae6fcc7d9bb 774
Kojto 119:aae6fcc7d9bb 775 The function reads the priority of an interrupt. The interrupt
Kojto 119:aae6fcc7d9bb 776 number can be positive to specify an external (device specific)
Kojto 119:aae6fcc7d9bb 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 119:aae6fcc7d9bb 778
Kojto 119:aae6fcc7d9bb 779
Kojto 119:aae6fcc7d9bb 780 \param [in] IRQn Interrupt number.
Kojto 119:aae6fcc7d9bb 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 119:aae6fcc7d9bb 782 priority bits of the microcontroller.
Kojto 119:aae6fcc7d9bb 783 */
Kojto 119:aae6fcc7d9bb 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 119:aae6fcc7d9bb 785 {
Kojto 119:aae6fcc7d9bb 786
Kojto 119:aae6fcc7d9bb 787 if((int32_t)(IRQn) < 0) {
Kojto 119:aae6fcc7d9bb 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 119:aae6fcc7d9bb 789 }
Kojto 119:aae6fcc7d9bb 790 else {
Kojto 119:aae6fcc7d9bb 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 119:aae6fcc7d9bb 792 }
Kojto 119:aae6fcc7d9bb 793 }
Kojto 119:aae6fcc7d9bb 794
Kojto 119:aae6fcc7d9bb 795
Kojto 119:aae6fcc7d9bb 796 /** \brief System Reset
Kojto 119:aae6fcc7d9bb 797
Kojto 119:aae6fcc7d9bb 798 The function initiates a system reset request to reset the MCU.
Kojto 119:aae6fcc7d9bb 799 */
Kojto 119:aae6fcc7d9bb 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 119:aae6fcc7d9bb 801 {
Kojto 119:aae6fcc7d9bb 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 119:aae6fcc7d9bb 803 buffered write are completed before reset */
Kojto 119:aae6fcc7d9bb 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 119:aae6fcc7d9bb 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 119:aae6fcc7d9bb 806 __DSB(); /* Ensure completion of memory access */
Kojto 119:aae6fcc7d9bb 807 while(1) { __NOP(); } /* wait until reset */
Kojto 119:aae6fcc7d9bb 808 }
Kojto 119:aae6fcc7d9bb 809
Kojto 119:aae6fcc7d9bb 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 119:aae6fcc7d9bb 811
Kojto 119:aae6fcc7d9bb 812
Kojto 119:aae6fcc7d9bb 813
Kojto 119:aae6fcc7d9bb 814 /* ################################## SysTick function ############################################ */
Kojto 119:aae6fcc7d9bb 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 119:aae6fcc7d9bb 817 \brief Functions that configure the System.
Kojto 119:aae6fcc7d9bb 818 @{
Kojto 119:aae6fcc7d9bb 819 */
Kojto 119:aae6fcc7d9bb 820
Kojto 119:aae6fcc7d9bb 821 #if (__Vendor_SysTickConfig == 0)
Kojto 119:aae6fcc7d9bb 822
Kojto 119:aae6fcc7d9bb 823 /** \brief System Tick Configuration
Kojto 119:aae6fcc7d9bb 824
Kojto 119:aae6fcc7d9bb 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 119:aae6fcc7d9bb 826 Counter is in free running mode to generate periodic interrupts.
Kojto 119:aae6fcc7d9bb 827
Kojto 119:aae6fcc7d9bb 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 119:aae6fcc7d9bb 829
Kojto 119:aae6fcc7d9bb 830 \return 0 Function succeeded.
Kojto 119:aae6fcc7d9bb 831 \return 1 Function failed.
Kojto 119:aae6fcc7d9bb 832
Kojto 119:aae6fcc7d9bb 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 119:aae6fcc7d9bb 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 119:aae6fcc7d9bb 835 must contain a vendor-specific implementation of this function.
Kojto 119:aae6fcc7d9bb 836
Kojto 119:aae6fcc7d9bb 837 */
Kojto 119:aae6fcc7d9bb 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 119:aae6fcc7d9bb 839 {
Kojto 119:aae6fcc7d9bb 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 119:aae6fcc7d9bb 841
Kojto 119:aae6fcc7d9bb 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 119:aae6fcc7d9bb 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 119:aae6fcc7d9bb 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 119:aae6fcc7d9bb 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 119:aae6fcc7d9bb 846 SysTick_CTRL_TICKINT_Msk |
Kojto 119:aae6fcc7d9bb 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 119:aae6fcc7d9bb 848 return (0UL); /* Function successful */
Kojto 119:aae6fcc7d9bb 849 }
Kojto 119:aae6fcc7d9bb 850
Kojto 119:aae6fcc7d9bb 851 #endif
Kojto 119:aae6fcc7d9bb 852
Kojto 119:aae6fcc7d9bb 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 119:aae6fcc7d9bb 854
Kojto 119:aae6fcc7d9bb 855
Kojto 119:aae6fcc7d9bb 856
Kojto 119:aae6fcc7d9bb 857
Kojto 119:aae6fcc7d9bb 858 #ifdef __cplusplus
Kojto 119:aae6fcc7d9bb 859 }
Kojto 119:aae6fcc7d9bb 860 #endif
Kojto 119:aae6fcc7d9bb 861
Kojto 119:aae6fcc7d9bb 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 119:aae6fcc7d9bb 863
Kojto 119:aae6fcc7d9bb 864 #endif /* __CMSIS_GENERIC */