mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L031K6/core_caFunc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
130:d75b3fe1f5cb 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 119:aae6fcc7d9bb 1 /**************************************************************************//**
Kojto 119:aae6fcc7d9bb 2 * @file core_caFunc.h
Kojto 119:aae6fcc7d9bb 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 119:aae6fcc7d9bb 4 * @version V3.10
Kojto 119:aae6fcc7d9bb 5 * @date 30 Oct 2013
Kojto 119:aae6fcc7d9bb 6 *
Kojto 119:aae6fcc7d9bb 7 * @note
Kojto 119:aae6fcc7d9bb 8 *
Kojto 119:aae6fcc7d9bb 9 ******************************************************************************/
Kojto 119:aae6fcc7d9bb 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 119:aae6fcc7d9bb 11
Kojto 119:aae6fcc7d9bb 12 All rights reserved.
Kojto 119:aae6fcc7d9bb 13 Redistribution and use in source and binary forms, with or without
Kojto 119:aae6fcc7d9bb 14 modification, are permitted provided that the following conditions are met:
Kojto 119:aae6fcc7d9bb 15 - Redistributions of source code must retain the above copyright
Kojto 119:aae6fcc7d9bb 16 notice, this list of conditions and the following disclaimer.
Kojto 119:aae6fcc7d9bb 17 - Redistributions in binary form must reproduce the above copyright
Kojto 119:aae6fcc7d9bb 18 notice, this list of conditions and the following disclaimer in the
Kojto 119:aae6fcc7d9bb 19 documentation and/or other materials provided with the distribution.
Kojto 119:aae6fcc7d9bb 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 119:aae6fcc7d9bb 21 to endorse or promote products derived from this software without
Kojto 119:aae6fcc7d9bb 22 specific prior written permission.
Kojto 119:aae6fcc7d9bb 23 *
Kojto 119:aae6fcc7d9bb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 119:aae6fcc7d9bb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 119:aae6fcc7d9bb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 119:aae6fcc7d9bb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 119:aae6fcc7d9bb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 119:aae6fcc7d9bb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 119:aae6fcc7d9bb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 119:aae6fcc7d9bb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 119:aae6fcc7d9bb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 119:aae6fcc7d9bb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 119:aae6fcc7d9bb 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 119:aae6fcc7d9bb 35 ---------------------------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 36
Kojto 119:aae6fcc7d9bb 37
Kojto 119:aae6fcc7d9bb 38 #ifndef __CORE_CAFUNC_H__
Kojto 119:aae6fcc7d9bb 39 #define __CORE_CAFUNC_H__
Kojto 119:aae6fcc7d9bb 40
Kojto 119:aae6fcc7d9bb 41
Kojto 119:aae6fcc7d9bb 42 /* ########################### Core Function Access ########################### */
Kojto 119:aae6fcc7d9bb 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 119:aae6fcc7d9bb 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 119:aae6fcc7d9bb 45 @{
Kojto 119:aae6fcc7d9bb 46 */
Kojto 119:aae6fcc7d9bb 47
Kojto 119:aae6fcc7d9bb 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 119:aae6fcc7d9bb 49 /* ARM armcc specific functions */
Kojto 119:aae6fcc7d9bb 50
Kojto 119:aae6fcc7d9bb 51 #if (__ARMCC_VERSION < 400677)
Kojto 119:aae6fcc7d9bb 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 119:aae6fcc7d9bb 53 #endif
Kojto 119:aae6fcc7d9bb 54
Kojto 119:aae6fcc7d9bb 55 #define MODE_USR 0x10
Kojto 119:aae6fcc7d9bb 56 #define MODE_FIQ 0x11
Kojto 119:aae6fcc7d9bb 57 #define MODE_IRQ 0x12
Kojto 119:aae6fcc7d9bb 58 #define MODE_SVC 0x13
Kojto 119:aae6fcc7d9bb 59 #define MODE_MON 0x16
Kojto 119:aae6fcc7d9bb 60 #define MODE_ABT 0x17
Kojto 119:aae6fcc7d9bb 61 #define MODE_HYP 0x1A
Kojto 119:aae6fcc7d9bb 62 #define MODE_UND 0x1B
Kojto 119:aae6fcc7d9bb 63 #define MODE_SYS 0x1F
Kojto 119:aae6fcc7d9bb 64
Kojto 119:aae6fcc7d9bb 65 /** \brief Get APSR Register
Kojto 119:aae6fcc7d9bb 66
Kojto 119:aae6fcc7d9bb 67 This function returns the content of the APSR Register.
Kojto 119:aae6fcc7d9bb 68
Kojto 119:aae6fcc7d9bb 69 \return APSR Register value
Kojto 119:aae6fcc7d9bb 70 */
Kojto 119:aae6fcc7d9bb 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 119:aae6fcc7d9bb 72 {
Kojto 119:aae6fcc7d9bb 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 119:aae6fcc7d9bb 74 return(__regAPSR);
Kojto 119:aae6fcc7d9bb 75 }
Kojto 119:aae6fcc7d9bb 76
Kojto 119:aae6fcc7d9bb 77
Kojto 119:aae6fcc7d9bb 78 /** \brief Get CPSR Register
Kojto 119:aae6fcc7d9bb 79
Kojto 119:aae6fcc7d9bb 80 This function returns the content of the CPSR Register.
Kojto 119:aae6fcc7d9bb 81
Kojto 119:aae6fcc7d9bb 82 \return CPSR Register value
Kojto 119:aae6fcc7d9bb 83 */
Kojto 119:aae6fcc7d9bb 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 119:aae6fcc7d9bb 85 {
Kojto 119:aae6fcc7d9bb 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 119:aae6fcc7d9bb 87 return(__regCPSR);
Kojto 119:aae6fcc7d9bb 88 }
Kojto 119:aae6fcc7d9bb 89
Kojto 119:aae6fcc7d9bb 90 /** \brief Set Stack Pointer
Kojto 119:aae6fcc7d9bb 91
Kojto 119:aae6fcc7d9bb 92 This function assigns the given value to the current stack pointer.
Kojto 119:aae6fcc7d9bb 93
Kojto 119:aae6fcc7d9bb 94 \param [in] topOfStack Stack Pointer value to set
Kojto 119:aae6fcc7d9bb 95 */
Kojto 119:aae6fcc7d9bb 96 register uint32_t __regSP __ASM("sp");
Kojto 119:aae6fcc7d9bb 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 119:aae6fcc7d9bb 98 {
Kojto 119:aae6fcc7d9bb 99 __regSP = topOfStack;
Kojto 119:aae6fcc7d9bb 100 }
Kojto 119:aae6fcc7d9bb 101
Kojto 119:aae6fcc7d9bb 102
Kojto 119:aae6fcc7d9bb 103 /** \brief Get link register
Kojto 119:aae6fcc7d9bb 104
Kojto 119:aae6fcc7d9bb 105 This function returns the value of the link register
Kojto 119:aae6fcc7d9bb 106
Kojto 119:aae6fcc7d9bb 107 \return Value of link register
Kojto 119:aae6fcc7d9bb 108 */
Kojto 119:aae6fcc7d9bb 109 register uint32_t __reglr __ASM("lr");
Kojto 119:aae6fcc7d9bb 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 119:aae6fcc7d9bb 111 {
Kojto 119:aae6fcc7d9bb 112 return(__reglr);
Kojto 119:aae6fcc7d9bb 113 }
Kojto 119:aae6fcc7d9bb 114
Kojto 119:aae6fcc7d9bb 115 /** \brief Set link register
Kojto 119:aae6fcc7d9bb 116
Kojto 119:aae6fcc7d9bb 117 This function sets the value of the link register
Kojto 119:aae6fcc7d9bb 118
Kojto 119:aae6fcc7d9bb 119 \param [in] lr LR value to set
Kojto 119:aae6fcc7d9bb 120 */
Kojto 119:aae6fcc7d9bb 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 119:aae6fcc7d9bb 122 {
Kojto 119:aae6fcc7d9bb 123 __reglr = lr;
Kojto 119:aae6fcc7d9bb 124 }
Kojto 119:aae6fcc7d9bb 125
Kojto 119:aae6fcc7d9bb 126 /** \brief Set Process Stack Pointer
Kojto 119:aae6fcc7d9bb 127
Kojto 119:aae6fcc7d9bb 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 119:aae6fcc7d9bb 129
Kojto 119:aae6fcc7d9bb 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 119:aae6fcc7d9bb 131 */
Kojto 119:aae6fcc7d9bb 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 119:aae6fcc7d9bb 133 {
Kojto 119:aae6fcc7d9bb 134 ARM
Kojto 119:aae6fcc7d9bb 135 PRESERVE8
Kojto 119:aae6fcc7d9bb 136
Kojto 119:aae6fcc7d9bb 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 119:aae6fcc7d9bb 138 MRS R1, CPSR
Kojto 119:aae6fcc7d9bb 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 119:aae6fcc7d9bb 140 MOV SP, R0
Kojto 119:aae6fcc7d9bb 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 119:aae6fcc7d9bb 142 ISB
Kojto 119:aae6fcc7d9bb 143 BX LR
Kojto 119:aae6fcc7d9bb 144
Kojto 119:aae6fcc7d9bb 145 }
Kojto 119:aae6fcc7d9bb 146
Kojto 119:aae6fcc7d9bb 147 /** \brief Set User Mode
Kojto 119:aae6fcc7d9bb 148
Kojto 119:aae6fcc7d9bb 149 This function changes the processor state to User Mode
Kojto 119:aae6fcc7d9bb 150 */
Kojto 119:aae6fcc7d9bb 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 119:aae6fcc7d9bb 152 {
Kojto 119:aae6fcc7d9bb 153 ARM
Kojto 119:aae6fcc7d9bb 154
Kojto 119:aae6fcc7d9bb 155 CPS #MODE_USR
Kojto 119:aae6fcc7d9bb 156 BX LR
Kojto 119:aae6fcc7d9bb 157 }
Kojto 119:aae6fcc7d9bb 158
Kojto 119:aae6fcc7d9bb 159
Kojto 119:aae6fcc7d9bb 160 /** \brief Enable FIQ
Kojto 119:aae6fcc7d9bb 161
Kojto 119:aae6fcc7d9bb 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 119:aae6fcc7d9bb 163 Can only be executed in Privileged modes.
Kojto 119:aae6fcc7d9bb 164 */
Kojto 119:aae6fcc7d9bb 165 #define __enable_fault_irq __enable_fiq
Kojto 119:aae6fcc7d9bb 166
Kojto 119:aae6fcc7d9bb 167
Kojto 119:aae6fcc7d9bb 168 /** \brief Disable FIQ
Kojto 119:aae6fcc7d9bb 169
Kojto 119:aae6fcc7d9bb 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 119:aae6fcc7d9bb 171 Can only be executed in Privileged modes.
Kojto 119:aae6fcc7d9bb 172 */
Kojto 119:aae6fcc7d9bb 173 #define __disable_fault_irq __disable_fiq
Kojto 119:aae6fcc7d9bb 174
Kojto 119:aae6fcc7d9bb 175
Kojto 119:aae6fcc7d9bb 176 /** \brief Get FPSCR
Kojto 119:aae6fcc7d9bb 177
Kojto 119:aae6fcc7d9bb 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 119:aae6fcc7d9bb 179
Kojto 119:aae6fcc7d9bb 180 \return Floating Point Status/Control register value
Kojto 119:aae6fcc7d9bb 181 */
Kojto 119:aae6fcc7d9bb 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 119:aae6fcc7d9bb 183 {
Kojto 119:aae6fcc7d9bb 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 119:aae6fcc7d9bb 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 119:aae6fcc7d9bb 186 return(__regfpscr);
Kojto 119:aae6fcc7d9bb 187 #else
Kojto 119:aae6fcc7d9bb 188 return(0);
Kojto 119:aae6fcc7d9bb 189 #endif
Kojto 119:aae6fcc7d9bb 190 }
Kojto 119:aae6fcc7d9bb 191
Kojto 119:aae6fcc7d9bb 192
Kojto 119:aae6fcc7d9bb 193 /** \brief Set FPSCR
Kojto 119:aae6fcc7d9bb 194
Kojto 119:aae6fcc7d9bb 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 119:aae6fcc7d9bb 196
Kojto 119:aae6fcc7d9bb 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 119:aae6fcc7d9bb 198 */
Kojto 119:aae6fcc7d9bb 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 119:aae6fcc7d9bb 200 {
Kojto 119:aae6fcc7d9bb 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 119:aae6fcc7d9bb 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 119:aae6fcc7d9bb 203 __regfpscr = (fpscr);
Kojto 119:aae6fcc7d9bb 204 #endif
Kojto 119:aae6fcc7d9bb 205 }
Kojto 119:aae6fcc7d9bb 206
Kojto 119:aae6fcc7d9bb 207 /** \brief Get FPEXC
Kojto 119:aae6fcc7d9bb 208
Kojto 119:aae6fcc7d9bb 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 119:aae6fcc7d9bb 210
Kojto 119:aae6fcc7d9bb 211 \return Floating Point Exception Control register value
Kojto 119:aae6fcc7d9bb 212 */
Kojto 119:aae6fcc7d9bb 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 119:aae6fcc7d9bb 214 {
Kojto 119:aae6fcc7d9bb 215 #if (__FPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 119:aae6fcc7d9bb 217 return(__regfpexc);
Kojto 119:aae6fcc7d9bb 218 #else
Kojto 119:aae6fcc7d9bb 219 return(0);
Kojto 119:aae6fcc7d9bb 220 #endif
Kojto 119:aae6fcc7d9bb 221 }
Kojto 119:aae6fcc7d9bb 222
Kojto 119:aae6fcc7d9bb 223
Kojto 119:aae6fcc7d9bb 224 /** \brief Set FPEXC
Kojto 119:aae6fcc7d9bb 225
Kojto 119:aae6fcc7d9bb 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 119:aae6fcc7d9bb 227
Kojto 119:aae6fcc7d9bb 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 119:aae6fcc7d9bb 229 */
Kojto 119:aae6fcc7d9bb 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 119:aae6fcc7d9bb 231 {
Kojto 119:aae6fcc7d9bb 232 #if (__FPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 119:aae6fcc7d9bb 234 __regfpexc = (fpexc);
Kojto 119:aae6fcc7d9bb 235 #endif
Kojto 119:aae6fcc7d9bb 236 }
Kojto 119:aae6fcc7d9bb 237
Kojto 119:aae6fcc7d9bb 238 /** \brief Get CPACR
Kojto 119:aae6fcc7d9bb 239
Kojto 119:aae6fcc7d9bb 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 119:aae6fcc7d9bb 241
Kojto 119:aae6fcc7d9bb 242 \return Coprocessor Access Control register value
Kojto 119:aae6fcc7d9bb 243 */
Kojto 119:aae6fcc7d9bb 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 119:aae6fcc7d9bb 245 {
Kojto 119:aae6fcc7d9bb 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 119:aae6fcc7d9bb 247 return __regCPACR;
Kojto 119:aae6fcc7d9bb 248 }
Kojto 119:aae6fcc7d9bb 249
Kojto 119:aae6fcc7d9bb 250 /** \brief Set CPACR
Kojto 119:aae6fcc7d9bb 251
Kojto 119:aae6fcc7d9bb 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 119:aae6fcc7d9bb 253
Kojto 119:aae6fcc7d9bb 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 119:aae6fcc7d9bb 255 */
Kojto 119:aae6fcc7d9bb 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 119:aae6fcc7d9bb 257 {
Kojto 119:aae6fcc7d9bb 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 119:aae6fcc7d9bb 259 __regCPACR = cpacr;
Kojto 119:aae6fcc7d9bb 260 __ISB();
Kojto 119:aae6fcc7d9bb 261 }
Kojto 119:aae6fcc7d9bb 262
Kojto 119:aae6fcc7d9bb 263 /** \brief Get CBAR
Kojto 119:aae6fcc7d9bb 264
Kojto 119:aae6fcc7d9bb 265 This function returns the value of the Configuration Base Address register.
Kojto 119:aae6fcc7d9bb 266
Kojto 119:aae6fcc7d9bb 267 \return Configuration Base Address register value
Kojto 119:aae6fcc7d9bb 268 */
Kojto 119:aae6fcc7d9bb 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 119:aae6fcc7d9bb 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 119:aae6fcc7d9bb 271 return(__regCBAR);
Kojto 119:aae6fcc7d9bb 272 }
Kojto 119:aae6fcc7d9bb 273
Kojto 119:aae6fcc7d9bb 274 /** \brief Get TTBR0
Kojto 119:aae6fcc7d9bb 275
Kojto 119:aae6fcc7d9bb 276 This function returns the value of the Translation Table Base Register 0.
Kojto 119:aae6fcc7d9bb 277
Kojto 119:aae6fcc7d9bb 278 \return Translation Table Base Register 0 value
Kojto 119:aae6fcc7d9bb 279 */
Kojto 119:aae6fcc7d9bb 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 119:aae6fcc7d9bb 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 119:aae6fcc7d9bb 282 return(__regTTBR0);
Kojto 119:aae6fcc7d9bb 283 }
Kojto 119:aae6fcc7d9bb 284
Kojto 119:aae6fcc7d9bb 285 /** \brief Set TTBR0
Kojto 119:aae6fcc7d9bb 286
Kojto 119:aae6fcc7d9bb 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 119:aae6fcc7d9bb 288
Kojto 119:aae6fcc7d9bb 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 119:aae6fcc7d9bb 290 */
Kojto 119:aae6fcc7d9bb 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 119:aae6fcc7d9bb 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 119:aae6fcc7d9bb 293 __regTTBR0 = ttbr0;
Kojto 119:aae6fcc7d9bb 294 __ISB();
Kojto 119:aae6fcc7d9bb 295 }
Kojto 119:aae6fcc7d9bb 296
Kojto 119:aae6fcc7d9bb 297 /** \brief Get DACR
Kojto 119:aae6fcc7d9bb 298
Kojto 119:aae6fcc7d9bb 299 This function returns the value of the Domain Access Control Register.
Kojto 119:aae6fcc7d9bb 300
Kojto 119:aae6fcc7d9bb 301 \return Domain Access Control Register value
Kojto 119:aae6fcc7d9bb 302 */
Kojto 119:aae6fcc7d9bb 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 119:aae6fcc7d9bb 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 119:aae6fcc7d9bb 305 return(__regDACR);
Kojto 119:aae6fcc7d9bb 306 }
Kojto 119:aae6fcc7d9bb 307
Kojto 119:aae6fcc7d9bb 308 /** \brief Set DACR
Kojto 119:aae6fcc7d9bb 309
Kojto 119:aae6fcc7d9bb 310 This function assigns the given value to the Domain Access Control Register.
Kojto 119:aae6fcc7d9bb 311
Kojto 119:aae6fcc7d9bb 312 \param [in] dacr Domain Access Control Register value to set
Kojto 119:aae6fcc7d9bb 313 */
Kojto 119:aae6fcc7d9bb 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 119:aae6fcc7d9bb 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 119:aae6fcc7d9bb 316 __regDACR = dacr;
Kojto 119:aae6fcc7d9bb 317 __ISB();
Kojto 119:aae6fcc7d9bb 318 }
Kojto 119:aae6fcc7d9bb 319
Kojto 119:aae6fcc7d9bb 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 119:aae6fcc7d9bb 321
Kojto 119:aae6fcc7d9bb 322 /** \brief Set SCTLR
Kojto 119:aae6fcc7d9bb 323
Kojto 119:aae6fcc7d9bb 324 This function assigns the given value to the System Control Register.
Kojto 119:aae6fcc7d9bb 325
Kojto 119:aae6fcc7d9bb 326 \param [in] sctlr System Control Register value to set
Kojto 119:aae6fcc7d9bb 327 */
Kojto 119:aae6fcc7d9bb 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 119:aae6fcc7d9bb 329 {
Kojto 119:aae6fcc7d9bb 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 119:aae6fcc7d9bb 331 __regSCTLR = sctlr;
Kojto 119:aae6fcc7d9bb 332 }
Kojto 119:aae6fcc7d9bb 333
Kojto 119:aae6fcc7d9bb 334 /** \brief Get SCTLR
Kojto 119:aae6fcc7d9bb 335
Kojto 119:aae6fcc7d9bb 336 This function returns the value of the System Control Register.
Kojto 119:aae6fcc7d9bb 337
Kojto 119:aae6fcc7d9bb 338 \return System Control Register value
Kojto 119:aae6fcc7d9bb 339 */
Kojto 119:aae6fcc7d9bb 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 119:aae6fcc7d9bb 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 119:aae6fcc7d9bb 342 return(__regSCTLR);
Kojto 119:aae6fcc7d9bb 343 }
Kojto 119:aae6fcc7d9bb 344
Kojto 119:aae6fcc7d9bb 345 /** \brief Enable Caches
Kojto 119:aae6fcc7d9bb 346
Kojto 119:aae6fcc7d9bb 347 Enable Caches
Kojto 119:aae6fcc7d9bb 348 */
Kojto 119:aae6fcc7d9bb 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 119:aae6fcc7d9bb 350 // Set I bit 12 to enable I Cache
Kojto 119:aae6fcc7d9bb 351 // Set C bit 2 to enable D Cache
Kojto 119:aae6fcc7d9bb 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 119:aae6fcc7d9bb 353 }
Kojto 119:aae6fcc7d9bb 354
Kojto 119:aae6fcc7d9bb 355 /** \brief Disable Caches
Kojto 119:aae6fcc7d9bb 356
Kojto 119:aae6fcc7d9bb 357 Disable Caches
Kojto 119:aae6fcc7d9bb 358 */
Kojto 119:aae6fcc7d9bb 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 119:aae6fcc7d9bb 360 // Clear I bit 12 to disable I Cache
Kojto 119:aae6fcc7d9bb 361 // Clear C bit 2 to disable D Cache
Kojto 119:aae6fcc7d9bb 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 119:aae6fcc7d9bb 363 __ISB();
Kojto 119:aae6fcc7d9bb 364 }
Kojto 119:aae6fcc7d9bb 365
Kojto 119:aae6fcc7d9bb 366 /** \brief Enable BTAC
Kojto 119:aae6fcc7d9bb 367
Kojto 119:aae6fcc7d9bb 368 Enable BTAC
Kojto 119:aae6fcc7d9bb 369 */
Kojto 119:aae6fcc7d9bb 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 119:aae6fcc7d9bb 371 // Set Z bit 11 to enable branch prediction
Kojto 119:aae6fcc7d9bb 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 119:aae6fcc7d9bb 373 __ISB();
Kojto 119:aae6fcc7d9bb 374 }
Kojto 119:aae6fcc7d9bb 375
Kojto 119:aae6fcc7d9bb 376 /** \brief Disable BTAC
Kojto 119:aae6fcc7d9bb 377
Kojto 119:aae6fcc7d9bb 378 Disable BTAC
Kojto 119:aae6fcc7d9bb 379 */
Kojto 119:aae6fcc7d9bb 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 119:aae6fcc7d9bb 381 // Clear Z bit 11 to disable branch prediction
Kojto 119:aae6fcc7d9bb 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 119:aae6fcc7d9bb 383 }
Kojto 119:aae6fcc7d9bb 384
Kojto 119:aae6fcc7d9bb 385
Kojto 119:aae6fcc7d9bb 386 /** \brief Enable MMU
Kojto 119:aae6fcc7d9bb 387
Kojto 119:aae6fcc7d9bb 388 Enable MMU
Kojto 119:aae6fcc7d9bb 389 */
Kojto 119:aae6fcc7d9bb 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 119:aae6fcc7d9bb 391 // Set M bit 0 to enable the MMU
Kojto 119:aae6fcc7d9bb 392 // Set AFE bit to enable simplified access permissions model
Kojto 119:aae6fcc7d9bb 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 119:aae6fcc7d9bb 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 119:aae6fcc7d9bb 395 __ISB();
Kojto 119:aae6fcc7d9bb 396 }
Kojto 119:aae6fcc7d9bb 397
Kojto 119:aae6fcc7d9bb 398 /** \brief Disable MMU
Kojto 119:aae6fcc7d9bb 399
Kojto 119:aae6fcc7d9bb 400 Disable MMU
Kojto 119:aae6fcc7d9bb 401 */
Kojto 119:aae6fcc7d9bb 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 119:aae6fcc7d9bb 403 // Clear M bit 0 to disable the MMU
Kojto 119:aae6fcc7d9bb 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 119:aae6fcc7d9bb 405 __ISB();
Kojto 119:aae6fcc7d9bb 406 }
Kojto 119:aae6fcc7d9bb 407
Kojto 119:aae6fcc7d9bb 408 /******************************** TLB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 409 /** \brief Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 410
Kojto 119:aae6fcc7d9bb 411 TLBIALL. Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 412 */
Kojto 119:aae6fcc7d9bb 413
Kojto 119:aae6fcc7d9bb 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 119:aae6fcc7d9bb 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 119:aae6fcc7d9bb 416 __TLBIALL = 0;
Kojto 119:aae6fcc7d9bb 417 __DSB();
Kojto 119:aae6fcc7d9bb 418 __ISB();
Kojto 119:aae6fcc7d9bb 419 }
Kojto 119:aae6fcc7d9bb 420
Kojto 119:aae6fcc7d9bb 421 /******************************** BTB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 422 /** \brief Invalidate entire branch predictor array
Kojto 119:aae6fcc7d9bb 423
Kojto 119:aae6fcc7d9bb 424 BPIALL. Branch Predictor Invalidate All.
Kojto 119:aae6fcc7d9bb 425 */
Kojto 119:aae6fcc7d9bb 426
Kojto 119:aae6fcc7d9bb 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 119:aae6fcc7d9bb 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 119:aae6fcc7d9bb 429 __BPIALL = 0;
Kojto 119:aae6fcc7d9bb 430 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 119:aae6fcc7d9bb 432 }
Kojto 119:aae6fcc7d9bb 433
Kojto 119:aae6fcc7d9bb 434
Kojto 119:aae6fcc7d9bb 435 /******************************** L1 cache operations ******************************************************/
Kojto 119:aae6fcc7d9bb 436
Kojto 119:aae6fcc7d9bb 437 /** \brief Invalidate the whole I$
Kojto 119:aae6fcc7d9bb 438
Kojto 119:aae6fcc7d9bb 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 119:aae6fcc7d9bb 440 */
Kojto 119:aae6fcc7d9bb 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 119:aae6fcc7d9bb 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 119:aae6fcc7d9bb 443 __ICIALLU = 0;
Kojto 119:aae6fcc7d9bb 444 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 119:aae6fcc7d9bb 446 }
Kojto 119:aae6fcc7d9bb 447
Kojto 119:aae6fcc7d9bb 448 /** \brief Clean D$ by MVA
Kojto 119:aae6fcc7d9bb 449
Kojto 119:aae6fcc7d9bb 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 119:aae6fcc7d9bb 451 */
Kojto 119:aae6fcc7d9bb 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 119:aae6fcc7d9bb 454 __DCCMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 456 }
Kojto 119:aae6fcc7d9bb 457
Kojto 119:aae6fcc7d9bb 458 /** \brief Invalidate D$ by MVA
Kojto 119:aae6fcc7d9bb 459
Kojto 119:aae6fcc7d9bb 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 119:aae6fcc7d9bb 461 */
Kojto 119:aae6fcc7d9bb 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 119:aae6fcc7d9bb 464 __DCIMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 466 }
Kojto 119:aae6fcc7d9bb 467
Kojto 119:aae6fcc7d9bb 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 119:aae6fcc7d9bb 469
Kojto 119:aae6fcc7d9bb 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 119:aae6fcc7d9bb 471 */
Kojto 119:aae6fcc7d9bb 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 119:aae6fcc7d9bb 474 __DCCIMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 476 }
Kojto 119:aae6fcc7d9bb 477
Kojto 119:aae6fcc7d9bb 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 119:aae6fcc7d9bb 479
Kojto 119:aae6fcc7d9bb 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 119:aae6fcc7d9bb 481 */
Kojto 119:aae6fcc7d9bb 482 #pragma push
Kojto 119:aae6fcc7d9bb 483 #pragma arm
Kojto 119:aae6fcc7d9bb 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 119:aae6fcc7d9bb 485 ARM
Kojto 119:aae6fcc7d9bb 486
Kojto 119:aae6fcc7d9bb 487 PUSH {R4-R11}
Kojto 119:aae6fcc7d9bb 488
Kojto 119:aae6fcc7d9bb 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 119:aae6fcc7d9bb 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 119:aae6fcc7d9bb 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 119:aae6fcc7d9bb 492 BEQ Finished // If 0, no need to clean
Kojto 119:aae6fcc7d9bb 493
Kojto 119:aae6fcc7d9bb 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 119:aae6fcc7d9bb 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 119:aae6fcc7d9bb 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 119:aae6fcc7d9bb 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 119:aae6fcc7d9bb 498 CMP R1, #2
Kojto 119:aae6fcc7d9bb 499 BLT Skip // No cache or only instruction cache at this level
Kojto 119:aae6fcc7d9bb 500
Kojto 119:aae6fcc7d9bb 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 119:aae6fcc7d9bb 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 119:aae6fcc7d9bb 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 119:aae6fcc7d9bb 504 AND R2, R1, #7 // Extract the line length field
Kojto 119:aae6fcc7d9bb 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 119:aae6fcc7d9bb 506 LDR R4, =0x3FF
Kojto 119:aae6fcc7d9bb 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 119:aae6fcc7d9bb 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 119:aae6fcc7d9bb 509 LDR R7, =0x7FFF
Kojto 119:aae6fcc7d9bb 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 119:aae6fcc7d9bb 511
Kojto 119:aae6fcc7d9bb 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 119:aae6fcc7d9bb 513
Kojto 119:aae6fcc7d9bb 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 119:aae6fcc7d9bb 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 119:aae6fcc7d9bb 516 CMP R0, #0
Kojto 119:aae6fcc7d9bb 517 BNE Dccsw
Kojto 119:aae6fcc7d9bb 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 519 B cont
Kojto 119:aae6fcc7d9bb 520 Dccsw CMP R0, #1
Kojto 119:aae6fcc7d9bb 521 BNE Dccisw
Kojto 119:aae6fcc7d9bb 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 119:aae6fcc7d9bb 523 B cont
Kojto 119:aae6fcc7d9bb 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 119:aae6fcc7d9bb 526 BGE Loop3
Kojto 119:aae6fcc7d9bb 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 119:aae6fcc7d9bb 528 BGE Loop2
Kojto 119:aae6fcc7d9bb 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 119:aae6fcc7d9bb 530 CMP R3, R10
Kojto 119:aae6fcc7d9bb 531 BGT Loop1
Kojto 119:aae6fcc7d9bb 532
Kojto 119:aae6fcc7d9bb 533 Finished
Kojto 119:aae6fcc7d9bb 534 DSB
Kojto 119:aae6fcc7d9bb 535 POP {R4-R11}
Kojto 119:aae6fcc7d9bb 536 BX lr
Kojto 119:aae6fcc7d9bb 537
Kojto 119:aae6fcc7d9bb 538 }
Kojto 119:aae6fcc7d9bb 539 #pragma pop
Kojto 119:aae6fcc7d9bb 540
Kojto 119:aae6fcc7d9bb 541
Kojto 119:aae6fcc7d9bb 542 /** \brief Invalidate the whole D$
Kojto 119:aae6fcc7d9bb 543
Kojto 119:aae6fcc7d9bb 544 DCISW. Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 545 */
Kojto 119:aae6fcc7d9bb 546
Kojto 119:aae6fcc7d9bb 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 548 __v7_all_cache(0);
Kojto 119:aae6fcc7d9bb 549 }
Kojto 119:aae6fcc7d9bb 550
Kojto 119:aae6fcc7d9bb 551 /** \brief Clean the whole D$
Kojto 119:aae6fcc7d9bb 552
Kojto 119:aae6fcc7d9bb 553 DCCSW. Clean by Set/Way
Kojto 119:aae6fcc7d9bb 554 */
Kojto 119:aae6fcc7d9bb 555
Kojto 119:aae6fcc7d9bb 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 557 __v7_all_cache(1);
Kojto 119:aae6fcc7d9bb 558 }
Kojto 119:aae6fcc7d9bb 559
Kojto 119:aae6fcc7d9bb 560 /** \brief Clean and invalidate the whole D$
Kojto 119:aae6fcc7d9bb 561
Kojto 119:aae6fcc7d9bb 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 563 */
Kojto 119:aae6fcc7d9bb 564
Kojto 119:aae6fcc7d9bb 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 566 __v7_all_cache(2);
Kojto 119:aae6fcc7d9bb 567 }
Kojto 119:aae6fcc7d9bb 568
Kojto 119:aae6fcc7d9bb 569 #include "core_ca_mmu.h"
Kojto 119:aae6fcc7d9bb 570
Kojto 119:aae6fcc7d9bb 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 119:aae6fcc7d9bb 572
Kojto 119:aae6fcc7d9bb 573 #define __inline inline
Kojto 119:aae6fcc7d9bb 574
Kojto 119:aae6fcc7d9bb 575 inline static uint32_t __disable_irq_iar() {
Kojto 119:aae6fcc7d9bb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 119:aae6fcc7d9bb 577 __disable_irq();
Kojto 119:aae6fcc7d9bb 578 return irq_dis;
Kojto 119:aae6fcc7d9bb 579 }
Kojto 119:aae6fcc7d9bb 580
Kojto 119:aae6fcc7d9bb 581 #define MODE_USR 0x10
Kojto 119:aae6fcc7d9bb 582 #define MODE_FIQ 0x11
Kojto 119:aae6fcc7d9bb 583 #define MODE_IRQ 0x12
Kojto 119:aae6fcc7d9bb 584 #define MODE_SVC 0x13
Kojto 119:aae6fcc7d9bb 585 #define MODE_MON 0x16
Kojto 119:aae6fcc7d9bb 586 #define MODE_ABT 0x17
Kojto 119:aae6fcc7d9bb 587 #define MODE_HYP 0x1A
Kojto 119:aae6fcc7d9bb 588 #define MODE_UND 0x1B
Kojto 119:aae6fcc7d9bb 589 #define MODE_SYS 0x1F
Kojto 119:aae6fcc7d9bb 590
Kojto 119:aae6fcc7d9bb 591 /** \brief Set Process Stack Pointer
Kojto 119:aae6fcc7d9bb 592
Kojto 119:aae6fcc7d9bb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 119:aae6fcc7d9bb 594
Kojto 119:aae6fcc7d9bb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 119:aae6fcc7d9bb 596 */
Kojto 119:aae6fcc7d9bb 597 // from rt_CMSIS.c
Kojto 119:aae6fcc7d9bb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 119:aae6fcc7d9bb 599 __asm(
Kojto 119:aae6fcc7d9bb 600 " ARM\n"
Kojto 119:aae6fcc7d9bb 601 // " PRESERVE8\n"
Kojto 119:aae6fcc7d9bb 602
Kojto 119:aae6fcc7d9bb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 119:aae6fcc7d9bb 604 " MRS R1, CPSR \n"
Kojto 119:aae6fcc7d9bb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 119:aae6fcc7d9bb 606 " MOV SP, R0 \n"
Kojto 119:aae6fcc7d9bb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 119:aae6fcc7d9bb 608 " ISB \n"
Kojto 119:aae6fcc7d9bb 609 " BX LR \n");
Kojto 119:aae6fcc7d9bb 610 }
Kojto 119:aae6fcc7d9bb 611
Kojto 119:aae6fcc7d9bb 612 /** \brief Set User Mode
Kojto 119:aae6fcc7d9bb 613
Kojto 119:aae6fcc7d9bb 614 This function changes the processor state to User Mode
Kojto 119:aae6fcc7d9bb 615 */
Kojto 119:aae6fcc7d9bb 616 // from rt_CMSIS.c
Kojto 119:aae6fcc7d9bb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 119:aae6fcc7d9bb 618 __asm(
Kojto 119:aae6fcc7d9bb 619 " ARM \n"
Kojto 119:aae6fcc7d9bb 620
Kojto 119:aae6fcc7d9bb 621 " CPS #0x10 \n" // MODE_USR
Kojto 119:aae6fcc7d9bb 622 " BX LR\n");
Kojto 119:aae6fcc7d9bb 623 }
Kojto 119:aae6fcc7d9bb 624
Kojto 119:aae6fcc7d9bb 625 /** \brief Set TTBR0
Kojto 119:aae6fcc7d9bb 626
Kojto 119:aae6fcc7d9bb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 119:aae6fcc7d9bb 628
Kojto 119:aae6fcc7d9bb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 119:aae6fcc7d9bb 630 */
Kojto 119:aae6fcc7d9bb 631 // from mmu_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 119:aae6fcc7d9bb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 634 __ISB();
Kojto 119:aae6fcc7d9bb 635 }
Kojto 119:aae6fcc7d9bb 636
Kojto 119:aae6fcc7d9bb 637 /** \brief Set DACR
Kojto 119:aae6fcc7d9bb 638
Kojto 119:aae6fcc7d9bb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 119:aae6fcc7d9bb 640
Kojto 119:aae6fcc7d9bb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 119:aae6fcc7d9bb 642 */
Kojto 119:aae6fcc7d9bb 643 // from mmu_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 119:aae6fcc7d9bb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 646 __ISB();
Kojto 119:aae6fcc7d9bb 647 }
Kojto 119:aae6fcc7d9bb 648
Kojto 119:aae6fcc7d9bb 649
Kojto 119:aae6fcc7d9bb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 119:aae6fcc7d9bb 651 /** \brief Set SCTLR
Kojto 119:aae6fcc7d9bb 652
Kojto 119:aae6fcc7d9bb 653 This function assigns the given value to the System Control Register.
Kojto 119:aae6fcc7d9bb 654
Kojto 119:aae6fcc7d9bb 655 \param [in] sctlr System Control Register value to set
Kojto 119:aae6fcc7d9bb 656 */
Kojto 119:aae6fcc7d9bb 657 // from __enable_mmu()
Kojto 119:aae6fcc7d9bb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 119:aae6fcc7d9bb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 660 }
Kojto 119:aae6fcc7d9bb 661
Kojto 119:aae6fcc7d9bb 662 /** \brief Get SCTLR
Kojto 119:aae6fcc7d9bb 663
Kojto 119:aae6fcc7d9bb 664 This function returns the value of the System Control Register.
Kojto 119:aae6fcc7d9bb 665
Kojto 119:aae6fcc7d9bb 666 \return System Control Register value
Kojto 119:aae6fcc7d9bb 667 */
Kojto 119:aae6fcc7d9bb 668 // from __enable_mmu()
Kojto 119:aae6fcc7d9bb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 119:aae6fcc7d9bb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 119:aae6fcc7d9bb 671 return __regSCTLR;
Kojto 119:aae6fcc7d9bb 672 }
Kojto 119:aae6fcc7d9bb 673
Kojto 119:aae6fcc7d9bb 674 /** \brief Enable Caches
Kojto 119:aae6fcc7d9bb 675
Kojto 119:aae6fcc7d9bb 676 Enable Caches
Kojto 119:aae6fcc7d9bb 677 */
Kojto 119:aae6fcc7d9bb 678 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 119:aae6fcc7d9bb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 119:aae6fcc7d9bb 681 }
Kojto 119:aae6fcc7d9bb 682
Kojto 119:aae6fcc7d9bb 683 /** \brief Enable BTAC
Kojto 119:aae6fcc7d9bb 684
Kojto 119:aae6fcc7d9bb 685 Enable BTAC
Kojto 119:aae6fcc7d9bb 686 */
Kojto 119:aae6fcc7d9bb 687 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 119:aae6fcc7d9bb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 119:aae6fcc7d9bb 690 __ISB();
Kojto 119:aae6fcc7d9bb 691 }
Kojto 119:aae6fcc7d9bb 692
Kojto 119:aae6fcc7d9bb 693 /** \brief Enable MMU
Kojto 119:aae6fcc7d9bb 694
Kojto 119:aae6fcc7d9bb 695 Enable MMU
Kojto 119:aae6fcc7d9bb 696 */
Kojto 119:aae6fcc7d9bb 697 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 119:aae6fcc7d9bb 699 // Set M bit 0 to enable the MMU
Kojto 119:aae6fcc7d9bb 700 // Set AFE bit to enable simplified access permissions model
Kojto 119:aae6fcc7d9bb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 119:aae6fcc7d9bb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 119:aae6fcc7d9bb 703 __ISB();
Kojto 119:aae6fcc7d9bb 704 }
Kojto 119:aae6fcc7d9bb 705
Kojto 119:aae6fcc7d9bb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 707 /** \brief Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 708
Kojto 119:aae6fcc7d9bb 709 TLBIALL. Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 710 */
Kojto 119:aae6fcc7d9bb 711 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 119:aae6fcc7d9bb 713 uint32_t val = 0;
Kojto 119:aae6fcc7d9bb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 717 __DSB();
Kojto 119:aae6fcc7d9bb 718 __ISB();
Kojto 119:aae6fcc7d9bb 719 }
Kojto 119:aae6fcc7d9bb 720
Kojto 119:aae6fcc7d9bb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 722 /** \brief Invalidate entire branch predictor array
Kojto 119:aae6fcc7d9bb 723
Kojto 119:aae6fcc7d9bb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 119:aae6fcc7d9bb 725 */
Kojto 119:aae6fcc7d9bb 726 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 119:aae6fcc7d9bb 728 uint32_t val = 0;
Kojto 119:aae6fcc7d9bb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 119:aae6fcc7d9bb 730 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 119:aae6fcc7d9bb 732 }
Kojto 119:aae6fcc7d9bb 733
Kojto 119:aae6fcc7d9bb 734
Kojto 119:aae6fcc7d9bb 735 /******************************** L1 cache operations ******************************************************/
Kojto 119:aae6fcc7d9bb 736
Kojto 119:aae6fcc7d9bb 737 /** \brief Invalidate the whole I$
Kojto 119:aae6fcc7d9bb 738
Kojto 119:aae6fcc7d9bb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 119:aae6fcc7d9bb 740 */
Kojto 119:aae6fcc7d9bb 741 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 119:aae6fcc7d9bb 743 uint32_t val = 0;
Kojto 119:aae6fcc7d9bb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 119:aae6fcc7d9bb 745 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 119:aae6fcc7d9bb 747 }
Kojto 119:aae6fcc7d9bb 748
Kojto 119:aae6fcc7d9bb 749 // from __v7_inv_dcache_all()
Kojto 119:aae6fcc7d9bb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 119:aae6fcc7d9bb 751 __asm(
Kojto 119:aae6fcc7d9bb 752 " ARM \n"
Kojto 119:aae6fcc7d9bb 753
Kojto 119:aae6fcc7d9bb 754 " PUSH {R4-R11} \n"
Kojto 119:aae6fcc7d9bb 755
Kojto 119:aae6fcc7d9bb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 119:aae6fcc7d9bb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 119:aae6fcc7d9bb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 119:aae6fcc7d9bb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 119:aae6fcc7d9bb 760
Kojto 119:aae6fcc7d9bb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 119:aae6fcc7d9bb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 119:aae6fcc7d9bb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 119:aae6fcc7d9bb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 119:aae6fcc7d9bb 765 " CMP R1, #2 \n"
Kojto 119:aae6fcc7d9bb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 119:aae6fcc7d9bb 767
Kojto 119:aae6fcc7d9bb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 119:aae6fcc7d9bb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 119:aae6fcc7d9bb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 119:aae6fcc7d9bb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 119:aae6fcc7d9bb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 119:aae6fcc7d9bb 773 " movw R4, #0x3FF \n"
Kojto 119:aae6fcc7d9bb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 119:aae6fcc7d9bb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 119:aae6fcc7d9bb 776 " movw R7, #0x7FFF \n"
Kojto 119:aae6fcc7d9bb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 119:aae6fcc7d9bb 778
Kojto 119:aae6fcc7d9bb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 119:aae6fcc7d9bb 780
Kojto 119:aae6fcc7d9bb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 119:aae6fcc7d9bb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 119:aae6fcc7d9bb 783 " CMP R0, #0 \n"
Kojto 119:aae6fcc7d9bb 784 " BNE Dccsw \n"
Kojto 119:aae6fcc7d9bb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 786 " B cont \n"
Kojto 119:aae6fcc7d9bb 787 "Dccsw: CMP R0, #1 \n"
Kojto 119:aae6fcc7d9bb 788 " BNE Dccisw \n"
Kojto 119:aae6fcc7d9bb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 119:aae6fcc7d9bb 790 " B cont \n"
Kojto 119:aae6fcc7d9bb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 119:aae6fcc7d9bb 793 " BGE Loop3 \n"
Kojto 119:aae6fcc7d9bb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 119:aae6fcc7d9bb 795 " BGE Loop2 \n"
Kojto 119:aae6fcc7d9bb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 119:aae6fcc7d9bb 797 " CMP R3, R10 \n"
Kojto 119:aae6fcc7d9bb 798 " BGT Loop1 \n"
Kojto 119:aae6fcc7d9bb 799
Kojto 119:aae6fcc7d9bb 800 "Finished: \n"
Kojto 119:aae6fcc7d9bb 801 " DSB \n"
Kojto 119:aae6fcc7d9bb 802 " POP {R4-R11} \n"
Kojto 119:aae6fcc7d9bb 803 " BX lr \n" );
Kojto 119:aae6fcc7d9bb 804 }
Kojto 119:aae6fcc7d9bb 805
Kojto 119:aae6fcc7d9bb 806 /** \brief Invalidate the whole D$
Kojto 119:aae6fcc7d9bb 807
Kojto 119:aae6fcc7d9bb 808 DCISW. Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 809 */
Kojto 119:aae6fcc7d9bb 810 // from system_Renesas_RZ_A1.c
Kojto 119:aae6fcc7d9bb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 812 __v7_all_cache(0);
Kojto 119:aae6fcc7d9bb 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 121:6c34061e7c34 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 832
Kojto 121:6c34061e7c34 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 834 */
Kojto 121:6c34061e7c34 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 837 __DMB();
Kojto 121:6c34061e7c34 838 }
Kojto 121:6c34061e7c34 839
Kojto 119:aae6fcc7d9bb 840 #include "core_ca_mmu.h"
Kojto 119:aae6fcc7d9bb 841
Kojto 119:aae6fcc7d9bb 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 119:aae6fcc7d9bb 843 /* GNU gcc specific functions */
Kojto 119:aae6fcc7d9bb 844
Kojto 119:aae6fcc7d9bb 845 #define MODE_USR 0x10
Kojto 119:aae6fcc7d9bb 846 #define MODE_FIQ 0x11
Kojto 119:aae6fcc7d9bb 847 #define MODE_IRQ 0x12
Kojto 119:aae6fcc7d9bb 848 #define MODE_SVC 0x13
Kojto 119:aae6fcc7d9bb 849 #define MODE_MON 0x16
Kojto 119:aae6fcc7d9bb 850 #define MODE_ABT 0x17
Kojto 119:aae6fcc7d9bb 851 #define MODE_HYP 0x1A
Kojto 119:aae6fcc7d9bb 852 #define MODE_UND 0x1B
Kojto 119:aae6fcc7d9bb 853 #define MODE_SYS 0x1F
Kojto 119:aae6fcc7d9bb 854
Kojto 119:aae6fcc7d9bb 855
Kojto 119:aae6fcc7d9bb 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 119:aae6fcc7d9bb 857 {
Kojto 119:aae6fcc7d9bb 858 __ASM volatile ("cpsie i");
Kojto 119:aae6fcc7d9bb 859 }
Kojto 119:aae6fcc7d9bb 860
Kojto 119:aae6fcc7d9bb 861 /** \brief Disable IRQ Interrupts
Kojto 119:aae6fcc7d9bb 862
Kojto 119:aae6fcc7d9bb 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 119:aae6fcc7d9bb 864 Can only be executed in Privileged modes.
Kojto 119:aae6fcc7d9bb 865 */
Kojto 119:aae6fcc7d9bb 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 119:aae6fcc7d9bb 867 {
Kojto 119:aae6fcc7d9bb 868 uint32_t result;
Kojto 119:aae6fcc7d9bb 869
Kojto 119:aae6fcc7d9bb 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 119:aae6fcc7d9bb 871 __ASM volatile ("cpsid i");
Kojto 119:aae6fcc7d9bb 872 return(result & 0x80);
Kojto 119:aae6fcc7d9bb 873 }
Kojto 119:aae6fcc7d9bb 874
Kojto 119:aae6fcc7d9bb 875
Kojto 119:aae6fcc7d9bb 876 /** \brief Get APSR Register
Kojto 119:aae6fcc7d9bb 877
Kojto 119:aae6fcc7d9bb 878 This function returns the content of the APSR Register.
Kojto 119:aae6fcc7d9bb 879
Kojto 119:aae6fcc7d9bb 880 \return APSR Register value
Kojto 119:aae6fcc7d9bb 881 */
Kojto 119:aae6fcc7d9bb 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 119:aae6fcc7d9bb 883 {
Kojto 119:aae6fcc7d9bb 884 #if 1
Kojto 119:aae6fcc7d9bb 885 register uint32_t __regAPSR;
Kojto 119:aae6fcc7d9bb 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 119:aae6fcc7d9bb 887 #else
Kojto 119:aae6fcc7d9bb 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 119:aae6fcc7d9bb 889 #endif
Kojto 119:aae6fcc7d9bb 890 return(__regAPSR);
Kojto 119:aae6fcc7d9bb 891 }
Kojto 119:aae6fcc7d9bb 892
Kojto 119:aae6fcc7d9bb 893
Kojto 119:aae6fcc7d9bb 894 /** \brief Get CPSR Register
Kojto 119:aae6fcc7d9bb 895
Kojto 119:aae6fcc7d9bb 896 This function returns the content of the CPSR Register.
Kojto 119:aae6fcc7d9bb 897
Kojto 119:aae6fcc7d9bb 898 \return CPSR Register value
Kojto 119:aae6fcc7d9bb 899 */
Kojto 119:aae6fcc7d9bb 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 119:aae6fcc7d9bb 901 {
Kojto 119:aae6fcc7d9bb 902 #if 1
Kojto 119:aae6fcc7d9bb 903 register uint32_t __regCPSR;
Kojto 119:aae6fcc7d9bb 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 119:aae6fcc7d9bb 905 #else
Kojto 119:aae6fcc7d9bb 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 119:aae6fcc7d9bb 907 #endif
Kojto 119:aae6fcc7d9bb 908 return(__regCPSR);
Kojto 119:aae6fcc7d9bb 909 }
Kojto 119:aae6fcc7d9bb 910
Kojto 119:aae6fcc7d9bb 911 #if 0
Kojto 119:aae6fcc7d9bb 912 /** \brief Set Stack Pointer
Kojto 119:aae6fcc7d9bb 913
Kojto 119:aae6fcc7d9bb 914 This function assigns the given value to the current stack pointer.
Kojto 119:aae6fcc7d9bb 915
Kojto 119:aae6fcc7d9bb 916 \param [in] topOfStack Stack Pointer value to set
Kojto 119:aae6fcc7d9bb 917 */
Kojto 119:aae6fcc7d9bb 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 119:aae6fcc7d9bb 919 {
Kojto 119:aae6fcc7d9bb 920 register uint32_t __regSP __ASM("sp");
Kojto 119:aae6fcc7d9bb 921 __regSP = topOfStack;
Kojto 119:aae6fcc7d9bb 922 }
Kojto 119:aae6fcc7d9bb 923 #endif
Kojto 119:aae6fcc7d9bb 924
Kojto 119:aae6fcc7d9bb 925 /** \brief Get link register
Kojto 119:aae6fcc7d9bb 926
Kojto 119:aae6fcc7d9bb 927 This function returns the value of the link register
Kojto 119:aae6fcc7d9bb 928
Kojto 119:aae6fcc7d9bb 929 \return Value of link register
Kojto 119:aae6fcc7d9bb 930 */
Kojto 119:aae6fcc7d9bb 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 119:aae6fcc7d9bb 932 {
Kojto 119:aae6fcc7d9bb 933 register uint32_t __reglr __ASM("lr");
Kojto 119:aae6fcc7d9bb 934 return(__reglr);
Kojto 119:aae6fcc7d9bb 935 }
Kojto 119:aae6fcc7d9bb 936
Kojto 119:aae6fcc7d9bb 937 #if 0
Kojto 119:aae6fcc7d9bb 938 /** \brief Set link register
Kojto 119:aae6fcc7d9bb 939
Kojto 119:aae6fcc7d9bb 940 This function sets the value of the link register
Kojto 119:aae6fcc7d9bb 941
Kojto 119:aae6fcc7d9bb 942 \param [in] lr LR value to set
Kojto 119:aae6fcc7d9bb 943 */
Kojto 119:aae6fcc7d9bb 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 119:aae6fcc7d9bb 945 {
Kojto 119:aae6fcc7d9bb 946 register uint32_t __reglr __ASM("lr");
Kojto 119:aae6fcc7d9bb 947 __reglr = lr;
Kojto 119:aae6fcc7d9bb 948 }
Kojto 119:aae6fcc7d9bb 949 #endif
Kojto 119:aae6fcc7d9bb 950
Kojto 119:aae6fcc7d9bb 951 /** \brief Set Process Stack Pointer
Kojto 119:aae6fcc7d9bb 952
Kojto 119:aae6fcc7d9bb 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 119:aae6fcc7d9bb 954
Kojto 119:aae6fcc7d9bb 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 119:aae6fcc7d9bb 956 */
Kojto 119:aae6fcc7d9bb 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 119:aae6fcc7d9bb 958 {
Kojto 119:aae6fcc7d9bb 959 __asm__ volatile (
Kojto 119:aae6fcc7d9bb 960 ".ARM;"
Kojto 119:aae6fcc7d9bb 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 119:aae6fcc7d9bb 962
Kojto 119:aae6fcc7d9bb 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 119:aae6fcc7d9bb 964 "MRS R1, CPSR;"
Kojto 119:aae6fcc7d9bb 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 119:aae6fcc7d9bb 966 "MOV SP, R0;"
Kojto 119:aae6fcc7d9bb 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 119:aae6fcc7d9bb 968 "ISB;"
Kojto 119:aae6fcc7d9bb 969 //"BX LR;"
Kojto 119:aae6fcc7d9bb 970 :
Kojto 119:aae6fcc7d9bb 971 : "i"(MODE_SYS)
Kojto 119:aae6fcc7d9bb 972 : "r0", "r1");
Kojto 119:aae6fcc7d9bb 973 return;
Kojto 119:aae6fcc7d9bb 974 }
Kojto 119:aae6fcc7d9bb 975
Kojto 119:aae6fcc7d9bb 976 /** \brief Set User Mode
Kojto 119:aae6fcc7d9bb 977
Kojto 119:aae6fcc7d9bb 978 This function changes the processor state to User Mode
Kojto 119:aae6fcc7d9bb 979 */
Kojto 119:aae6fcc7d9bb 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 119:aae6fcc7d9bb 981 {
Kojto 119:aae6fcc7d9bb 982 __asm__ volatile (
Kojto 119:aae6fcc7d9bb 983 ".ARM;"
Kojto 119:aae6fcc7d9bb 984
Kojto 119:aae6fcc7d9bb 985 "CPS %0;"
Kojto 119:aae6fcc7d9bb 986 //"BX LR;"
Kojto 119:aae6fcc7d9bb 987 :
Kojto 119:aae6fcc7d9bb 988 : "i"(MODE_USR)
Kojto 119:aae6fcc7d9bb 989 : );
Kojto 119:aae6fcc7d9bb 990 return;
Kojto 119:aae6fcc7d9bb 991 }
Kojto 119:aae6fcc7d9bb 992
Kojto 119:aae6fcc7d9bb 993
Kojto 119:aae6fcc7d9bb 994 /** \brief Enable FIQ
Kojto 119:aae6fcc7d9bb 995
Kojto 119:aae6fcc7d9bb 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 119:aae6fcc7d9bb 997 Can only be executed in Privileged modes.
Kojto 119:aae6fcc7d9bb 998 */
Kojto 119:aae6fcc7d9bb 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 119:aae6fcc7d9bb 1000
Kojto 119:aae6fcc7d9bb 1001
Kojto 119:aae6fcc7d9bb 1002 /** \brief Disable FIQ
Kojto 119:aae6fcc7d9bb 1003
Kojto 119:aae6fcc7d9bb 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 119:aae6fcc7d9bb 1005 Can only be executed in Privileged modes.
Kojto 119:aae6fcc7d9bb 1006 */
Kojto 119:aae6fcc7d9bb 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 119:aae6fcc7d9bb 1008
Kojto 119:aae6fcc7d9bb 1009
Kojto 119:aae6fcc7d9bb 1010 /** \brief Get FPSCR
Kojto 119:aae6fcc7d9bb 1011
Kojto 119:aae6fcc7d9bb 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 119:aae6fcc7d9bb 1013
Kojto 119:aae6fcc7d9bb 1014 \return Floating Point Status/Control register value
Kojto 119:aae6fcc7d9bb 1015 */
Kojto 119:aae6fcc7d9bb 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 119:aae6fcc7d9bb 1017 {
Kojto 119:aae6fcc7d9bb 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 119:aae6fcc7d9bb 1019 #if 1
Kojto 119:aae6fcc7d9bb 1020 uint32_t result;
Kojto 119:aae6fcc7d9bb 1021
Kojto 119:aae6fcc7d9bb 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 119:aae6fcc7d9bb 1023 return (result);
Kojto 119:aae6fcc7d9bb 1024 #else
Kojto 119:aae6fcc7d9bb 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 119:aae6fcc7d9bb 1026 return(__regfpscr);
Kojto 119:aae6fcc7d9bb 1027 #endif
Kojto 119:aae6fcc7d9bb 1028 #else
Kojto 119:aae6fcc7d9bb 1029 return(0);
Kojto 119:aae6fcc7d9bb 1030 #endif
Kojto 119:aae6fcc7d9bb 1031 }
Kojto 119:aae6fcc7d9bb 1032
Kojto 119:aae6fcc7d9bb 1033
Kojto 119:aae6fcc7d9bb 1034 /** \brief Set FPSCR
Kojto 119:aae6fcc7d9bb 1035
Kojto 119:aae6fcc7d9bb 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 119:aae6fcc7d9bb 1037
Kojto 119:aae6fcc7d9bb 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 119:aae6fcc7d9bb 1039 */
Kojto 119:aae6fcc7d9bb 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 119:aae6fcc7d9bb 1041 {
Kojto 119:aae6fcc7d9bb 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 119:aae6fcc7d9bb 1043 #if 1
Kojto 119:aae6fcc7d9bb 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 119:aae6fcc7d9bb 1045 #else
Kojto 119:aae6fcc7d9bb 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 119:aae6fcc7d9bb 1047 __regfpscr = (fpscr);
Kojto 119:aae6fcc7d9bb 1048 #endif
Kojto 119:aae6fcc7d9bb 1049 #endif
Kojto 119:aae6fcc7d9bb 1050 }
Kojto 119:aae6fcc7d9bb 1051
Kojto 119:aae6fcc7d9bb 1052 /** \brief Get FPEXC
Kojto 119:aae6fcc7d9bb 1053
Kojto 119:aae6fcc7d9bb 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 119:aae6fcc7d9bb 1055
Kojto 119:aae6fcc7d9bb 1056 \return Floating Point Exception Control register value
Kojto 119:aae6fcc7d9bb 1057 */
Kojto 119:aae6fcc7d9bb 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 119:aae6fcc7d9bb 1059 {
Kojto 119:aae6fcc7d9bb 1060 #if (__FPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 1061 #if 1
Kojto 119:aae6fcc7d9bb 1062 uint32_t result;
Kojto 119:aae6fcc7d9bb 1063
Kojto 119:aae6fcc7d9bb 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 119:aae6fcc7d9bb 1065 return (result);
Kojto 119:aae6fcc7d9bb 1066 #else
Kojto 119:aae6fcc7d9bb 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 119:aae6fcc7d9bb 1068 return(__regfpexc);
Kojto 119:aae6fcc7d9bb 1069 #endif
Kojto 119:aae6fcc7d9bb 1070 #else
Kojto 119:aae6fcc7d9bb 1071 return(0);
Kojto 119:aae6fcc7d9bb 1072 #endif
Kojto 119:aae6fcc7d9bb 1073 }
Kojto 119:aae6fcc7d9bb 1074
Kojto 119:aae6fcc7d9bb 1075
Kojto 119:aae6fcc7d9bb 1076 /** \brief Set FPEXC
Kojto 119:aae6fcc7d9bb 1077
Kojto 119:aae6fcc7d9bb 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 119:aae6fcc7d9bb 1079
Kojto 119:aae6fcc7d9bb 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 119:aae6fcc7d9bb 1081 */
Kojto 119:aae6fcc7d9bb 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 119:aae6fcc7d9bb 1083 {
Kojto 119:aae6fcc7d9bb 1084 #if (__FPU_PRESENT == 1)
Kojto 119:aae6fcc7d9bb 1085 #if 1
Kojto 119:aae6fcc7d9bb 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 119:aae6fcc7d9bb 1087 #else
Kojto 119:aae6fcc7d9bb 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 119:aae6fcc7d9bb 1089 __regfpexc = (fpexc);
Kojto 119:aae6fcc7d9bb 1090 #endif
Kojto 119:aae6fcc7d9bb 1091 #endif
Kojto 119:aae6fcc7d9bb 1092 }
Kojto 119:aae6fcc7d9bb 1093
Kojto 119:aae6fcc7d9bb 1094 /** \brief Get CPACR
Kojto 119:aae6fcc7d9bb 1095
Kojto 119:aae6fcc7d9bb 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 119:aae6fcc7d9bb 1097
Kojto 119:aae6fcc7d9bb 1098 \return Coprocessor Access Control register value
Kojto 119:aae6fcc7d9bb 1099 */
Kojto 119:aae6fcc7d9bb 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 119:aae6fcc7d9bb 1101 {
Kojto 119:aae6fcc7d9bb 1102 #if 1
Kojto 119:aae6fcc7d9bb 1103 register uint32_t __regCPACR;
Kojto 119:aae6fcc7d9bb 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 119:aae6fcc7d9bb 1105 #else
Kojto 119:aae6fcc7d9bb 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 119:aae6fcc7d9bb 1107 #endif
Kojto 119:aae6fcc7d9bb 1108 return __regCPACR;
Kojto 119:aae6fcc7d9bb 1109 }
Kojto 119:aae6fcc7d9bb 1110
Kojto 119:aae6fcc7d9bb 1111 /** \brief Set CPACR
Kojto 119:aae6fcc7d9bb 1112
Kojto 119:aae6fcc7d9bb 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 119:aae6fcc7d9bb 1114
Kojto 119:aae6fcc7d9bb 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 119:aae6fcc7d9bb 1116 */
Kojto 119:aae6fcc7d9bb 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 119:aae6fcc7d9bb 1118 {
Kojto 119:aae6fcc7d9bb 1119 #if 1
Kojto 119:aae6fcc7d9bb 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 119:aae6fcc7d9bb 1121 #else
Kojto 119:aae6fcc7d9bb 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 119:aae6fcc7d9bb 1123 __regCPACR = cpacr;
Kojto 119:aae6fcc7d9bb 1124 #endif
Kojto 119:aae6fcc7d9bb 1125 __ISB();
Kojto 119:aae6fcc7d9bb 1126 }
Kojto 119:aae6fcc7d9bb 1127
Kojto 119:aae6fcc7d9bb 1128 /** \brief Get CBAR
Kojto 119:aae6fcc7d9bb 1129
Kojto 119:aae6fcc7d9bb 1130 This function returns the value of the Configuration Base Address register.
Kojto 119:aae6fcc7d9bb 1131
Kojto 119:aae6fcc7d9bb 1132 \return Configuration Base Address register value
Kojto 119:aae6fcc7d9bb 1133 */
Kojto 119:aae6fcc7d9bb 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 119:aae6fcc7d9bb 1135 #if 1
Kojto 119:aae6fcc7d9bb 1136 register uint32_t __regCBAR;
Kojto 119:aae6fcc7d9bb 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 119:aae6fcc7d9bb 1138 #else
Kojto 119:aae6fcc7d9bb 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 119:aae6fcc7d9bb 1140 #endif
Kojto 119:aae6fcc7d9bb 1141 return(__regCBAR);
Kojto 119:aae6fcc7d9bb 1142 }
Kojto 119:aae6fcc7d9bb 1143
Kojto 119:aae6fcc7d9bb 1144 /** \brief Get TTBR0
Kojto 119:aae6fcc7d9bb 1145
Kojto 119:aae6fcc7d9bb 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 119:aae6fcc7d9bb 1147
Kojto 119:aae6fcc7d9bb 1148 \return Translation Table Base Register 0 value
Kojto 119:aae6fcc7d9bb 1149 */
Kojto 119:aae6fcc7d9bb 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 119:aae6fcc7d9bb 1151 #if 1
Kojto 119:aae6fcc7d9bb 1152 register uint32_t __regTTBR0;
Kojto 119:aae6fcc7d9bb 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 119:aae6fcc7d9bb 1154 #else
Kojto 119:aae6fcc7d9bb 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 119:aae6fcc7d9bb 1156 #endif
Kojto 119:aae6fcc7d9bb 1157 return(__regTTBR0);
Kojto 119:aae6fcc7d9bb 1158 }
Kojto 119:aae6fcc7d9bb 1159
Kojto 119:aae6fcc7d9bb 1160 /** \brief Set TTBR0
Kojto 119:aae6fcc7d9bb 1161
Kojto 119:aae6fcc7d9bb 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 119:aae6fcc7d9bb 1163
Kojto 119:aae6fcc7d9bb 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 119:aae6fcc7d9bb 1165 */
Kojto 119:aae6fcc7d9bb 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 119:aae6fcc7d9bb 1167 #if 1
Kojto 119:aae6fcc7d9bb 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 119:aae6fcc7d9bb 1169 #else
Kojto 119:aae6fcc7d9bb 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 119:aae6fcc7d9bb 1171 __regTTBR0 = ttbr0;
Kojto 119:aae6fcc7d9bb 1172 #endif
Kojto 119:aae6fcc7d9bb 1173 __ISB();
Kojto 119:aae6fcc7d9bb 1174 }
Kojto 119:aae6fcc7d9bb 1175
Kojto 119:aae6fcc7d9bb 1176 /** \brief Get DACR
Kojto 119:aae6fcc7d9bb 1177
Kojto 119:aae6fcc7d9bb 1178 This function returns the value of the Domain Access Control Register.
Kojto 119:aae6fcc7d9bb 1179
Kojto 119:aae6fcc7d9bb 1180 \return Domain Access Control Register value
Kojto 119:aae6fcc7d9bb 1181 */
Kojto 119:aae6fcc7d9bb 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 119:aae6fcc7d9bb 1183 #if 1
Kojto 119:aae6fcc7d9bb 1184 register uint32_t __regDACR;
Kojto 119:aae6fcc7d9bb 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 119:aae6fcc7d9bb 1186 #else
Kojto 119:aae6fcc7d9bb 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 119:aae6fcc7d9bb 1188 #endif
Kojto 119:aae6fcc7d9bb 1189 return(__regDACR);
Kojto 119:aae6fcc7d9bb 1190 }
Kojto 119:aae6fcc7d9bb 1191
Kojto 119:aae6fcc7d9bb 1192 /** \brief Set DACR
Kojto 119:aae6fcc7d9bb 1193
Kojto 119:aae6fcc7d9bb 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 119:aae6fcc7d9bb 1195
Kojto 119:aae6fcc7d9bb 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 119:aae6fcc7d9bb 1197 */
Kojto 119:aae6fcc7d9bb 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 119:aae6fcc7d9bb 1199 #if 1
Kojto 119:aae6fcc7d9bb 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 119:aae6fcc7d9bb 1201 #else
Kojto 119:aae6fcc7d9bb 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 119:aae6fcc7d9bb 1203 __regDACR = dacr;
Kojto 119:aae6fcc7d9bb 1204 #endif
Kojto 119:aae6fcc7d9bb 1205 __ISB();
Kojto 119:aae6fcc7d9bb 1206 }
Kojto 119:aae6fcc7d9bb 1207
Kojto 119:aae6fcc7d9bb 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 119:aae6fcc7d9bb 1209
Kojto 119:aae6fcc7d9bb 1210 /** \brief Set SCTLR
Kojto 119:aae6fcc7d9bb 1211
Kojto 119:aae6fcc7d9bb 1212 This function assigns the given value to the System Control Register.
Kojto 119:aae6fcc7d9bb 1213
Kojto 119:aae6fcc7d9bb 1214 \param [in] sctlr System Control Register value to set
Kojto 119:aae6fcc7d9bb 1215 */
Kojto 119:aae6fcc7d9bb 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 119:aae6fcc7d9bb 1217 {
Kojto 119:aae6fcc7d9bb 1218 #if 1
Kojto 119:aae6fcc7d9bb 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 119:aae6fcc7d9bb 1220 #else
Kojto 119:aae6fcc7d9bb 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 119:aae6fcc7d9bb 1222 __regSCTLR = sctlr;
Kojto 119:aae6fcc7d9bb 1223 #endif
Kojto 119:aae6fcc7d9bb 1224 }
Kojto 119:aae6fcc7d9bb 1225
Kojto 119:aae6fcc7d9bb 1226 /** \brief Get SCTLR
Kojto 119:aae6fcc7d9bb 1227
Kojto 119:aae6fcc7d9bb 1228 This function returns the value of the System Control Register.
Kojto 119:aae6fcc7d9bb 1229
Kojto 119:aae6fcc7d9bb 1230 \return System Control Register value
Kojto 119:aae6fcc7d9bb 1231 */
Kojto 119:aae6fcc7d9bb 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 119:aae6fcc7d9bb 1233 #if 1
Kojto 119:aae6fcc7d9bb 1234 register uint32_t __regSCTLR;
Kojto 119:aae6fcc7d9bb 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 119:aae6fcc7d9bb 1236 #else
Kojto 119:aae6fcc7d9bb 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 119:aae6fcc7d9bb 1238 #endif
Kojto 119:aae6fcc7d9bb 1239 return(__regSCTLR);
Kojto 119:aae6fcc7d9bb 1240 }
Kojto 119:aae6fcc7d9bb 1241
Kojto 119:aae6fcc7d9bb 1242 /** \brief Enable Caches
Kojto 119:aae6fcc7d9bb 1243
Kojto 119:aae6fcc7d9bb 1244 Enable Caches
Kojto 119:aae6fcc7d9bb 1245 */
Kojto 119:aae6fcc7d9bb 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 119:aae6fcc7d9bb 1247 // Set I bit 12 to enable I Cache
Kojto 119:aae6fcc7d9bb 1248 // Set C bit 2 to enable D Cache
Kojto 119:aae6fcc7d9bb 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 119:aae6fcc7d9bb 1250 }
Kojto 119:aae6fcc7d9bb 1251
Kojto 119:aae6fcc7d9bb 1252 /** \brief Disable Caches
Kojto 119:aae6fcc7d9bb 1253
Kojto 119:aae6fcc7d9bb 1254 Disable Caches
Kojto 119:aae6fcc7d9bb 1255 */
Kojto 119:aae6fcc7d9bb 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 119:aae6fcc7d9bb 1257 // Clear I bit 12 to disable I Cache
Kojto 119:aae6fcc7d9bb 1258 // Clear C bit 2 to disable D Cache
Kojto 119:aae6fcc7d9bb 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 119:aae6fcc7d9bb 1260 __ISB();
Kojto 119:aae6fcc7d9bb 1261 }
Kojto 119:aae6fcc7d9bb 1262
Kojto 119:aae6fcc7d9bb 1263 /** \brief Enable BTAC
Kojto 119:aae6fcc7d9bb 1264
Kojto 119:aae6fcc7d9bb 1265 Enable BTAC
Kojto 119:aae6fcc7d9bb 1266 */
Kojto 119:aae6fcc7d9bb 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 119:aae6fcc7d9bb 1268 // Set Z bit 11 to enable branch prediction
Kojto 119:aae6fcc7d9bb 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 119:aae6fcc7d9bb 1270 __ISB();
Kojto 119:aae6fcc7d9bb 1271 }
Kojto 119:aae6fcc7d9bb 1272
Kojto 119:aae6fcc7d9bb 1273 /** \brief Disable BTAC
Kojto 119:aae6fcc7d9bb 1274
Kojto 119:aae6fcc7d9bb 1275 Disable BTAC
Kojto 119:aae6fcc7d9bb 1276 */
Kojto 119:aae6fcc7d9bb 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 119:aae6fcc7d9bb 1278 // Clear Z bit 11 to disable branch prediction
Kojto 119:aae6fcc7d9bb 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 119:aae6fcc7d9bb 1280 }
Kojto 119:aae6fcc7d9bb 1281
Kojto 119:aae6fcc7d9bb 1282
Kojto 119:aae6fcc7d9bb 1283 /** \brief Enable MMU
Kojto 119:aae6fcc7d9bb 1284
Kojto 119:aae6fcc7d9bb 1285 Enable MMU
Kojto 119:aae6fcc7d9bb 1286 */
Kojto 119:aae6fcc7d9bb 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 119:aae6fcc7d9bb 1288 // Set M bit 0 to enable the MMU
Kojto 119:aae6fcc7d9bb 1289 // Set AFE bit to enable simplified access permissions model
Kojto 119:aae6fcc7d9bb 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 119:aae6fcc7d9bb 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 119:aae6fcc7d9bb 1292 __ISB();
Kojto 119:aae6fcc7d9bb 1293 }
Kojto 119:aae6fcc7d9bb 1294
Kojto 119:aae6fcc7d9bb 1295 /** \brief Disable MMU
Kojto 119:aae6fcc7d9bb 1296
Kojto 119:aae6fcc7d9bb 1297 Disable MMU
Kojto 119:aae6fcc7d9bb 1298 */
Kojto 119:aae6fcc7d9bb 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 119:aae6fcc7d9bb 1300 // Clear M bit 0 to disable the MMU
Kojto 119:aae6fcc7d9bb 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 119:aae6fcc7d9bb 1302 __ISB();
Kojto 119:aae6fcc7d9bb 1303 }
Kojto 119:aae6fcc7d9bb 1304
Kojto 119:aae6fcc7d9bb 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 1306 /** \brief Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 1307
Kojto 119:aae6fcc7d9bb 1308 TLBIALL. Invalidate the whole tlb
Kojto 119:aae6fcc7d9bb 1309 */
Kojto 119:aae6fcc7d9bb 1310
Kojto 119:aae6fcc7d9bb 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 119:aae6fcc7d9bb 1312 #if 1
Kojto 119:aae6fcc7d9bb 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 119:aae6fcc7d9bb 1314 #else
Kojto 119:aae6fcc7d9bb 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 119:aae6fcc7d9bb 1316 __TLBIALL = 0;
Kojto 119:aae6fcc7d9bb 1317 #endif
Kojto 119:aae6fcc7d9bb 1318 __DSB();
Kojto 119:aae6fcc7d9bb 1319 __ISB();
Kojto 119:aae6fcc7d9bb 1320 }
Kojto 119:aae6fcc7d9bb 1321
Kojto 119:aae6fcc7d9bb 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 119:aae6fcc7d9bb 1323 /** \brief Invalidate entire branch predictor array
Kojto 119:aae6fcc7d9bb 1324
Kojto 119:aae6fcc7d9bb 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 119:aae6fcc7d9bb 1326 */
Kojto 119:aae6fcc7d9bb 1327
Kojto 119:aae6fcc7d9bb 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 119:aae6fcc7d9bb 1329 #if 1
Kojto 119:aae6fcc7d9bb 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 119:aae6fcc7d9bb 1331 #else
Kojto 119:aae6fcc7d9bb 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 119:aae6fcc7d9bb 1333 __BPIALL = 0;
Kojto 119:aae6fcc7d9bb 1334 #endif
Kojto 119:aae6fcc7d9bb 1335 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 119:aae6fcc7d9bb 1337 }
Kojto 119:aae6fcc7d9bb 1338
Kojto 119:aae6fcc7d9bb 1339
Kojto 119:aae6fcc7d9bb 1340 /******************************** L1 cache operations ******************************************************/
Kojto 119:aae6fcc7d9bb 1341
Kojto 119:aae6fcc7d9bb 1342 /** \brief Invalidate the whole I$
Kojto 119:aae6fcc7d9bb 1343
Kojto 119:aae6fcc7d9bb 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 119:aae6fcc7d9bb 1345 */
Kojto 119:aae6fcc7d9bb 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 119:aae6fcc7d9bb 1347 #if 1
Kojto 119:aae6fcc7d9bb 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 119:aae6fcc7d9bb 1349 #else
Kojto 119:aae6fcc7d9bb 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 119:aae6fcc7d9bb 1351 __ICIALLU = 0;
Kojto 119:aae6fcc7d9bb 1352 #endif
Kojto 119:aae6fcc7d9bb 1353 __DSB(); //ensure completion of the invalidation
Kojto 119:aae6fcc7d9bb 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 119:aae6fcc7d9bb 1355 }
Kojto 119:aae6fcc7d9bb 1356
Kojto 119:aae6fcc7d9bb 1357 /** \brief Clean D$ by MVA
Kojto 119:aae6fcc7d9bb 1358
Kojto 119:aae6fcc7d9bb 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 119:aae6fcc7d9bb 1360 */
Kojto 119:aae6fcc7d9bb 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 1362 #if 1
Kojto 119:aae6fcc7d9bb 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 119:aae6fcc7d9bb 1364 #else
Kojto 119:aae6fcc7d9bb 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 119:aae6fcc7d9bb 1366 __DCCMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 1367 #endif
Kojto 119:aae6fcc7d9bb 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 1369 }
Kojto 119:aae6fcc7d9bb 1370
Kojto 119:aae6fcc7d9bb 1371 /** \brief Invalidate D$ by MVA
Kojto 119:aae6fcc7d9bb 1372
Kojto 119:aae6fcc7d9bb 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 119:aae6fcc7d9bb 1374 */
Kojto 119:aae6fcc7d9bb 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 1376 #if 1
Kojto 119:aae6fcc7d9bb 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 119:aae6fcc7d9bb 1378 #else
Kojto 119:aae6fcc7d9bb 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 119:aae6fcc7d9bb 1380 __DCIMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 1381 #endif
Kojto 119:aae6fcc7d9bb 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 1383 }
Kojto 119:aae6fcc7d9bb 1384
Kojto 119:aae6fcc7d9bb 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 119:aae6fcc7d9bb 1386
Kojto 119:aae6fcc7d9bb 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 119:aae6fcc7d9bb 1388 */
Kojto 119:aae6fcc7d9bb 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 119:aae6fcc7d9bb 1390 #if 1
Kojto 119:aae6fcc7d9bb 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 119:aae6fcc7d9bb 1392 #else
Kojto 119:aae6fcc7d9bb 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 119:aae6fcc7d9bb 1394 __DCCIMVAC = (uint32_t)va;
Kojto 119:aae6fcc7d9bb 1395 #endif
Kojto 119:aae6fcc7d9bb 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 119:aae6fcc7d9bb 1397 }
Kojto 119:aae6fcc7d9bb 1398
Kojto 119:aae6fcc7d9bb 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 119:aae6fcc7d9bb 1400
Kojto 119:aae6fcc7d9bb 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 119:aae6fcc7d9bb 1402 */
Kojto 119:aae6fcc7d9bb 1403 extern void __v7_all_cache(uint32_t op);
Kojto 119:aae6fcc7d9bb 1404
Kojto 119:aae6fcc7d9bb 1405
Kojto 119:aae6fcc7d9bb 1406 /** \brief Invalidate the whole D$
Kojto 119:aae6fcc7d9bb 1407
Kojto 119:aae6fcc7d9bb 1408 DCISW. Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 1409 */
Kojto 119:aae6fcc7d9bb 1410
Kojto 119:aae6fcc7d9bb 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 1412 __v7_all_cache(0);
Kojto 119:aae6fcc7d9bb 1413 }
Kojto 119:aae6fcc7d9bb 1414
Kojto 119:aae6fcc7d9bb 1415 /** \brief Clean the whole D$
Kojto 119:aae6fcc7d9bb 1416
Kojto 119:aae6fcc7d9bb 1417 DCCSW. Clean by Set/Way
Kojto 119:aae6fcc7d9bb 1418 */
Kojto 119:aae6fcc7d9bb 1419
Kojto 119:aae6fcc7d9bb 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 1421 __v7_all_cache(1);
Kojto 119:aae6fcc7d9bb 1422 }
Kojto 119:aae6fcc7d9bb 1423
Kojto 119:aae6fcc7d9bb 1424 /** \brief Clean and invalidate the whole D$
Kojto 119:aae6fcc7d9bb 1425
Kojto 119:aae6fcc7d9bb 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 119:aae6fcc7d9bb 1427 */
Kojto 119:aae6fcc7d9bb 1428
Kojto 119:aae6fcc7d9bb 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 119:aae6fcc7d9bb 1430 __v7_all_cache(2);
Kojto 119:aae6fcc7d9bb 1431 }
Kojto 119:aae6fcc7d9bb 1432
Kojto 119:aae6fcc7d9bb 1433 #include "core_ca_mmu.h"
Kojto 119:aae6fcc7d9bb 1434
Kojto 119:aae6fcc7d9bb 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 119:aae6fcc7d9bb 1436
Kojto 119:aae6fcc7d9bb 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 119:aae6fcc7d9bb 1438
Kojto 119:aae6fcc7d9bb 1439 #endif
Kojto 119:aae6fcc7d9bb 1440
Kojto 119:aae6fcc7d9bb 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 119:aae6fcc7d9bb 1442
Kojto 119:aae6fcc7d9bb 1443
Kojto 119:aae6fcc7d9bb 1444 #endif /* __CORE_CAFUNC_H__ */