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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F446ZE/core_caFunc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
130:d75b3fe1f5cb 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**************************************************************************//**
Kojto 122:f9eeca106725 2 * @file core_caFunc.h
Kojto 122:f9eeca106725 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 122:f9eeca106725 4 * @version V3.10
Kojto 122:f9eeca106725 5 * @date 30 Oct 2013
Kojto 122:f9eeca106725 6 *
Kojto 122:f9eeca106725 7 * @note
Kojto 122:f9eeca106725 8 *
Kojto 122:f9eeca106725 9 ******************************************************************************/
Kojto 122:f9eeca106725 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 122:f9eeca106725 11
Kojto 122:f9eeca106725 12 All rights reserved.
Kojto 122:f9eeca106725 13 Redistribution and use in source and binary forms, with or without
Kojto 122:f9eeca106725 14 modification, are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 - Redistributions of source code must retain the above copyright
Kojto 122:f9eeca106725 16 notice, this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 - Redistributions in binary form must reproduce the above copyright
Kojto 122:f9eeca106725 18 notice, this list of conditions and the following disclaimer in the
Kojto 122:f9eeca106725 19 documentation and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 122:f9eeca106725 21 to endorse or promote products derived from this software without
Kojto 122:f9eeca106725 22 specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 122:f9eeca106725 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 122:f9eeca106725 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 122:f9eeca106725 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 122:f9eeca106725 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 122:f9eeca106725 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 122:f9eeca106725 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 122:f9eeca106725 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 122:f9eeca106725 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 35 ---------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 36
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 #ifndef __CORE_CAFUNC_H__
Kojto 122:f9eeca106725 39 #define __CORE_CAFUNC_H__
Kojto 122:f9eeca106725 40
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 /* ########################### Core Function Access ########################### */
Kojto 122:f9eeca106725 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 122:f9eeca106725 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 122:f9eeca106725 45 @{
Kojto 122:f9eeca106725 46 */
Kojto 122:f9eeca106725 47
Kojto 122:f9eeca106725 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 122:f9eeca106725 49 /* ARM armcc specific functions */
Kojto 122:f9eeca106725 50
Kojto 122:f9eeca106725 51 #if (__ARMCC_VERSION < 400677)
Kojto 122:f9eeca106725 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 122:f9eeca106725 53 #endif
Kojto 122:f9eeca106725 54
Kojto 122:f9eeca106725 55 #define MODE_USR 0x10
Kojto 122:f9eeca106725 56 #define MODE_FIQ 0x11
Kojto 122:f9eeca106725 57 #define MODE_IRQ 0x12
Kojto 122:f9eeca106725 58 #define MODE_SVC 0x13
Kojto 122:f9eeca106725 59 #define MODE_MON 0x16
Kojto 122:f9eeca106725 60 #define MODE_ABT 0x17
Kojto 122:f9eeca106725 61 #define MODE_HYP 0x1A
Kojto 122:f9eeca106725 62 #define MODE_UND 0x1B
Kojto 122:f9eeca106725 63 #define MODE_SYS 0x1F
Kojto 122:f9eeca106725 64
Kojto 122:f9eeca106725 65 /** \brief Get APSR Register
Kojto 122:f9eeca106725 66
Kojto 122:f9eeca106725 67 This function returns the content of the APSR Register.
Kojto 122:f9eeca106725 68
Kojto 122:f9eeca106725 69 \return APSR Register value
Kojto 122:f9eeca106725 70 */
Kojto 122:f9eeca106725 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 122:f9eeca106725 72 {
Kojto 122:f9eeca106725 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 122:f9eeca106725 74 return(__regAPSR);
Kojto 122:f9eeca106725 75 }
Kojto 122:f9eeca106725 76
Kojto 122:f9eeca106725 77
Kojto 122:f9eeca106725 78 /** \brief Get CPSR Register
Kojto 122:f9eeca106725 79
Kojto 122:f9eeca106725 80 This function returns the content of the CPSR Register.
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 \return CPSR Register value
Kojto 122:f9eeca106725 83 */
Kojto 122:f9eeca106725 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 122:f9eeca106725 85 {
Kojto 122:f9eeca106725 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 122:f9eeca106725 87 return(__regCPSR);
Kojto 122:f9eeca106725 88 }
Kojto 122:f9eeca106725 89
Kojto 122:f9eeca106725 90 /** \brief Set Stack Pointer
Kojto 122:f9eeca106725 91
Kojto 122:f9eeca106725 92 This function assigns the given value to the current stack pointer.
Kojto 122:f9eeca106725 93
Kojto 122:f9eeca106725 94 \param [in] topOfStack Stack Pointer value to set
Kojto 122:f9eeca106725 95 */
Kojto 122:f9eeca106725 96 register uint32_t __regSP __ASM("sp");
Kojto 122:f9eeca106725 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 122:f9eeca106725 98 {
Kojto 122:f9eeca106725 99 __regSP = topOfStack;
Kojto 122:f9eeca106725 100 }
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102
Kojto 122:f9eeca106725 103 /** \brief Get link register
Kojto 122:f9eeca106725 104
Kojto 122:f9eeca106725 105 This function returns the value of the link register
Kojto 122:f9eeca106725 106
Kojto 122:f9eeca106725 107 \return Value of link register
Kojto 122:f9eeca106725 108 */
Kojto 122:f9eeca106725 109 register uint32_t __reglr __ASM("lr");
Kojto 122:f9eeca106725 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 122:f9eeca106725 111 {
Kojto 122:f9eeca106725 112 return(__reglr);
Kojto 122:f9eeca106725 113 }
Kojto 122:f9eeca106725 114
Kojto 122:f9eeca106725 115 /** \brief Set link register
Kojto 122:f9eeca106725 116
Kojto 122:f9eeca106725 117 This function sets the value of the link register
Kojto 122:f9eeca106725 118
Kojto 122:f9eeca106725 119 \param [in] lr LR value to set
Kojto 122:f9eeca106725 120 */
Kojto 122:f9eeca106725 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 122:f9eeca106725 122 {
Kojto 122:f9eeca106725 123 __reglr = lr;
Kojto 122:f9eeca106725 124 }
Kojto 122:f9eeca106725 125
Kojto 122:f9eeca106725 126 /** \brief Set Process Stack Pointer
Kojto 122:f9eeca106725 127
Kojto 122:f9eeca106725 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 122:f9eeca106725 129
Kojto 122:f9eeca106725 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 122:f9eeca106725 131 */
Kojto 122:f9eeca106725 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 122:f9eeca106725 133 {
Kojto 122:f9eeca106725 134 ARM
Kojto 122:f9eeca106725 135 PRESERVE8
Kojto 122:f9eeca106725 136
Kojto 122:f9eeca106725 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 122:f9eeca106725 138 MRS R1, CPSR
Kojto 122:f9eeca106725 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 122:f9eeca106725 140 MOV SP, R0
Kojto 122:f9eeca106725 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 122:f9eeca106725 142 ISB
Kojto 122:f9eeca106725 143 BX LR
Kojto 122:f9eeca106725 144
Kojto 122:f9eeca106725 145 }
Kojto 122:f9eeca106725 146
Kojto 122:f9eeca106725 147 /** \brief Set User Mode
Kojto 122:f9eeca106725 148
Kojto 122:f9eeca106725 149 This function changes the processor state to User Mode
Kojto 122:f9eeca106725 150 */
Kojto 122:f9eeca106725 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 122:f9eeca106725 152 {
Kojto 122:f9eeca106725 153 ARM
Kojto 122:f9eeca106725 154
Kojto 122:f9eeca106725 155 CPS #MODE_USR
Kojto 122:f9eeca106725 156 BX LR
Kojto 122:f9eeca106725 157 }
Kojto 122:f9eeca106725 158
Kojto 122:f9eeca106725 159
Kojto 122:f9eeca106725 160 /** \brief Enable FIQ
Kojto 122:f9eeca106725 161
Kojto 122:f9eeca106725 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 122:f9eeca106725 163 Can only be executed in Privileged modes.
Kojto 122:f9eeca106725 164 */
Kojto 122:f9eeca106725 165 #define __enable_fault_irq __enable_fiq
Kojto 122:f9eeca106725 166
Kojto 122:f9eeca106725 167
Kojto 122:f9eeca106725 168 /** \brief Disable FIQ
Kojto 122:f9eeca106725 169
Kojto 122:f9eeca106725 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 122:f9eeca106725 171 Can only be executed in Privileged modes.
Kojto 122:f9eeca106725 172 */
Kojto 122:f9eeca106725 173 #define __disable_fault_irq __disable_fiq
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175
Kojto 122:f9eeca106725 176 /** \brief Get FPSCR
Kojto 122:f9eeca106725 177
Kojto 122:f9eeca106725 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 122:f9eeca106725 179
Kojto 122:f9eeca106725 180 \return Floating Point Status/Control register value
Kojto 122:f9eeca106725 181 */
Kojto 122:f9eeca106725 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 122:f9eeca106725 183 {
Kojto 122:f9eeca106725 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 122:f9eeca106725 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 122:f9eeca106725 186 return(__regfpscr);
Kojto 122:f9eeca106725 187 #else
Kojto 122:f9eeca106725 188 return(0);
Kojto 122:f9eeca106725 189 #endif
Kojto 122:f9eeca106725 190 }
Kojto 122:f9eeca106725 191
Kojto 122:f9eeca106725 192
Kojto 122:f9eeca106725 193 /** \brief Set FPSCR
Kojto 122:f9eeca106725 194
Kojto 122:f9eeca106725 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 122:f9eeca106725 196
Kojto 122:f9eeca106725 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 122:f9eeca106725 198 */
Kojto 122:f9eeca106725 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 122:f9eeca106725 200 {
Kojto 122:f9eeca106725 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 122:f9eeca106725 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 122:f9eeca106725 203 __regfpscr = (fpscr);
Kojto 122:f9eeca106725 204 #endif
Kojto 122:f9eeca106725 205 }
Kojto 122:f9eeca106725 206
Kojto 122:f9eeca106725 207 /** \brief Get FPEXC
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 122:f9eeca106725 210
Kojto 122:f9eeca106725 211 \return Floating Point Exception Control register value
Kojto 122:f9eeca106725 212 */
Kojto 122:f9eeca106725 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 122:f9eeca106725 214 {
Kojto 122:f9eeca106725 215 #if (__FPU_PRESENT == 1)
Kojto 122:f9eeca106725 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 122:f9eeca106725 217 return(__regfpexc);
Kojto 122:f9eeca106725 218 #else
Kojto 122:f9eeca106725 219 return(0);
Kojto 122:f9eeca106725 220 #endif
Kojto 122:f9eeca106725 221 }
Kojto 122:f9eeca106725 222
Kojto 122:f9eeca106725 223
Kojto 122:f9eeca106725 224 /** \brief Set FPEXC
Kojto 122:f9eeca106725 225
Kojto 122:f9eeca106725 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 122:f9eeca106725 227
Kojto 122:f9eeca106725 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 122:f9eeca106725 229 */
Kojto 122:f9eeca106725 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 122:f9eeca106725 231 {
Kojto 122:f9eeca106725 232 #if (__FPU_PRESENT == 1)
Kojto 122:f9eeca106725 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 122:f9eeca106725 234 __regfpexc = (fpexc);
Kojto 122:f9eeca106725 235 #endif
Kojto 122:f9eeca106725 236 }
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 /** \brief Get CPACR
Kojto 122:f9eeca106725 239
Kojto 122:f9eeca106725 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 \return Coprocessor Access Control register value
Kojto 122:f9eeca106725 243 */
Kojto 122:f9eeca106725 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 122:f9eeca106725 245 {
Kojto 122:f9eeca106725 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 122:f9eeca106725 247 return __regCPACR;
Kojto 122:f9eeca106725 248 }
Kojto 122:f9eeca106725 249
Kojto 122:f9eeca106725 250 /** \brief Set CPACR
Kojto 122:f9eeca106725 251
Kojto 122:f9eeca106725 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 122:f9eeca106725 253
Kojto 122:f9eeca106725 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 122:f9eeca106725 255 */
Kojto 122:f9eeca106725 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 122:f9eeca106725 257 {
Kojto 122:f9eeca106725 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 122:f9eeca106725 259 __regCPACR = cpacr;
Kojto 122:f9eeca106725 260 __ISB();
Kojto 122:f9eeca106725 261 }
Kojto 122:f9eeca106725 262
Kojto 122:f9eeca106725 263 /** \brief Get CBAR
Kojto 122:f9eeca106725 264
Kojto 122:f9eeca106725 265 This function returns the value of the Configuration Base Address register.
Kojto 122:f9eeca106725 266
Kojto 122:f9eeca106725 267 \return Configuration Base Address register value
Kojto 122:f9eeca106725 268 */
Kojto 122:f9eeca106725 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 122:f9eeca106725 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 122:f9eeca106725 271 return(__regCBAR);
Kojto 122:f9eeca106725 272 }
Kojto 122:f9eeca106725 273
Kojto 122:f9eeca106725 274 /** \brief Get TTBR0
Kojto 122:f9eeca106725 275
Kojto 122:f9eeca106725 276 This function returns the value of the Translation Table Base Register 0.
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278 \return Translation Table Base Register 0 value
Kojto 122:f9eeca106725 279 */
Kojto 122:f9eeca106725 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 122:f9eeca106725 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 122:f9eeca106725 282 return(__regTTBR0);
Kojto 122:f9eeca106725 283 }
Kojto 122:f9eeca106725 284
Kojto 122:f9eeca106725 285 /** \brief Set TTBR0
Kojto 122:f9eeca106725 286
Kojto 122:f9eeca106725 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 122:f9eeca106725 288
Kojto 122:f9eeca106725 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 122:f9eeca106725 290 */
Kojto 122:f9eeca106725 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 122:f9eeca106725 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 122:f9eeca106725 293 __regTTBR0 = ttbr0;
Kojto 122:f9eeca106725 294 __ISB();
Kojto 122:f9eeca106725 295 }
Kojto 122:f9eeca106725 296
Kojto 122:f9eeca106725 297 /** \brief Get DACR
Kojto 122:f9eeca106725 298
Kojto 122:f9eeca106725 299 This function returns the value of the Domain Access Control Register.
Kojto 122:f9eeca106725 300
Kojto 122:f9eeca106725 301 \return Domain Access Control Register value
Kojto 122:f9eeca106725 302 */
Kojto 122:f9eeca106725 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 122:f9eeca106725 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 122:f9eeca106725 305 return(__regDACR);
Kojto 122:f9eeca106725 306 }
Kojto 122:f9eeca106725 307
Kojto 122:f9eeca106725 308 /** \brief Set DACR
Kojto 122:f9eeca106725 309
Kojto 122:f9eeca106725 310 This function assigns the given value to the Domain Access Control Register.
Kojto 122:f9eeca106725 311
Kojto 122:f9eeca106725 312 \param [in] dacr Domain Access Control Register value to set
Kojto 122:f9eeca106725 313 */
Kojto 122:f9eeca106725 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 122:f9eeca106725 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 122:f9eeca106725 316 __regDACR = dacr;
Kojto 122:f9eeca106725 317 __ISB();
Kojto 122:f9eeca106725 318 }
Kojto 122:f9eeca106725 319
Kojto 122:f9eeca106725 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 122:f9eeca106725 321
Kojto 122:f9eeca106725 322 /** \brief Set SCTLR
Kojto 122:f9eeca106725 323
Kojto 122:f9eeca106725 324 This function assigns the given value to the System Control Register.
Kojto 122:f9eeca106725 325
Kojto 122:f9eeca106725 326 \param [in] sctlr System Control Register value to set
Kojto 122:f9eeca106725 327 */
Kojto 122:f9eeca106725 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 122:f9eeca106725 329 {
Kojto 122:f9eeca106725 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 122:f9eeca106725 331 __regSCTLR = sctlr;
Kojto 122:f9eeca106725 332 }
Kojto 122:f9eeca106725 333
Kojto 122:f9eeca106725 334 /** \brief Get SCTLR
Kojto 122:f9eeca106725 335
Kojto 122:f9eeca106725 336 This function returns the value of the System Control Register.
Kojto 122:f9eeca106725 337
Kojto 122:f9eeca106725 338 \return System Control Register value
Kojto 122:f9eeca106725 339 */
Kojto 122:f9eeca106725 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 122:f9eeca106725 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 122:f9eeca106725 342 return(__regSCTLR);
Kojto 122:f9eeca106725 343 }
Kojto 122:f9eeca106725 344
Kojto 122:f9eeca106725 345 /** \brief Enable Caches
Kojto 122:f9eeca106725 346
Kojto 122:f9eeca106725 347 Enable Caches
Kojto 122:f9eeca106725 348 */
Kojto 122:f9eeca106725 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 122:f9eeca106725 350 // Set I bit 12 to enable I Cache
Kojto 122:f9eeca106725 351 // Set C bit 2 to enable D Cache
Kojto 122:f9eeca106725 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 122:f9eeca106725 353 }
Kojto 122:f9eeca106725 354
Kojto 122:f9eeca106725 355 /** \brief Disable Caches
Kojto 122:f9eeca106725 356
Kojto 122:f9eeca106725 357 Disable Caches
Kojto 122:f9eeca106725 358 */
Kojto 122:f9eeca106725 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 122:f9eeca106725 360 // Clear I bit 12 to disable I Cache
Kojto 122:f9eeca106725 361 // Clear C bit 2 to disable D Cache
Kojto 122:f9eeca106725 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 122:f9eeca106725 363 __ISB();
Kojto 122:f9eeca106725 364 }
Kojto 122:f9eeca106725 365
Kojto 122:f9eeca106725 366 /** \brief Enable BTAC
Kojto 122:f9eeca106725 367
Kojto 122:f9eeca106725 368 Enable BTAC
Kojto 122:f9eeca106725 369 */
Kojto 122:f9eeca106725 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 122:f9eeca106725 371 // Set Z bit 11 to enable branch prediction
Kojto 122:f9eeca106725 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 122:f9eeca106725 373 __ISB();
Kojto 122:f9eeca106725 374 }
Kojto 122:f9eeca106725 375
Kojto 122:f9eeca106725 376 /** \brief Disable BTAC
Kojto 122:f9eeca106725 377
Kojto 122:f9eeca106725 378 Disable BTAC
Kojto 122:f9eeca106725 379 */
Kojto 122:f9eeca106725 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 122:f9eeca106725 381 // Clear Z bit 11 to disable branch prediction
Kojto 122:f9eeca106725 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 122:f9eeca106725 383 }
Kojto 122:f9eeca106725 384
Kojto 122:f9eeca106725 385
Kojto 122:f9eeca106725 386 /** \brief Enable MMU
Kojto 122:f9eeca106725 387
Kojto 122:f9eeca106725 388 Enable MMU
Kojto 122:f9eeca106725 389 */
Kojto 122:f9eeca106725 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 122:f9eeca106725 391 // Set M bit 0 to enable the MMU
Kojto 122:f9eeca106725 392 // Set AFE bit to enable simplified access permissions model
Kojto 122:f9eeca106725 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 122:f9eeca106725 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 122:f9eeca106725 395 __ISB();
Kojto 122:f9eeca106725 396 }
Kojto 122:f9eeca106725 397
Kojto 122:f9eeca106725 398 /** \brief Disable MMU
Kojto 122:f9eeca106725 399
Kojto 122:f9eeca106725 400 Disable MMU
Kojto 122:f9eeca106725 401 */
Kojto 122:f9eeca106725 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 122:f9eeca106725 403 // Clear M bit 0 to disable the MMU
Kojto 122:f9eeca106725 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 122:f9eeca106725 405 __ISB();
Kojto 122:f9eeca106725 406 }
Kojto 122:f9eeca106725 407
Kojto 122:f9eeca106725 408 /******************************** TLB maintenance operations ************************************************/
Kojto 122:f9eeca106725 409 /** \brief Invalidate the whole tlb
Kojto 122:f9eeca106725 410
Kojto 122:f9eeca106725 411 TLBIALL. Invalidate the whole tlb
Kojto 122:f9eeca106725 412 */
Kojto 122:f9eeca106725 413
Kojto 122:f9eeca106725 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 122:f9eeca106725 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 122:f9eeca106725 416 __TLBIALL = 0;
Kojto 122:f9eeca106725 417 __DSB();
Kojto 122:f9eeca106725 418 __ISB();
Kojto 122:f9eeca106725 419 }
Kojto 122:f9eeca106725 420
Kojto 122:f9eeca106725 421 /******************************** BTB maintenance operations ************************************************/
Kojto 122:f9eeca106725 422 /** \brief Invalidate entire branch predictor array
Kojto 122:f9eeca106725 423
Kojto 122:f9eeca106725 424 BPIALL. Branch Predictor Invalidate All.
Kojto 122:f9eeca106725 425 */
Kojto 122:f9eeca106725 426
Kojto 122:f9eeca106725 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 122:f9eeca106725 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 122:f9eeca106725 429 __BPIALL = 0;
Kojto 122:f9eeca106725 430 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 122:f9eeca106725 432 }
Kojto 122:f9eeca106725 433
Kojto 122:f9eeca106725 434
Kojto 122:f9eeca106725 435 /******************************** L1 cache operations ******************************************************/
Kojto 122:f9eeca106725 436
Kojto 122:f9eeca106725 437 /** \brief Invalidate the whole I$
Kojto 122:f9eeca106725 438
Kojto 122:f9eeca106725 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 122:f9eeca106725 440 */
Kojto 122:f9eeca106725 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 122:f9eeca106725 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 122:f9eeca106725 443 __ICIALLU = 0;
Kojto 122:f9eeca106725 444 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 122:f9eeca106725 446 }
Kojto 122:f9eeca106725 447
Kojto 122:f9eeca106725 448 /** \brief Clean D$ by MVA
Kojto 122:f9eeca106725 449
Kojto 122:f9eeca106725 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 122:f9eeca106725 451 */
Kojto 122:f9eeca106725 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 122:f9eeca106725 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 122:f9eeca106725 454 __DCCMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 456 }
Kojto 122:f9eeca106725 457
Kojto 122:f9eeca106725 458 /** \brief Invalidate D$ by MVA
Kojto 122:f9eeca106725 459
Kojto 122:f9eeca106725 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 122:f9eeca106725 461 */
Kojto 122:f9eeca106725 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 122:f9eeca106725 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 122:f9eeca106725 464 __DCIMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 466 }
Kojto 122:f9eeca106725 467
Kojto 122:f9eeca106725 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 122:f9eeca106725 469
Kojto 122:f9eeca106725 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 122:f9eeca106725 471 */
Kojto 122:f9eeca106725 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 122:f9eeca106725 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 122:f9eeca106725 474 __DCCIMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 476 }
Kojto 122:f9eeca106725 477
Kojto 122:f9eeca106725 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 122:f9eeca106725 479
Kojto 122:f9eeca106725 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 122:f9eeca106725 481 */
Kojto 122:f9eeca106725 482 #pragma push
Kojto 122:f9eeca106725 483 #pragma arm
Kojto 122:f9eeca106725 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 122:f9eeca106725 485 ARM
Kojto 122:f9eeca106725 486
Kojto 122:f9eeca106725 487 PUSH {R4-R11}
Kojto 122:f9eeca106725 488
Kojto 122:f9eeca106725 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 122:f9eeca106725 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 122:f9eeca106725 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 122:f9eeca106725 492 BEQ Finished // If 0, no need to clean
Kojto 122:f9eeca106725 493
Kojto 122:f9eeca106725 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 122:f9eeca106725 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 122:f9eeca106725 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 122:f9eeca106725 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 122:f9eeca106725 498 CMP R1, #2
Kojto 122:f9eeca106725 499 BLT Skip // No cache or only instruction cache at this level
Kojto 122:f9eeca106725 500
Kojto 122:f9eeca106725 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 122:f9eeca106725 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 122:f9eeca106725 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 122:f9eeca106725 504 AND R2, R1, #7 // Extract the line length field
Kojto 122:f9eeca106725 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 122:f9eeca106725 506 LDR R4, =0x3FF
Kojto 122:f9eeca106725 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 122:f9eeca106725 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 122:f9eeca106725 509 LDR R7, =0x7FFF
Kojto 122:f9eeca106725 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 122:f9eeca106725 511
Kojto 122:f9eeca106725 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 122:f9eeca106725 513
Kojto 122:f9eeca106725 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 122:f9eeca106725 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 122:f9eeca106725 516 CMP R0, #0
Kojto 122:f9eeca106725 517 BNE Dccsw
Kojto 122:f9eeca106725 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 122:f9eeca106725 519 B cont
Kojto 122:f9eeca106725 520 Dccsw CMP R0, #1
Kojto 122:f9eeca106725 521 BNE Dccisw
Kojto 122:f9eeca106725 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 122:f9eeca106725 523 B cont
Kojto 122:f9eeca106725 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 122:f9eeca106725 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 122:f9eeca106725 526 BGE Loop3
Kojto 122:f9eeca106725 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 122:f9eeca106725 528 BGE Loop2
Kojto 122:f9eeca106725 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 122:f9eeca106725 530 CMP R3, R10
Kojto 122:f9eeca106725 531 BGT Loop1
Kojto 122:f9eeca106725 532
Kojto 122:f9eeca106725 533 Finished
Kojto 122:f9eeca106725 534 DSB
Kojto 122:f9eeca106725 535 POP {R4-R11}
Kojto 122:f9eeca106725 536 BX lr
Kojto 122:f9eeca106725 537
Kojto 122:f9eeca106725 538 }
Kojto 122:f9eeca106725 539 #pragma pop
Kojto 122:f9eeca106725 540
Kojto 122:f9eeca106725 541
Kojto 122:f9eeca106725 542 /** \brief Invalidate the whole D$
Kojto 122:f9eeca106725 543
Kojto 122:f9eeca106725 544 DCISW. Invalidate by Set/Way
Kojto 122:f9eeca106725 545 */
Kojto 122:f9eeca106725 546
Kojto 122:f9eeca106725 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 122:f9eeca106725 548 __v7_all_cache(0);
Kojto 122:f9eeca106725 549 }
Kojto 122:f9eeca106725 550
Kojto 122:f9eeca106725 551 /** \brief Clean the whole D$
Kojto 122:f9eeca106725 552
Kojto 122:f9eeca106725 553 DCCSW. Clean by Set/Way
Kojto 122:f9eeca106725 554 */
Kojto 122:f9eeca106725 555
Kojto 122:f9eeca106725 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 122:f9eeca106725 557 __v7_all_cache(1);
Kojto 122:f9eeca106725 558 }
Kojto 122:f9eeca106725 559
Kojto 122:f9eeca106725 560 /** \brief Clean and invalidate the whole D$
Kojto 122:f9eeca106725 561
Kojto 122:f9eeca106725 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 122:f9eeca106725 563 */
Kojto 122:f9eeca106725 564
Kojto 122:f9eeca106725 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 122:f9eeca106725 566 __v7_all_cache(2);
Kojto 122:f9eeca106725 567 }
Kojto 122:f9eeca106725 568
Kojto 122:f9eeca106725 569 #include "core_ca_mmu.h"
Kojto 122:f9eeca106725 570
Kojto 122:f9eeca106725 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573 #define __inline inline
Kojto 122:f9eeca106725 574
Kojto 122:f9eeca106725 575 inline static uint32_t __disable_irq_iar() {
Kojto 122:f9eeca106725 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 122:f9eeca106725 577 __disable_irq();
Kojto 122:f9eeca106725 578 return irq_dis;
Kojto 122:f9eeca106725 579 }
Kojto 122:f9eeca106725 580
Kojto 122:f9eeca106725 581 #define MODE_USR 0x10
Kojto 122:f9eeca106725 582 #define MODE_FIQ 0x11
Kojto 122:f9eeca106725 583 #define MODE_IRQ 0x12
Kojto 122:f9eeca106725 584 #define MODE_SVC 0x13
Kojto 122:f9eeca106725 585 #define MODE_MON 0x16
Kojto 122:f9eeca106725 586 #define MODE_ABT 0x17
Kojto 122:f9eeca106725 587 #define MODE_HYP 0x1A
Kojto 122:f9eeca106725 588 #define MODE_UND 0x1B
Kojto 122:f9eeca106725 589 #define MODE_SYS 0x1F
Kojto 122:f9eeca106725 590
Kojto 122:f9eeca106725 591 /** \brief Set Process Stack Pointer
Kojto 122:f9eeca106725 592
Kojto 122:f9eeca106725 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 122:f9eeca106725 594
Kojto 122:f9eeca106725 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 122:f9eeca106725 596 */
Kojto 122:f9eeca106725 597 // from rt_CMSIS.c
Kojto 122:f9eeca106725 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 122:f9eeca106725 599 __asm(
Kojto 122:f9eeca106725 600 " ARM\n"
Kojto 122:f9eeca106725 601 // " PRESERVE8\n"
Kojto 122:f9eeca106725 602
Kojto 122:f9eeca106725 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 122:f9eeca106725 604 " MRS R1, CPSR \n"
Kojto 122:f9eeca106725 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 122:f9eeca106725 606 " MOV SP, R0 \n"
Kojto 122:f9eeca106725 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 122:f9eeca106725 608 " ISB \n"
Kojto 122:f9eeca106725 609 " BX LR \n");
Kojto 122:f9eeca106725 610 }
Kojto 122:f9eeca106725 611
Kojto 122:f9eeca106725 612 /** \brief Set User Mode
Kojto 122:f9eeca106725 613
Kojto 122:f9eeca106725 614 This function changes the processor state to User Mode
Kojto 122:f9eeca106725 615 */
Kojto 122:f9eeca106725 616 // from rt_CMSIS.c
Kojto 122:f9eeca106725 617 __arm static inline void __set_CPS_USR(void) {
Kojto 122:f9eeca106725 618 __asm(
Kojto 122:f9eeca106725 619 " ARM \n"
Kojto 122:f9eeca106725 620
Kojto 122:f9eeca106725 621 " CPS #0x10 \n" // MODE_USR
Kojto 122:f9eeca106725 622 " BX LR\n");
Kojto 122:f9eeca106725 623 }
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625 /** \brief Set TTBR0
Kojto 122:f9eeca106725 626
Kojto 122:f9eeca106725 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 122:f9eeca106725 628
Kojto 122:f9eeca106725 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 122:f9eeca106725 630 */
Kojto 122:f9eeca106725 631 // from mmu_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 122:f9eeca106725 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 122:f9eeca106725 634 __ISB();
Kojto 122:f9eeca106725 635 }
Kojto 122:f9eeca106725 636
Kojto 122:f9eeca106725 637 /** \brief Set DACR
Kojto 122:f9eeca106725 638
Kojto 122:f9eeca106725 639 This function assigns the given value to the Domain Access Control Register.
Kojto 122:f9eeca106725 640
Kojto 122:f9eeca106725 641 \param [in] dacr Domain Access Control Register value to set
Kojto 122:f9eeca106725 642 */
Kojto 122:f9eeca106725 643 // from mmu_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 122:f9eeca106725 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 122:f9eeca106725 646 __ISB();
Kojto 122:f9eeca106725 647 }
Kojto 122:f9eeca106725 648
Kojto 122:f9eeca106725 649
Kojto 122:f9eeca106725 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 122:f9eeca106725 651 /** \brief Set SCTLR
Kojto 122:f9eeca106725 652
Kojto 122:f9eeca106725 653 This function assigns the given value to the System Control Register.
Kojto 122:f9eeca106725 654
Kojto 122:f9eeca106725 655 \param [in] sctlr System Control Register value to set
Kojto 122:f9eeca106725 656 */
Kojto 122:f9eeca106725 657 // from __enable_mmu()
Kojto 122:f9eeca106725 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 122:f9eeca106725 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 122:f9eeca106725 660 }
Kojto 122:f9eeca106725 661
Kojto 122:f9eeca106725 662 /** \brief Get SCTLR
Kojto 122:f9eeca106725 663
Kojto 122:f9eeca106725 664 This function returns the value of the System Control Register.
Kojto 122:f9eeca106725 665
Kojto 122:f9eeca106725 666 \return System Control Register value
Kojto 122:f9eeca106725 667 */
Kojto 122:f9eeca106725 668 // from __enable_mmu()
Kojto 122:f9eeca106725 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 122:f9eeca106725 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 122:f9eeca106725 671 return __regSCTLR;
Kojto 122:f9eeca106725 672 }
Kojto 122:f9eeca106725 673
Kojto 122:f9eeca106725 674 /** \brief Enable Caches
Kojto 122:f9eeca106725 675
Kojto 122:f9eeca106725 676 Enable Caches
Kojto 122:f9eeca106725 677 */
Kojto 122:f9eeca106725 678 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 122:f9eeca106725 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 122:f9eeca106725 681 }
Kojto 122:f9eeca106725 682
Kojto 122:f9eeca106725 683 /** \brief Enable BTAC
Kojto 122:f9eeca106725 684
Kojto 122:f9eeca106725 685 Enable BTAC
Kojto 122:f9eeca106725 686 */
Kojto 122:f9eeca106725 687 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 122:f9eeca106725 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 122:f9eeca106725 690 __ISB();
Kojto 122:f9eeca106725 691 }
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 /** \brief Enable MMU
Kojto 122:f9eeca106725 694
Kojto 122:f9eeca106725 695 Enable MMU
Kojto 122:f9eeca106725 696 */
Kojto 122:f9eeca106725 697 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 122:f9eeca106725 699 // Set M bit 0 to enable the MMU
Kojto 122:f9eeca106725 700 // Set AFE bit to enable simplified access permissions model
Kojto 122:f9eeca106725 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 122:f9eeca106725 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 122:f9eeca106725 703 __ISB();
Kojto 122:f9eeca106725 704 }
Kojto 122:f9eeca106725 705
Kojto 122:f9eeca106725 706 /******************************** TLB maintenance operations ************************************************/
Kojto 122:f9eeca106725 707 /** \brief Invalidate the whole tlb
Kojto 122:f9eeca106725 708
Kojto 122:f9eeca106725 709 TLBIALL. Invalidate the whole tlb
Kojto 122:f9eeca106725 710 */
Kojto 122:f9eeca106725 711 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 122:f9eeca106725 713 uint32_t val = 0;
Kojto 122:f9eeca106725 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 122:f9eeca106725 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 122:f9eeca106725 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 122:f9eeca106725 717 __DSB();
Kojto 122:f9eeca106725 718 __ISB();
Kojto 122:f9eeca106725 719 }
Kojto 122:f9eeca106725 720
Kojto 122:f9eeca106725 721 /******************************** BTB maintenance operations ************************************************/
Kojto 122:f9eeca106725 722 /** \brief Invalidate entire branch predictor array
Kojto 122:f9eeca106725 723
Kojto 122:f9eeca106725 724 BPIALL. Branch Predictor Invalidate All.
Kojto 122:f9eeca106725 725 */
Kojto 122:f9eeca106725 726 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 122:f9eeca106725 728 uint32_t val = 0;
Kojto 122:f9eeca106725 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 122:f9eeca106725 730 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 122:f9eeca106725 732 }
Kojto 122:f9eeca106725 733
Kojto 122:f9eeca106725 734
Kojto 122:f9eeca106725 735 /******************************** L1 cache operations ******************************************************/
Kojto 122:f9eeca106725 736
Kojto 122:f9eeca106725 737 /** \brief Invalidate the whole I$
Kojto 122:f9eeca106725 738
Kojto 122:f9eeca106725 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 122:f9eeca106725 740 */
Kojto 122:f9eeca106725 741 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 122:f9eeca106725 743 uint32_t val = 0;
Kojto 122:f9eeca106725 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 122:f9eeca106725 745 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 122:f9eeca106725 747 }
Kojto 122:f9eeca106725 748
Kojto 122:f9eeca106725 749 // from __v7_inv_dcache_all()
Kojto 122:f9eeca106725 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 122:f9eeca106725 751 __asm(
Kojto 122:f9eeca106725 752 " ARM \n"
Kojto 122:f9eeca106725 753
Kojto 122:f9eeca106725 754 " PUSH {R4-R11} \n"
Kojto 122:f9eeca106725 755
Kojto 122:f9eeca106725 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 122:f9eeca106725 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 122:f9eeca106725 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 122:f9eeca106725 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 122:f9eeca106725 760
Kojto 122:f9eeca106725 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 122:f9eeca106725 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 122:f9eeca106725 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 122:f9eeca106725 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 122:f9eeca106725 765 " CMP R1, #2 \n"
Kojto 122:f9eeca106725 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 122:f9eeca106725 767
Kojto 122:f9eeca106725 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 122:f9eeca106725 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 122:f9eeca106725 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 122:f9eeca106725 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 122:f9eeca106725 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 122:f9eeca106725 773 " movw R4, #0x3FF \n"
Kojto 122:f9eeca106725 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 122:f9eeca106725 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 122:f9eeca106725 776 " movw R7, #0x7FFF \n"
Kojto 122:f9eeca106725 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 122:f9eeca106725 778
Kojto 122:f9eeca106725 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 122:f9eeca106725 780
Kojto 122:f9eeca106725 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 122:f9eeca106725 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 122:f9eeca106725 783 " CMP R0, #0 \n"
Kojto 122:f9eeca106725 784 " BNE Dccsw \n"
Kojto 122:f9eeca106725 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 122:f9eeca106725 786 " B cont \n"
Kojto 122:f9eeca106725 787 "Dccsw: CMP R0, #1 \n"
Kojto 122:f9eeca106725 788 " BNE Dccisw \n"
Kojto 122:f9eeca106725 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 122:f9eeca106725 790 " B cont \n"
Kojto 122:f9eeca106725 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 122:f9eeca106725 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 122:f9eeca106725 793 " BGE Loop3 \n"
Kojto 122:f9eeca106725 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 122:f9eeca106725 795 " BGE Loop2 \n"
Kojto 122:f9eeca106725 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 122:f9eeca106725 797 " CMP R3, R10 \n"
Kojto 122:f9eeca106725 798 " BGT Loop1 \n"
Kojto 122:f9eeca106725 799
Kojto 122:f9eeca106725 800 "Finished: \n"
Kojto 122:f9eeca106725 801 " DSB \n"
Kojto 122:f9eeca106725 802 " POP {R4-R11} \n"
Kojto 122:f9eeca106725 803 " BX lr \n" );
Kojto 122:f9eeca106725 804 }
Kojto 122:f9eeca106725 805
Kojto 122:f9eeca106725 806 /** \brief Invalidate the whole D$
Kojto 122:f9eeca106725 807
Kojto 122:f9eeca106725 808 DCISW. Invalidate by Set/Way
Kojto 122:f9eeca106725 809 */
Kojto 122:f9eeca106725 810 // from system_Renesas_RZ_A1.c
Kojto 122:f9eeca106725 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 122:f9eeca106725 812 __v7_all_cache(0);
Kojto 122:f9eeca106725 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 122:f9eeca106725 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 122:f9eeca106725 832
Kojto 122:f9eeca106725 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 122:f9eeca106725 834 */
Kojto 122:f9eeca106725 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 122:f9eeca106725 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 122:f9eeca106725 837 __DMB();
Kojto 122:f9eeca106725 838 }
Kojto 122:f9eeca106725 839
Kojto 122:f9eeca106725 840 #include "core_ca_mmu.h"
Kojto 122:f9eeca106725 841
Kojto 122:f9eeca106725 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 122:f9eeca106725 843 /* GNU gcc specific functions */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 #define MODE_USR 0x10
Kojto 122:f9eeca106725 846 #define MODE_FIQ 0x11
Kojto 122:f9eeca106725 847 #define MODE_IRQ 0x12
Kojto 122:f9eeca106725 848 #define MODE_SVC 0x13
Kojto 122:f9eeca106725 849 #define MODE_MON 0x16
Kojto 122:f9eeca106725 850 #define MODE_ABT 0x17
Kojto 122:f9eeca106725 851 #define MODE_HYP 0x1A
Kojto 122:f9eeca106725 852 #define MODE_UND 0x1B
Kojto 122:f9eeca106725 853 #define MODE_SYS 0x1F
Kojto 122:f9eeca106725 854
Kojto 122:f9eeca106725 855
Kojto 122:f9eeca106725 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 122:f9eeca106725 857 {
Kojto 122:f9eeca106725 858 __ASM volatile ("cpsie i");
Kojto 122:f9eeca106725 859 }
Kojto 122:f9eeca106725 860
Kojto 122:f9eeca106725 861 /** \brief Disable IRQ Interrupts
Kojto 122:f9eeca106725 862
Kojto 122:f9eeca106725 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 122:f9eeca106725 864 Can only be executed in Privileged modes.
Kojto 122:f9eeca106725 865 */
Kojto 122:f9eeca106725 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 122:f9eeca106725 867 {
Kojto 122:f9eeca106725 868 uint32_t result;
Kojto 122:f9eeca106725 869
Kojto 122:f9eeca106725 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 122:f9eeca106725 871 __ASM volatile ("cpsid i");
Kojto 122:f9eeca106725 872 return(result & 0x80);
Kojto 122:f9eeca106725 873 }
Kojto 122:f9eeca106725 874
Kojto 122:f9eeca106725 875
Kojto 122:f9eeca106725 876 /** \brief Get APSR Register
Kojto 122:f9eeca106725 877
Kojto 122:f9eeca106725 878 This function returns the content of the APSR Register.
Kojto 122:f9eeca106725 879
Kojto 122:f9eeca106725 880 \return APSR Register value
Kojto 122:f9eeca106725 881 */
Kojto 122:f9eeca106725 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 122:f9eeca106725 883 {
Kojto 122:f9eeca106725 884 #if 1
Kojto 122:f9eeca106725 885 register uint32_t __regAPSR;
Kojto 122:f9eeca106725 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 122:f9eeca106725 887 #else
Kojto 122:f9eeca106725 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 122:f9eeca106725 889 #endif
Kojto 122:f9eeca106725 890 return(__regAPSR);
Kojto 122:f9eeca106725 891 }
Kojto 122:f9eeca106725 892
Kojto 122:f9eeca106725 893
Kojto 122:f9eeca106725 894 /** \brief Get CPSR Register
Kojto 122:f9eeca106725 895
Kojto 122:f9eeca106725 896 This function returns the content of the CPSR Register.
Kojto 122:f9eeca106725 897
Kojto 122:f9eeca106725 898 \return CPSR Register value
Kojto 122:f9eeca106725 899 */
Kojto 122:f9eeca106725 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 122:f9eeca106725 901 {
Kojto 122:f9eeca106725 902 #if 1
Kojto 122:f9eeca106725 903 register uint32_t __regCPSR;
Kojto 122:f9eeca106725 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 122:f9eeca106725 905 #else
Kojto 122:f9eeca106725 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 122:f9eeca106725 907 #endif
Kojto 122:f9eeca106725 908 return(__regCPSR);
Kojto 122:f9eeca106725 909 }
Kojto 122:f9eeca106725 910
Kojto 122:f9eeca106725 911 #if 0
Kojto 122:f9eeca106725 912 /** \brief Set Stack Pointer
Kojto 122:f9eeca106725 913
Kojto 122:f9eeca106725 914 This function assigns the given value to the current stack pointer.
Kojto 122:f9eeca106725 915
Kojto 122:f9eeca106725 916 \param [in] topOfStack Stack Pointer value to set
Kojto 122:f9eeca106725 917 */
Kojto 122:f9eeca106725 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 122:f9eeca106725 919 {
Kojto 122:f9eeca106725 920 register uint32_t __regSP __ASM("sp");
Kojto 122:f9eeca106725 921 __regSP = topOfStack;
Kojto 122:f9eeca106725 922 }
Kojto 122:f9eeca106725 923 #endif
Kojto 122:f9eeca106725 924
Kojto 122:f9eeca106725 925 /** \brief Get link register
Kojto 122:f9eeca106725 926
Kojto 122:f9eeca106725 927 This function returns the value of the link register
Kojto 122:f9eeca106725 928
Kojto 122:f9eeca106725 929 \return Value of link register
Kojto 122:f9eeca106725 930 */
Kojto 122:f9eeca106725 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 122:f9eeca106725 932 {
Kojto 122:f9eeca106725 933 register uint32_t __reglr __ASM("lr");
Kojto 122:f9eeca106725 934 return(__reglr);
Kojto 122:f9eeca106725 935 }
Kojto 122:f9eeca106725 936
Kojto 122:f9eeca106725 937 #if 0
Kojto 122:f9eeca106725 938 /** \brief Set link register
Kojto 122:f9eeca106725 939
Kojto 122:f9eeca106725 940 This function sets the value of the link register
Kojto 122:f9eeca106725 941
Kojto 122:f9eeca106725 942 \param [in] lr LR value to set
Kojto 122:f9eeca106725 943 */
Kojto 122:f9eeca106725 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 122:f9eeca106725 945 {
Kojto 122:f9eeca106725 946 register uint32_t __reglr __ASM("lr");
Kojto 122:f9eeca106725 947 __reglr = lr;
Kojto 122:f9eeca106725 948 }
Kojto 122:f9eeca106725 949 #endif
Kojto 122:f9eeca106725 950
Kojto 122:f9eeca106725 951 /** \brief Set Process Stack Pointer
Kojto 122:f9eeca106725 952
Kojto 122:f9eeca106725 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 122:f9eeca106725 954
Kojto 122:f9eeca106725 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 122:f9eeca106725 956 */
Kojto 122:f9eeca106725 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 122:f9eeca106725 958 {
Kojto 122:f9eeca106725 959 __asm__ volatile (
Kojto 122:f9eeca106725 960 ".ARM;"
Kojto 122:f9eeca106725 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 122:f9eeca106725 962
Kojto 122:f9eeca106725 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 122:f9eeca106725 964 "MRS R1, CPSR;"
Kojto 122:f9eeca106725 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 122:f9eeca106725 966 "MOV SP, R0;"
Kojto 122:f9eeca106725 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 122:f9eeca106725 968 "ISB;"
Kojto 122:f9eeca106725 969 //"BX LR;"
Kojto 122:f9eeca106725 970 :
Kojto 122:f9eeca106725 971 : "i"(MODE_SYS)
Kojto 122:f9eeca106725 972 : "r0", "r1");
Kojto 122:f9eeca106725 973 return;
Kojto 122:f9eeca106725 974 }
Kojto 122:f9eeca106725 975
Kojto 122:f9eeca106725 976 /** \brief Set User Mode
Kojto 122:f9eeca106725 977
Kojto 122:f9eeca106725 978 This function changes the processor state to User Mode
Kojto 122:f9eeca106725 979 */
Kojto 122:f9eeca106725 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 122:f9eeca106725 981 {
Kojto 122:f9eeca106725 982 __asm__ volatile (
Kojto 122:f9eeca106725 983 ".ARM;"
Kojto 122:f9eeca106725 984
Kojto 122:f9eeca106725 985 "CPS %0;"
Kojto 122:f9eeca106725 986 //"BX LR;"
Kojto 122:f9eeca106725 987 :
Kojto 122:f9eeca106725 988 : "i"(MODE_USR)
Kojto 122:f9eeca106725 989 : );
Kojto 122:f9eeca106725 990 return;
Kojto 122:f9eeca106725 991 }
Kojto 122:f9eeca106725 992
Kojto 122:f9eeca106725 993
Kojto 122:f9eeca106725 994 /** \brief Enable FIQ
Kojto 122:f9eeca106725 995
Kojto 122:f9eeca106725 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 122:f9eeca106725 997 Can only be executed in Privileged modes.
Kojto 122:f9eeca106725 998 */
Kojto 122:f9eeca106725 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 122:f9eeca106725 1000
Kojto 122:f9eeca106725 1001
Kojto 122:f9eeca106725 1002 /** \brief Disable FIQ
Kojto 122:f9eeca106725 1003
Kojto 122:f9eeca106725 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 122:f9eeca106725 1005 Can only be executed in Privileged modes.
Kojto 122:f9eeca106725 1006 */
Kojto 122:f9eeca106725 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 122:f9eeca106725 1008
Kojto 122:f9eeca106725 1009
Kojto 122:f9eeca106725 1010 /** \brief Get FPSCR
Kojto 122:f9eeca106725 1011
Kojto 122:f9eeca106725 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 122:f9eeca106725 1013
Kojto 122:f9eeca106725 1014 \return Floating Point Status/Control register value
Kojto 122:f9eeca106725 1015 */
Kojto 122:f9eeca106725 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 122:f9eeca106725 1017 {
Kojto 122:f9eeca106725 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 122:f9eeca106725 1019 #if 1
Kojto 122:f9eeca106725 1020 uint32_t result;
Kojto 122:f9eeca106725 1021
Kojto 122:f9eeca106725 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 122:f9eeca106725 1023 return (result);
Kojto 122:f9eeca106725 1024 #else
Kojto 122:f9eeca106725 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 122:f9eeca106725 1026 return(__regfpscr);
Kojto 122:f9eeca106725 1027 #endif
Kojto 122:f9eeca106725 1028 #else
Kojto 122:f9eeca106725 1029 return(0);
Kojto 122:f9eeca106725 1030 #endif
Kojto 122:f9eeca106725 1031 }
Kojto 122:f9eeca106725 1032
Kojto 122:f9eeca106725 1033
Kojto 122:f9eeca106725 1034 /** \brief Set FPSCR
Kojto 122:f9eeca106725 1035
Kojto 122:f9eeca106725 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 122:f9eeca106725 1037
Kojto 122:f9eeca106725 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 122:f9eeca106725 1039 */
Kojto 122:f9eeca106725 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 122:f9eeca106725 1041 {
Kojto 122:f9eeca106725 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 122:f9eeca106725 1043 #if 1
Kojto 122:f9eeca106725 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 122:f9eeca106725 1045 #else
Kojto 122:f9eeca106725 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 122:f9eeca106725 1047 __regfpscr = (fpscr);
Kojto 122:f9eeca106725 1048 #endif
Kojto 122:f9eeca106725 1049 #endif
Kojto 122:f9eeca106725 1050 }
Kojto 122:f9eeca106725 1051
Kojto 122:f9eeca106725 1052 /** \brief Get FPEXC
Kojto 122:f9eeca106725 1053
Kojto 122:f9eeca106725 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 122:f9eeca106725 1055
Kojto 122:f9eeca106725 1056 \return Floating Point Exception Control register value
Kojto 122:f9eeca106725 1057 */
Kojto 122:f9eeca106725 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 122:f9eeca106725 1059 {
Kojto 122:f9eeca106725 1060 #if (__FPU_PRESENT == 1)
Kojto 122:f9eeca106725 1061 #if 1
Kojto 122:f9eeca106725 1062 uint32_t result;
Kojto 122:f9eeca106725 1063
Kojto 122:f9eeca106725 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 122:f9eeca106725 1065 return (result);
Kojto 122:f9eeca106725 1066 #else
Kojto 122:f9eeca106725 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 122:f9eeca106725 1068 return(__regfpexc);
Kojto 122:f9eeca106725 1069 #endif
Kojto 122:f9eeca106725 1070 #else
Kojto 122:f9eeca106725 1071 return(0);
Kojto 122:f9eeca106725 1072 #endif
Kojto 122:f9eeca106725 1073 }
Kojto 122:f9eeca106725 1074
Kojto 122:f9eeca106725 1075
Kojto 122:f9eeca106725 1076 /** \brief Set FPEXC
Kojto 122:f9eeca106725 1077
Kojto 122:f9eeca106725 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 122:f9eeca106725 1079
Kojto 122:f9eeca106725 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 122:f9eeca106725 1081 */
Kojto 122:f9eeca106725 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 122:f9eeca106725 1083 {
Kojto 122:f9eeca106725 1084 #if (__FPU_PRESENT == 1)
Kojto 122:f9eeca106725 1085 #if 1
Kojto 122:f9eeca106725 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 122:f9eeca106725 1087 #else
Kojto 122:f9eeca106725 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 122:f9eeca106725 1089 __regfpexc = (fpexc);
Kojto 122:f9eeca106725 1090 #endif
Kojto 122:f9eeca106725 1091 #endif
Kojto 122:f9eeca106725 1092 }
Kojto 122:f9eeca106725 1093
Kojto 122:f9eeca106725 1094 /** \brief Get CPACR
Kojto 122:f9eeca106725 1095
Kojto 122:f9eeca106725 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 122:f9eeca106725 1097
Kojto 122:f9eeca106725 1098 \return Coprocessor Access Control register value
Kojto 122:f9eeca106725 1099 */
Kojto 122:f9eeca106725 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 122:f9eeca106725 1101 {
Kojto 122:f9eeca106725 1102 #if 1
Kojto 122:f9eeca106725 1103 register uint32_t __regCPACR;
Kojto 122:f9eeca106725 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 122:f9eeca106725 1105 #else
Kojto 122:f9eeca106725 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 122:f9eeca106725 1107 #endif
Kojto 122:f9eeca106725 1108 return __regCPACR;
Kojto 122:f9eeca106725 1109 }
Kojto 122:f9eeca106725 1110
Kojto 122:f9eeca106725 1111 /** \brief Set CPACR
Kojto 122:f9eeca106725 1112
Kojto 122:f9eeca106725 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 122:f9eeca106725 1114
Kojto 122:f9eeca106725 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 122:f9eeca106725 1116 */
Kojto 122:f9eeca106725 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 122:f9eeca106725 1118 {
Kojto 122:f9eeca106725 1119 #if 1
Kojto 122:f9eeca106725 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 122:f9eeca106725 1121 #else
Kojto 122:f9eeca106725 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 122:f9eeca106725 1123 __regCPACR = cpacr;
Kojto 122:f9eeca106725 1124 #endif
Kojto 122:f9eeca106725 1125 __ISB();
Kojto 122:f9eeca106725 1126 }
Kojto 122:f9eeca106725 1127
Kojto 122:f9eeca106725 1128 /** \brief Get CBAR
Kojto 122:f9eeca106725 1129
Kojto 122:f9eeca106725 1130 This function returns the value of the Configuration Base Address register.
Kojto 122:f9eeca106725 1131
Kojto 122:f9eeca106725 1132 \return Configuration Base Address register value
Kojto 122:f9eeca106725 1133 */
Kojto 122:f9eeca106725 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 122:f9eeca106725 1135 #if 1
Kojto 122:f9eeca106725 1136 register uint32_t __regCBAR;
Kojto 122:f9eeca106725 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 122:f9eeca106725 1138 #else
Kojto 122:f9eeca106725 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 122:f9eeca106725 1140 #endif
Kojto 122:f9eeca106725 1141 return(__regCBAR);
Kojto 122:f9eeca106725 1142 }
Kojto 122:f9eeca106725 1143
Kojto 122:f9eeca106725 1144 /** \brief Get TTBR0
Kojto 122:f9eeca106725 1145
Kojto 122:f9eeca106725 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 122:f9eeca106725 1147
Kojto 122:f9eeca106725 1148 \return Translation Table Base Register 0 value
Kojto 122:f9eeca106725 1149 */
Kojto 122:f9eeca106725 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 122:f9eeca106725 1151 #if 1
Kojto 122:f9eeca106725 1152 register uint32_t __regTTBR0;
Kojto 122:f9eeca106725 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 122:f9eeca106725 1154 #else
Kojto 122:f9eeca106725 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 122:f9eeca106725 1156 #endif
Kojto 122:f9eeca106725 1157 return(__regTTBR0);
Kojto 122:f9eeca106725 1158 }
Kojto 122:f9eeca106725 1159
Kojto 122:f9eeca106725 1160 /** \brief Set TTBR0
Kojto 122:f9eeca106725 1161
Kojto 122:f9eeca106725 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 122:f9eeca106725 1163
Kojto 122:f9eeca106725 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 122:f9eeca106725 1165 */
Kojto 122:f9eeca106725 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 122:f9eeca106725 1167 #if 1
Kojto 122:f9eeca106725 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 122:f9eeca106725 1169 #else
Kojto 122:f9eeca106725 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 122:f9eeca106725 1171 __regTTBR0 = ttbr0;
Kojto 122:f9eeca106725 1172 #endif
Kojto 122:f9eeca106725 1173 __ISB();
Kojto 122:f9eeca106725 1174 }
Kojto 122:f9eeca106725 1175
Kojto 122:f9eeca106725 1176 /** \brief Get DACR
Kojto 122:f9eeca106725 1177
Kojto 122:f9eeca106725 1178 This function returns the value of the Domain Access Control Register.
Kojto 122:f9eeca106725 1179
Kojto 122:f9eeca106725 1180 \return Domain Access Control Register value
Kojto 122:f9eeca106725 1181 */
Kojto 122:f9eeca106725 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 122:f9eeca106725 1183 #if 1
Kojto 122:f9eeca106725 1184 register uint32_t __regDACR;
Kojto 122:f9eeca106725 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 122:f9eeca106725 1186 #else
Kojto 122:f9eeca106725 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 122:f9eeca106725 1188 #endif
Kojto 122:f9eeca106725 1189 return(__regDACR);
Kojto 122:f9eeca106725 1190 }
Kojto 122:f9eeca106725 1191
Kojto 122:f9eeca106725 1192 /** \brief Set DACR
Kojto 122:f9eeca106725 1193
Kojto 122:f9eeca106725 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 122:f9eeca106725 1195
Kojto 122:f9eeca106725 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 122:f9eeca106725 1197 */
Kojto 122:f9eeca106725 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 122:f9eeca106725 1199 #if 1
Kojto 122:f9eeca106725 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 122:f9eeca106725 1201 #else
Kojto 122:f9eeca106725 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 122:f9eeca106725 1203 __regDACR = dacr;
Kojto 122:f9eeca106725 1204 #endif
Kojto 122:f9eeca106725 1205 __ISB();
Kojto 122:f9eeca106725 1206 }
Kojto 122:f9eeca106725 1207
Kojto 122:f9eeca106725 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 122:f9eeca106725 1209
Kojto 122:f9eeca106725 1210 /** \brief Set SCTLR
Kojto 122:f9eeca106725 1211
Kojto 122:f9eeca106725 1212 This function assigns the given value to the System Control Register.
Kojto 122:f9eeca106725 1213
Kojto 122:f9eeca106725 1214 \param [in] sctlr System Control Register value to set
Kojto 122:f9eeca106725 1215 */
Kojto 122:f9eeca106725 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 122:f9eeca106725 1217 {
Kojto 122:f9eeca106725 1218 #if 1
Kojto 122:f9eeca106725 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 122:f9eeca106725 1220 #else
Kojto 122:f9eeca106725 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 122:f9eeca106725 1222 __regSCTLR = sctlr;
Kojto 122:f9eeca106725 1223 #endif
Kojto 122:f9eeca106725 1224 }
Kojto 122:f9eeca106725 1225
Kojto 122:f9eeca106725 1226 /** \brief Get SCTLR
Kojto 122:f9eeca106725 1227
Kojto 122:f9eeca106725 1228 This function returns the value of the System Control Register.
Kojto 122:f9eeca106725 1229
Kojto 122:f9eeca106725 1230 \return System Control Register value
Kojto 122:f9eeca106725 1231 */
Kojto 122:f9eeca106725 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 122:f9eeca106725 1233 #if 1
Kojto 122:f9eeca106725 1234 register uint32_t __regSCTLR;
Kojto 122:f9eeca106725 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 122:f9eeca106725 1236 #else
Kojto 122:f9eeca106725 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 122:f9eeca106725 1238 #endif
Kojto 122:f9eeca106725 1239 return(__regSCTLR);
Kojto 122:f9eeca106725 1240 }
Kojto 122:f9eeca106725 1241
Kojto 122:f9eeca106725 1242 /** \brief Enable Caches
Kojto 122:f9eeca106725 1243
Kojto 122:f9eeca106725 1244 Enable Caches
Kojto 122:f9eeca106725 1245 */
Kojto 122:f9eeca106725 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 122:f9eeca106725 1247 // Set I bit 12 to enable I Cache
Kojto 122:f9eeca106725 1248 // Set C bit 2 to enable D Cache
Kojto 122:f9eeca106725 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 122:f9eeca106725 1250 }
Kojto 122:f9eeca106725 1251
Kojto 122:f9eeca106725 1252 /** \brief Disable Caches
Kojto 122:f9eeca106725 1253
Kojto 122:f9eeca106725 1254 Disable Caches
Kojto 122:f9eeca106725 1255 */
Kojto 122:f9eeca106725 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 122:f9eeca106725 1257 // Clear I bit 12 to disable I Cache
Kojto 122:f9eeca106725 1258 // Clear C bit 2 to disable D Cache
Kojto 122:f9eeca106725 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 122:f9eeca106725 1260 __ISB();
Kojto 122:f9eeca106725 1261 }
Kojto 122:f9eeca106725 1262
Kojto 122:f9eeca106725 1263 /** \brief Enable BTAC
Kojto 122:f9eeca106725 1264
Kojto 122:f9eeca106725 1265 Enable BTAC
Kojto 122:f9eeca106725 1266 */
Kojto 122:f9eeca106725 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 122:f9eeca106725 1268 // Set Z bit 11 to enable branch prediction
Kojto 122:f9eeca106725 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 122:f9eeca106725 1270 __ISB();
Kojto 122:f9eeca106725 1271 }
Kojto 122:f9eeca106725 1272
Kojto 122:f9eeca106725 1273 /** \brief Disable BTAC
Kojto 122:f9eeca106725 1274
Kojto 122:f9eeca106725 1275 Disable BTAC
Kojto 122:f9eeca106725 1276 */
Kojto 122:f9eeca106725 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 122:f9eeca106725 1278 // Clear Z bit 11 to disable branch prediction
Kojto 122:f9eeca106725 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 122:f9eeca106725 1280 }
Kojto 122:f9eeca106725 1281
Kojto 122:f9eeca106725 1282
Kojto 122:f9eeca106725 1283 /** \brief Enable MMU
Kojto 122:f9eeca106725 1284
Kojto 122:f9eeca106725 1285 Enable MMU
Kojto 122:f9eeca106725 1286 */
Kojto 122:f9eeca106725 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 122:f9eeca106725 1288 // Set M bit 0 to enable the MMU
Kojto 122:f9eeca106725 1289 // Set AFE bit to enable simplified access permissions model
Kojto 122:f9eeca106725 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 122:f9eeca106725 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 122:f9eeca106725 1292 __ISB();
Kojto 122:f9eeca106725 1293 }
Kojto 122:f9eeca106725 1294
Kojto 122:f9eeca106725 1295 /** \brief Disable MMU
Kojto 122:f9eeca106725 1296
Kojto 122:f9eeca106725 1297 Disable MMU
Kojto 122:f9eeca106725 1298 */
Kojto 122:f9eeca106725 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 122:f9eeca106725 1300 // Clear M bit 0 to disable the MMU
Kojto 122:f9eeca106725 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 122:f9eeca106725 1302 __ISB();
Kojto 122:f9eeca106725 1303 }
Kojto 122:f9eeca106725 1304
Kojto 122:f9eeca106725 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 122:f9eeca106725 1306 /** \brief Invalidate the whole tlb
Kojto 122:f9eeca106725 1307
Kojto 122:f9eeca106725 1308 TLBIALL. Invalidate the whole tlb
Kojto 122:f9eeca106725 1309 */
Kojto 122:f9eeca106725 1310
Kojto 122:f9eeca106725 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 122:f9eeca106725 1312 #if 1
Kojto 122:f9eeca106725 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 122:f9eeca106725 1314 #else
Kojto 122:f9eeca106725 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 122:f9eeca106725 1316 __TLBIALL = 0;
Kojto 122:f9eeca106725 1317 #endif
Kojto 122:f9eeca106725 1318 __DSB();
Kojto 122:f9eeca106725 1319 __ISB();
Kojto 122:f9eeca106725 1320 }
Kojto 122:f9eeca106725 1321
Kojto 122:f9eeca106725 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 122:f9eeca106725 1323 /** \brief Invalidate entire branch predictor array
Kojto 122:f9eeca106725 1324
Kojto 122:f9eeca106725 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 122:f9eeca106725 1326 */
Kojto 122:f9eeca106725 1327
Kojto 122:f9eeca106725 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 122:f9eeca106725 1329 #if 1
Kojto 122:f9eeca106725 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 122:f9eeca106725 1331 #else
Kojto 122:f9eeca106725 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 122:f9eeca106725 1333 __BPIALL = 0;
Kojto 122:f9eeca106725 1334 #endif
Kojto 122:f9eeca106725 1335 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 122:f9eeca106725 1337 }
Kojto 122:f9eeca106725 1338
Kojto 122:f9eeca106725 1339
Kojto 122:f9eeca106725 1340 /******************************** L1 cache operations ******************************************************/
Kojto 122:f9eeca106725 1341
Kojto 122:f9eeca106725 1342 /** \brief Invalidate the whole I$
Kojto 122:f9eeca106725 1343
Kojto 122:f9eeca106725 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 122:f9eeca106725 1345 */
Kojto 122:f9eeca106725 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 122:f9eeca106725 1347 #if 1
Kojto 122:f9eeca106725 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 122:f9eeca106725 1349 #else
Kojto 122:f9eeca106725 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 122:f9eeca106725 1351 __ICIALLU = 0;
Kojto 122:f9eeca106725 1352 #endif
Kojto 122:f9eeca106725 1353 __DSB(); //ensure completion of the invalidation
Kojto 122:f9eeca106725 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 122:f9eeca106725 1355 }
Kojto 122:f9eeca106725 1356
Kojto 122:f9eeca106725 1357 /** \brief Clean D$ by MVA
Kojto 122:f9eeca106725 1358
Kojto 122:f9eeca106725 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 122:f9eeca106725 1360 */
Kojto 122:f9eeca106725 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 122:f9eeca106725 1362 #if 1
Kojto 122:f9eeca106725 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 122:f9eeca106725 1364 #else
Kojto 122:f9eeca106725 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 122:f9eeca106725 1366 __DCCMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 1367 #endif
Kojto 122:f9eeca106725 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 1369 }
Kojto 122:f9eeca106725 1370
Kojto 122:f9eeca106725 1371 /** \brief Invalidate D$ by MVA
Kojto 122:f9eeca106725 1372
Kojto 122:f9eeca106725 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 122:f9eeca106725 1374 */
Kojto 122:f9eeca106725 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 122:f9eeca106725 1376 #if 1
Kojto 122:f9eeca106725 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 122:f9eeca106725 1378 #else
Kojto 122:f9eeca106725 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 122:f9eeca106725 1380 __DCIMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 1381 #endif
Kojto 122:f9eeca106725 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 1383 }
Kojto 122:f9eeca106725 1384
Kojto 122:f9eeca106725 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 122:f9eeca106725 1386
Kojto 122:f9eeca106725 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 122:f9eeca106725 1388 */
Kojto 122:f9eeca106725 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 122:f9eeca106725 1390 #if 1
Kojto 122:f9eeca106725 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 122:f9eeca106725 1392 #else
Kojto 122:f9eeca106725 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 122:f9eeca106725 1394 __DCCIMVAC = (uint32_t)va;
Kojto 122:f9eeca106725 1395 #endif
Kojto 122:f9eeca106725 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 122:f9eeca106725 1397 }
Kojto 122:f9eeca106725 1398
Kojto 122:f9eeca106725 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 122:f9eeca106725 1400
Kojto 122:f9eeca106725 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 122:f9eeca106725 1402 */
Kojto 122:f9eeca106725 1403 extern void __v7_all_cache(uint32_t op);
Kojto 122:f9eeca106725 1404
Kojto 122:f9eeca106725 1405
Kojto 122:f9eeca106725 1406 /** \brief Invalidate the whole D$
Kojto 122:f9eeca106725 1407
Kojto 122:f9eeca106725 1408 DCISW. Invalidate by Set/Way
Kojto 122:f9eeca106725 1409 */
Kojto 122:f9eeca106725 1410
Kojto 122:f9eeca106725 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 122:f9eeca106725 1412 __v7_all_cache(0);
Kojto 122:f9eeca106725 1413 }
Kojto 122:f9eeca106725 1414
Kojto 122:f9eeca106725 1415 /** \brief Clean the whole D$
Kojto 122:f9eeca106725 1416
Kojto 122:f9eeca106725 1417 DCCSW. Clean by Set/Way
Kojto 122:f9eeca106725 1418 */
Kojto 122:f9eeca106725 1419
Kojto 122:f9eeca106725 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 122:f9eeca106725 1421 __v7_all_cache(1);
Kojto 122:f9eeca106725 1422 }
Kojto 122:f9eeca106725 1423
Kojto 122:f9eeca106725 1424 /** \brief Clean and invalidate the whole D$
Kojto 122:f9eeca106725 1425
Kojto 122:f9eeca106725 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 122:f9eeca106725 1427 */
Kojto 122:f9eeca106725 1428
Kojto 122:f9eeca106725 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 122:f9eeca106725 1430 __v7_all_cache(2);
Kojto 122:f9eeca106725 1431 }
Kojto 122:f9eeca106725 1432
Kojto 122:f9eeca106725 1433 #include "core_ca_mmu.h"
Kojto 122:f9eeca106725 1434
Kojto 122:f9eeca106725 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 122:f9eeca106725 1436
Kojto 122:f9eeca106725 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 122:f9eeca106725 1438
Kojto 122:f9eeca106725 1439 #endif
Kojto 122:f9eeca106725 1440
Kojto 122:f9eeca106725 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 122:f9eeca106725 1442
Kojto 122:f9eeca106725 1443
Kojto 122:f9eeca106725 1444 #endif /* __CORE_CAFUNC_H__ */