mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**************************************************************************//**
Kojto 110:165afa46840b 2 * @file core_cm0plus.h
Kojto 110:165afa46840b 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 110:165afa46840b 6 *
Kojto 110:165afa46840b 7 * @note
Kojto 110:165afa46840b 8 *
Kojto 110:165afa46840b 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 110:165afa46840b 11
Kojto 110:165afa46840b 12 All rights reserved.
Kojto 110:165afa46840b 13 Redistribution and use in source and binary forms, with or without
Kojto 110:165afa46840b 14 modification, are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 15 - Redistributions of source code must retain the above copyright
Kojto 110:165afa46840b 16 notice, this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 17 - Redistributions in binary form must reproduce the above copyright
Kojto 110:165afa46840b 18 notice, this list of conditions and the following disclaimer in the
Kojto 110:165afa46840b 19 documentation and/or other materials provided with the distribution.
Kojto 110:165afa46840b 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 110:165afa46840b 21 to endorse or promote products derived from this software without
Kojto 110:165afa46840b 22 specific prior written permission.
Kojto 110:165afa46840b 23 *
Kojto 110:165afa46840b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 110:165afa46840b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 110:165afa46840b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 110:165afa46840b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 110:165afa46840b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 110:165afa46840b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 110:165afa46840b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 110:165afa46840b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 110:165afa46840b 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 35 ---------------------------------------------------------------------------*/
Kojto 110:165afa46840b 36
Kojto 110:165afa46840b 37
Kojto 110:165afa46840b 38 #if defined ( __ICCARM__ )
Kojto 110:165afa46840b 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 110:165afa46840b 40 #endif
Kojto 110:165afa46840b 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 110:165afa46840b 45 #ifdef __cplusplus
Kojto 110:165afa46840b 46 extern "C" {
Kojto 110:165afa46840b 47 #endif
Kojto 110:165afa46840b 48
Kojto 110:165afa46840b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 110:165afa46840b 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 110:165afa46840b 51
Kojto 110:165afa46840b 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 110:165afa46840b 53 Function definitions in header files are used to allow 'inlining'.
Kojto 110:165afa46840b 54
Kojto 110:165afa46840b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 110:165afa46840b 56 Unions are used for effective representation of core registers.
Kojto 110:165afa46840b 57
Kojto 110:165afa46840b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 110:165afa46840b 59 Function-like macros are used to allow more efficient code.
Kojto 110:165afa46840b 60 */
Kojto 110:165afa46840b 61
Kojto 110:165afa46840b 62
Kojto 110:165afa46840b 63 /*******************************************************************************
Kojto 110:165afa46840b 64 * CMSIS definitions
Kojto 110:165afa46840b 65 ******************************************************************************/
Kojto 110:165afa46840b 66 /** \ingroup Cortex-M0+
Kojto 110:165afa46840b 67 @{
Kojto 110:165afa46840b 68 */
Kojto 110:165afa46840b 69
Kojto 110:165afa46840b 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 110:165afa46840b 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 110:165afa46840b 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 110:165afa46840b 75
Kojto 110:165afa46840b 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 110:165afa46840b 77
Kojto 110:165afa46840b 78
Kojto 110:165afa46840b 79 #if defined ( __CC_ARM )
Kojto 110:165afa46840b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 110:165afa46840b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 110:165afa46840b 82 #define __STATIC_INLINE static __inline
Kojto 110:165afa46840b 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 110:165afa46840b 89 #elif defined ( __ICCARM__ )
Kojto 110:165afa46840b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 110:165afa46840b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 110:165afa46840b 92 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 110:165afa46840b 96 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 97
Kojto 110:165afa46840b 98 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 110:165afa46840b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 110:165afa46840b 101 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 110:165afa46840b 109 #endif
Kojto 110:165afa46840b 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 110:165afa46840b 113 */
Kojto 110:165afa46840b 114 #define __FPU_USED 0
Kojto 110:165afa46840b 115
Kojto 110:165afa46840b 116 #if defined ( __CC_ARM )
Kojto 110:165afa46840b 117 #if defined __TARGET_FPU_VFP
Kojto 110:165afa46840b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 119 #endif
Kojto 110:165afa46840b 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 110:165afa46840b 126 #elif defined ( __ICCARM__ )
Kojto 110:165afa46840b 127 #if defined __ARMVFP__
Kojto 110:165afa46840b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 129 #endif
Kojto 110:165afa46840b 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 110:165afa46840b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 134 #endif
Kojto 110:165afa46840b 135
Kojto 110:165afa46840b 136 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 137 #if defined __FPU_VFP__
Kojto 110:165afa46840b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 110:165afa46840b 145 #endif
Kojto 110:165afa46840b 146
Kojto 110:165afa46840b 147 #include <stdint.h> /* standard types definitions */
Kojto 110:165afa46840b 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 110:165afa46840b 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 110:165afa46840b 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 110:165afa46840b 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 110:165afa46840b 156
Kojto 110:165afa46840b 157 #ifndef __CMSIS_GENERIC
Kojto 110:165afa46840b 158
Kojto 110:165afa46840b 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 110:165afa46840b 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 110:165afa46840b 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 110:165afa46840b 166 /* check device defines and use defaults */
Kojto 110:165afa46840b 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 110:165afa46840b 168 #ifndef __CM0PLUS_REV
Kojto 110:165afa46840b 169 #define __CM0PLUS_REV 0x0000
Kojto 110:165afa46840b 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 110:165afa46840b 171 #endif
Kojto 110:165afa46840b 172
Kojto 110:165afa46840b 173 #ifndef __MPU_PRESENT
Kojto 110:165afa46840b 174 #define __MPU_PRESENT 0
Kojto 110:165afa46840b 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 110:165afa46840b 176 #endif
Kojto 110:165afa46840b 177
Kojto 110:165afa46840b 178 #ifndef __VTOR_PRESENT
Kojto 110:165afa46840b 179 #define __VTOR_PRESENT 0
Kojto 110:165afa46840b 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 110:165afa46840b 181 #endif
Kojto 110:165afa46840b 182
Kojto 110:165afa46840b 183 #ifndef __NVIC_PRIO_BITS
Kojto 110:165afa46840b 184 #define __NVIC_PRIO_BITS 2
Kojto 110:165afa46840b 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 110:165afa46840b 186 #endif
Kojto 110:165afa46840b 187
Kojto 110:165afa46840b 188 #ifndef __Vendor_SysTickConfig
Kojto 110:165afa46840b 189 #define __Vendor_SysTickConfig 0
Kojto 110:165afa46840b 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 110:165afa46840b 191 #endif
Kojto 110:165afa46840b 192 #endif
Kojto 110:165afa46840b 193
Kojto 110:165afa46840b 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 110:165afa46840b 195 /**
Kojto 110:165afa46840b 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 110:165afa46840b 197
Kojto 110:165afa46840b 198 <strong>IO Type Qualifiers</strong> are used
Kojto 110:165afa46840b 199 \li to specify the access to peripheral variables.
Kojto 110:165afa46840b 200 \li for automatic generation of peripheral register debug information.
Kojto 110:165afa46840b 201 */
Kojto 110:165afa46840b 202 #ifdef __cplusplus
Kojto 110:165afa46840b 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 110:165afa46840b 204 #else
Kojto 110:165afa46840b 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 110:165afa46840b 206 #endif
Kojto 110:165afa46840b 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 110:165afa46840b 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 110:165afa46840b 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 110:165afa46840b 218 /*@} end of group Cortex-M0+ */
Kojto 110:165afa46840b 219
Kojto 110:165afa46840b 220
Kojto 110:165afa46840b 221
Kojto 110:165afa46840b 222 /*******************************************************************************
Kojto 110:165afa46840b 223 * Register Abstraction
Kojto 110:165afa46840b 224 Core Register contain:
Kojto 110:165afa46840b 225 - Core Register
Kojto 110:165afa46840b 226 - Core NVIC Register
Kojto 110:165afa46840b 227 - Core SCB Register
Kojto 110:165afa46840b 228 - Core SysTick Register
Kojto 110:165afa46840b 229 - Core MPU Register
Kojto 110:165afa46840b 230 ******************************************************************************/
Kojto 110:165afa46840b 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 110:165afa46840b 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 110:165afa46840b 233 */
Kojto 110:165afa46840b 234
Kojto 110:165afa46840b 235 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 110:165afa46840b 237 \brief Core Register type definitions.
Kojto 110:165afa46840b 238 @{
Kojto 110:165afa46840b 239 */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 110:165afa46840b 242 */
Kojto 110:165afa46840b 243 typedef union
Kojto 110:165afa46840b 244 {
Kojto 110:165afa46840b 245 struct
Kojto 110:165afa46840b 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 110:165afa46840b 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 110:165afa46840b 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 110:165afa46840b 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 110:165afa46840b 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 110:165afa46840b 252 } b; /*!< Structure used for bit access */
Kojto 110:165afa46840b 253 uint32_t w; /*!< Type used for word access */
Kojto 110:165afa46840b 254 } APSR_Type;
Kojto 110:165afa46840b 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 110:165afa46840b 269
Kojto 110:165afa46840b 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 110:165afa46840b 271 */
Kojto 110:165afa46840b 272 typedef union
Kojto 110:165afa46840b 273 {
Kojto 110:165afa46840b 274 struct
Kojto 110:165afa46840b 275 {
Kojto 110:165afa46840b 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 110:165afa46840b 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 110:165afa46840b 278 } b; /*!< Structure used for bit access */
Kojto 110:165afa46840b 279 uint32_t w; /*!< Type used for word access */
Kojto 110:165afa46840b 280 } IPSR_Type;
Kojto 110:165afa46840b 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 110:165afa46840b 286
Kojto 110:165afa46840b 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 110:165afa46840b 288 */
Kojto 110:165afa46840b 289 typedef union
Kojto 110:165afa46840b 290 {
Kojto 110:165afa46840b 291 struct
Kojto 110:165afa46840b 292 {
Kojto 110:165afa46840b 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 110:165afa46840b 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 110:165afa46840b 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 110:165afa46840b 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 110:165afa46840b 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 110:165afa46840b 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 110:165afa46840b 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 110:165afa46840b 301 } b; /*!< Structure used for bit access */
Kojto 110:165afa46840b 302 uint32_t w; /*!< Type used for word access */
Kojto 110:165afa46840b 303 } xPSR_Type;
Kojto 110:165afa46840b 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 110:165afa46840b 324
Kojto 110:165afa46840b 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 110:165afa46840b 326 */
Kojto 110:165afa46840b 327 typedef union
Kojto 110:165afa46840b 328 {
Kojto 110:165afa46840b 329 struct
Kojto 110:165afa46840b 330 {
Kojto 110:165afa46840b 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 110:165afa46840b 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 110:165afa46840b 334 } b; /*!< Structure used for bit access */
Kojto 110:165afa46840b 335 uint32_t w; /*!< Type used for word access */
Kojto 110:165afa46840b 336 } CONTROL_Type;
Kojto 110:165afa46840b 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 110:165afa46840b 345 /*@} end of group CMSIS_CORE */
Kojto 110:165afa46840b 346
Kojto 110:165afa46840b 347
Kojto 110:165afa46840b 348 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 110:165afa46840b 350 \brief Type definitions for the NVIC Registers
Kojto 110:165afa46840b 351 @{
Kojto 110:165afa46840b 352 */
Kojto 110:165afa46840b 353
Kojto 110:165afa46840b 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 110:165afa46840b 355 */
Kojto 110:165afa46840b 356 typedef struct
Kojto 110:165afa46840b 357 {
Kojto 110:165afa46840b 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 110:165afa46840b 359 uint32_t RESERVED0[31];
Kojto 110:165afa46840b 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 110:165afa46840b 361 uint32_t RSERVED1[31];
Kojto 110:165afa46840b 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 110:165afa46840b 363 uint32_t RESERVED2[31];
Kojto 110:165afa46840b 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 110:165afa46840b 365 uint32_t RESERVED3[31];
Kojto 110:165afa46840b 366 uint32_t RESERVED4[64];
Kojto 110:165afa46840b 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 110:165afa46840b 368 } NVIC_Type;
Kojto 110:165afa46840b 369
Kojto 110:165afa46840b 370 /*@} end of group CMSIS_NVIC */
Kojto 110:165afa46840b 371
Kojto 110:165afa46840b 372
Kojto 110:165afa46840b 373 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 110:165afa46840b 375 \brief Type definitions for the System Control Block Registers
Kojto 110:165afa46840b 376 @{
Kojto 110:165afa46840b 377 */
Kojto 110:165afa46840b 378
Kojto 110:165afa46840b 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 110:165afa46840b 380 */
Kojto 110:165afa46840b 381 typedef struct
Kojto 110:165afa46840b 382 {
Kojto 110:165afa46840b 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 110:165afa46840b 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 110:165afa46840b 385 #if (__VTOR_PRESENT == 1)
Kojto 110:165afa46840b 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 110:165afa46840b 387 #else
Kojto 110:165afa46840b 388 uint32_t RESERVED0;
Kojto 110:165afa46840b 389 #endif
Kojto 110:165afa46840b 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 110:165afa46840b 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 110:165afa46840b 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 110:165afa46840b 393 uint32_t RESERVED1;
Kojto 110:165afa46840b 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 110:165afa46840b 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 110:165afa46840b 396 } SCB_Type;
Kojto 110:165afa46840b 397
Kojto 110:165afa46840b 398 /* SCB CPUID Register Definitions */
Kojto 110:165afa46840b 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 110:165afa46840b 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 110:165afa46840b 401
Kojto 110:165afa46840b 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 110:165afa46840b 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 110:165afa46840b 404
Kojto 110:165afa46840b 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 110:165afa46840b 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 110:165afa46840b 407
Kojto 110:165afa46840b 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 110:165afa46840b 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 110:165afa46840b 410
Kojto 110:165afa46840b 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 110:165afa46840b 413
Kojto 110:165afa46840b 414 /* SCB Interrupt Control State Register Definitions */
Kojto 110:165afa46840b 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 110:165afa46840b 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 110:165afa46840b 417
Kojto 110:165afa46840b 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 110:165afa46840b 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 110:165afa46840b 420
Kojto 110:165afa46840b 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 110:165afa46840b 423
Kojto 110:165afa46840b 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 110:165afa46840b 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 110:165afa46840b 426
Kojto 110:165afa46840b 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 110:165afa46840b 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 110:165afa46840b 429
Kojto 110:165afa46840b 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 110:165afa46840b 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 110:165afa46840b 432
Kojto 110:165afa46840b 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 110:165afa46840b 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 110:165afa46840b 435
Kojto 110:165afa46840b 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 110:165afa46840b 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 110:165afa46840b 438
Kojto 110:165afa46840b 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 110:165afa46840b 441
Kojto 110:165afa46840b 442 #if (__VTOR_PRESENT == 1)
Kojto 110:165afa46840b 443 /* SCB Interrupt Control State Register Definitions */
Kojto 110:165afa46840b 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 110:165afa46840b 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 110:165afa46840b 446 #endif
Kojto 110:165afa46840b 447
Kojto 110:165afa46840b 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 110:165afa46840b 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 110:165afa46840b 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 110:165afa46840b 451
Kojto 110:165afa46840b 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 110:165afa46840b 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 110:165afa46840b 454
Kojto 110:165afa46840b 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 110:165afa46840b 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 110:165afa46840b 457
Kojto 110:165afa46840b 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 110:165afa46840b 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 110:165afa46840b 460
Kojto 110:165afa46840b 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 110:165afa46840b 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 110:165afa46840b 463
Kojto 110:165afa46840b 464 /* SCB System Control Register Definitions */
Kojto 110:165afa46840b 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 110:165afa46840b 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 110:165afa46840b 467
Kojto 110:165afa46840b 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 110:165afa46840b 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 110:165afa46840b 470
Kojto 110:165afa46840b 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 110:165afa46840b 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 110:165afa46840b 473
Kojto 110:165afa46840b 474 /* SCB Configuration Control Register Definitions */
Kojto 110:165afa46840b 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 110:165afa46840b 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 110:165afa46840b 477
Kojto 110:165afa46840b 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 110:165afa46840b 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 110:165afa46840b 480
Kojto 110:165afa46840b 481 /* SCB System Handler Control and State Register Definitions */
Kojto 110:165afa46840b 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 110:165afa46840b 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 110:165afa46840b 484
Kojto 110:165afa46840b 485 /*@} end of group CMSIS_SCB */
Kojto 110:165afa46840b 486
Kojto 110:165afa46840b 487
Kojto 110:165afa46840b 488 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 110:165afa46840b 490 \brief Type definitions for the System Timer Registers.
Kojto 110:165afa46840b 491 @{
Kojto 110:165afa46840b 492 */
Kojto 110:165afa46840b 493
Kojto 110:165afa46840b 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 110:165afa46840b 495 */
Kojto 110:165afa46840b 496 typedef struct
Kojto 110:165afa46840b 497 {
Kojto 110:165afa46840b 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 110:165afa46840b 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 110:165afa46840b 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 110:165afa46840b 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 110:165afa46840b 502 } SysTick_Type;
Kojto 110:165afa46840b 503
Kojto 110:165afa46840b 504 /* SysTick Control / Status Register Definitions */
Kojto 110:165afa46840b 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 110:165afa46840b 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 110:165afa46840b 507
Kojto 110:165afa46840b 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 110:165afa46840b 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 110:165afa46840b 510
Kojto 110:165afa46840b 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 110:165afa46840b 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 110:165afa46840b 513
Kojto 110:165afa46840b 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 110:165afa46840b 516
Kojto 110:165afa46840b 517 /* SysTick Reload Register Definitions */
Kojto 110:165afa46840b 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 110:165afa46840b 520
Kojto 110:165afa46840b 521 /* SysTick Current Register Definitions */
Kojto 110:165afa46840b 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 110:165afa46840b 524
Kojto 110:165afa46840b 525 /* SysTick Calibration Register Definitions */
Kojto 110:165afa46840b 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 110:165afa46840b 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 110:165afa46840b 528
Kojto 110:165afa46840b 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 110:165afa46840b 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 110:165afa46840b 531
Kojto 110:165afa46840b 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 110:165afa46840b 534
Kojto 110:165afa46840b 535 /*@} end of group CMSIS_SysTick */
Kojto 110:165afa46840b 536
Kojto 110:165afa46840b 537 #if (__MPU_PRESENT == 1)
Kojto 110:165afa46840b 538 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 110:165afa46840b 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 110:165afa46840b 541 @{
Kojto 110:165afa46840b 542 */
Kojto 110:165afa46840b 543
Kojto 110:165afa46840b 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 110:165afa46840b 545 */
Kojto 110:165afa46840b 546 typedef struct
Kojto 110:165afa46840b 547 {
Kojto 110:165afa46840b 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 110:165afa46840b 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 110:165afa46840b 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 110:165afa46840b 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 110:165afa46840b 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 110:165afa46840b 553 } MPU_Type;
Kojto 110:165afa46840b 554
Kojto 110:165afa46840b 555 /* MPU Type Register */
Kojto 110:165afa46840b 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 110:165afa46840b 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 110:165afa46840b 558
Kojto 110:165afa46840b 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 110:165afa46840b 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 110:165afa46840b 561
Kojto 110:165afa46840b 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 110:165afa46840b 564
Kojto 110:165afa46840b 565 /* MPU Control Register */
Kojto 110:165afa46840b 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 110:165afa46840b 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 110:165afa46840b 568
Kojto 110:165afa46840b 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 110:165afa46840b 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 110:165afa46840b 571
Kojto 110:165afa46840b 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 110:165afa46840b 574
Kojto 110:165afa46840b 575 /* MPU Region Number Register */
Kojto 110:165afa46840b 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 110:165afa46840b 578
Kojto 110:165afa46840b 579 /* MPU Region Base Address Register */
Kojto 110:165afa46840b 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 110:165afa46840b 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 110:165afa46840b 582
Kojto 110:165afa46840b 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 110:165afa46840b 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 110:165afa46840b 585
Kojto 110:165afa46840b 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 110:165afa46840b 588
Kojto 110:165afa46840b 589 /* MPU Region Attribute and Size Register */
Kojto 110:165afa46840b 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 110:165afa46840b 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 110:165afa46840b 592
Kojto 110:165afa46840b 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 110:165afa46840b 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 110:165afa46840b 595
Kojto 110:165afa46840b 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 110:165afa46840b 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 110:165afa46840b 598
Kojto 110:165afa46840b 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 110:165afa46840b 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 110:165afa46840b 601
Kojto 110:165afa46840b 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 110:165afa46840b 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 110:165afa46840b 604
Kojto 110:165afa46840b 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 110:165afa46840b 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 110:165afa46840b 607
Kojto 110:165afa46840b 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 110:165afa46840b 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 110:165afa46840b 610
Kojto 110:165afa46840b 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 110:165afa46840b 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 110:165afa46840b 613
Kojto 110:165afa46840b 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 110:165afa46840b 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 110:165afa46840b 616
Kojto 110:165afa46840b 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 110:165afa46840b 619
Kojto 110:165afa46840b 620 /*@} end of group CMSIS_MPU */
Kojto 110:165afa46840b 621 #endif
Kojto 110:165afa46840b 622
Kojto 110:165afa46840b 623
Kojto 110:165afa46840b 624 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 110:165afa46840b 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 110:165afa46840b 627 are only accessible over DAP and not via processor. Therefore
Kojto 110:165afa46840b 628 they are not covered by the Cortex-M0 header file.
Kojto 110:165afa46840b 629 @{
Kojto 110:165afa46840b 630 */
Kojto 110:165afa46840b 631 /*@} end of group CMSIS_CoreDebug */
Kojto 110:165afa46840b 632
Kojto 110:165afa46840b 633
Kojto 110:165afa46840b 634 /** \ingroup CMSIS_core_register
Kojto 110:165afa46840b 635 \defgroup CMSIS_core_base Core Definitions
Kojto 110:165afa46840b 636 \brief Definitions for base addresses, unions, and structures.
Kojto 110:165afa46840b 637 @{
Kojto 110:165afa46840b 638 */
Kojto 110:165afa46840b 639
Kojto 110:165afa46840b 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 110:165afa46840b 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 110:165afa46840b 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 110:165afa46840b 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 110:165afa46840b 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 110:165afa46840b 645
Kojto 110:165afa46840b 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 110:165afa46840b 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 110:165afa46840b 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 110:165afa46840b 649
Kojto 110:165afa46840b 650 #if (__MPU_PRESENT == 1)
Kojto 110:165afa46840b 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 110:165afa46840b 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 110:165afa46840b 653 #endif
Kojto 110:165afa46840b 654
Kojto 110:165afa46840b 655 /*@} */
Kojto 110:165afa46840b 656
Kojto 110:165afa46840b 657
Kojto 110:165afa46840b 658
Kojto 110:165afa46840b 659 /*******************************************************************************
Kojto 110:165afa46840b 660 * Hardware Abstraction Layer
Kojto 110:165afa46840b 661 Core Function Interface contains:
Kojto 110:165afa46840b 662 - Core NVIC Functions
Kojto 110:165afa46840b 663 - Core SysTick Functions
Kojto 110:165afa46840b 664 - Core Register Access Functions
Kojto 110:165afa46840b 665 ******************************************************************************/
Kojto 110:165afa46840b 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 110:165afa46840b 667 */
Kojto 110:165afa46840b 668
Kojto 110:165afa46840b 669
Kojto 110:165afa46840b 670
Kojto 110:165afa46840b 671 /* ########################## NVIC functions #################################### */
Kojto 110:165afa46840b 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 110:165afa46840b 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 110:165afa46840b 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 110:165afa46840b 675 @{
Kojto 110:165afa46840b 676 */
Kojto 110:165afa46840b 677
Kojto 110:165afa46840b 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 110:165afa46840b 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 110:165afa46840b 683
Kojto 110:165afa46840b 684
Kojto 110:165afa46840b 685 /** \brief Enable External Interrupt
Kojto 110:165afa46840b 686
Kojto 110:165afa46840b 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 110:165afa46840b 688
Kojto 110:165afa46840b 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 110:165afa46840b 690 */
Kojto 110:165afa46840b 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 110:165afa46840b 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 110:165afa46840b 694 }
Kojto 110:165afa46840b 695
Kojto 110:165afa46840b 696
Kojto 110:165afa46840b 697 /** \brief Disable External Interrupt
Kojto 110:165afa46840b 698
Kojto 110:165afa46840b 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 110:165afa46840b 700
Kojto 110:165afa46840b 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 110:165afa46840b 702 */
Kojto 110:165afa46840b 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 110:165afa46840b 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 110:165afa46840b 708 }
Kojto 110:165afa46840b 709
Kojto 110:165afa46840b 710
Kojto 110:165afa46840b 711 /** \brief Get Pending Interrupt
Kojto 110:165afa46840b 712
Kojto 110:165afa46840b 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 110:165afa46840b 714 for the specified interrupt.
Kojto 110:165afa46840b 715
Kojto 110:165afa46840b 716 \param [in] IRQn Interrupt number.
Kojto 110:165afa46840b 717
Kojto 110:165afa46840b 718 \return 0 Interrupt status is not pending.
Kojto 110:165afa46840b 719 \return 1 Interrupt status is pending.
Kojto 110:165afa46840b 720 */
Kojto 110:165afa46840b 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 110:165afa46840b 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 110:165afa46840b 724 }
Kojto 110:165afa46840b 725
Kojto 110:165afa46840b 726
Kojto 110:165afa46840b 727 /** \brief Set Pending Interrupt
Kojto 110:165afa46840b 728
Kojto 110:165afa46840b 729 The function sets the pending bit of an external interrupt.
Kojto 110:165afa46840b 730
Kojto 110:165afa46840b 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 110:165afa46840b 732 */
Kojto 110:165afa46840b 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 110:165afa46840b 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 110:165afa46840b 736 }
Kojto 110:165afa46840b 737
Kojto 110:165afa46840b 738
Kojto 110:165afa46840b 739 /** \brief Clear Pending Interrupt
Kojto 110:165afa46840b 740
Kojto 110:165afa46840b 741 The function clears the pending bit of an external interrupt.
Kojto 110:165afa46840b 742
Kojto 110:165afa46840b 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 110:165afa46840b 744 */
Kojto 110:165afa46840b 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 110:165afa46840b 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 110:165afa46840b 748 }
Kojto 110:165afa46840b 749
Kojto 110:165afa46840b 750
Kojto 110:165afa46840b 751 /** \brief Set Interrupt Priority
Kojto 110:165afa46840b 752
Kojto 110:165afa46840b 753 The function sets the priority of an interrupt.
Kojto 110:165afa46840b 754
Kojto 110:165afa46840b 755 \note The priority cannot be set for every core interrupt.
Kojto 110:165afa46840b 756
Kojto 110:165afa46840b 757 \param [in] IRQn Interrupt number.
Kojto 110:165afa46840b 758 \param [in] priority Priority to set.
Kojto 110:165afa46840b 759 */
Kojto 110:165afa46840b 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 110:165afa46840b 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 110:165afa46840b 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 110:165afa46840b 770 }
Kojto 110:165afa46840b 771
Kojto 110:165afa46840b 772
Kojto 110:165afa46840b 773 /** \brief Get Interrupt Priority
Kojto 110:165afa46840b 774
Kojto 110:165afa46840b 775 The function reads the priority of an interrupt. The interrupt
Kojto 110:165afa46840b 776 number can be positive to specify an external (device specific)
Kojto 110:165afa46840b 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 110:165afa46840b 778
Kojto 110:165afa46840b 779
Kojto 110:165afa46840b 780 \param [in] IRQn Interrupt number.
Kojto 110:165afa46840b 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 110:165afa46840b 782 priority bits of the microcontroller.
Kojto 110:165afa46840b 783 */
Kojto 110:165afa46840b 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 110:165afa46840b 785 {
Kojto 110:165afa46840b 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 110:165afa46840b 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 110:165afa46840b 793 }
Kojto 110:165afa46840b 794
Kojto 110:165afa46840b 795
Kojto 110:165afa46840b 796 /** \brief System Reset
Kojto 110:165afa46840b 797
Kojto 110:165afa46840b 798 The function initiates a system reset request to reset the MCU.
Kojto 110:165afa46840b 799 */
Kojto 110:165afa46840b 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 110:165afa46840b 801 {
Kojto 110:165afa46840b 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 110:165afa46840b 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 110:165afa46840b 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 110:165afa46840b 808 }
Kojto 110:165afa46840b 809
Kojto 110:165afa46840b 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 110:165afa46840b 811
Kojto 110:165afa46840b 812
Kojto 110:165afa46840b 813
Kojto 110:165afa46840b 814 /* ################################## SysTick function ############################################ */
Kojto 110:165afa46840b 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 110:165afa46840b 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 110:165afa46840b 817 \brief Functions that configure the System.
Kojto 110:165afa46840b 818 @{
Kojto 110:165afa46840b 819 */
Kojto 110:165afa46840b 820
Kojto 110:165afa46840b 821 #if (__Vendor_SysTickConfig == 0)
Kojto 110:165afa46840b 822
Kojto 110:165afa46840b 823 /** \brief System Tick Configuration
Kojto 110:165afa46840b 824
Kojto 110:165afa46840b 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 110:165afa46840b 826 Counter is in free running mode to generate periodic interrupts.
Kojto 110:165afa46840b 827
Kojto 110:165afa46840b 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 110:165afa46840b 829
Kojto 110:165afa46840b 830 \return 0 Function succeeded.
Kojto 110:165afa46840b 831 \return 1 Function failed.
Kojto 110:165afa46840b 832
Kojto 110:165afa46840b 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 110:165afa46840b 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 110:165afa46840b 835 must contain a vendor-specific implementation of this function.
Kojto 110:165afa46840b 836
Kojto 110:165afa46840b 837 */
Kojto 110:165afa46840b 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 110:165afa46840b 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 110:165afa46840b 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 110:165afa46840b 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 110:165afa46840b 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 110:165afa46840b 849 }
Kojto 110:165afa46840b 850
Kojto 110:165afa46840b 851 #endif
Kojto 110:165afa46840b 852
Kojto 110:165afa46840b 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 110:165afa46840b 854
Kojto 110:165afa46840b 855
Kojto 110:165afa46840b 856
Kojto 110:165afa46840b 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 110:165afa46840b 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 110:165afa46840b 863
Kojto 110:165afa46840b 864 #endif /* __CMSIS_GENERIC */