mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620HSP/core_sc300.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 /**************************************************************************//**
AnnaBridge 125:2e9cc70d1897 2 * @file core_sc300.h
AnnaBridge 125:2e9cc70d1897 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
AnnaBridge 125:2e9cc70d1897 4 * @version V4.10
AnnaBridge 125:2e9cc70d1897 5 * @date 18. March 2015
AnnaBridge 125:2e9cc70d1897 6 *
AnnaBridge 125:2e9cc70d1897 7 * @note
AnnaBridge 125:2e9cc70d1897 8 *
AnnaBridge 125:2e9cc70d1897 9 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 125:2e9cc70d1897 11
AnnaBridge 125:2e9cc70d1897 12 All rights reserved.
AnnaBridge 125:2e9cc70d1897 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 125:2e9cc70d1897 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 125:2e9cc70d1897 15 - Redistributions of source code must retain the above copyright
AnnaBridge 125:2e9cc70d1897 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 125:2e9cc70d1897 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 125:2e9cc70d1897 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 125:2e9cc70d1897 19 documentation and/or other materials provided with the distribution.
AnnaBridge 125:2e9cc70d1897 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 125:2e9cc70d1897 21 to endorse or promote products derived from this software without
AnnaBridge 125:2e9cc70d1897 22 specific prior written permission.
AnnaBridge 125:2e9cc70d1897 23 *
AnnaBridge 125:2e9cc70d1897 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 125:2e9cc70d1897 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 125:2e9cc70d1897 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 125:2e9cc70d1897 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 125:2e9cc70d1897 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 125:2e9cc70d1897 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 125:2e9cc70d1897 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 125:2e9cc70d1897 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 125:2e9cc70d1897 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 125:2e9cc70d1897 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 125:2e9cc70d1897 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 125:2e9cc70d1897 35 ---------------------------------------------------------------------------*/
AnnaBridge 125:2e9cc70d1897 36
AnnaBridge 125:2e9cc70d1897 37
AnnaBridge 125:2e9cc70d1897 38 #if defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 125:2e9cc70d1897 40 #endif
AnnaBridge 125:2e9cc70d1897 41
AnnaBridge 125:2e9cc70d1897 42 #ifndef __CORE_SC300_H_GENERIC
AnnaBridge 125:2e9cc70d1897 43 #define __CORE_SC300_H_GENERIC
AnnaBridge 125:2e9cc70d1897 44
AnnaBridge 125:2e9cc70d1897 45 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 46 extern "C" {
AnnaBridge 125:2e9cc70d1897 47 #endif
AnnaBridge 125:2e9cc70d1897 48
AnnaBridge 125:2e9cc70d1897 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 125:2e9cc70d1897 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 125:2e9cc70d1897 51
AnnaBridge 125:2e9cc70d1897 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 125:2e9cc70d1897 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 125:2e9cc70d1897 54
AnnaBridge 125:2e9cc70d1897 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 125:2e9cc70d1897 56 Unions are used for effective representation of core registers.
AnnaBridge 125:2e9cc70d1897 57
AnnaBridge 125:2e9cc70d1897 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 125:2e9cc70d1897 59 Function-like macros are used to allow more efficient code.
AnnaBridge 125:2e9cc70d1897 60 */
AnnaBridge 125:2e9cc70d1897 61
AnnaBridge 125:2e9cc70d1897 62
AnnaBridge 125:2e9cc70d1897 63 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 64 * CMSIS definitions
AnnaBridge 125:2e9cc70d1897 65 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 66 /** \ingroup SC3000
AnnaBridge 125:2e9cc70d1897 67 @{
AnnaBridge 125:2e9cc70d1897 68 */
AnnaBridge 125:2e9cc70d1897 69
AnnaBridge 125:2e9cc70d1897 70 /* CMSIS SC300 definitions */
AnnaBridge 125:2e9cc70d1897 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 125:2e9cc70d1897 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 125:2e9cc70d1897 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 125:2e9cc70d1897 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 125:2e9cc70d1897 75
AnnaBridge 125:2e9cc70d1897 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
AnnaBridge 125:2e9cc70d1897 77
AnnaBridge 125:2e9cc70d1897 78
AnnaBridge 125:2e9cc70d1897 79 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 82 #define __STATIC_INLINE static __inline
AnnaBridge 125:2e9cc70d1897 83
AnnaBridge 125:2e9cc70d1897 84 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 87 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 88
AnnaBridge 125:2e9cc70d1897 89 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 125:2e9cc70d1897 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 125:2e9cc70d1897 92 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 93
AnnaBridge 125:2e9cc70d1897 94 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 125:2e9cc70d1897 96 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 97
AnnaBridge 125:2e9cc70d1897 98 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 101 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 102
AnnaBridge 125:2e9cc70d1897 103 #elif defined ( __CSMC__ )
AnnaBridge 125:2e9cc70d1897 104 #define __packed
AnnaBridge 125:2e9cc70d1897 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 125:2e9cc70d1897 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 125:2e9cc70d1897 107 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 108
AnnaBridge 125:2e9cc70d1897 109 #endif
AnnaBridge 125:2e9cc70d1897 110
AnnaBridge 125:2e9cc70d1897 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 125:2e9cc70d1897 112 This core does not support an FPU at all
AnnaBridge 125:2e9cc70d1897 113 */
AnnaBridge 125:2e9cc70d1897 114 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 115
AnnaBridge 125:2e9cc70d1897 116 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 117 #if defined __TARGET_FPU_VFP
AnnaBridge 125:2e9cc70d1897 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 119 #endif
AnnaBridge 125:2e9cc70d1897 120
AnnaBridge 125:2e9cc70d1897 121 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 125:2e9cc70d1897 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 124 #endif
AnnaBridge 125:2e9cc70d1897 125
AnnaBridge 125:2e9cc70d1897 126 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 127 #if defined __ARMVFP__
AnnaBridge 125:2e9cc70d1897 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 129 #endif
AnnaBridge 125:2e9cc70d1897 130
AnnaBridge 125:2e9cc70d1897 131 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 125:2e9cc70d1897 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 134 #endif
AnnaBridge 125:2e9cc70d1897 135
AnnaBridge 125:2e9cc70d1897 136 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 137 #if defined __FPU_VFP__
AnnaBridge 125:2e9cc70d1897 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 139 #endif
AnnaBridge 125:2e9cc70d1897 140
AnnaBridge 125:2e9cc70d1897 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 125:2e9cc70d1897 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 125:2e9cc70d1897 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 144 #endif
AnnaBridge 125:2e9cc70d1897 145 #endif
AnnaBridge 125:2e9cc70d1897 146
AnnaBridge 125:2e9cc70d1897 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 125:2e9cc70d1897 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 125:2e9cc70d1897 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 125:2e9cc70d1897 150
AnnaBridge 125:2e9cc70d1897 151 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 152 }
AnnaBridge 125:2e9cc70d1897 153 #endif
AnnaBridge 125:2e9cc70d1897 154
AnnaBridge 125:2e9cc70d1897 155 #endif /* __CORE_SC300_H_GENERIC */
AnnaBridge 125:2e9cc70d1897 156
AnnaBridge 125:2e9cc70d1897 157 #ifndef __CMSIS_GENERIC
AnnaBridge 125:2e9cc70d1897 158
AnnaBridge 125:2e9cc70d1897 159 #ifndef __CORE_SC300_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 160 #define __CORE_SC300_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 161
AnnaBridge 125:2e9cc70d1897 162 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 163 extern "C" {
AnnaBridge 125:2e9cc70d1897 164 #endif
AnnaBridge 125:2e9cc70d1897 165
AnnaBridge 125:2e9cc70d1897 166 /* check device defines and use defaults */
AnnaBridge 125:2e9cc70d1897 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 125:2e9cc70d1897 168 #ifndef __SC300_REV
AnnaBridge 125:2e9cc70d1897 169 #define __SC300_REV 0x0000
AnnaBridge 125:2e9cc70d1897 170 #warning "__SC300_REV not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 171 #endif
AnnaBridge 125:2e9cc70d1897 172
AnnaBridge 125:2e9cc70d1897 173 #ifndef __MPU_PRESENT
AnnaBridge 125:2e9cc70d1897 174 #define __MPU_PRESENT 0
AnnaBridge 125:2e9cc70d1897 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 176 #endif
AnnaBridge 125:2e9cc70d1897 177
AnnaBridge 125:2e9cc70d1897 178 #ifndef __NVIC_PRIO_BITS
AnnaBridge 125:2e9cc70d1897 179 #define __NVIC_PRIO_BITS 4
AnnaBridge 125:2e9cc70d1897 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 181 #endif
AnnaBridge 125:2e9cc70d1897 182
AnnaBridge 125:2e9cc70d1897 183 #ifndef __Vendor_SysTickConfig
AnnaBridge 125:2e9cc70d1897 184 #define __Vendor_SysTickConfig 0
AnnaBridge 125:2e9cc70d1897 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 186 #endif
AnnaBridge 125:2e9cc70d1897 187 #endif
AnnaBridge 125:2e9cc70d1897 188
AnnaBridge 125:2e9cc70d1897 189 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 125:2e9cc70d1897 190 /**
AnnaBridge 125:2e9cc70d1897 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 125:2e9cc70d1897 192
AnnaBridge 125:2e9cc70d1897 193 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 125:2e9cc70d1897 194 \li to specify the access to peripheral variables.
AnnaBridge 125:2e9cc70d1897 195 \li for automatic generation of peripheral register debug information.
AnnaBridge 125:2e9cc70d1897 196 */
AnnaBridge 125:2e9cc70d1897 197 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 198 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 199 #else
AnnaBridge 125:2e9cc70d1897 200 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 201 #endif
AnnaBridge 125:2e9cc70d1897 202 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 125:2e9cc70d1897 203 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 125:2e9cc70d1897 204
AnnaBridge 125:2e9cc70d1897 205 /*@} end of group SC300 */
AnnaBridge 125:2e9cc70d1897 206
AnnaBridge 125:2e9cc70d1897 207
AnnaBridge 125:2e9cc70d1897 208
AnnaBridge 125:2e9cc70d1897 209 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 210 * Register Abstraction
AnnaBridge 125:2e9cc70d1897 211 Core Register contain:
AnnaBridge 125:2e9cc70d1897 212 - Core Register
AnnaBridge 125:2e9cc70d1897 213 - Core NVIC Register
AnnaBridge 125:2e9cc70d1897 214 - Core SCB Register
AnnaBridge 125:2e9cc70d1897 215 - Core SysTick Register
AnnaBridge 125:2e9cc70d1897 216 - Core Debug Register
AnnaBridge 125:2e9cc70d1897 217 - Core MPU Register
AnnaBridge 125:2e9cc70d1897 218 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 125:2e9cc70d1897 220 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 125:2e9cc70d1897 221 */
AnnaBridge 125:2e9cc70d1897 222
AnnaBridge 125:2e9cc70d1897 223 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 224 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 125:2e9cc70d1897 225 \brief Core Register type definitions.
AnnaBridge 125:2e9cc70d1897 226 @{
AnnaBridge 125:2e9cc70d1897 227 */
AnnaBridge 125:2e9cc70d1897 228
AnnaBridge 125:2e9cc70d1897 229 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 125:2e9cc70d1897 230 */
AnnaBridge 125:2e9cc70d1897 231 typedef union
AnnaBridge 125:2e9cc70d1897 232 {
AnnaBridge 125:2e9cc70d1897 233 struct
AnnaBridge 125:2e9cc70d1897 234 {
AnnaBridge 125:2e9cc70d1897 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 125:2e9cc70d1897 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 125:2e9cc70d1897 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 125:2e9cc70d1897 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 125:2e9cc70d1897 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 125:2e9cc70d1897 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 125:2e9cc70d1897 241 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 243 } APSR_Type;
AnnaBridge 125:2e9cc70d1897 244
AnnaBridge 125:2e9cc70d1897 245 /* APSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 125:2e9cc70d1897 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 125:2e9cc70d1897 248
AnnaBridge 125:2e9cc70d1897 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 125:2e9cc70d1897 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 125:2e9cc70d1897 251
AnnaBridge 125:2e9cc70d1897 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 125:2e9cc70d1897 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 125:2e9cc70d1897 254
AnnaBridge 125:2e9cc70d1897 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 125:2e9cc70d1897 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 125:2e9cc70d1897 257
AnnaBridge 125:2e9cc70d1897 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
AnnaBridge 125:2e9cc70d1897 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 125:2e9cc70d1897 260
AnnaBridge 125:2e9cc70d1897 261
AnnaBridge 125:2e9cc70d1897 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 125:2e9cc70d1897 263 */
AnnaBridge 125:2e9cc70d1897 264 typedef union
AnnaBridge 125:2e9cc70d1897 265 {
AnnaBridge 125:2e9cc70d1897 266 struct
AnnaBridge 125:2e9cc70d1897 267 {
AnnaBridge 125:2e9cc70d1897 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 125:2e9cc70d1897 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 125:2e9cc70d1897 270 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 271 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 272 } IPSR_Type;
AnnaBridge 125:2e9cc70d1897 273
AnnaBridge 125:2e9cc70d1897 274 /* IPSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 125:2e9cc70d1897 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 125:2e9cc70d1897 277
AnnaBridge 125:2e9cc70d1897 278
AnnaBridge 125:2e9cc70d1897 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 125:2e9cc70d1897 280 */
AnnaBridge 125:2e9cc70d1897 281 typedef union
AnnaBridge 125:2e9cc70d1897 282 {
AnnaBridge 125:2e9cc70d1897 283 struct
AnnaBridge 125:2e9cc70d1897 284 {
AnnaBridge 125:2e9cc70d1897 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 125:2e9cc70d1897 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 125:2e9cc70d1897 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 125:2e9cc70d1897 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
AnnaBridge 125:2e9cc70d1897 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 125:2e9cc70d1897 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 125:2e9cc70d1897 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 125:2e9cc70d1897 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 125:2e9cc70d1897 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 125:2e9cc70d1897 294 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 295 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 296 } xPSR_Type;
AnnaBridge 125:2e9cc70d1897 297
AnnaBridge 125:2e9cc70d1897 298 /* xPSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 125:2e9cc70d1897 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 125:2e9cc70d1897 301
AnnaBridge 125:2e9cc70d1897 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 125:2e9cc70d1897 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 125:2e9cc70d1897 304
AnnaBridge 125:2e9cc70d1897 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 125:2e9cc70d1897 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 125:2e9cc70d1897 307
AnnaBridge 125:2e9cc70d1897 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 125:2e9cc70d1897 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 125:2e9cc70d1897 310
AnnaBridge 125:2e9cc70d1897 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
AnnaBridge 125:2e9cc70d1897 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 125:2e9cc70d1897 313
AnnaBridge 125:2e9cc70d1897 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
AnnaBridge 125:2e9cc70d1897 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
AnnaBridge 125:2e9cc70d1897 316
AnnaBridge 125:2e9cc70d1897 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 125:2e9cc70d1897 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 125:2e9cc70d1897 319
AnnaBridge 125:2e9cc70d1897 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 125:2e9cc70d1897 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 125:2e9cc70d1897 322
AnnaBridge 125:2e9cc70d1897 323
AnnaBridge 125:2e9cc70d1897 324 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 125:2e9cc70d1897 325 */
AnnaBridge 125:2e9cc70d1897 326 typedef union
AnnaBridge 125:2e9cc70d1897 327 {
AnnaBridge 125:2e9cc70d1897 328 struct
AnnaBridge 125:2e9cc70d1897 329 {
AnnaBridge 125:2e9cc70d1897 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 125:2e9cc70d1897 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 125:2e9cc70d1897 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 125:2e9cc70d1897 333 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 334 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 335 } CONTROL_Type;
AnnaBridge 125:2e9cc70d1897 336
AnnaBridge 125:2e9cc70d1897 337 /* CONTROL Register Definitions */
AnnaBridge 125:2e9cc70d1897 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 125:2e9cc70d1897 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 125:2e9cc70d1897 340
AnnaBridge 125:2e9cc70d1897 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
AnnaBridge 125:2e9cc70d1897 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 125:2e9cc70d1897 343
AnnaBridge 125:2e9cc70d1897 344 /*@} end of group CMSIS_CORE */
AnnaBridge 125:2e9cc70d1897 345
AnnaBridge 125:2e9cc70d1897 346
AnnaBridge 125:2e9cc70d1897 347 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 125:2e9cc70d1897 349 \brief Type definitions for the NVIC Registers
AnnaBridge 125:2e9cc70d1897 350 @{
AnnaBridge 125:2e9cc70d1897 351 */
AnnaBridge 125:2e9cc70d1897 352
AnnaBridge 125:2e9cc70d1897 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 125:2e9cc70d1897 354 */
AnnaBridge 125:2e9cc70d1897 355 typedef struct
AnnaBridge 125:2e9cc70d1897 356 {
AnnaBridge 125:2e9cc70d1897 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 125:2e9cc70d1897 358 uint32_t RESERVED0[24];
AnnaBridge 125:2e9cc70d1897 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 125:2e9cc70d1897 360 uint32_t RSERVED1[24];
AnnaBridge 125:2e9cc70d1897 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 125:2e9cc70d1897 362 uint32_t RESERVED2[24];
AnnaBridge 125:2e9cc70d1897 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 125:2e9cc70d1897 364 uint32_t RESERVED3[24];
AnnaBridge 125:2e9cc70d1897 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 125:2e9cc70d1897 366 uint32_t RESERVED4[56];
AnnaBridge 125:2e9cc70d1897 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 125:2e9cc70d1897 368 uint32_t RESERVED5[644];
AnnaBridge 125:2e9cc70d1897 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 125:2e9cc70d1897 370 } NVIC_Type;
AnnaBridge 125:2e9cc70d1897 371
AnnaBridge 125:2e9cc70d1897 372 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 125:2e9cc70d1897 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
AnnaBridge 125:2e9cc70d1897 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 125:2e9cc70d1897 375
AnnaBridge 125:2e9cc70d1897 376 /*@} end of group CMSIS_NVIC */
AnnaBridge 125:2e9cc70d1897 377
AnnaBridge 125:2e9cc70d1897 378
AnnaBridge 125:2e9cc70d1897 379 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 380 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 125:2e9cc70d1897 381 \brief Type definitions for the System Control Block Registers
AnnaBridge 125:2e9cc70d1897 382 @{
AnnaBridge 125:2e9cc70d1897 383 */
AnnaBridge 125:2e9cc70d1897 384
AnnaBridge 125:2e9cc70d1897 385 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 125:2e9cc70d1897 386 */
AnnaBridge 125:2e9cc70d1897 387 typedef struct
AnnaBridge 125:2e9cc70d1897 388 {
AnnaBridge 125:2e9cc70d1897 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 125:2e9cc70d1897 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 125:2e9cc70d1897 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 125:2e9cc70d1897 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 125:2e9cc70d1897 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 125:2e9cc70d1897 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 125:2e9cc70d1897 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 125:2e9cc70d1897 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 125:2e9cc70d1897 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 125:2e9cc70d1897 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 125:2e9cc70d1897 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 125:2e9cc70d1897 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 125:2e9cc70d1897 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 125:2e9cc70d1897 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 125:2e9cc70d1897 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 125:2e9cc70d1897 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 125:2e9cc70d1897 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 125:2e9cc70d1897 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 125:2e9cc70d1897 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 125:2e9cc70d1897 408 uint32_t RESERVED0[5];
AnnaBridge 125:2e9cc70d1897 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 125:2e9cc70d1897 410 uint32_t RESERVED1[129];
AnnaBridge 125:2e9cc70d1897 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 125:2e9cc70d1897 412 } SCB_Type;
AnnaBridge 125:2e9cc70d1897 413
AnnaBridge 125:2e9cc70d1897 414 /* SCB CPUID Register Definitions */
AnnaBridge 125:2e9cc70d1897 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 125:2e9cc70d1897 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 125:2e9cc70d1897 417
AnnaBridge 125:2e9cc70d1897 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 125:2e9cc70d1897 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 125:2e9cc70d1897 420
AnnaBridge 125:2e9cc70d1897 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 125:2e9cc70d1897 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 125:2e9cc70d1897 423
AnnaBridge 125:2e9cc70d1897 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 125:2e9cc70d1897 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 125:2e9cc70d1897 426
AnnaBridge 125:2e9cc70d1897 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 125:2e9cc70d1897 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 125:2e9cc70d1897 429
AnnaBridge 125:2e9cc70d1897 430 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 125:2e9cc70d1897 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 125:2e9cc70d1897 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 125:2e9cc70d1897 433
AnnaBridge 125:2e9cc70d1897 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 125:2e9cc70d1897 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 125:2e9cc70d1897 436
AnnaBridge 125:2e9cc70d1897 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 125:2e9cc70d1897 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 125:2e9cc70d1897 439
AnnaBridge 125:2e9cc70d1897 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 125:2e9cc70d1897 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 125:2e9cc70d1897 442
AnnaBridge 125:2e9cc70d1897 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 125:2e9cc70d1897 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 125:2e9cc70d1897 445
AnnaBridge 125:2e9cc70d1897 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 125:2e9cc70d1897 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 125:2e9cc70d1897 448
AnnaBridge 125:2e9cc70d1897 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 125:2e9cc70d1897 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 125:2e9cc70d1897 451
AnnaBridge 125:2e9cc70d1897 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 125:2e9cc70d1897 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 125:2e9cc70d1897 454
AnnaBridge 125:2e9cc70d1897 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 125:2e9cc70d1897 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 125:2e9cc70d1897 457
AnnaBridge 125:2e9cc70d1897 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 125:2e9cc70d1897 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 125:2e9cc70d1897 460
AnnaBridge 125:2e9cc70d1897 461 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 125:2e9cc70d1897 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
AnnaBridge 125:2e9cc70d1897 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
AnnaBridge 125:2e9cc70d1897 464
AnnaBridge 125:2e9cc70d1897 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 125:2e9cc70d1897 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 125:2e9cc70d1897 467
AnnaBridge 125:2e9cc70d1897 468 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 125:2e9cc70d1897 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 125:2e9cc70d1897 471
AnnaBridge 125:2e9cc70d1897 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 125:2e9cc70d1897 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 125:2e9cc70d1897 474
AnnaBridge 125:2e9cc70d1897 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 125:2e9cc70d1897 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 125:2e9cc70d1897 477
AnnaBridge 125:2e9cc70d1897 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 125:2e9cc70d1897 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 125:2e9cc70d1897 480
AnnaBridge 125:2e9cc70d1897 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 125:2e9cc70d1897 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 125:2e9cc70d1897 483
AnnaBridge 125:2e9cc70d1897 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 125:2e9cc70d1897 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 125:2e9cc70d1897 486
AnnaBridge 125:2e9cc70d1897 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 125:2e9cc70d1897 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 125:2e9cc70d1897 489
AnnaBridge 125:2e9cc70d1897 490 /* SCB System Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 125:2e9cc70d1897 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 125:2e9cc70d1897 493
AnnaBridge 125:2e9cc70d1897 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 125:2e9cc70d1897 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 125:2e9cc70d1897 496
AnnaBridge 125:2e9cc70d1897 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 125:2e9cc70d1897 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 125:2e9cc70d1897 499
AnnaBridge 125:2e9cc70d1897 500 /* SCB Configuration Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 125:2e9cc70d1897 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 125:2e9cc70d1897 503
AnnaBridge 125:2e9cc70d1897 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 125:2e9cc70d1897 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 125:2e9cc70d1897 506
AnnaBridge 125:2e9cc70d1897 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 125:2e9cc70d1897 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 125:2e9cc70d1897 509
AnnaBridge 125:2e9cc70d1897 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 125:2e9cc70d1897 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 125:2e9cc70d1897 512
AnnaBridge 125:2e9cc70d1897 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 125:2e9cc70d1897 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 125:2e9cc70d1897 515
AnnaBridge 125:2e9cc70d1897 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 125:2e9cc70d1897 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 125:2e9cc70d1897 518
AnnaBridge 125:2e9cc70d1897 519 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 125:2e9cc70d1897 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 125:2e9cc70d1897 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 125:2e9cc70d1897 522
AnnaBridge 125:2e9cc70d1897 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 125:2e9cc70d1897 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 125:2e9cc70d1897 525
AnnaBridge 125:2e9cc70d1897 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 125:2e9cc70d1897 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 125:2e9cc70d1897 528
AnnaBridge 125:2e9cc70d1897 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 125:2e9cc70d1897 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 125:2e9cc70d1897 531
AnnaBridge 125:2e9cc70d1897 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 125:2e9cc70d1897 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 125:2e9cc70d1897 534
AnnaBridge 125:2e9cc70d1897 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 125:2e9cc70d1897 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 125:2e9cc70d1897 537
AnnaBridge 125:2e9cc70d1897 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 125:2e9cc70d1897 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 125:2e9cc70d1897 540
AnnaBridge 125:2e9cc70d1897 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 125:2e9cc70d1897 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 125:2e9cc70d1897 543
AnnaBridge 125:2e9cc70d1897 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 125:2e9cc70d1897 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 125:2e9cc70d1897 546
AnnaBridge 125:2e9cc70d1897 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 125:2e9cc70d1897 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 125:2e9cc70d1897 549
AnnaBridge 125:2e9cc70d1897 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 125:2e9cc70d1897 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 125:2e9cc70d1897 552
AnnaBridge 125:2e9cc70d1897 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 125:2e9cc70d1897 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 125:2e9cc70d1897 555
AnnaBridge 125:2e9cc70d1897 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 125:2e9cc70d1897 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 125:2e9cc70d1897 558
AnnaBridge 125:2e9cc70d1897 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 125:2e9cc70d1897 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 125:2e9cc70d1897 561
AnnaBridge 125:2e9cc70d1897 562 /* SCB Configurable Fault Status Registers Definitions */
AnnaBridge 125:2e9cc70d1897 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 125:2e9cc70d1897 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 125:2e9cc70d1897 565
AnnaBridge 125:2e9cc70d1897 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 125:2e9cc70d1897 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 125:2e9cc70d1897 568
AnnaBridge 125:2e9cc70d1897 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 125:2e9cc70d1897 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 125:2e9cc70d1897 571
AnnaBridge 125:2e9cc70d1897 572 /* SCB Hard Fault Status Registers Definitions */
AnnaBridge 125:2e9cc70d1897 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 125:2e9cc70d1897 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 125:2e9cc70d1897 575
AnnaBridge 125:2e9cc70d1897 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
AnnaBridge 125:2e9cc70d1897 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 125:2e9cc70d1897 578
AnnaBridge 125:2e9cc70d1897 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 125:2e9cc70d1897 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 125:2e9cc70d1897 581
AnnaBridge 125:2e9cc70d1897 582 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 125:2e9cc70d1897 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 125:2e9cc70d1897 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 125:2e9cc70d1897 585
AnnaBridge 125:2e9cc70d1897 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
AnnaBridge 125:2e9cc70d1897 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 125:2e9cc70d1897 588
AnnaBridge 125:2e9cc70d1897 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 125:2e9cc70d1897 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 125:2e9cc70d1897 591
AnnaBridge 125:2e9cc70d1897 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
AnnaBridge 125:2e9cc70d1897 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 125:2e9cc70d1897 594
AnnaBridge 125:2e9cc70d1897 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
AnnaBridge 125:2e9cc70d1897 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 125:2e9cc70d1897 597
AnnaBridge 125:2e9cc70d1897 598 /*@} end of group CMSIS_SCB */
AnnaBridge 125:2e9cc70d1897 599
AnnaBridge 125:2e9cc70d1897 600
AnnaBridge 125:2e9cc70d1897 601 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 125:2e9cc70d1897 603 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 125:2e9cc70d1897 604 @{
AnnaBridge 125:2e9cc70d1897 605 */
AnnaBridge 125:2e9cc70d1897 606
AnnaBridge 125:2e9cc70d1897 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 125:2e9cc70d1897 608 */
AnnaBridge 125:2e9cc70d1897 609 typedef struct
AnnaBridge 125:2e9cc70d1897 610 {
AnnaBridge 125:2e9cc70d1897 611 uint32_t RESERVED0[1];
AnnaBridge 125:2e9cc70d1897 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 125:2e9cc70d1897 613 uint32_t RESERVED1[1];
AnnaBridge 125:2e9cc70d1897 614 } SCnSCB_Type;
AnnaBridge 125:2e9cc70d1897 615
AnnaBridge 125:2e9cc70d1897 616 /* Interrupt Controller Type Register Definitions */
AnnaBridge 125:2e9cc70d1897 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
AnnaBridge 125:2e9cc70d1897 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 125:2e9cc70d1897 619
AnnaBridge 125:2e9cc70d1897 620 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 125:2e9cc70d1897 621
AnnaBridge 125:2e9cc70d1897 622
AnnaBridge 125:2e9cc70d1897 623 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 125:2e9cc70d1897 625 \brief Type definitions for the System Timer Registers.
AnnaBridge 125:2e9cc70d1897 626 @{
AnnaBridge 125:2e9cc70d1897 627 */
AnnaBridge 125:2e9cc70d1897 628
AnnaBridge 125:2e9cc70d1897 629 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 125:2e9cc70d1897 630 */
AnnaBridge 125:2e9cc70d1897 631 typedef struct
AnnaBridge 125:2e9cc70d1897 632 {
AnnaBridge 125:2e9cc70d1897 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 125:2e9cc70d1897 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 125:2e9cc70d1897 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 125:2e9cc70d1897 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 125:2e9cc70d1897 637 } SysTick_Type;
AnnaBridge 125:2e9cc70d1897 638
AnnaBridge 125:2e9cc70d1897 639 /* SysTick Control / Status Register Definitions */
AnnaBridge 125:2e9cc70d1897 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 125:2e9cc70d1897 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 125:2e9cc70d1897 642
AnnaBridge 125:2e9cc70d1897 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 125:2e9cc70d1897 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 125:2e9cc70d1897 645
AnnaBridge 125:2e9cc70d1897 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 125:2e9cc70d1897 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 125:2e9cc70d1897 648
AnnaBridge 125:2e9cc70d1897 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 125:2e9cc70d1897 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 125:2e9cc70d1897 651
AnnaBridge 125:2e9cc70d1897 652 /* SysTick Reload Register Definitions */
AnnaBridge 125:2e9cc70d1897 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 125:2e9cc70d1897 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 125:2e9cc70d1897 655
AnnaBridge 125:2e9cc70d1897 656 /* SysTick Current Register Definitions */
AnnaBridge 125:2e9cc70d1897 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 125:2e9cc70d1897 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 125:2e9cc70d1897 659
AnnaBridge 125:2e9cc70d1897 660 /* SysTick Calibration Register Definitions */
AnnaBridge 125:2e9cc70d1897 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 125:2e9cc70d1897 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 125:2e9cc70d1897 663
AnnaBridge 125:2e9cc70d1897 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 125:2e9cc70d1897 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 125:2e9cc70d1897 666
AnnaBridge 125:2e9cc70d1897 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 125:2e9cc70d1897 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 125:2e9cc70d1897 669
AnnaBridge 125:2e9cc70d1897 670 /*@} end of group CMSIS_SysTick */
AnnaBridge 125:2e9cc70d1897 671
AnnaBridge 125:2e9cc70d1897 672
AnnaBridge 125:2e9cc70d1897 673 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 125:2e9cc70d1897 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 125:2e9cc70d1897 676 @{
AnnaBridge 125:2e9cc70d1897 677 */
AnnaBridge 125:2e9cc70d1897 678
AnnaBridge 125:2e9cc70d1897 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 125:2e9cc70d1897 680 */
AnnaBridge 125:2e9cc70d1897 681 typedef struct
AnnaBridge 125:2e9cc70d1897 682 {
AnnaBridge 125:2e9cc70d1897 683 __O union
AnnaBridge 125:2e9cc70d1897 684 {
AnnaBridge 125:2e9cc70d1897 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 125:2e9cc70d1897 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 125:2e9cc70d1897 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 125:2e9cc70d1897 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 125:2e9cc70d1897 689 uint32_t RESERVED0[864];
AnnaBridge 125:2e9cc70d1897 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 125:2e9cc70d1897 691 uint32_t RESERVED1[15];
AnnaBridge 125:2e9cc70d1897 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 125:2e9cc70d1897 693 uint32_t RESERVED2[15];
AnnaBridge 125:2e9cc70d1897 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 125:2e9cc70d1897 695 uint32_t RESERVED3[29];
AnnaBridge 125:2e9cc70d1897 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 125:2e9cc70d1897 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 125:2e9cc70d1897 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 125:2e9cc70d1897 699 uint32_t RESERVED4[43];
AnnaBridge 125:2e9cc70d1897 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 125:2e9cc70d1897 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 125:2e9cc70d1897 702 uint32_t RESERVED5[6];
AnnaBridge 125:2e9cc70d1897 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 125:2e9cc70d1897 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 125:2e9cc70d1897 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 125:2e9cc70d1897 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 125:2e9cc70d1897 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 125:2e9cc70d1897 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 125:2e9cc70d1897 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 125:2e9cc70d1897 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 125:2e9cc70d1897 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 125:2e9cc70d1897 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 125:2e9cc70d1897 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 125:2e9cc70d1897 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 125:2e9cc70d1897 715 } ITM_Type;
AnnaBridge 125:2e9cc70d1897 716
AnnaBridge 125:2e9cc70d1897 717 /* ITM Trace Privilege Register Definitions */
AnnaBridge 125:2e9cc70d1897 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 125:2e9cc70d1897 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 125:2e9cc70d1897 720
AnnaBridge 125:2e9cc70d1897 721 /* ITM Trace Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
AnnaBridge 125:2e9cc70d1897 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 125:2e9cc70d1897 724
AnnaBridge 125:2e9cc70d1897 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
AnnaBridge 125:2e9cc70d1897 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 125:2e9cc70d1897 727
AnnaBridge 125:2e9cc70d1897 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 125:2e9cc70d1897 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 125:2e9cc70d1897 730
AnnaBridge 125:2e9cc70d1897 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
AnnaBridge 125:2e9cc70d1897 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 125:2e9cc70d1897 733
AnnaBridge 125:2e9cc70d1897 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
AnnaBridge 125:2e9cc70d1897 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 125:2e9cc70d1897 736
AnnaBridge 125:2e9cc70d1897 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
AnnaBridge 125:2e9cc70d1897 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 125:2e9cc70d1897 739
AnnaBridge 125:2e9cc70d1897 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
AnnaBridge 125:2e9cc70d1897 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 125:2e9cc70d1897 742
AnnaBridge 125:2e9cc70d1897 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
AnnaBridge 125:2e9cc70d1897 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 125:2e9cc70d1897 745
AnnaBridge 125:2e9cc70d1897 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 125:2e9cc70d1897 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 125:2e9cc70d1897 748
AnnaBridge 125:2e9cc70d1897 749 /* ITM Integration Write Register Definitions */
AnnaBridge 125:2e9cc70d1897 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 125:2e9cc70d1897 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 125:2e9cc70d1897 752
AnnaBridge 125:2e9cc70d1897 753 /* ITM Integration Read Register Definitions */
AnnaBridge 125:2e9cc70d1897 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
AnnaBridge 125:2e9cc70d1897 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 125:2e9cc70d1897 756
AnnaBridge 125:2e9cc70d1897 757 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 125:2e9cc70d1897 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 125:2e9cc70d1897 760
AnnaBridge 125:2e9cc70d1897 761 /* ITM Lock Status Register Definitions */
AnnaBridge 125:2e9cc70d1897 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
AnnaBridge 125:2e9cc70d1897 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 125:2e9cc70d1897 764
AnnaBridge 125:2e9cc70d1897 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
AnnaBridge 125:2e9cc70d1897 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 125:2e9cc70d1897 767
AnnaBridge 125:2e9cc70d1897 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
AnnaBridge 125:2e9cc70d1897 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 125:2e9cc70d1897 770
AnnaBridge 125:2e9cc70d1897 771 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 125:2e9cc70d1897 772
AnnaBridge 125:2e9cc70d1897 773
AnnaBridge 125:2e9cc70d1897 774 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 125:2e9cc70d1897 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 125:2e9cc70d1897 777 @{
AnnaBridge 125:2e9cc70d1897 778 */
AnnaBridge 125:2e9cc70d1897 779
AnnaBridge 125:2e9cc70d1897 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 125:2e9cc70d1897 781 */
AnnaBridge 125:2e9cc70d1897 782 typedef struct
AnnaBridge 125:2e9cc70d1897 783 {
AnnaBridge 125:2e9cc70d1897 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 125:2e9cc70d1897 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 125:2e9cc70d1897 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 125:2e9cc70d1897 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 125:2e9cc70d1897 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 125:2e9cc70d1897 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 125:2e9cc70d1897 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 125:2e9cc70d1897 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 125:2e9cc70d1897 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 125:2e9cc70d1897 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 125:2e9cc70d1897 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 125:2e9cc70d1897 795 uint32_t RESERVED0[1];
AnnaBridge 125:2e9cc70d1897 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 125:2e9cc70d1897 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 125:2e9cc70d1897 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 125:2e9cc70d1897 799 uint32_t RESERVED1[1];
AnnaBridge 125:2e9cc70d1897 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 125:2e9cc70d1897 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 125:2e9cc70d1897 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 125:2e9cc70d1897 803 uint32_t RESERVED2[1];
AnnaBridge 125:2e9cc70d1897 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 125:2e9cc70d1897 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 125:2e9cc70d1897 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 125:2e9cc70d1897 807 } DWT_Type;
AnnaBridge 125:2e9cc70d1897 808
AnnaBridge 125:2e9cc70d1897 809 /* DWT Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 125:2e9cc70d1897 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 125:2e9cc70d1897 812
AnnaBridge 125:2e9cc70d1897 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 125:2e9cc70d1897 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 125:2e9cc70d1897 815
AnnaBridge 125:2e9cc70d1897 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 125:2e9cc70d1897 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 125:2e9cc70d1897 818
AnnaBridge 125:2e9cc70d1897 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 125:2e9cc70d1897 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 125:2e9cc70d1897 821
AnnaBridge 125:2e9cc70d1897 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 125:2e9cc70d1897 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 125:2e9cc70d1897 824
AnnaBridge 125:2e9cc70d1897 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 125:2e9cc70d1897 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 827
AnnaBridge 125:2e9cc70d1897 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 125:2e9cc70d1897 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 830
AnnaBridge 125:2e9cc70d1897 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 125:2e9cc70d1897 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 833
AnnaBridge 125:2e9cc70d1897 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 125:2e9cc70d1897 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 836
AnnaBridge 125:2e9cc70d1897 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 125:2e9cc70d1897 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 839
AnnaBridge 125:2e9cc70d1897 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 125:2e9cc70d1897 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 125:2e9cc70d1897 842
AnnaBridge 125:2e9cc70d1897 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 125:2e9cc70d1897 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 125:2e9cc70d1897 845
AnnaBridge 125:2e9cc70d1897 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 125:2e9cc70d1897 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 125:2e9cc70d1897 848
AnnaBridge 125:2e9cc70d1897 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 125:2e9cc70d1897 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 125:2e9cc70d1897 851
AnnaBridge 125:2e9cc70d1897 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 125:2e9cc70d1897 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 125:2e9cc70d1897 854
AnnaBridge 125:2e9cc70d1897 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 125:2e9cc70d1897 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 125:2e9cc70d1897 857
AnnaBridge 125:2e9cc70d1897 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 125:2e9cc70d1897 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 125:2e9cc70d1897 860
AnnaBridge 125:2e9cc70d1897 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 125:2e9cc70d1897 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 125:2e9cc70d1897 863
AnnaBridge 125:2e9cc70d1897 864 /* DWT CPI Count Register Definitions */
AnnaBridge 125:2e9cc70d1897 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 125:2e9cc70d1897 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 125:2e9cc70d1897 867
AnnaBridge 125:2e9cc70d1897 868 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 125:2e9cc70d1897 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 125:2e9cc70d1897 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 125:2e9cc70d1897 871
AnnaBridge 125:2e9cc70d1897 872 /* DWT Sleep Count Register Definitions */
AnnaBridge 125:2e9cc70d1897 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 125:2e9cc70d1897 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 125:2e9cc70d1897 875
AnnaBridge 125:2e9cc70d1897 876 /* DWT LSU Count Register Definitions */
AnnaBridge 125:2e9cc70d1897 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 125:2e9cc70d1897 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 125:2e9cc70d1897 879
AnnaBridge 125:2e9cc70d1897 880 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 125:2e9cc70d1897 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 125:2e9cc70d1897 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 125:2e9cc70d1897 883
AnnaBridge 125:2e9cc70d1897 884 /* DWT Comparator Mask Register Definitions */
AnnaBridge 125:2e9cc70d1897 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
AnnaBridge 125:2e9cc70d1897 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 125:2e9cc70d1897 887
AnnaBridge 125:2e9cc70d1897 888 /* DWT Comparator Function Register Definitions */
AnnaBridge 125:2e9cc70d1897 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 125:2e9cc70d1897 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 125:2e9cc70d1897 891
AnnaBridge 125:2e9cc70d1897 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 125:2e9cc70d1897 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 125:2e9cc70d1897 894
AnnaBridge 125:2e9cc70d1897 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 125:2e9cc70d1897 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 125:2e9cc70d1897 897
AnnaBridge 125:2e9cc70d1897 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 125:2e9cc70d1897 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 125:2e9cc70d1897 900
AnnaBridge 125:2e9cc70d1897 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 125:2e9cc70d1897 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 125:2e9cc70d1897 903
AnnaBridge 125:2e9cc70d1897 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 125:2e9cc70d1897 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 125:2e9cc70d1897 906
AnnaBridge 125:2e9cc70d1897 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 125:2e9cc70d1897 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 125:2e9cc70d1897 909
AnnaBridge 125:2e9cc70d1897 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 125:2e9cc70d1897 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 125:2e9cc70d1897 912
AnnaBridge 125:2e9cc70d1897 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 125:2e9cc70d1897 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 125:2e9cc70d1897 915
AnnaBridge 125:2e9cc70d1897 916 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 125:2e9cc70d1897 917
AnnaBridge 125:2e9cc70d1897 918
AnnaBridge 125:2e9cc70d1897 919 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 125:2e9cc70d1897 921 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 125:2e9cc70d1897 922 @{
AnnaBridge 125:2e9cc70d1897 923 */
AnnaBridge 125:2e9cc70d1897 924
AnnaBridge 125:2e9cc70d1897 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 125:2e9cc70d1897 926 */
AnnaBridge 125:2e9cc70d1897 927 typedef struct
AnnaBridge 125:2e9cc70d1897 928 {
AnnaBridge 125:2e9cc70d1897 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 125:2e9cc70d1897 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 125:2e9cc70d1897 931 uint32_t RESERVED0[2];
AnnaBridge 125:2e9cc70d1897 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 125:2e9cc70d1897 933 uint32_t RESERVED1[55];
AnnaBridge 125:2e9cc70d1897 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 125:2e9cc70d1897 935 uint32_t RESERVED2[131];
AnnaBridge 125:2e9cc70d1897 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 125:2e9cc70d1897 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 125:2e9cc70d1897 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 125:2e9cc70d1897 939 uint32_t RESERVED3[759];
AnnaBridge 125:2e9cc70d1897 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 125:2e9cc70d1897 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 125:2e9cc70d1897 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 125:2e9cc70d1897 943 uint32_t RESERVED4[1];
AnnaBridge 125:2e9cc70d1897 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 125:2e9cc70d1897 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 125:2e9cc70d1897 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 125:2e9cc70d1897 947 uint32_t RESERVED5[39];
AnnaBridge 125:2e9cc70d1897 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 125:2e9cc70d1897 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 125:2e9cc70d1897 950 uint32_t RESERVED7[8];
AnnaBridge 125:2e9cc70d1897 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 125:2e9cc70d1897 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 125:2e9cc70d1897 953 } TPI_Type;
AnnaBridge 125:2e9cc70d1897 954
AnnaBridge 125:2e9cc70d1897 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 125:2e9cc70d1897 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 125:2e9cc70d1897 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 125:2e9cc70d1897 958
AnnaBridge 125:2e9cc70d1897 959 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 125:2e9cc70d1897 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
AnnaBridge 125:2e9cc70d1897 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 125:2e9cc70d1897 962
AnnaBridge 125:2e9cc70d1897 963 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 125:2e9cc70d1897 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 125:2e9cc70d1897 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 125:2e9cc70d1897 966
AnnaBridge 125:2e9cc70d1897 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
AnnaBridge 125:2e9cc70d1897 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 125:2e9cc70d1897 969
AnnaBridge 125:2e9cc70d1897 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
AnnaBridge 125:2e9cc70d1897 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 125:2e9cc70d1897 972
AnnaBridge 125:2e9cc70d1897 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
AnnaBridge 125:2e9cc70d1897 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 125:2e9cc70d1897 975
AnnaBridge 125:2e9cc70d1897 976 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
AnnaBridge 125:2e9cc70d1897 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 125:2e9cc70d1897 979
AnnaBridge 125:2e9cc70d1897 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
AnnaBridge 125:2e9cc70d1897 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 125:2e9cc70d1897 982
AnnaBridge 125:2e9cc70d1897 983 /* TPI TRIGGER Register Definitions */
AnnaBridge 125:2e9cc70d1897 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 125:2e9cc70d1897 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 125:2e9cc70d1897 986
AnnaBridge 125:2e9cc70d1897 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 125:2e9cc70d1897 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 125:2e9cc70d1897 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 125:2e9cc70d1897 990
AnnaBridge 125:2e9cc70d1897 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 125:2e9cc70d1897 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 125:2e9cc70d1897 993
AnnaBridge 125:2e9cc70d1897 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 125:2e9cc70d1897 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 125:2e9cc70d1897 996
AnnaBridge 125:2e9cc70d1897 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 125:2e9cc70d1897 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 125:2e9cc70d1897 999
AnnaBridge 125:2e9cc70d1897 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 125:2e9cc70d1897 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 125:2e9cc70d1897 1002
AnnaBridge 125:2e9cc70d1897 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 125:2e9cc70d1897 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 125:2e9cc70d1897 1005
AnnaBridge 125:2e9cc70d1897 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 125:2e9cc70d1897 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 125:2e9cc70d1897 1008
AnnaBridge 125:2e9cc70d1897 1009 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 125:2e9cc70d1897 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 125:2e9cc70d1897 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 125:2e9cc70d1897 1012
AnnaBridge 125:2e9cc70d1897 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 125:2e9cc70d1897 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 125:2e9cc70d1897 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 125:2e9cc70d1897 1016
AnnaBridge 125:2e9cc70d1897 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 125:2e9cc70d1897 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 125:2e9cc70d1897 1019
AnnaBridge 125:2e9cc70d1897 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 125:2e9cc70d1897 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 125:2e9cc70d1897 1022
AnnaBridge 125:2e9cc70d1897 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 125:2e9cc70d1897 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 125:2e9cc70d1897 1025
AnnaBridge 125:2e9cc70d1897 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 125:2e9cc70d1897 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 125:2e9cc70d1897 1028
AnnaBridge 125:2e9cc70d1897 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 125:2e9cc70d1897 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 125:2e9cc70d1897 1031
AnnaBridge 125:2e9cc70d1897 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 125:2e9cc70d1897 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 125:2e9cc70d1897 1034
AnnaBridge 125:2e9cc70d1897 1035 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 125:2e9cc70d1897 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 125:2e9cc70d1897 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 125:2e9cc70d1897 1038
AnnaBridge 125:2e9cc70d1897 1039 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
AnnaBridge 125:2e9cc70d1897 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 125:2e9cc70d1897 1042
AnnaBridge 125:2e9cc70d1897 1043 /* TPI DEVID Register Definitions */
AnnaBridge 125:2e9cc70d1897 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 125:2e9cc70d1897 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 125:2e9cc70d1897 1046
AnnaBridge 125:2e9cc70d1897 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 125:2e9cc70d1897 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 125:2e9cc70d1897 1049
AnnaBridge 125:2e9cc70d1897 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 125:2e9cc70d1897 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 125:2e9cc70d1897 1052
AnnaBridge 125:2e9cc70d1897 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 125:2e9cc70d1897 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 125:2e9cc70d1897 1055
AnnaBridge 125:2e9cc70d1897 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 125:2e9cc70d1897 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 125:2e9cc70d1897 1058
AnnaBridge 125:2e9cc70d1897 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 125:2e9cc70d1897 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 125:2e9cc70d1897 1061
AnnaBridge 125:2e9cc70d1897 1062 /* TPI DEVTYPE Register Definitions */
AnnaBridge 125:2e9cc70d1897 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 125:2e9cc70d1897 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 125:2e9cc70d1897 1065
AnnaBridge 125:2e9cc70d1897 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 125:2e9cc70d1897 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 125:2e9cc70d1897 1068
AnnaBridge 125:2e9cc70d1897 1069 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 125:2e9cc70d1897 1070
AnnaBridge 125:2e9cc70d1897 1071
AnnaBridge 125:2e9cc70d1897 1072 #if (__MPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 1073 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 125:2e9cc70d1897 1075 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 125:2e9cc70d1897 1076 @{
AnnaBridge 125:2e9cc70d1897 1077 */
AnnaBridge 125:2e9cc70d1897 1078
AnnaBridge 125:2e9cc70d1897 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 125:2e9cc70d1897 1080 */
AnnaBridge 125:2e9cc70d1897 1081 typedef struct
AnnaBridge 125:2e9cc70d1897 1082 {
AnnaBridge 125:2e9cc70d1897 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 125:2e9cc70d1897 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 125:2e9cc70d1897 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 125:2e9cc70d1897 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 125:2e9cc70d1897 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 125:2e9cc70d1897 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 125:2e9cc70d1897 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 125:2e9cc70d1897 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 125:2e9cc70d1897 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 125:2e9cc70d1897 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 125:2e9cc70d1897 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 125:2e9cc70d1897 1094 } MPU_Type;
AnnaBridge 125:2e9cc70d1897 1095
AnnaBridge 125:2e9cc70d1897 1096 /* MPU Type Register */
AnnaBridge 125:2e9cc70d1897 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 125:2e9cc70d1897 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 125:2e9cc70d1897 1099
AnnaBridge 125:2e9cc70d1897 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 125:2e9cc70d1897 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 125:2e9cc70d1897 1102
AnnaBridge 125:2e9cc70d1897 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 125:2e9cc70d1897 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 125:2e9cc70d1897 1105
AnnaBridge 125:2e9cc70d1897 1106 /* MPU Control Register */
AnnaBridge 125:2e9cc70d1897 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 125:2e9cc70d1897 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 125:2e9cc70d1897 1109
AnnaBridge 125:2e9cc70d1897 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 125:2e9cc70d1897 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 125:2e9cc70d1897 1112
AnnaBridge 125:2e9cc70d1897 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 125:2e9cc70d1897 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 125:2e9cc70d1897 1115
AnnaBridge 125:2e9cc70d1897 1116 /* MPU Region Number Register */
AnnaBridge 125:2e9cc70d1897 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 125:2e9cc70d1897 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 125:2e9cc70d1897 1119
AnnaBridge 125:2e9cc70d1897 1120 /* MPU Region Base Address Register */
AnnaBridge 125:2e9cc70d1897 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
AnnaBridge 125:2e9cc70d1897 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 125:2e9cc70d1897 1123
AnnaBridge 125:2e9cc70d1897 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 125:2e9cc70d1897 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 125:2e9cc70d1897 1126
AnnaBridge 125:2e9cc70d1897 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 125:2e9cc70d1897 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 125:2e9cc70d1897 1129
AnnaBridge 125:2e9cc70d1897 1130 /* MPU Region Attribute and Size Register */
AnnaBridge 125:2e9cc70d1897 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 125:2e9cc70d1897 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 125:2e9cc70d1897 1133
AnnaBridge 125:2e9cc70d1897 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 125:2e9cc70d1897 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 125:2e9cc70d1897 1136
AnnaBridge 125:2e9cc70d1897 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 125:2e9cc70d1897 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 125:2e9cc70d1897 1139
AnnaBridge 125:2e9cc70d1897 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 125:2e9cc70d1897 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 125:2e9cc70d1897 1142
AnnaBridge 125:2e9cc70d1897 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 125:2e9cc70d1897 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 125:2e9cc70d1897 1145
AnnaBridge 125:2e9cc70d1897 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 125:2e9cc70d1897 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 125:2e9cc70d1897 1148
AnnaBridge 125:2e9cc70d1897 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 125:2e9cc70d1897 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 125:2e9cc70d1897 1151
AnnaBridge 125:2e9cc70d1897 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 125:2e9cc70d1897 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 125:2e9cc70d1897 1154
AnnaBridge 125:2e9cc70d1897 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 125:2e9cc70d1897 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 125:2e9cc70d1897 1157
AnnaBridge 125:2e9cc70d1897 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 125:2e9cc70d1897 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 125:2e9cc70d1897 1160
AnnaBridge 125:2e9cc70d1897 1161 /*@} end of group CMSIS_MPU */
AnnaBridge 125:2e9cc70d1897 1162 #endif
AnnaBridge 125:2e9cc70d1897 1163
AnnaBridge 125:2e9cc70d1897 1164
AnnaBridge 125:2e9cc70d1897 1165 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 125:2e9cc70d1897 1167 \brief Type definitions for the Core Debug Registers
AnnaBridge 125:2e9cc70d1897 1168 @{
AnnaBridge 125:2e9cc70d1897 1169 */
AnnaBridge 125:2e9cc70d1897 1170
AnnaBridge 125:2e9cc70d1897 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 125:2e9cc70d1897 1172 */
AnnaBridge 125:2e9cc70d1897 1173 typedef struct
AnnaBridge 125:2e9cc70d1897 1174 {
AnnaBridge 125:2e9cc70d1897 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 125:2e9cc70d1897 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 125:2e9cc70d1897 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 125:2e9cc70d1897 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 125:2e9cc70d1897 1179 } CoreDebug_Type;
AnnaBridge 125:2e9cc70d1897 1180
AnnaBridge 125:2e9cc70d1897 1181 /* Debug Halting Control and Status Register */
AnnaBridge 125:2e9cc70d1897 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 125:2e9cc70d1897 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 125:2e9cc70d1897 1184
AnnaBridge 125:2e9cc70d1897 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 125:2e9cc70d1897 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 125:2e9cc70d1897 1187
AnnaBridge 125:2e9cc70d1897 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 125:2e9cc70d1897 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 125:2e9cc70d1897 1190
AnnaBridge 125:2e9cc70d1897 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 125:2e9cc70d1897 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 125:2e9cc70d1897 1193
AnnaBridge 125:2e9cc70d1897 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 125:2e9cc70d1897 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 125:2e9cc70d1897 1196
AnnaBridge 125:2e9cc70d1897 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 125:2e9cc70d1897 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 125:2e9cc70d1897 1199
AnnaBridge 125:2e9cc70d1897 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 125:2e9cc70d1897 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 125:2e9cc70d1897 1202
AnnaBridge 125:2e9cc70d1897 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 125:2e9cc70d1897 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 125:2e9cc70d1897 1205
AnnaBridge 125:2e9cc70d1897 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 125:2e9cc70d1897 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 125:2e9cc70d1897 1208
AnnaBridge 125:2e9cc70d1897 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 125:2e9cc70d1897 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 125:2e9cc70d1897 1211
AnnaBridge 125:2e9cc70d1897 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 125:2e9cc70d1897 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 125:2e9cc70d1897 1214
AnnaBridge 125:2e9cc70d1897 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 125:2e9cc70d1897 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 125:2e9cc70d1897 1217
AnnaBridge 125:2e9cc70d1897 1218 /* Debug Core Register Selector Register */
AnnaBridge 125:2e9cc70d1897 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 125:2e9cc70d1897 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 125:2e9cc70d1897 1221
AnnaBridge 125:2e9cc70d1897 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 125:2e9cc70d1897 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 125:2e9cc70d1897 1224
AnnaBridge 125:2e9cc70d1897 1225 /* Debug Exception and Monitor Control Register */
AnnaBridge 125:2e9cc70d1897 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 125:2e9cc70d1897 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 125:2e9cc70d1897 1228
AnnaBridge 125:2e9cc70d1897 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 125:2e9cc70d1897 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 125:2e9cc70d1897 1231
AnnaBridge 125:2e9cc70d1897 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 125:2e9cc70d1897 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 125:2e9cc70d1897 1234
AnnaBridge 125:2e9cc70d1897 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 125:2e9cc70d1897 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 125:2e9cc70d1897 1237
AnnaBridge 125:2e9cc70d1897 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 125:2e9cc70d1897 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 125:2e9cc70d1897 1240
AnnaBridge 125:2e9cc70d1897 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 125:2e9cc70d1897 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 125:2e9cc70d1897 1243
AnnaBridge 125:2e9cc70d1897 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 125:2e9cc70d1897 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 125:2e9cc70d1897 1246
AnnaBridge 125:2e9cc70d1897 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 125:2e9cc70d1897 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 125:2e9cc70d1897 1249
AnnaBridge 125:2e9cc70d1897 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 125:2e9cc70d1897 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 125:2e9cc70d1897 1252
AnnaBridge 125:2e9cc70d1897 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 125:2e9cc70d1897 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 125:2e9cc70d1897 1255
AnnaBridge 125:2e9cc70d1897 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 125:2e9cc70d1897 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 125:2e9cc70d1897 1258
AnnaBridge 125:2e9cc70d1897 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 125:2e9cc70d1897 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 125:2e9cc70d1897 1261
AnnaBridge 125:2e9cc70d1897 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 125:2e9cc70d1897 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 125:2e9cc70d1897 1264
AnnaBridge 125:2e9cc70d1897 1265 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 125:2e9cc70d1897 1266
AnnaBridge 125:2e9cc70d1897 1267
AnnaBridge 125:2e9cc70d1897 1268 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 1269 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 125:2e9cc70d1897 1270 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 125:2e9cc70d1897 1271 @{
AnnaBridge 125:2e9cc70d1897 1272 */
AnnaBridge 125:2e9cc70d1897 1273
AnnaBridge 125:2e9cc70d1897 1274 /* Memory mapping of Cortex-M3 Hardware */
AnnaBridge 125:2e9cc70d1897 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 125:2e9cc70d1897 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 125:2e9cc70d1897 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 125:2e9cc70d1897 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 125:2e9cc70d1897 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 125:2e9cc70d1897 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 125:2e9cc70d1897 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 125:2e9cc70d1897 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 125:2e9cc70d1897 1283
AnnaBridge 125:2e9cc70d1897 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 125:2e9cc70d1897 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 125:2e9cc70d1897 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 125:2e9cc70d1897 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 125:2e9cc70d1897 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 125:2e9cc70d1897 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 125:2e9cc70d1897 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 125:2e9cc70d1897 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 125:2e9cc70d1897 1292
AnnaBridge 125:2e9cc70d1897 1293 #if (__MPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 125:2e9cc70d1897 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 125:2e9cc70d1897 1296 #endif
AnnaBridge 125:2e9cc70d1897 1297
AnnaBridge 125:2e9cc70d1897 1298 /*@} */
AnnaBridge 125:2e9cc70d1897 1299
AnnaBridge 125:2e9cc70d1897 1300
AnnaBridge 125:2e9cc70d1897 1301
AnnaBridge 125:2e9cc70d1897 1302 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 1303 * Hardware Abstraction Layer
AnnaBridge 125:2e9cc70d1897 1304 Core Function Interface contains:
AnnaBridge 125:2e9cc70d1897 1305 - Core NVIC Functions
AnnaBridge 125:2e9cc70d1897 1306 - Core SysTick Functions
AnnaBridge 125:2e9cc70d1897 1307 - Core Debug Functions
AnnaBridge 125:2e9cc70d1897 1308 - Core Register Access Functions
AnnaBridge 125:2e9cc70d1897 1309 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 125:2e9cc70d1897 1311 */
AnnaBridge 125:2e9cc70d1897 1312
AnnaBridge 125:2e9cc70d1897 1313
AnnaBridge 125:2e9cc70d1897 1314
AnnaBridge 125:2e9cc70d1897 1315 /* ########################## NVIC functions #################################### */
AnnaBridge 125:2e9cc70d1897 1316 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 125:2e9cc70d1897 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 125:2e9cc70d1897 1319 @{
AnnaBridge 125:2e9cc70d1897 1320 */
AnnaBridge 125:2e9cc70d1897 1321
AnnaBridge 125:2e9cc70d1897 1322 /** \brief Set Priority Grouping
AnnaBridge 125:2e9cc70d1897 1323
AnnaBridge 125:2e9cc70d1897 1324 The function sets the priority grouping field using the required unlock sequence.
AnnaBridge 125:2e9cc70d1897 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 125:2e9cc70d1897 1326 Only values from 0..7 are used.
AnnaBridge 125:2e9cc70d1897 1327 In case of a conflict between priority grouping and available
AnnaBridge 125:2e9cc70d1897 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 125:2e9cc70d1897 1329
AnnaBridge 125:2e9cc70d1897 1330 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 125:2e9cc70d1897 1331 */
AnnaBridge 125:2e9cc70d1897 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 125:2e9cc70d1897 1333 {
AnnaBridge 125:2e9cc70d1897 1334 uint32_t reg_value;
AnnaBridge 125:2e9cc70d1897 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 125:2e9cc70d1897 1336
AnnaBridge 125:2e9cc70d1897 1337 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 125:2e9cc70d1897 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 125:2e9cc70d1897 1339 reg_value = (reg_value |
AnnaBridge 125:2e9cc70d1897 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 125:2e9cc70d1897 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
AnnaBridge 125:2e9cc70d1897 1342 SCB->AIRCR = reg_value;
AnnaBridge 125:2e9cc70d1897 1343 }
AnnaBridge 125:2e9cc70d1897 1344
AnnaBridge 125:2e9cc70d1897 1345
AnnaBridge 125:2e9cc70d1897 1346 /** \brief Get Priority Grouping
AnnaBridge 125:2e9cc70d1897 1347
AnnaBridge 125:2e9cc70d1897 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 125:2e9cc70d1897 1349
AnnaBridge 125:2e9cc70d1897 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 125:2e9cc70d1897 1351 */
AnnaBridge 125:2e9cc70d1897 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
AnnaBridge 125:2e9cc70d1897 1353 {
AnnaBridge 125:2e9cc70d1897 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 125:2e9cc70d1897 1355 }
AnnaBridge 125:2e9cc70d1897 1356
AnnaBridge 125:2e9cc70d1897 1357
AnnaBridge 125:2e9cc70d1897 1358 /** \brief Enable External Interrupt
AnnaBridge 125:2e9cc70d1897 1359
AnnaBridge 125:2e9cc70d1897 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 125:2e9cc70d1897 1361
AnnaBridge 125:2e9cc70d1897 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 1363 */
AnnaBridge 125:2e9cc70d1897 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1365 {
AnnaBridge 125:2e9cc70d1897 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 1367 }
AnnaBridge 125:2e9cc70d1897 1368
AnnaBridge 125:2e9cc70d1897 1369
AnnaBridge 125:2e9cc70d1897 1370 /** \brief Disable External Interrupt
AnnaBridge 125:2e9cc70d1897 1371
AnnaBridge 125:2e9cc70d1897 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 125:2e9cc70d1897 1373
AnnaBridge 125:2e9cc70d1897 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 1375 */
AnnaBridge 125:2e9cc70d1897 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1377 {
AnnaBridge 125:2e9cc70d1897 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1379 __DSB();
<> 131:faff56e089b2 1380 __ISB();
AnnaBridge 125:2e9cc70d1897 1381 }
AnnaBridge 125:2e9cc70d1897 1382
AnnaBridge 125:2e9cc70d1897 1383
AnnaBridge 125:2e9cc70d1897 1384 /** \brief Get Pending Interrupt
AnnaBridge 125:2e9cc70d1897 1385
AnnaBridge 125:2e9cc70d1897 1386 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 125:2e9cc70d1897 1387 for the specified interrupt.
AnnaBridge 125:2e9cc70d1897 1388
AnnaBridge 125:2e9cc70d1897 1389 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 1390
AnnaBridge 125:2e9cc70d1897 1391 \return 0 Interrupt status is not pending.
AnnaBridge 125:2e9cc70d1897 1392 \return 1 Interrupt status is pending.
AnnaBridge 125:2e9cc70d1897 1393 */
AnnaBridge 125:2e9cc70d1897 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1395 {
AnnaBridge 125:2e9cc70d1897 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 125:2e9cc70d1897 1397 }
AnnaBridge 125:2e9cc70d1897 1398
AnnaBridge 125:2e9cc70d1897 1399
AnnaBridge 125:2e9cc70d1897 1400 /** \brief Set Pending Interrupt
AnnaBridge 125:2e9cc70d1897 1401
AnnaBridge 125:2e9cc70d1897 1402 The function sets the pending bit of an external interrupt.
AnnaBridge 125:2e9cc70d1897 1403
AnnaBridge 125:2e9cc70d1897 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 1405 */
AnnaBridge 125:2e9cc70d1897 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1407 {
AnnaBridge 125:2e9cc70d1897 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 1409 }
AnnaBridge 125:2e9cc70d1897 1410
AnnaBridge 125:2e9cc70d1897 1411
AnnaBridge 125:2e9cc70d1897 1412 /** \brief Clear Pending Interrupt
AnnaBridge 125:2e9cc70d1897 1413
AnnaBridge 125:2e9cc70d1897 1414 The function clears the pending bit of an external interrupt.
AnnaBridge 125:2e9cc70d1897 1415
AnnaBridge 125:2e9cc70d1897 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 1417 */
AnnaBridge 125:2e9cc70d1897 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1419 {
AnnaBridge 125:2e9cc70d1897 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 1421 }
AnnaBridge 125:2e9cc70d1897 1422
AnnaBridge 125:2e9cc70d1897 1423
AnnaBridge 125:2e9cc70d1897 1424 /** \brief Get Active Interrupt
AnnaBridge 125:2e9cc70d1897 1425
AnnaBridge 125:2e9cc70d1897 1426 The function reads the active register in NVIC and returns the active bit.
AnnaBridge 125:2e9cc70d1897 1427
AnnaBridge 125:2e9cc70d1897 1428 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 1429
AnnaBridge 125:2e9cc70d1897 1430 \return 0 Interrupt status is not active.
AnnaBridge 125:2e9cc70d1897 1431 \return 1 Interrupt status is active.
AnnaBridge 125:2e9cc70d1897 1432 */
AnnaBridge 125:2e9cc70d1897 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1434 {
AnnaBridge 125:2e9cc70d1897 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 125:2e9cc70d1897 1436 }
AnnaBridge 125:2e9cc70d1897 1437
AnnaBridge 125:2e9cc70d1897 1438
AnnaBridge 125:2e9cc70d1897 1439 /** \brief Set Interrupt Priority
AnnaBridge 125:2e9cc70d1897 1440
AnnaBridge 125:2e9cc70d1897 1441 The function sets the priority of an interrupt.
AnnaBridge 125:2e9cc70d1897 1442
AnnaBridge 125:2e9cc70d1897 1443 \note The priority cannot be set for every core interrupt.
AnnaBridge 125:2e9cc70d1897 1444
AnnaBridge 125:2e9cc70d1897 1445 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 1446 \param [in] priority Priority to set.
AnnaBridge 125:2e9cc70d1897 1447 */
AnnaBridge 125:2e9cc70d1897 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 125:2e9cc70d1897 1449 {
AnnaBridge 125:2e9cc70d1897 1450 if((int32_t)IRQn < 0) {
AnnaBridge 125:2e9cc70d1897 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 125:2e9cc70d1897 1452 }
AnnaBridge 125:2e9cc70d1897 1453 else {
AnnaBridge 125:2e9cc70d1897 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 125:2e9cc70d1897 1455 }
AnnaBridge 125:2e9cc70d1897 1456 }
AnnaBridge 125:2e9cc70d1897 1457
AnnaBridge 125:2e9cc70d1897 1458
AnnaBridge 125:2e9cc70d1897 1459 /** \brief Get Interrupt Priority
AnnaBridge 125:2e9cc70d1897 1460
AnnaBridge 125:2e9cc70d1897 1461 The function reads the priority of an interrupt. The interrupt
AnnaBridge 125:2e9cc70d1897 1462 number can be positive to specify an external (device specific)
AnnaBridge 125:2e9cc70d1897 1463 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 125:2e9cc70d1897 1464
AnnaBridge 125:2e9cc70d1897 1465
AnnaBridge 125:2e9cc70d1897 1466 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 125:2e9cc70d1897 1468 priority bits of the microcontroller.
AnnaBridge 125:2e9cc70d1897 1469 */
AnnaBridge 125:2e9cc70d1897 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 1471 {
AnnaBridge 125:2e9cc70d1897 1472
AnnaBridge 125:2e9cc70d1897 1473 if((int32_t)IRQn < 0) {
AnnaBridge 125:2e9cc70d1897 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 125:2e9cc70d1897 1475 }
AnnaBridge 125:2e9cc70d1897 1476 else {
AnnaBridge 125:2e9cc70d1897 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 125:2e9cc70d1897 1478 }
AnnaBridge 125:2e9cc70d1897 1479 }
AnnaBridge 125:2e9cc70d1897 1480
AnnaBridge 125:2e9cc70d1897 1481
AnnaBridge 125:2e9cc70d1897 1482 /** \brief Encode Priority
AnnaBridge 125:2e9cc70d1897 1483
AnnaBridge 125:2e9cc70d1897 1484 The function encodes the priority for an interrupt with the given priority group,
AnnaBridge 125:2e9cc70d1897 1485 preemptive priority value, and subpriority value.
AnnaBridge 125:2e9cc70d1897 1486 In case of a conflict between priority grouping and available
AnnaBridge 125:2e9cc70d1897 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 125:2e9cc70d1897 1488
AnnaBridge 125:2e9cc70d1897 1489 \param [in] PriorityGroup Used priority group.
AnnaBridge 125:2e9cc70d1897 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 125:2e9cc70d1897 1491 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 125:2e9cc70d1897 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 125:2e9cc70d1897 1493 */
AnnaBridge 125:2e9cc70d1897 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 125:2e9cc70d1897 1495 {
AnnaBridge 125:2e9cc70d1897 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 125:2e9cc70d1897 1497 uint32_t PreemptPriorityBits;
AnnaBridge 125:2e9cc70d1897 1498 uint32_t SubPriorityBits;
AnnaBridge 125:2e9cc70d1897 1499
AnnaBridge 125:2e9cc70d1897 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 125:2e9cc70d1897 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 125:2e9cc70d1897 1502
AnnaBridge 125:2e9cc70d1897 1503 return (
AnnaBridge 125:2e9cc70d1897 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 125:2e9cc70d1897 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 125:2e9cc70d1897 1506 );
AnnaBridge 125:2e9cc70d1897 1507 }
AnnaBridge 125:2e9cc70d1897 1508
AnnaBridge 125:2e9cc70d1897 1509
AnnaBridge 125:2e9cc70d1897 1510 /** \brief Decode Priority
AnnaBridge 125:2e9cc70d1897 1511
AnnaBridge 125:2e9cc70d1897 1512 The function decodes an interrupt priority value with a given priority group to
AnnaBridge 125:2e9cc70d1897 1513 preemptive priority value and subpriority value.
AnnaBridge 125:2e9cc70d1897 1514 In case of a conflict between priority grouping and available
AnnaBridge 125:2e9cc70d1897 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 125:2e9cc70d1897 1516
AnnaBridge 125:2e9cc70d1897 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 125:2e9cc70d1897 1518 \param [in] PriorityGroup Used priority group.
AnnaBridge 125:2e9cc70d1897 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 125:2e9cc70d1897 1520 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 125:2e9cc70d1897 1521 */
AnnaBridge 125:2e9cc70d1897 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
AnnaBridge 125:2e9cc70d1897 1523 {
AnnaBridge 125:2e9cc70d1897 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 125:2e9cc70d1897 1525 uint32_t PreemptPriorityBits;
AnnaBridge 125:2e9cc70d1897 1526 uint32_t SubPriorityBits;
AnnaBridge 125:2e9cc70d1897 1527
AnnaBridge 125:2e9cc70d1897 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 125:2e9cc70d1897 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 125:2e9cc70d1897 1530
AnnaBridge 125:2e9cc70d1897 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 125:2e9cc70d1897 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 125:2e9cc70d1897 1533 }
AnnaBridge 125:2e9cc70d1897 1534
AnnaBridge 125:2e9cc70d1897 1535
AnnaBridge 125:2e9cc70d1897 1536 /** \brief System Reset
AnnaBridge 125:2e9cc70d1897 1537
AnnaBridge 125:2e9cc70d1897 1538 The function initiates a system reset request to reset the MCU.
AnnaBridge 125:2e9cc70d1897 1539 */
AnnaBridge 125:2e9cc70d1897 1540 __STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge 125:2e9cc70d1897 1541 {
AnnaBridge 125:2e9cc70d1897 1542 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 125:2e9cc70d1897 1543 buffered write are completed before reset */
AnnaBridge 125:2e9cc70d1897 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 125:2e9cc70d1897 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 125:2e9cc70d1897 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 125:2e9cc70d1897 1547 __DSB(); /* Ensure completion of memory access */
AnnaBridge 125:2e9cc70d1897 1548 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 125:2e9cc70d1897 1549 }
AnnaBridge 125:2e9cc70d1897 1550
AnnaBridge 125:2e9cc70d1897 1551 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 125:2e9cc70d1897 1552
AnnaBridge 125:2e9cc70d1897 1553
AnnaBridge 125:2e9cc70d1897 1554
AnnaBridge 125:2e9cc70d1897 1555 /* ################################## SysTick function ############################################ */
AnnaBridge 125:2e9cc70d1897 1556 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 125:2e9cc70d1897 1558 \brief Functions that configure the System.
AnnaBridge 125:2e9cc70d1897 1559 @{
AnnaBridge 125:2e9cc70d1897 1560 */
AnnaBridge 125:2e9cc70d1897 1561
AnnaBridge 125:2e9cc70d1897 1562 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 125:2e9cc70d1897 1563
AnnaBridge 125:2e9cc70d1897 1564 /** \brief System Tick Configuration
AnnaBridge 125:2e9cc70d1897 1565
AnnaBridge 125:2e9cc70d1897 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 125:2e9cc70d1897 1567 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 125:2e9cc70d1897 1568
AnnaBridge 125:2e9cc70d1897 1569 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 125:2e9cc70d1897 1570
AnnaBridge 125:2e9cc70d1897 1571 \return 0 Function succeeded.
AnnaBridge 125:2e9cc70d1897 1572 \return 1 Function failed.
AnnaBridge 125:2e9cc70d1897 1573
AnnaBridge 125:2e9cc70d1897 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 125:2e9cc70d1897 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 125:2e9cc70d1897 1576 must contain a vendor-specific implementation of this function.
AnnaBridge 125:2e9cc70d1897 1577
AnnaBridge 125:2e9cc70d1897 1578 */
AnnaBridge 125:2e9cc70d1897 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 125:2e9cc70d1897 1580 {
AnnaBridge 125:2e9cc70d1897 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge 125:2e9cc70d1897 1582
AnnaBridge 125:2e9cc70d1897 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 125:2e9cc70d1897 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 125:2e9cc70d1897 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 125:2e9cc70d1897 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 125:2e9cc70d1897 1587 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 125:2e9cc70d1897 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 125:2e9cc70d1897 1589 return (0UL); /* Function successful */
AnnaBridge 125:2e9cc70d1897 1590 }
AnnaBridge 125:2e9cc70d1897 1591
AnnaBridge 125:2e9cc70d1897 1592 #endif
AnnaBridge 125:2e9cc70d1897 1593
AnnaBridge 125:2e9cc70d1897 1594 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 125:2e9cc70d1897 1595
AnnaBridge 125:2e9cc70d1897 1596
AnnaBridge 125:2e9cc70d1897 1597
AnnaBridge 125:2e9cc70d1897 1598 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 125:2e9cc70d1897 1599 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 125:2e9cc70d1897 1601 \brief Functions that access the ITM debug interface.
AnnaBridge 125:2e9cc70d1897 1602 @{
AnnaBridge 125:2e9cc70d1897 1603 */
AnnaBridge 125:2e9cc70d1897 1604
AnnaBridge 125:2e9cc70d1897 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 125:2e9cc70d1897 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 125:2e9cc70d1897 1607
AnnaBridge 125:2e9cc70d1897 1608
AnnaBridge 125:2e9cc70d1897 1609 /** \brief ITM Send Character
AnnaBridge 125:2e9cc70d1897 1610
AnnaBridge 125:2e9cc70d1897 1611 The function transmits a character via the ITM channel 0, and
AnnaBridge 125:2e9cc70d1897 1612 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 125:2e9cc70d1897 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 125:2e9cc70d1897 1614
AnnaBridge 125:2e9cc70d1897 1615 \param [in] ch Character to transmit.
AnnaBridge 125:2e9cc70d1897 1616
AnnaBridge 125:2e9cc70d1897 1617 \returns Character to transmit.
AnnaBridge 125:2e9cc70d1897 1618 */
AnnaBridge 125:2e9cc70d1897 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 125:2e9cc70d1897 1620 {
AnnaBridge 125:2e9cc70d1897 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 125:2e9cc70d1897 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 125:2e9cc70d1897 1623 {
AnnaBridge 125:2e9cc70d1897 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
AnnaBridge 125:2e9cc70d1897 1625 ITM->PORT[0].u8 = (uint8_t)ch;
AnnaBridge 125:2e9cc70d1897 1626 }
AnnaBridge 125:2e9cc70d1897 1627 return (ch);
AnnaBridge 125:2e9cc70d1897 1628 }
AnnaBridge 125:2e9cc70d1897 1629
AnnaBridge 125:2e9cc70d1897 1630
AnnaBridge 125:2e9cc70d1897 1631 /** \brief ITM Receive Character
AnnaBridge 125:2e9cc70d1897 1632
AnnaBridge 125:2e9cc70d1897 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 125:2e9cc70d1897 1634
AnnaBridge 125:2e9cc70d1897 1635 \return Received character.
AnnaBridge 125:2e9cc70d1897 1636 \return -1 No character pending.
AnnaBridge 125:2e9cc70d1897 1637 */
AnnaBridge 125:2e9cc70d1897 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
AnnaBridge 125:2e9cc70d1897 1639 int32_t ch = -1; /* no character available */
AnnaBridge 125:2e9cc70d1897 1640
AnnaBridge 125:2e9cc70d1897 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
AnnaBridge 125:2e9cc70d1897 1642 ch = ITM_RxBuffer;
AnnaBridge 125:2e9cc70d1897 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 125:2e9cc70d1897 1644 }
AnnaBridge 125:2e9cc70d1897 1645
AnnaBridge 125:2e9cc70d1897 1646 return (ch);
AnnaBridge 125:2e9cc70d1897 1647 }
AnnaBridge 125:2e9cc70d1897 1648
AnnaBridge 125:2e9cc70d1897 1649
AnnaBridge 125:2e9cc70d1897 1650 /** \brief ITM Check Character
AnnaBridge 125:2e9cc70d1897 1651
AnnaBridge 125:2e9cc70d1897 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 125:2e9cc70d1897 1653
AnnaBridge 125:2e9cc70d1897 1654 \return 0 No character available.
AnnaBridge 125:2e9cc70d1897 1655 \return 1 Character available.
AnnaBridge 125:2e9cc70d1897 1656 */
AnnaBridge 125:2e9cc70d1897 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
AnnaBridge 125:2e9cc70d1897 1658
AnnaBridge 125:2e9cc70d1897 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
AnnaBridge 125:2e9cc70d1897 1660 return (0); /* no character available */
AnnaBridge 125:2e9cc70d1897 1661 } else {
AnnaBridge 125:2e9cc70d1897 1662 return (1); /* character available */
AnnaBridge 125:2e9cc70d1897 1663 }
AnnaBridge 125:2e9cc70d1897 1664 }
AnnaBridge 125:2e9cc70d1897 1665
AnnaBridge 125:2e9cc70d1897 1666 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 125:2e9cc70d1897 1667
AnnaBridge 125:2e9cc70d1897 1668
AnnaBridge 125:2e9cc70d1897 1669
AnnaBridge 125:2e9cc70d1897 1670
AnnaBridge 125:2e9cc70d1897 1671 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 1672 }
AnnaBridge 125:2e9cc70d1897 1673 #endif
AnnaBridge 125:2e9cc70d1897 1674
AnnaBridge 125:2e9cc70d1897 1675 #endif /* __CORE_SC300_H_DEPENDANT */
AnnaBridge 125:2e9cc70d1897 1676
AnnaBridge 125:2e9cc70d1897 1677 #endif /* __CMSIS_GENERIC */