mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620HSP/core_cm0.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 /**************************************************************************//**
AnnaBridge 125:2e9cc70d1897 2 * @file core_cm0.h
AnnaBridge 125:2e9cc70d1897 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 125:2e9cc70d1897 4 * @version V4.10
AnnaBridge 125:2e9cc70d1897 5 * @date 18. March 2015
AnnaBridge 125:2e9cc70d1897 6 *
AnnaBridge 125:2e9cc70d1897 7 * @note
AnnaBridge 125:2e9cc70d1897 8 *
AnnaBridge 125:2e9cc70d1897 9 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 125:2e9cc70d1897 11
AnnaBridge 125:2e9cc70d1897 12 All rights reserved.
AnnaBridge 125:2e9cc70d1897 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 125:2e9cc70d1897 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 125:2e9cc70d1897 15 - Redistributions of source code must retain the above copyright
AnnaBridge 125:2e9cc70d1897 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 125:2e9cc70d1897 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 125:2e9cc70d1897 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 125:2e9cc70d1897 19 documentation and/or other materials provided with the distribution.
AnnaBridge 125:2e9cc70d1897 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 125:2e9cc70d1897 21 to endorse or promote products derived from this software without
AnnaBridge 125:2e9cc70d1897 22 specific prior written permission.
AnnaBridge 125:2e9cc70d1897 23 *
AnnaBridge 125:2e9cc70d1897 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 125:2e9cc70d1897 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 125:2e9cc70d1897 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 125:2e9cc70d1897 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 125:2e9cc70d1897 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 125:2e9cc70d1897 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 125:2e9cc70d1897 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 125:2e9cc70d1897 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 125:2e9cc70d1897 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 125:2e9cc70d1897 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 125:2e9cc70d1897 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 125:2e9cc70d1897 35 ---------------------------------------------------------------------------*/
AnnaBridge 125:2e9cc70d1897 36
AnnaBridge 125:2e9cc70d1897 37
AnnaBridge 125:2e9cc70d1897 38 #if defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 125:2e9cc70d1897 40 #endif
AnnaBridge 125:2e9cc70d1897 41
AnnaBridge 125:2e9cc70d1897 42 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 125:2e9cc70d1897 43 #define __CORE_CM0_H_GENERIC
AnnaBridge 125:2e9cc70d1897 44
AnnaBridge 125:2e9cc70d1897 45 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 46 extern "C" {
AnnaBridge 125:2e9cc70d1897 47 #endif
AnnaBridge 125:2e9cc70d1897 48
AnnaBridge 125:2e9cc70d1897 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 125:2e9cc70d1897 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 125:2e9cc70d1897 51
AnnaBridge 125:2e9cc70d1897 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 125:2e9cc70d1897 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 125:2e9cc70d1897 54
AnnaBridge 125:2e9cc70d1897 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 125:2e9cc70d1897 56 Unions are used for effective representation of core registers.
AnnaBridge 125:2e9cc70d1897 57
AnnaBridge 125:2e9cc70d1897 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 125:2e9cc70d1897 59 Function-like macros are used to allow more efficient code.
AnnaBridge 125:2e9cc70d1897 60 */
AnnaBridge 125:2e9cc70d1897 61
AnnaBridge 125:2e9cc70d1897 62
AnnaBridge 125:2e9cc70d1897 63 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 64 * CMSIS definitions
AnnaBridge 125:2e9cc70d1897 65 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 66 /** \ingroup Cortex_M0
AnnaBridge 125:2e9cc70d1897 67 @{
AnnaBridge 125:2e9cc70d1897 68 */
AnnaBridge 125:2e9cc70d1897 69
AnnaBridge 125:2e9cc70d1897 70 /* CMSIS CM0 definitions */
AnnaBridge 125:2e9cc70d1897 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 125:2e9cc70d1897 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 125:2e9cc70d1897 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 125:2e9cc70d1897 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 125:2e9cc70d1897 75
AnnaBridge 125:2e9cc70d1897 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
AnnaBridge 125:2e9cc70d1897 77
AnnaBridge 125:2e9cc70d1897 78
AnnaBridge 125:2e9cc70d1897 79 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 82 #define __STATIC_INLINE static __inline
AnnaBridge 125:2e9cc70d1897 83
AnnaBridge 125:2e9cc70d1897 84 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 87 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 88
AnnaBridge 125:2e9cc70d1897 89 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 125:2e9cc70d1897 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 125:2e9cc70d1897 92 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 93
AnnaBridge 125:2e9cc70d1897 94 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 125:2e9cc70d1897 96 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 97
AnnaBridge 125:2e9cc70d1897 98 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 101 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 102
AnnaBridge 125:2e9cc70d1897 103 #elif defined ( __CSMC__ )
AnnaBridge 125:2e9cc70d1897 104 #define __packed
AnnaBridge 125:2e9cc70d1897 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 125:2e9cc70d1897 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 125:2e9cc70d1897 107 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 108
AnnaBridge 125:2e9cc70d1897 109 #endif
AnnaBridge 125:2e9cc70d1897 110
AnnaBridge 125:2e9cc70d1897 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 125:2e9cc70d1897 112 This core does not support an FPU at all
AnnaBridge 125:2e9cc70d1897 113 */
AnnaBridge 125:2e9cc70d1897 114 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 115
AnnaBridge 125:2e9cc70d1897 116 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 117 #if defined __TARGET_FPU_VFP
AnnaBridge 125:2e9cc70d1897 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 119 #endif
AnnaBridge 125:2e9cc70d1897 120
AnnaBridge 125:2e9cc70d1897 121 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 125:2e9cc70d1897 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 124 #endif
AnnaBridge 125:2e9cc70d1897 125
AnnaBridge 125:2e9cc70d1897 126 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 127 #if defined __ARMVFP__
AnnaBridge 125:2e9cc70d1897 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 129 #endif
AnnaBridge 125:2e9cc70d1897 130
AnnaBridge 125:2e9cc70d1897 131 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 125:2e9cc70d1897 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 134 #endif
AnnaBridge 125:2e9cc70d1897 135
AnnaBridge 125:2e9cc70d1897 136 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 137 #if defined __FPU_VFP__
AnnaBridge 125:2e9cc70d1897 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 139 #endif
AnnaBridge 125:2e9cc70d1897 140
AnnaBridge 125:2e9cc70d1897 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 125:2e9cc70d1897 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 125:2e9cc70d1897 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 144 #endif
AnnaBridge 125:2e9cc70d1897 145 #endif
AnnaBridge 125:2e9cc70d1897 146
AnnaBridge 125:2e9cc70d1897 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 125:2e9cc70d1897 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 125:2e9cc70d1897 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 125:2e9cc70d1897 150
AnnaBridge 125:2e9cc70d1897 151 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 152 }
AnnaBridge 125:2e9cc70d1897 153 #endif
AnnaBridge 125:2e9cc70d1897 154
AnnaBridge 125:2e9cc70d1897 155 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 125:2e9cc70d1897 156
AnnaBridge 125:2e9cc70d1897 157 #ifndef __CMSIS_GENERIC
AnnaBridge 125:2e9cc70d1897 158
AnnaBridge 125:2e9cc70d1897 159 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 160 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 161
AnnaBridge 125:2e9cc70d1897 162 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 163 extern "C" {
AnnaBridge 125:2e9cc70d1897 164 #endif
AnnaBridge 125:2e9cc70d1897 165
AnnaBridge 125:2e9cc70d1897 166 /* check device defines and use defaults */
AnnaBridge 125:2e9cc70d1897 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 125:2e9cc70d1897 168 #ifndef __CM0_REV
AnnaBridge 125:2e9cc70d1897 169 #define __CM0_REV 0x0000
AnnaBridge 125:2e9cc70d1897 170 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 171 #endif
AnnaBridge 125:2e9cc70d1897 172
AnnaBridge 125:2e9cc70d1897 173 #ifndef __NVIC_PRIO_BITS
AnnaBridge 125:2e9cc70d1897 174 #define __NVIC_PRIO_BITS 2
AnnaBridge 125:2e9cc70d1897 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 176 #endif
AnnaBridge 125:2e9cc70d1897 177
AnnaBridge 125:2e9cc70d1897 178 #ifndef __Vendor_SysTickConfig
AnnaBridge 125:2e9cc70d1897 179 #define __Vendor_SysTickConfig 0
AnnaBridge 125:2e9cc70d1897 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 181 #endif
AnnaBridge 125:2e9cc70d1897 182 #endif
AnnaBridge 125:2e9cc70d1897 183
AnnaBridge 125:2e9cc70d1897 184 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 125:2e9cc70d1897 185 /**
AnnaBridge 125:2e9cc70d1897 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 125:2e9cc70d1897 187
AnnaBridge 125:2e9cc70d1897 188 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 125:2e9cc70d1897 189 \li to specify the access to peripheral variables.
AnnaBridge 125:2e9cc70d1897 190 \li for automatic generation of peripheral register debug information.
AnnaBridge 125:2e9cc70d1897 191 */
AnnaBridge 125:2e9cc70d1897 192 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 193 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 194 #else
AnnaBridge 125:2e9cc70d1897 195 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 196 #endif
AnnaBridge 125:2e9cc70d1897 197 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 125:2e9cc70d1897 198 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 125:2e9cc70d1897 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
AnnaBridge 125:2e9cc70d1897 208 /*@} end of group Cortex_M0 */
AnnaBridge 125:2e9cc70d1897 209
AnnaBridge 125:2e9cc70d1897 210
AnnaBridge 125:2e9cc70d1897 211
AnnaBridge 125:2e9cc70d1897 212 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 213 * Register Abstraction
AnnaBridge 125:2e9cc70d1897 214 Core Register contain:
AnnaBridge 125:2e9cc70d1897 215 - Core Register
AnnaBridge 125:2e9cc70d1897 216 - Core NVIC Register
AnnaBridge 125:2e9cc70d1897 217 - Core SCB Register
AnnaBridge 125:2e9cc70d1897 218 - Core SysTick Register
AnnaBridge 125:2e9cc70d1897 219 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 125:2e9cc70d1897 221 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 125:2e9cc70d1897 222 */
AnnaBridge 125:2e9cc70d1897 223
AnnaBridge 125:2e9cc70d1897 224 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 225 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 125:2e9cc70d1897 226 \brief Core Register type definitions.
AnnaBridge 125:2e9cc70d1897 227 @{
AnnaBridge 125:2e9cc70d1897 228 */
AnnaBridge 125:2e9cc70d1897 229
AnnaBridge 125:2e9cc70d1897 230 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 125:2e9cc70d1897 231 */
AnnaBridge 125:2e9cc70d1897 232 typedef union
AnnaBridge 125:2e9cc70d1897 233 {
AnnaBridge 125:2e9cc70d1897 234 struct
AnnaBridge 125:2e9cc70d1897 235 {
AnnaBridge 125:2e9cc70d1897 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 125:2e9cc70d1897 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 125:2e9cc70d1897 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 125:2e9cc70d1897 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 125:2e9cc70d1897 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 125:2e9cc70d1897 241 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 243 } APSR_Type;
AnnaBridge 125:2e9cc70d1897 244
AnnaBridge 125:2e9cc70d1897 245 /* APSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 125:2e9cc70d1897 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 125:2e9cc70d1897 248
AnnaBridge 125:2e9cc70d1897 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 125:2e9cc70d1897 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 125:2e9cc70d1897 251
AnnaBridge 125:2e9cc70d1897 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 125:2e9cc70d1897 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 125:2e9cc70d1897 254
AnnaBridge 125:2e9cc70d1897 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 125:2e9cc70d1897 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 125:2e9cc70d1897 257
AnnaBridge 125:2e9cc70d1897 258
AnnaBridge 125:2e9cc70d1897 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 125:2e9cc70d1897 260 */
AnnaBridge 125:2e9cc70d1897 261 typedef union
AnnaBridge 125:2e9cc70d1897 262 {
AnnaBridge 125:2e9cc70d1897 263 struct
AnnaBridge 125:2e9cc70d1897 264 {
AnnaBridge 125:2e9cc70d1897 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 125:2e9cc70d1897 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 125:2e9cc70d1897 267 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 268 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 269 } IPSR_Type;
AnnaBridge 125:2e9cc70d1897 270
AnnaBridge 125:2e9cc70d1897 271 /* IPSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 125:2e9cc70d1897 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 125:2e9cc70d1897 274
AnnaBridge 125:2e9cc70d1897 275
AnnaBridge 125:2e9cc70d1897 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 125:2e9cc70d1897 277 */
AnnaBridge 125:2e9cc70d1897 278 typedef union
AnnaBridge 125:2e9cc70d1897 279 {
AnnaBridge 125:2e9cc70d1897 280 struct
AnnaBridge 125:2e9cc70d1897 281 {
AnnaBridge 125:2e9cc70d1897 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 125:2e9cc70d1897 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 125:2e9cc70d1897 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 125:2e9cc70d1897 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 125:2e9cc70d1897 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 125:2e9cc70d1897 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 125:2e9cc70d1897 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 125:2e9cc70d1897 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 125:2e9cc70d1897 290 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 291 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 292 } xPSR_Type;
AnnaBridge 125:2e9cc70d1897 293
AnnaBridge 125:2e9cc70d1897 294 /* xPSR Register Definitions */
AnnaBridge 125:2e9cc70d1897 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 125:2e9cc70d1897 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 125:2e9cc70d1897 297
AnnaBridge 125:2e9cc70d1897 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 125:2e9cc70d1897 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 125:2e9cc70d1897 300
AnnaBridge 125:2e9cc70d1897 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 125:2e9cc70d1897 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 125:2e9cc70d1897 303
AnnaBridge 125:2e9cc70d1897 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 125:2e9cc70d1897 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 125:2e9cc70d1897 306
AnnaBridge 125:2e9cc70d1897 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 125:2e9cc70d1897 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 125:2e9cc70d1897 309
AnnaBridge 125:2e9cc70d1897 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 125:2e9cc70d1897 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 125:2e9cc70d1897 312
AnnaBridge 125:2e9cc70d1897 313
AnnaBridge 125:2e9cc70d1897 314 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 125:2e9cc70d1897 315 */
AnnaBridge 125:2e9cc70d1897 316 typedef union
AnnaBridge 125:2e9cc70d1897 317 {
AnnaBridge 125:2e9cc70d1897 318 struct
AnnaBridge 125:2e9cc70d1897 319 {
AnnaBridge 125:2e9cc70d1897 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 125:2e9cc70d1897 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 125:2e9cc70d1897 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 125:2e9cc70d1897 323 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 324 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 325 } CONTROL_Type;
AnnaBridge 125:2e9cc70d1897 326
AnnaBridge 125:2e9cc70d1897 327 /* CONTROL Register Definitions */
AnnaBridge 125:2e9cc70d1897 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 125:2e9cc70d1897 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 125:2e9cc70d1897 330
AnnaBridge 125:2e9cc70d1897 331 /*@} end of group CMSIS_CORE */
AnnaBridge 125:2e9cc70d1897 332
AnnaBridge 125:2e9cc70d1897 333
AnnaBridge 125:2e9cc70d1897 334 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 125:2e9cc70d1897 336 \brief Type definitions for the NVIC Registers
AnnaBridge 125:2e9cc70d1897 337 @{
AnnaBridge 125:2e9cc70d1897 338 */
AnnaBridge 125:2e9cc70d1897 339
AnnaBridge 125:2e9cc70d1897 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 125:2e9cc70d1897 341 */
AnnaBridge 125:2e9cc70d1897 342 typedef struct
AnnaBridge 125:2e9cc70d1897 343 {
AnnaBridge 125:2e9cc70d1897 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 125:2e9cc70d1897 345 uint32_t RESERVED0[31];
AnnaBridge 125:2e9cc70d1897 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 125:2e9cc70d1897 347 uint32_t RSERVED1[31];
AnnaBridge 125:2e9cc70d1897 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 125:2e9cc70d1897 349 uint32_t RESERVED2[31];
AnnaBridge 125:2e9cc70d1897 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 125:2e9cc70d1897 351 uint32_t RESERVED3[31];
AnnaBridge 125:2e9cc70d1897 352 uint32_t RESERVED4[64];
AnnaBridge 125:2e9cc70d1897 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 125:2e9cc70d1897 354 } NVIC_Type;
AnnaBridge 125:2e9cc70d1897 355
AnnaBridge 125:2e9cc70d1897 356 /*@} end of group CMSIS_NVIC */
AnnaBridge 125:2e9cc70d1897 357
AnnaBridge 125:2e9cc70d1897 358
AnnaBridge 125:2e9cc70d1897 359 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 360 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 125:2e9cc70d1897 361 \brief Type definitions for the System Control Block Registers
AnnaBridge 125:2e9cc70d1897 362 @{
AnnaBridge 125:2e9cc70d1897 363 */
AnnaBridge 125:2e9cc70d1897 364
AnnaBridge 125:2e9cc70d1897 365 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 125:2e9cc70d1897 366 */
AnnaBridge 125:2e9cc70d1897 367 typedef struct
AnnaBridge 125:2e9cc70d1897 368 {
AnnaBridge 125:2e9cc70d1897 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 125:2e9cc70d1897 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 125:2e9cc70d1897 371 uint32_t RESERVED0;
AnnaBridge 125:2e9cc70d1897 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 125:2e9cc70d1897 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 125:2e9cc70d1897 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 125:2e9cc70d1897 375 uint32_t RESERVED1;
AnnaBridge 125:2e9cc70d1897 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 125:2e9cc70d1897 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 125:2e9cc70d1897 378 } SCB_Type;
AnnaBridge 125:2e9cc70d1897 379
AnnaBridge 125:2e9cc70d1897 380 /* SCB CPUID Register Definitions */
AnnaBridge 125:2e9cc70d1897 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 125:2e9cc70d1897 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 125:2e9cc70d1897 383
AnnaBridge 125:2e9cc70d1897 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 125:2e9cc70d1897 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 125:2e9cc70d1897 386
AnnaBridge 125:2e9cc70d1897 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 125:2e9cc70d1897 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 125:2e9cc70d1897 389
AnnaBridge 125:2e9cc70d1897 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 125:2e9cc70d1897 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 125:2e9cc70d1897 392
AnnaBridge 125:2e9cc70d1897 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 125:2e9cc70d1897 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 125:2e9cc70d1897 395
AnnaBridge 125:2e9cc70d1897 396 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 125:2e9cc70d1897 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 125:2e9cc70d1897 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 125:2e9cc70d1897 399
AnnaBridge 125:2e9cc70d1897 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 125:2e9cc70d1897 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 125:2e9cc70d1897 402
AnnaBridge 125:2e9cc70d1897 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 125:2e9cc70d1897 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 125:2e9cc70d1897 405
AnnaBridge 125:2e9cc70d1897 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 125:2e9cc70d1897 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 125:2e9cc70d1897 408
AnnaBridge 125:2e9cc70d1897 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 125:2e9cc70d1897 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 125:2e9cc70d1897 411
AnnaBridge 125:2e9cc70d1897 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 125:2e9cc70d1897 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 125:2e9cc70d1897 414
AnnaBridge 125:2e9cc70d1897 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 125:2e9cc70d1897 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 125:2e9cc70d1897 417
AnnaBridge 125:2e9cc70d1897 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 125:2e9cc70d1897 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 125:2e9cc70d1897 420
AnnaBridge 125:2e9cc70d1897 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 125:2e9cc70d1897 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 125:2e9cc70d1897 423
AnnaBridge 125:2e9cc70d1897 424 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 125:2e9cc70d1897 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 125:2e9cc70d1897 427
AnnaBridge 125:2e9cc70d1897 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 125:2e9cc70d1897 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 125:2e9cc70d1897 430
AnnaBridge 125:2e9cc70d1897 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 125:2e9cc70d1897 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 125:2e9cc70d1897 433
AnnaBridge 125:2e9cc70d1897 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 125:2e9cc70d1897 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 125:2e9cc70d1897 436
AnnaBridge 125:2e9cc70d1897 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 125:2e9cc70d1897 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 125:2e9cc70d1897 439
AnnaBridge 125:2e9cc70d1897 440 /* SCB System Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 125:2e9cc70d1897 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 125:2e9cc70d1897 443
AnnaBridge 125:2e9cc70d1897 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 125:2e9cc70d1897 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 125:2e9cc70d1897 446
AnnaBridge 125:2e9cc70d1897 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 125:2e9cc70d1897 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 125:2e9cc70d1897 449
AnnaBridge 125:2e9cc70d1897 450 /* SCB Configuration Control Register Definitions */
AnnaBridge 125:2e9cc70d1897 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 125:2e9cc70d1897 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 125:2e9cc70d1897 453
AnnaBridge 125:2e9cc70d1897 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 125:2e9cc70d1897 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 125:2e9cc70d1897 456
AnnaBridge 125:2e9cc70d1897 457 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 125:2e9cc70d1897 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 125:2e9cc70d1897 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 125:2e9cc70d1897 460
AnnaBridge 125:2e9cc70d1897 461 /*@} end of group CMSIS_SCB */
AnnaBridge 125:2e9cc70d1897 462
AnnaBridge 125:2e9cc70d1897 463
AnnaBridge 125:2e9cc70d1897 464 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 125:2e9cc70d1897 466 \brief Type definitions for the System Timer Registers.
AnnaBridge 125:2e9cc70d1897 467 @{
AnnaBridge 125:2e9cc70d1897 468 */
AnnaBridge 125:2e9cc70d1897 469
AnnaBridge 125:2e9cc70d1897 470 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 125:2e9cc70d1897 471 */
AnnaBridge 125:2e9cc70d1897 472 typedef struct
AnnaBridge 125:2e9cc70d1897 473 {
AnnaBridge 125:2e9cc70d1897 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 125:2e9cc70d1897 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 125:2e9cc70d1897 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 125:2e9cc70d1897 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 125:2e9cc70d1897 478 } SysTick_Type;
AnnaBridge 125:2e9cc70d1897 479
AnnaBridge 125:2e9cc70d1897 480 /* SysTick Control / Status Register Definitions */
AnnaBridge 125:2e9cc70d1897 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 125:2e9cc70d1897 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 125:2e9cc70d1897 483
AnnaBridge 125:2e9cc70d1897 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 125:2e9cc70d1897 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 125:2e9cc70d1897 486
AnnaBridge 125:2e9cc70d1897 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 125:2e9cc70d1897 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 125:2e9cc70d1897 489
AnnaBridge 125:2e9cc70d1897 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 125:2e9cc70d1897 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 125:2e9cc70d1897 492
AnnaBridge 125:2e9cc70d1897 493 /* SysTick Reload Register Definitions */
AnnaBridge 125:2e9cc70d1897 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 125:2e9cc70d1897 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 125:2e9cc70d1897 496
AnnaBridge 125:2e9cc70d1897 497 /* SysTick Current Register Definitions */
AnnaBridge 125:2e9cc70d1897 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 125:2e9cc70d1897 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 125:2e9cc70d1897 500
AnnaBridge 125:2e9cc70d1897 501 /* SysTick Calibration Register Definitions */
AnnaBridge 125:2e9cc70d1897 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 125:2e9cc70d1897 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 125:2e9cc70d1897 504
AnnaBridge 125:2e9cc70d1897 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 125:2e9cc70d1897 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 125:2e9cc70d1897 507
AnnaBridge 125:2e9cc70d1897 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 125:2e9cc70d1897 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 125:2e9cc70d1897 510
AnnaBridge 125:2e9cc70d1897 511 /*@} end of group CMSIS_SysTick */
AnnaBridge 125:2e9cc70d1897 512
AnnaBridge 125:2e9cc70d1897 513
AnnaBridge 125:2e9cc70d1897 514 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 125:2e9cc70d1897 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
AnnaBridge 125:2e9cc70d1897 517 are only accessible over DAP and not via processor. Therefore
AnnaBridge 125:2e9cc70d1897 518 they are not covered by the Cortex-M0 header file.
AnnaBridge 125:2e9cc70d1897 519 @{
AnnaBridge 125:2e9cc70d1897 520 */
AnnaBridge 125:2e9cc70d1897 521 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 125:2e9cc70d1897 522
AnnaBridge 125:2e9cc70d1897 523
AnnaBridge 125:2e9cc70d1897 524 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 525 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 125:2e9cc70d1897 526 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 125:2e9cc70d1897 527 @{
AnnaBridge 125:2e9cc70d1897 528 */
AnnaBridge 125:2e9cc70d1897 529
AnnaBridge 125:2e9cc70d1897 530 /* Memory mapping of Cortex-M0 Hardware */
AnnaBridge 125:2e9cc70d1897 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 125:2e9cc70d1897 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 125:2e9cc70d1897 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 125:2e9cc70d1897 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 125:2e9cc70d1897 535
AnnaBridge 125:2e9cc70d1897 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 125:2e9cc70d1897 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 125:2e9cc70d1897 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 125:2e9cc70d1897 539
AnnaBridge 125:2e9cc70d1897 540
AnnaBridge 125:2e9cc70d1897 541 /*@} */
AnnaBridge 125:2e9cc70d1897 542
AnnaBridge 125:2e9cc70d1897 543
AnnaBridge 125:2e9cc70d1897 544
AnnaBridge 125:2e9cc70d1897 545 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 546 * Hardware Abstraction Layer
AnnaBridge 125:2e9cc70d1897 547 Core Function Interface contains:
AnnaBridge 125:2e9cc70d1897 548 - Core NVIC Functions
AnnaBridge 125:2e9cc70d1897 549 - Core SysTick Functions
AnnaBridge 125:2e9cc70d1897 550 - Core Register Access Functions
AnnaBridge 125:2e9cc70d1897 551 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 125:2e9cc70d1897 553 */
AnnaBridge 125:2e9cc70d1897 554
AnnaBridge 125:2e9cc70d1897 555
AnnaBridge 125:2e9cc70d1897 556
AnnaBridge 125:2e9cc70d1897 557 /* ########################## NVIC functions #################################### */
AnnaBridge 125:2e9cc70d1897 558 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 125:2e9cc70d1897 560 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 125:2e9cc70d1897 561 @{
AnnaBridge 125:2e9cc70d1897 562 */
AnnaBridge 125:2e9cc70d1897 563
AnnaBridge 125:2e9cc70d1897 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 125:2e9cc70d1897 565 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 125:2e9cc70d1897 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 125:2e9cc70d1897 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 125:2e9cc70d1897 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 125:2e9cc70d1897 569
AnnaBridge 125:2e9cc70d1897 570
AnnaBridge 125:2e9cc70d1897 571 /** \brief Enable External Interrupt
AnnaBridge 125:2e9cc70d1897 572
AnnaBridge 125:2e9cc70d1897 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 125:2e9cc70d1897 574
AnnaBridge 125:2e9cc70d1897 575 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 576 */
AnnaBridge 125:2e9cc70d1897 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 578 {
AnnaBridge 125:2e9cc70d1897 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 580 }
AnnaBridge 125:2e9cc70d1897 581
AnnaBridge 125:2e9cc70d1897 582
AnnaBridge 125:2e9cc70d1897 583 /** \brief Disable External Interrupt
AnnaBridge 125:2e9cc70d1897 584
AnnaBridge 125:2e9cc70d1897 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 125:2e9cc70d1897 586
AnnaBridge 125:2e9cc70d1897 587 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 588 */
AnnaBridge 125:2e9cc70d1897 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 590 {
AnnaBridge 125:2e9cc70d1897 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
AnnaBridge 125:2e9cc70d1897 594 }
AnnaBridge 125:2e9cc70d1897 595
AnnaBridge 125:2e9cc70d1897 596
AnnaBridge 125:2e9cc70d1897 597 /** \brief Get Pending Interrupt
AnnaBridge 125:2e9cc70d1897 598
AnnaBridge 125:2e9cc70d1897 599 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 125:2e9cc70d1897 600 for the specified interrupt.
AnnaBridge 125:2e9cc70d1897 601
AnnaBridge 125:2e9cc70d1897 602 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 603
AnnaBridge 125:2e9cc70d1897 604 \return 0 Interrupt status is not pending.
AnnaBridge 125:2e9cc70d1897 605 \return 1 Interrupt status is pending.
AnnaBridge 125:2e9cc70d1897 606 */
AnnaBridge 125:2e9cc70d1897 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 608 {
AnnaBridge 125:2e9cc70d1897 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 125:2e9cc70d1897 610 }
AnnaBridge 125:2e9cc70d1897 611
AnnaBridge 125:2e9cc70d1897 612
AnnaBridge 125:2e9cc70d1897 613 /** \brief Set Pending Interrupt
AnnaBridge 125:2e9cc70d1897 614
AnnaBridge 125:2e9cc70d1897 615 The function sets the pending bit of an external interrupt.
AnnaBridge 125:2e9cc70d1897 616
AnnaBridge 125:2e9cc70d1897 617 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 618 */
AnnaBridge 125:2e9cc70d1897 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 620 {
AnnaBridge 125:2e9cc70d1897 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 622 }
AnnaBridge 125:2e9cc70d1897 623
AnnaBridge 125:2e9cc70d1897 624
AnnaBridge 125:2e9cc70d1897 625 /** \brief Clear Pending Interrupt
AnnaBridge 125:2e9cc70d1897 626
AnnaBridge 125:2e9cc70d1897 627 The function clears the pending bit of an external interrupt.
AnnaBridge 125:2e9cc70d1897 628
AnnaBridge 125:2e9cc70d1897 629 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 125:2e9cc70d1897 630 */
AnnaBridge 125:2e9cc70d1897 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 632 {
AnnaBridge 125:2e9cc70d1897 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 125:2e9cc70d1897 634 }
AnnaBridge 125:2e9cc70d1897 635
AnnaBridge 125:2e9cc70d1897 636
AnnaBridge 125:2e9cc70d1897 637 /** \brief Set Interrupt Priority
AnnaBridge 125:2e9cc70d1897 638
AnnaBridge 125:2e9cc70d1897 639 The function sets the priority of an interrupt.
AnnaBridge 125:2e9cc70d1897 640
AnnaBridge 125:2e9cc70d1897 641 \note The priority cannot be set for every core interrupt.
AnnaBridge 125:2e9cc70d1897 642
AnnaBridge 125:2e9cc70d1897 643 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 644 \param [in] priority Priority to set.
AnnaBridge 125:2e9cc70d1897 645 */
AnnaBridge 125:2e9cc70d1897 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 125:2e9cc70d1897 647 {
AnnaBridge 125:2e9cc70d1897 648 if((int32_t)(IRQn) < 0) {
AnnaBridge 125:2e9cc70d1897 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 125:2e9cc70d1897 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 125:2e9cc70d1897 651 }
AnnaBridge 125:2e9cc70d1897 652 else {
AnnaBridge 125:2e9cc70d1897 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 125:2e9cc70d1897 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 125:2e9cc70d1897 655 }
AnnaBridge 125:2e9cc70d1897 656 }
AnnaBridge 125:2e9cc70d1897 657
AnnaBridge 125:2e9cc70d1897 658
AnnaBridge 125:2e9cc70d1897 659 /** \brief Get Interrupt Priority
AnnaBridge 125:2e9cc70d1897 660
AnnaBridge 125:2e9cc70d1897 661 The function reads the priority of an interrupt. The interrupt
AnnaBridge 125:2e9cc70d1897 662 number can be positive to specify an external (device specific)
AnnaBridge 125:2e9cc70d1897 663 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 125:2e9cc70d1897 664
AnnaBridge 125:2e9cc70d1897 665
AnnaBridge 125:2e9cc70d1897 666 \param [in] IRQn Interrupt number.
AnnaBridge 125:2e9cc70d1897 667 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 125:2e9cc70d1897 668 priority bits of the microcontroller.
AnnaBridge 125:2e9cc70d1897 669 */
AnnaBridge 125:2e9cc70d1897 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 125:2e9cc70d1897 671 {
AnnaBridge 125:2e9cc70d1897 672
AnnaBridge 125:2e9cc70d1897 673 if((int32_t)(IRQn) < 0) {
AnnaBridge 125:2e9cc70d1897 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 125:2e9cc70d1897 675 }
AnnaBridge 125:2e9cc70d1897 676 else {
AnnaBridge 125:2e9cc70d1897 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 125:2e9cc70d1897 678 }
AnnaBridge 125:2e9cc70d1897 679 }
AnnaBridge 125:2e9cc70d1897 680
AnnaBridge 125:2e9cc70d1897 681
AnnaBridge 125:2e9cc70d1897 682 /** \brief System Reset
AnnaBridge 125:2e9cc70d1897 683
AnnaBridge 125:2e9cc70d1897 684 The function initiates a system reset request to reset the MCU.
AnnaBridge 125:2e9cc70d1897 685 */
AnnaBridge 125:2e9cc70d1897 686 __STATIC_INLINE void NVIC_SystemReset(void)
AnnaBridge 125:2e9cc70d1897 687 {
AnnaBridge 125:2e9cc70d1897 688 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 125:2e9cc70d1897 689 buffered write are completed before reset */
AnnaBridge 125:2e9cc70d1897 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 125:2e9cc70d1897 691 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 125:2e9cc70d1897 692 __DSB(); /* Ensure completion of memory access */
AnnaBridge 125:2e9cc70d1897 693 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 125:2e9cc70d1897 694 }
AnnaBridge 125:2e9cc70d1897 695
AnnaBridge 125:2e9cc70d1897 696 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 125:2e9cc70d1897 697
AnnaBridge 125:2e9cc70d1897 698
AnnaBridge 125:2e9cc70d1897 699
AnnaBridge 125:2e9cc70d1897 700 /* ################################## SysTick function ############################################ */
AnnaBridge 125:2e9cc70d1897 701 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 125:2e9cc70d1897 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 125:2e9cc70d1897 703 \brief Functions that configure the System.
AnnaBridge 125:2e9cc70d1897 704 @{
AnnaBridge 125:2e9cc70d1897 705 */
AnnaBridge 125:2e9cc70d1897 706
AnnaBridge 125:2e9cc70d1897 707 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 125:2e9cc70d1897 708
AnnaBridge 125:2e9cc70d1897 709 /** \brief System Tick Configuration
AnnaBridge 125:2e9cc70d1897 710
AnnaBridge 125:2e9cc70d1897 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 125:2e9cc70d1897 712 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 125:2e9cc70d1897 713
AnnaBridge 125:2e9cc70d1897 714 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 125:2e9cc70d1897 715
AnnaBridge 125:2e9cc70d1897 716 \return 0 Function succeeded.
AnnaBridge 125:2e9cc70d1897 717 \return 1 Function failed.
AnnaBridge 125:2e9cc70d1897 718
AnnaBridge 125:2e9cc70d1897 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 125:2e9cc70d1897 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 125:2e9cc70d1897 721 must contain a vendor-specific implementation of this function.
AnnaBridge 125:2e9cc70d1897 722
AnnaBridge 125:2e9cc70d1897 723 */
AnnaBridge 125:2e9cc70d1897 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 125:2e9cc70d1897 725 {
AnnaBridge 125:2e9cc70d1897 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge 125:2e9cc70d1897 727
AnnaBridge 125:2e9cc70d1897 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 125:2e9cc70d1897 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 125:2e9cc70d1897 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 125:2e9cc70d1897 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 125:2e9cc70d1897 732 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 125:2e9cc70d1897 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 125:2e9cc70d1897 734 return (0UL); /* Function successful */
AnnaBridge 125:2e9cc70d1897 735 }
AnnaBridge 125:2e9cc70d1897 736
AnnaBridge 125:2e9cc70d1897 737 #endif
AnnaBridge 125:2e9cc70d1897 738
AnnaBridge 125:2e9cc70d1897 739 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 125:2e9cc70d1897 740
AnnaBridge 125:2e9cc70d1897 741
AnnaBridge 125:2e9cc70d1897 742
AnnaBridge 125:2e9cc70d1897 743
AnnaBridge 125:2e9cc70d1897 744 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 745 }
AnnaBridge 125:2e9cc70d1897 746 #endif
AnnaBridge 125:2e9cc70d1897 747
AnnaBridge 125:2e9cc70d1897 748 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 125:2e9cc70d1897 749
AnnaBridge 125:2e9cc70d1897 750 #endif /* __CMSIS_GENERIC */