mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620HSP/core_ca_mmu.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
125:2e9cc70d1897 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 ;/**************************************************************************//**
AnnaBridge 125:2e9cc70d1897 2 ; * @file core_ca_mmu.h
AnnaBridge 125:2e9cc70d1897 3 ; * @brief MMU Startup File for A9_MP Device Series
AnnaBridge 125:2e9cc70d1897 4 ; * @version V1.01
AnnaBridge 125:2e9cc70d1897 5 ; * @date 10 Sept 2014
AnnaBridge 125:2e9cc70d1897 6 ; *
AnnaBridge 125:2e9cc70d1897 7 ; * @note
AnnaBridge 125:2e9cc70d1897 8 ; *
AnnaBridge 125:2e9cc70d1897 9 ; ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
AnnaBridge 125:2e9cc70d1897 11 ;
AnnaBridge 125:2e9cc70d1897 12 ; All rights reserved.
AnnaBridge 125:2e9cc70d1897 13 ; Redistribution and use in source and binary forms, with or without
AnnaBridge 125:2e9cc70d1897 14 ; modification, are permitted provided that the following conditions are met:
AnnaBridge 125:2e9cc70d1897 15 ; - Redistributions of source code must retain the above copyright
AnnaBridge 125:2e9cc70d1897 16 ; notice, this list of conditions and the following disclaimer.
AnnaBridge 125:2e9cc70d1897 17 ; - Redistributions in binary form must reproduce the above copyright
AnnaBridge 125:2e9cc70d1897 18 ; notice, this list of conditions and the following disclaimer in the
AnnaBridge 125:2e9cc70d1897 19 ; documentation and/or other materials provided with the distribution.
AnnaBridge 125:2e9cc70d1897 20 ; - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 125:2e9cc70d1897 21 ; to endorse or promote products derived from this software without
AnnaBridge 125:2e9cc70d1897 22 ; specific prior written permission.
AnnaBridge 125:2e9cc70d1897 23 ; *
AnnaBridge 125:2e9cc70d1897 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 125:2e9cc70d1897 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 125:2e9cc70d1897 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 125:2e9cc70d1897 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 125:2e9cc70d1897 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 125:2e9cc70d1897 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 125:2e9cc70d1897 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 125:2e9cc70d1897 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 125:2e9cc70d1897 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 125:2e9cc70d1897 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 125:2e9cc70d1897 34 ; POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 125:2e9cc70d1897 35 ; ---------------------------------------------------------------------------*/
AnnaBridge 125:2e9cc70d1897 36
AnnaBridge 125:2e9cc70d1897 37 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 38 extern "C" {
AnnaBridge 125:2e9cc70d1897 39 #endif
AnnaBridge 125:2e9cc70d1897 40
AnnaBridge 125:2e9cc70d1897 41 #ifndef _MMU_FUNC_H
AnnaBridge 125:2e9cc70d1897 42 #define _MMU_FUNC_H
AnnaBridge 125:2e9cc70d1897 43
AnnaBridge 125:2e9cc70d1897 44 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 125:2e9cc70d1897 45 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 125:2e9cc70d1897 46
AnnaBridge 125:2e9cc70d1897 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 125:2e9cc70d1897 48 #define SECTION_B_SHIFT (2)
AnnaBridge 125:2e9cc70d1897 49 #define SECTION_C_SHIFT (3)
AnnaBridge 125:2e9cc70d1897 50 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 125:2e9cc70d1897 51 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 125:2e9cc70d1897 52 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 125:2e9cc70d1897 53
AnnaBridge 125:2e9cc70d1897 54 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 125:2e9cc70d1897 55 #define SECTION_XN_SHIFT (4)
AnnaBridge 125:2e9cc70d1897 56
AnnaBridge 125:2e9cc70d1897 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 125:2e9cc70d1897 58 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 125:2e9cc70d1897 59
AnnaBridge 125:2e9cc70d1897 60 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 125:2e9cc70d1897 61 #define SECTION_P_SHIFT (9)
AnnaBridge 125:2e9cc70d1897 62
AnnaBridge 125:2e9cc70d1897 63 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 125:2e9cc70d1897 64 #define SECTION_AP_SHIFT (10)
AnnaBridge 125:2e9cc70d1897 65 #define SECTION_AP2_SHIFT (15)
AnnaBridge 125:2e9cc70d1897 66
AnnaBridge 125:2e9cc70d1897 67 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 125:2e9cc70d1897 68 #define SECTION_S_SHIFT (16)
AnnaBridge 125:2e9cc70d1897 69
AnnaBridge 125:2e9cc70d1897 70 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 125:2e9cc70d1897 71 #define SECTION_NG_SHIFT (17)
AnnaBridge 125:2e9cc70d1897 72
AnnaBridge 125:2e9cc70d1897 73 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 125:2e9cc70d1897 74 #define SECTION_NS_SHIFT (19)
AnnaBridge 125:2e9cc70d1897 75
AnnaBridge 125:2e9cc70d1897 76
AnnaBridge 125:2e9cc70d1897 77 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 125:2e9cc70d1897 78 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 125:2e9cc70d1897 79
AnnaBridge 125:2e9cc70d1897 80 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 125:2e9cc70d1897 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 125:2e9cc70d1897 82
AnnaBridge 125:2e9cc70d1897 83 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 125:2e9cc70d1897 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 125:2e9cc70d1897 85
AnnaBridge 125:2e9cc70d1897 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 125:2e9cc70d1897 87 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 125:2e9cc70d1897 88 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 125:2e9cc70d1897 89 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 125:2e9cc70d1897 90 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 125:2e9cc70d1897 91 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 125:2e9cc70d1897 92
AnnaBridge 125:2e9cc70d1897 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 125:2e9cc70d1897 94 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 125:2e9cc70d1897 95 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 125:2e9cc70d1897 96 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 125:2e9cc70d1897 97 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 125:2e9cc70d1897 98 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 125:2e9cc70d1897 99
AnnaBridge 125:2e9cc70d1897 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 125:2e9cc70d1897 101 #define PAGE_B_SHIFT (2)
AnnaBridge 125:2e9cc70d1897 102 #define PAGE_C_SHIFT (3)
AnnaBridge 125:2e9cc70d1897 103 #define PAGE_TEX_SHIFT (12)
AnnaBridge 125:2e9cc70d1897 104
AnnaBridge 125:2e9cc70d1897 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 125:2e9cc70d1897 106 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 125:2e9cc70d1897 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 125:2e9cc70d1897 108 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 125:2e9cc70d1897 109
AnnaBridge 125:2e9cc70d1897 110
AnnaBridge 125:2e9cc70d1897 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 125:2e9cc70d1897 112 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 125:2e9cc70d1897 113
AnnaBridge 125:2e9cc70d1897 114 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 125:2e9cc70d1897 115 #define PAGE_P_SHIFT (9)
AnnaBridge 125:2e9cc70d1897 116
AnnaBridge 125:2e9cc70d1897 117 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 125:2e9cc70d1897 118 #define PAGE_AP_SHIFT (4)
AnnaBridge 125:2e9cc70d1897 119 #define PAGE_AP2_SHIFT (9)
AnnaBridge 125:2e9cc70d1897 120
AnnaBridge 125:2e9cc70d1897 121 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 125:2e9cc70d1897 122 #define PAGE_S_SHIFT (10)
AnnaBridge 125:2e9cc70d1897 123
AnnaBridge 125:2e9cc70d1897 124 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 125:2e9cc70d1897 125 #define PAGE_NG_SHIFT (11)
AnnaBridge 125:2e9cc70d1897 126
AnnaBridge 125:2e9cc70d1897 127 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 125:2e9cc70d1897 128 #define PAGE_NS_SHIFT (3)
AnnaBridge 125:2e9cc70d1897 129
AnnaBridge 125:2e9cc70d1897 130 #define OFFSET_1M (0x00100000)
AnnaBridge 125:2e9cc70d1897 131 #define OFFSET_64K (0x00010000)
AnnaBridge 125:2e9cc70d1897 132 #define OFFSET_4K (0x00001000)
AnnaBridge 125:2e9cc70d1897 133
AnnaBridge 125:2e9cc70d1897 134 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 125:2e9cc70d1897 135
AnnaBridge 125:2e9cc70d1897 136 /* ########################### MMU Function Access ########################### */
AnnaBridge 125:2e9cc70d1897 137 /** \ingroup MMU_FunctionInterface
AnnaBridge 125:2e9cc70d1897 138 \defgroup MMU_Functions MMU Functions Interface
AnnaBridge 125:2e9cc70d1897 139 @{
AnnaBridge 125:2e9cc70d1897 140 */
AnnaBridge 125:2e9cc70d1897 141
AnnaBridge 125:2e9cc70d1897 142 /* Attributes enumerations */
AnnaBridge 125:2e9cc70d1897 143
AnnaBridge 125:2e9cc70d1897 144 /* Region size attributes */
AnnaBridge 125:2e9cc70d1897 145 typedef enum
AnnaBridge 125:2e9cc70d1897 146 {
AnnaBridge 125:2e9cc70d1897 147 SECTION,
AnnaBridge 125:2e9cc70d1897 148 PAGE_4k,
AnnaBridge 125:2e9cc70d1897 149 PAGE_64k,
AnnaBridge 125:2e9cc70d1897 150 } mmu_region_size_Type;
AnnaBridge 125:2e9cc70d1897 151
AnnaBridge 125:2e9cc70d1897 152 /* Region type attributes */
AnnaBridge 125:2e9cc70d1897 153 typedef enum
AnnaBridge 125:2e9cc70d1897 154 {
AnnaBridge 125:2e9cc70d1897 155 NORMAL,
AnnaBridge 125:2e9cc70d1897 156 DEVICE,
AnnaBridge 125:2e9cc70d1897 157 SHARED_DEVICE,
AnnaBridge 125:2e9cc70d1897 158 NON_SHARED_DEVICE,
AnnaBridge 125:2e9cc70d1897 159 STRONGLY_ORDERED
AnnaBridge 125:2e9cc70d1897 160 } mmu_memory_Type;
AnnaBridge 125:2e9cc70d1897 161
AnnaBridge 125:2e9cc70d1897 162 /* Region cacheability attributes */
AnnaBridge 125:2e9cc70d1897 163 typedef enum
AnnaBridge 125:2e9cc70d1897 164 {
AnnaBridge 125:2e9cc70d1897 165 NON_CACHEABLE,
AnnaBridge 125:2e9cc70d1897 166 WB_WA,
AnnaBridge 125:2e9cc70d1897 167 WT,
AnnaBridge 125:2e9cc70d1897 168 WB_NO_WA,
AnnaBridge 125:2e9cc70d1897 169 } mmu_cacheability_Type;
AnnaBridge 125:2e9cc70d1897 170
AnnaBridge 125:2e9cc70d1897 171 /* Region parity check attributes */
AnnaBridge 125:2e9cc70d1897 172 typedef enum
AnnaBridge 125:2e9cc70d1897 173 {
AnnaBridge 125:2e9cc70d1897 174 ECC_DISABLED,
AnnaBridge 125:2e9cc70d1897 175 ECC_ENABLED,
AnnaBridge 125:2e9cc70d1897 176 } mmu_ecc_check_Type;
AnnaBridge 125:2e9cc70d1897 177
AnnaBridge 125:2e9cc70d1897 178 /* Region execution attributes */
AnnaBridge 125:2e9cc70d1897 179 typedef enum
AnnaBridge 125:2e9cc70d1897 180 {
AnnaBridge 125:2e9cc70d1897 181 EXECUTE,
AnnaBridge 125:2e9cc70d1897 182 NON_EXECUTE,
AnnaBridge 125:2e9cc70d1897 183 } mmu_execute_Type;
AnnaBridge 125:2e9cc70d1897 184
AnnaBridge 125:2e9cc70d1897 185 /* Region global attributes */
AnnaBridge 125:2e9cc70d1897 186 typedef enum
AnnaBridge 125:2e9cc70d1897 187 {
AnnaBridge 125:2e9cc70d1897 188 GLOBAL,
AnnaBridge 125:2e9cc70d1897 189 NON_GLOBAL,
AnnaBridge 125:2e9cc70d1897 190 } mmu_global_Type;
AnnaBridge 125:2e9cc70d1897 191
AnnaBridge 125:2e9cc70d1897 192 /* Region shareability attributes */
AnnaBridge 125:2e9cc70d1897 193 typedef enum
AnnaBridge 125:2e9cc70d1897 194 {
AnnaBridge 125:2e9cc70d1897 195 NON_SHARED,
AnnaBridge 125:2e9cc70d1897 196 SHARED,
AnnaBridge 125:2e9cc70d1897 197 } mmu_shared_Type;
AnnaBridge 125:2e9cc70d1897 198
AnnaBridge 125:2e9cc70d1897 199 /* Region security attributes */
AnnaBridge 125:2e9cc70d1897 200 typedef enum
AnnaBridge 125:2e9cc70d1897 201 {
AnnaBridge 125:2e9cc70d1897 202 SECURE,
AnnaBridge 125:2e9cc70d1897 203 NON_SECURE,
AnnaBridge 125:2e9cc70d1897 204 } mmu_secure_Type;
AnnaBridge 125:2e9cc70d1897 205
AnnaBridge 125:2e9cc70d1897 206 /* Region access attributes */
AnnaBridge 125:2e9cc70d1897 207 typedef enum
AnnaBridge 125:2e9cc70d1897 208 {
AnnaBridge 125:2e9cc70d1897 209 NO_ACCESS,
AnnaBridge 125:2e9cc70d1897 210 RW,
AnnaBridge 125:2e9cc70d1897 211 READ,
AnnaBridge 125:2e9cc70d1897 212 } mmu_access_Type;
AnnaBridge 125:2e9cc70d1897 213
AnnaBridge 125:2e9cc70d1897 214 /* Memory Region definition */
AnnaBridge 125:2e9cc70d1897 215 typedef struct RegionStruct {
AnnaBridge 125:2e9cc70d1897 216 mmu_region_size_Type rg_t;
AnnaBridge 125:2e9cc70d1897 217 mmu_memory_Type mem_t;
AnnaBridge 125:2e9cc70d1897 218 uint8_t domain;
AnnaBridge 125:2e9cc70d1897 219 mmu_cacheability_Type inner_norm_t;
AnnaBridge 125:2e9cc70d1897 220 mmu_cacheability_Type outer_norm_t;
AnnaBridge 125:2e9cc70d1897 221 mmu_ecc_check_Type e_t;
AnnaBridge 125:2e9cc70d1897 222 mmu_execute_Type xn_t;
AnnaBridge 125:2e9cc70d1897 223 mmu_global_Type g_t;
AnnaBridge 125:2e9cc70d1897 224 mmu_secure_Type sec_t;
AnnaBridge 125:2e9cc70d1897 225 mmu_access_Type priv_t;
AnnaBridge 125:2e9cc70d1897 226 mmu_access_Type user_t;
AnnaBridge 125:2e9cc70d1897 227 mmu_shared_Type sh_t;
AnnaBridge 125:2e9cc70d1897 228
AnnaBridge 125:2e9cc70d1897 229 } mmu_region_attributes_Type;
AnnaBridge 125:2e9cc70d1897 230
AnnaBridge 125:2e9cc70d1897 231 /** \brief Set section execution-never attribute
AnnaBridge 125:2e9cc70d1897 232
AnnaBridge 125:2e9cc70d1897 233 The function sets section execution-never attribute
AnnaBridge 125:2e9cc70d1897 234
AnnaBridge 125:2e9cc70d1897 235 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 125:2e9cc70d1897 237
AnnaBridge 125:2e9cc70d1897 238 \return 0
AnnaBridge 125:2e9cc70d1897 239 */
AnnaBridge 125:2e9cc70d1897 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 125:2e9cc70d1897 241 {
AnnaBridge 125:2e9cc70d1897 242 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 125:2e9cc70d1897 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 125:2e9cc70d1897 244 return 0;
AnnaBridge 125:2e9cc70d1897 245 }
AnnaBridge 125:2e9cc70d1897 246
AnnaBridge 125:2e9cc70d1897 247 /** \brief Set section domain
AnnaBridge 125:2e9cc70d1897 248
AnnaBridge 125:2e9cc70d1897 249 The function sets section domain
AnnaBridge 125:2e9cc70d1897 250
AnnaBridge 125:2e9cc70d1897 251 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 252 \param [in] domain Section domain
AnnaBridge 125:2e9cc70d1897 253
AnnaBridge 125:2e9cc70d1897 254 \return 0
AnnaBridge 125:2e9cc70d1897 255 */
AnnaBridge 125:2e9cc70d1897 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 125:2e9cc70d1897 257 {
AnnaBridge 125:2e9cc70d1897 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 125:2e9cc70d1897 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 125:2e9cc70d1897 260 return 0;
AnnaBridge 125:2e9cc70d1897 261 }
AnnaBridge 125:2e9cc70d1897 262
AnnaBridge 125:2e9cc70d1897 263 /** \brief Set section parity check
AnnaBridge 125:2e9cc70d1897 264
AnnaBridge 125:2e9cc70d1897 265 The function sets section parity check
AnnaBridge 125:2e9cc70d1897 266
AnnaBridge 125:2e9cc70d1897 267 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 125:2e9cc70d1897 269
AnnaBridge 125:2e9cc70d1897 270 \return 0
AnnaBridge 125:2e9cc70d1897 271 */
AnnaBridge 125:2e9cc70d1897 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 125:2e9cc70d1897 273 {
AnnaBridge 125:2e9cc70d1897 274 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 125:2e9cc70d1897 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 125:2e9cc70d1897 276 return 0;
AnnaBridge 125:2e9cc70d1897 277 }
AnnaBridge 125:2e9cc70d1897 278
AnnaBridge 125:2e9cc70d1897 279 /** \brief Set section access privileges
AnnaBridge 125:2e9cc70d1897 280
AnnaBridge 125:2e9cc70d1897 281 The function sets section access privileges
AnnaBridge 125:2e9cc70d1897 282
AnnaBridge 125:2e9cc70d1897 283 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 125:2e9cc70d1897 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 125:2e9cc70d1897 286 \param [in] afe Access flag enable
AnnaBridge 125:2e9cc70d1897 287
AnnaBridge 125:2e9cc70d1897 288 \return 0
AnnaBridge 125:2e9cc70d1897 289 */
AnnaBridge 125:2e9cc70d1897 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 125:2e9cc70d1897 291 {
AnnaBridge 125:2e9cc70d1897 292 uint32_t ap = 0;
AnnaBridge 125:2e9cc70d1897 293
AnnaBridge 125:2e9cc70d1897 294 if (afe == 0) { //full access
AnnaBridge 125:2e9cc70d1897 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 125:2e9cc70d1897 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 125:2e9cc70d1897 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 125:2e9cc70d1897 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 125:2e9cc70d1897 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 125:2e9cc70d1897 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 125:2e9cc70d1897 301 }
AnnaBridge 125:2e9cc70d1897 302
AnnaBridge 125:2e9cc70d1897 303 else { //Simplified access
AnnaBridge 125:2e9cc70d1897 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 125:2e9cc70d1897 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 125:2e9cc70d1897 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 125:2e9cc70d1897 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 125:2e9cc70d1897 308 }
AnnaBridge 125:2e9cc70d1897 309
AnnaBridge 125:2e9cc70d1897 310 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 125:2e9cc70d1897 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 125:2e9cc70d1897 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 125:2e9cc70d1897 313
AnnaBridge 125:2e9cc70d1897 314 return 0;
AnnaBridge 125:2e9cc70d1897 315 }
AnnaBridge 125:2e9cc70d1897 316
AnnaBridge 125:2e9cc70d1897 317 /** \brief Set section shareability
AnnaBridge 125:2e9cc70d1897 318
AnnaBridge 125:2e9cc70d1897 319 The function sets section shareability
AnnaBridge 125:2e9cc70d1897 320
AnnaBridge 125:2e9cc70d1897 321 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 125:2e9cc70d1897 323
AnnaBridge 125:2e9cc70d1897 324 \return 0
AnnaBridge 125:2e9cc70d1897 325 */
AnnaBridge 125:2e9cc70d1897 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 125:2e9cc70d1897 327 {
AnnaBridge 125:2e9cc70d1897 328 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 125:2e9cc70d1897 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 125:2e9cc70d1897 330 return 0;
AnnaBridge 125:2e9cc70d1897 331 }
AnnaBridge 125:2e9cc70d1897 332
AnnaBridge 125:2e9cc70d1897 333 /** \brief Set section Global attribute
AnnaBridge 125:2e9cc70d1897 334
AnnaBridge 125:2e9cc70d1897 335 The function sets section Global attribute
AnnaBridge 125:2e9cc70d1897 336
AnnaBridge 125:2e9cc70d1897 337 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 125:2e9cc70d1897 339
AnnaBridge 125:2e9cc70d1897 340 \return 0
AnnaBridge 125:2e9cc70d1897 341 */
AnnaBridge 125:2e9cc70d1897 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 125:2e9cc70d1897 343 {
AnnaBridge 125:2e9cc70d1897 344 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 125:2e9cc70d1897 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 125:2e9cc70d1897 346 return 0;
AnnaBridge 125:2e9cc70d1897 347 }
AnnaBridge 125:2e9cc70d1897 348
AnnaBridge 125:2e9cc70d1897 349 /** \brief Set section Security attribute
AnnaBridge 125:2e9cc70d1897 350
AnnaBridge 125:2e9cc70d1897 351 The function sets section Global attribute
AnnaBridge 125:2e9cc70d1897 352
AnnaBridge 125:2e9cc70d1897 353 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 125:2e9cc70d1897 355
AnnaBridge 125:2e9cc70d1897 356 \return 0
AnnaBridge 125:2e9cc70d1897 357 */
AnnaBridge 125:2e9cc70d1897 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 125:2e9cc70d1897 359 {
AnnaBridge 125:2e9cc70d1897 360 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 125:2e9cc70d1897 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 125:2e9cc70d1897 362 return 0;
AnnaBridge 125:2e9cc70d1897 363 }
AnnaBridge 125:2e9cc70d1897 364
AnnaBridge 125:2e9cc70d1897 365 /* Page 4k or 64k */
AnnaBridge 125:2e9cc70d1897 366 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 125:2e9cc70d1897 367
AnnaBridge 125:2e9cc70d1897 368 The function sets 4k/64k page execution-never attribute
AnnaBridge 125:2e9cc70d1897 369
AnnaBridge 125:2e9cc70d1897 370 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 125:2e9cc70d1897 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 125:2e9cc70d1897 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 125:2e9cc70d1897 373
AnnaBridge 125:2e9cc70d1897 374 \return 0
AnnaBridge 125:2e9cc70d1897 375 */
AnnaBridge 125:2e9cc70d1897 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 125:2e9cc70d1897 377 {
AnnaBridge 125:2e9cc70d1897 378 if (page == PAGE_4k)
AnnaBridge 125:2e9cc70d1897 379 {
AnnaBridge 125:2e9cc70d1897 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 125:2e9cc70d1897 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 125:2e9cc70d1897 382 }
AnnaBridge 125:2e9cc70d1897 383 else
AnnaBridge 125:2e9cc70d1897 384 {
AnnaBridge 125:2e9cc70d1897 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 125:2e9cc70d1897 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 125:2e9cc70d1897 387 }
AnnaBridge 125:2e9cc70d1897 388 return 0;
AnnaBridge 125:2e9cc70d1897 389 }
AnnaBridge 125:2e9cc70d1897 390
AnnaBridge 125:2e9cc70d1897 391 /** \brief Set 4k/64k page domain
AnnaBridge 125:2e9cc70d1897 392
AnnaBridge 125:2e9cc70d1897 393 The function sets 4k/64k page domain
AnnaBridge 125:2e9cc70d1897 394
AnnaBridge 125:2e9cc70d1897 395 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 396 \param [in] domain Page domain
AnnaBridge 125:2e9cc70d1897 397
AnnaBridge 125:2e9cc70d1897 398 \return 0
AnnaBridge 125:2e9cc70d1897 399 */
AnnaBridge 125:2e9cc70d1897 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 125:2e9cc70d1897 401 {
AnnaBridge 125:2e9cc70d1897 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 125:2e9cc70d1897 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 125:2e9cc70d1897 404 return 0;
AnnaBridge 125:2e9cc70d1897 405 }
AnnaBridge 125:2e9cc70d1897 406
AnnaBridge 125:2e9cc70d1897 407 /** \brief Set 4k/64k page parity check
AnnaBridge 125:2e9cc70d1897 408
AnnaBridge 125:2e9cc70d1897 409 The function sets 4k/64k page parity check
AnnaBridge 125:2e9cc70d1897 410
AnnaBridge 125:2e9cc70d1897 411 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 125:2e9cc70d1897 413
AnnaBridge 125:2e9cc70d1897 414 \return 0
AnnaBridge 125:2e9cc70d1897 415 */
AnnaBridge 125:2e9cc70d1897 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 125:2e9cc70d1897 417 {
AnnaBridge 125:2e9cc70d1897 418 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 125:2e9cc70d1897 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 125:2e9cc70d1897 420 return 0;
AnnaBridge 125:2e9cc70d1897 421 }
AnnaBridge 125:2e9cc70d1897 422
AnnaBridge 125:2e9cc70d1897 423 /** \brief Set 4k/64k page access privileges
AnnaBridge 125:2e9cc70d1897 424
AnnaBridge 125:2e9cc70d1897 425 The function sets 4k/64k page access privileges
AnnaBridge 125:2e9cc70d1897 426
AnnaBridge 125:2e9cc70d1897 427 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 125:2e9cc70d1897 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 125:2e9cc70d1897 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 125:2e9cc70d1897 430 \param [in] afe Access flag enable
AnnaBridge 125:2e9cc70d1897 431
AnnaBridge 125:2e9cc70d1897 432 \return 0
AnnaBridge 125:2e9cc70d1897 433 */
AnnaBridge 125:2e9cc70d1897 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 125:2e9cc70d1897 435 {
AnnaBridge 125:2e9cc70d1897 436 uint32_t ap = 0;
AnnaBridge 125:2e9cc70d1897 437
AnnaBridge 125:2e9cc70d1897 438 if (afe == 0) { //full access
AnnaBridge 125:2e9cc70d1897 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 125:2e9cc70d1897 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 125:2e9cc70d1897 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 125:2e9cc70d1897 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 125:2e9cc70d1897 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 125:2e9cc70d1897 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 125:2e9cc70d1897 445 }
AnnaBridge 125:2e9cc70d1897 446
AnnaBridge 125:2e9cc70d1897 447 else { //Simplified access
AnnaBridge 125:2e9cc70d1897 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 125:2e9cc70d1897 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 125:2e9cc70d1897 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 125:2e9cc70d1897 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 125:2e9cc70d1897 452 }
AnnaBridge 125:2e9cc70d1897 453
AnnaBridge 125:2e9cc70d1897 454 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 125:2e9cc70d1897 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 125:2e9cc70d1897 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 125:2e9cc70d1897 457
AnnaBridge 125:2e9cc70d1897 458 return 0;
AnnaBridge 125:2e9cc70d1897 459 }
AnnaBridge 125:2e9cc70d1897 460
AnnaBridge 125:2e9cc70d1897 461 /** \brief Set 4k/64k page shareability
AnnaBridge 125:2e9cc70d1897 462
AnnaBridge 125:2e9cc70d1897 463 The function sets 4k/64k page shareability
AnnaBridge 125:2e9cc70d1897 464
AnnaBridge 125:2e9cc70d1897 465 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 125:2e9cc70d1897 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 125:2e9cc70d1897 467
AnnaBridge 125:2e9cc70d1897 468 \return 0
AnnaBridge 125:2e9cc70d1897 469 */
AnnaBridge 125:2e9cc70d1897 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 125:2e9cc70d1897 471 {
AnnaBridge 125:2e9cc70d1897 472 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 125:2e9cc70d1897 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 125:2e9cc70d1897 474 return 0;
AnnaBridge 125:2e9cc70d1897 475 }
AnnaBridge 125:2e9cc70d1897 476
AnnaBridge 125:2e9cc70d1897 477 /** \brief Set 4k/64k page Global attribute
AnnaBridge 125:2e9cc70d1897 478
AnnaBridge 125:2e9cc70d1897 479 The function sets 4k/64k page Global attribute
AnnaBridge 125:2e9cc70d1897 480
AnnaBridge 125:2e9cc70d1897 481 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 125:2e9cc70d1897 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 125:2e9cc70d1897 483
AnnaBridge 125:2e9cc70d1897 484 \return 0
AnnaBridge 125:2e9cc70d1897 485 */
AnnaBridge 125:2e9cc70d1897 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 125:2e9cc70d1897 487 {
AnnaBridge 125:2e9cc70d1897 488 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 125:2e9cc70d1897 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 125:2e9cc70d1897 490 return 0;
AnnaBridge 125:2e9cc70d1897 491 }
AnnaBridge 125:2e9cc70d1897 492
AnnaBridge 125:2e9cc70d1897 493 /** \brief Set 4k/64k page Security attribute
AnnaBridge 125:2e9cc70d1897 494
AnnaBridge 125:2e9cc70d1897 495 The function sets 4k/64k page Global attribute
AnnaBridge 125:2e9cc70d1897 496
AnnaBridge 125:2e9cc70d1897 497 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 125:2e9cc70d1897 499
AnnaBridge 125:2e9cc70d1897 500 \return 0
AnnaBridge 125:2e9cc70d1897 501 */
AnnaBridge 125:2e9cc70d1897 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 125:2e9cc70d1897 503 {
AnnaBridge 125:2e9cc70d1897 504 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 125:2e9cc70d1897 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 125:2e9cc70d1897 506 return 0;
AnnaBridge 125:2e9cc70d1897 507 }
AnnaBridge 125:2e9cc70d1897 508
AnnaBridge 125:2e9cc70d1897 509
AnnaBridge 125:2e9cc70d1897 510 /** \brief Set Section memory attributes
AnnaBridge 125:2e9cc70d1897 511
AnnaBridge 125:2e9cc70d1897 512 The function sets section memory attributes
AnnaBridge 125:2e9cc70d1897 513
AnnaBridge 125:2e9cc70d1897 514 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 125:2e9cc70d1897 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 125:2e9cc70d1897 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 125:2e9cc70d1897 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 125:2e9cc70d1897 518
AnnaBridge 125:2e9cc70d1897 519 \return 0
AnnaBridge 125:2e9cc70d1897 520 */
AnnaBridge 125:2e9cc70d1897 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 125:2e9cc70d1897 522 {
AnnaBridge 125:2e9cc70d1897 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 125:2e9cc70d1897 524
AnnaBridge 125:2e9cc70d1897 525 if (STRONGLY_ORDERED == mem)
AnnaBridge 125:2e9cc70d1897 526 {
AnnaBridge 125:2e9cc70d1897 527 return 0;
AnnaBridge 125:2e9cc70d1897 528 }
AnnaBridge 125:2e9cc70d1897 529 else if (SHARED_DEVICE == mem)
AnnaBridge 125:2e9cc70d1897 530 {
AnnaBridge 125:2e9cc70d1897 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 125:2e9cc70d1897 532 }
AnnaBridge 125:2e9cc70d1897 533 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 125:2e9cc70d1897 534 {
AnnaBridge 125:2e9cc70d1897 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 125:2e9cc70d1897 536 }
AnnaBridge 125:2e9cc70d1897 537 else if (NORMAL == mem)
AnnaBridge 125:2e9cc70d1897 538 {
AnnaBridge 125:2e9cc70d1897 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 125:2e9cc70d1897 540 switch(inner)
AnnaBridge 125:2e9cc70d1897 541 {
AnnaBridge 125:2e9cc70d1897 542 case NON_CACHEABLE:
AnnaBridge 125:2e9cc70d1897 543 break;
AnnaBridge 125:2e9cc70d1897 544 case WB_WA:
AnnaBridge 125:2e9cc70d1897 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 125:2e9cc70d1897 546 break;
AnnaBridge 125:2e9cc70d1897 547 case WT:
AnnaBridge 125:2e9cc70d1897 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 125:2e9cc70d1897 549 break;
AnnaBridge 125:2e9cc70d1897 550 case WB_NO_WA:
AnnaBridge 125:2e9cc70d1897 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 125:2e9cc70d1897 552 break;
AnnaBridge 125:2e9cc70d1897 553 }
AnnaBridge 125:2e9cc70d1897 554 switch(outer)
AnnaBridge 125:2e9cc70d1897 555 {
AnnaBridge 125:2e9cc70d1897 556 case NON_CACHEABLE:
AnnaBridge 125:2e9cc70d1897 557 break;
AnnaBridge 125:2e9cc70d1897 558 case WB_WA:
AnnaBridge 125:2e9cc70d1897 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 125:2e9cc70d1897 560 break;
AnnaBridge 125:2e9cc70d1897 561 case WT:
AnnaBridge 125:2e9cc70d1897 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 125:2e9cc70d1897 563 break;
AnnaBridge 125:2e9cc70d1897 564 case WB_NO_WA:
AnnaBridge 125:2e9cc70d1897 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 125:2e9cc70d1897 566 break;
AnnaBridge 125:2e9cc70d1897 567 }
AnnaBridge 125:2e9cc70d1897 568 }
AnnaBridge 125:2e9cc70d1897 569
AnnaBridge 125:2e9cc70d1897 570 return 0;
AnnaBridge 125:2e9cc70d1897 571 }
AnnaBridge 125:2e9cc70d1897 572
AnnaBridge 125:2e9cc70d1897 573 /** \brief Set 4k/64k page memory attributes
AnnaBridge 125:2e9cc70d1897 574
AnnaBridge 125:2e9cc70d1897 575 The function sets 4k/64k page memory attributes
AnnaBridge 125:2e9cc70d1897 576
AnnaBridge 125:2e9cc70d1897 577 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 125:2e9cc70d1897 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 125:2e9cc70d1897 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 125:2e9cc70d1897 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 125:2e9cc70d1897 581
AnnaBridge 125:2e9cc70d1897 582 \return 0
AnnaBridge 125:2e9cc70d1897 583 */
AnnaBridge 125:2e9cc70d1897 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 125:2e9cc70d1897 585 {
AnnaBridge 125:2e9cc70d1897 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 125:2e9cc70d1897 587
AnnaBridge 125:2e9cc70d1897 588 if (page == PAGE_64k)
AnnaBridge 125:2e9cc70d1897 589 {
AnnaBridge 125:2e9cc70d1897 590 //same as section
AnnaBridge 125:2e9cc70d1897 591 __memory_section(descriptor_l2, mem, outer, inner);
AnnaBridge 125:2e9cc70d1897 592 }
AnnaBridge 125:2e9cc70d1897 593 else
AnnaBridge 125:2e9cc70d1897 594 {
AnnaBridge 125:2e9cc70d1897 595 if (STRONGLY_ORDERED == mem)
AnnaBridge 125:2e9cc70d1897 596 {
AnnaBridge 125:2e9cc70d1897 597 return 0;
AnnaBridge 125:2e9cc70d1897 598 }
AnnaBridge 125:2e9cc70d1897 599 else if (SHARED_DEVICE == mem)
AnnaBridge 125:2e9cc70d1897 600 {
AnnaBridge 125:2e9cc70d1897 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 125:2e9cc70d1897 602 }
AnnaBridge 125:2e9cc70d1897 603 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 125:2e9cc70d1897 604 {
AnnaBridge 125:2e9cc70d1897 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 125:2e9cc70d1897 606 }
AnnaBridge 125:2e9cc70d1897 607 else if (NORMAL == mem)
AnnaBridge 125:2e9cc70d1897 608 {
AnnaBridge 125:2e9cc70d1897 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 125:2e9cc70d1897 610 switch(inner)
AnnaBridge 125:2e9cc70d1897 611 {
AnnaBridge 125:2e9cc70d1897 612 case NON_CACHEABLE:
AnnaBridge 125:2e9cc70d1897 613 break;
AnnaBridge 125:2e9cc70d1897 614 case WB_WA:
AnnaBridge 125:2e9cc70d1897 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 125:2e9cc70d1897 616 break;
AnnaBridge 125:2e9cc70d1897 617 case WT:
AnnaBridge 125:2e9cc70d1897 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 125:2e9cc70d1897 619 break;
AnnaBridge 125:2e9cc70d1897 620 case WB_NO_WA:
AnnaBridge 125:2e9cc70d1897 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 125:2e9cc70d1897 622 break;
AnnaBridge 125:2e9cc70d1897 623 }
AnnaBridge 125:2e9cc70d1897 624 switch(outer)
AnnaBridge 125:2e9cc70d1897 625 {
AnnaBridge 125:2e9cc70d1897 626 case NON_CACHEABLE:
AnnaBridge 125:2e9cc70d1897 627 break;
AnnaBridge 125:2e9cc70d1897 628 case WB_WA:
AnnaBridge 125:2e9cc70d1897 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 125:2e9cc70d1897 630 break;
AnnaBridge 125:2e9cc70d1897 631 case WT:
AnnaBridge 125:2e9cc70d1897 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 125:2e9cc70d1897 633 break;
AnnaBridge 125:2e9cc70d1897 634 case WB_NO_WA:
AnnaBridge 125:2e9cc70d1897 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 125:2e9cc70d1897 636 break;
AnnaBridge 125:2e9cc70d1897 637 }
AnnaBridge 125:2e9cc70d1897 638 }
AnnaBridge 125:2e9cc70d1897 639 }
AnnaBridge 125:2e9cc70d1897 640
AnnaBridge 125:2e9cc70d1897 641 return 0;
AnnaBridge 125:2e9cc70d1897 642 }
AnnaBridge 125:2e9cc70d1897 643
AnnaBridge 125:2e9cc70d1897 644 /** \brief Create a L1 section descriptor
AnnaBridge 125:2e9cc70d1897 645
AnnaBridge 125:2e9cc70d1897 646 The function creates a section descriptor.
AnnaBridge 125:2e9cc70d1897 647
AnnaBridge 125:2e9cc70d1897 648 Assumptions:
AnnaBridge 125:2e9cc70d1897 649 - 16MB super sections not supported
AnnaBridge 125:2e9cc70d1897 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 125:2e9cc70d1897 651 - Functions always return 0
AnnaBridge 125:2e9cc70d1897 652
AnnaBridge 125:2e9cc70d1897 653 \param [out] descriptor L1 descriptor
AnnaBridge 125:2e9cc70d1897 654 \param [out] descriptor2 L2 descriptor
AnnaBridge 125:2e9cc70d1897 655 \param [in] reg Section attributes
AnnaBridge 125:2e9cc70d1897 656
AnnaBridge 125:2e9cc70d1897 657 \return 0
AnnaBridge 125:2e9cc70d1897 658 */
AnnaBridge 125:2e9cc70d1897 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 125:2e9cc70d1897 660 {
AnnaBridge 125:2e9cc70d1897 661 *descriptor = 0;
AnnaBridge 125:2e9cc70d1897 662
AnnaBridge 125:2e9cc70d1897 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 125:2e9cc70d1897 664 __xn_section(descriptor,reg.xn_t);
AnnaBridge 125:2e9cc70d1897 665 __domain_section(descriptor, reg.domain);
AnnaBridge 125:2e9cc70d1897 666 __p_section(descriptor, reg.e_t);
AnnaBridge 125:2e9cc70d1897 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 125:2e9cc70d1897 668 __shared_section(descriptor,reg.sh_t);
AnnaBridge 125:2e9cc70d1897 669 __global_section(descriptor,reg.g_t);
AnnaBridge 125:2e9cc70d1897 670 __secure_section(descriptor,reg.sec_t);
AnnaBridge 125:2e9cc70d1897 671 *descriptor &= SECTION_MASK;
AnnaBridge 125:2e9cc70d1897 672 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 125:2e9cc70d1897 673
AnnaBridge 125:2e9cc70d1897 674 return 0;
AnnaBridge 125:2e9cc70d1897 675
AnnaBridge 125:2e9cc70d1897 676 }
AnnaBridge 125:2e9cc70d1897 677
AnnaBridge 125:2e9cc70d1897 678
AnnaBridge 125:2e9cc70d1897 679 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 125:2e9cc70d1897 680
AnnaBridge 125:2e9cc70d1897 681 The function creates a 4k/64k page descriptor.
AnnaBridge 125:2e9cc70d1897 682 Assumptions:
AnnaBridge 125:2e9cc70d1897 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 125:2e9cc70d1897 684 - Functions always return 0
AnnaBridge 125:2e9cc70d1897 685
AnnaBridge 125:2e9cc70d1897 686 \param [out] descriptor L1 descriptor
AnnaBridge 125:2e9cc70d1897 687 \param [out] descriptor2 L2 descriptor
AnnaBridge 125:2e9cc70d1897 688 \param [in] reg 4k/64k page attributes
AnnaBridge 125:2e9cc70d1897 689
AnnaBridge 125:2e9cc70d1897 690 \return 0
AnnaBridge 125:2e9cc70d1897 691 */
AnnaBridge 125:2e9cc70d1897 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 125:2e9cc70d1897 693 {
AnnaBridge 125:2e9cc70d1897 694 *descriptor = 0;
AnnaBridge 125:2e9cc70d1897 695 *descriptor2 = 0;
AnnaBridge 125:2e9cc70d1897 696
AnnaBridge 125:2e9cc70d1897 697 switch (reg.rg_t)
AnnaBridge 125:2e9cc70d1897 698 {
AnnaBridge 125:2e9cc70d1897 699 case PAGE_4k:
AnnaBridge 125:2e9cc70d1897 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 125:2e9cc70d1897 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 125:2e9cc70d1897 702 __domain_page(descriptor, reg.domain);
AnnaBridge 125:2e9cc70d1897 703 __p_page(descriptor, reg.e_t);
AnnaBridge 125:2e9cc70d1897 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 125:2e9cc70d1897 705 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 125:2e9cc70d1897 706 __global_page(descriptor2,reg.g_t);
AnnaBridge 125:2e9cc70d1897 707 __secure_page(descriptor,reg.sec_t);
AnnaBridge 125:2e9cc70d1897 708 *descriptor &= PAGE_L1_MASK;
AnnaBridge 125:2e9cc70d1897 709 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 125:2e9cc70d1897 710 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 125:2e9cc70d1897 711 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 125:2e9cc70d1897 712 break;
AnnaBridge 125:2e9cc70d1897 713
AnnaBridge 125:2e9cc70d1897 714 case PAGE_64k:
AnnaBridge 125:2e9cc70d1897 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 125:2e9cc70d1897 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 125:2e9cc70d1897 717 __domain_page(descriptor, reg.domain);
AnnaBridge 125:2e9cc70d1897 718 __p_page(descriptor, reg.e_t);
AnnaBridge 125:2e9cc70d1897 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 125:2e9cc70d1897 720 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 125:2e9cc70d1897 721 __global_page(descriptor2,reg.g_t);
AnnaBridge 125:2e9cc70d1897 722 __secure_page(descriptor,reg.sec_t);
AnnaBridge 125:2e9cc70d1897 723 *descriptor &= PAGE_L1_MASK;
AnnaBridge 125:2e9cc70d1897 724 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 125:2e9cc70d1897 725 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 125:2e9cc70d1897 726 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 125:2e9cc70d1897 727 break;
AnnaBridge 125:2e9cc70d1897 728
AnnaBridge 125:2e9cc70d1897 729 case SECTION:
AnnaBridge 125:2e9cc70d1897 730 //error
AnnaBridge 125:2e9cc70d1897 731 break;
AnnaBridge 125:2e9cc70d1897 732
AnnaBridge 125:2e9cc70d1897 733 }
AnnaBridge 125:2e9cc70d1897 734
AnnaBridge 125:2e9cc70d1897 735 return 0;
AnnaBridge 125:2e9cc70d1897 736
AnnaBridge 125:2e9cc70d1897 737 }
AnnaBridge 125:2e9cc70d1897 738
AnnaBridge 125:2e9cc70d1897 739 /** \brief Create a 1MB Section
AnnaBridge 125:2e9cc70d1897 740
AnnaBridge 125:2e9cc70d1897 741 \param [in] ttb Translation table base address
AnnaBridge 125:2e9cc70d1897 742 \param [in] base_address Section base address
AnnaBridge 125:2e9cc70d1897 743 \param [in] count Number of sections to create
AnnaBridge 125:2e9cc70d1897 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 125:2e9cc70d1897 745
AnnaBridge 125:2e9cc70d1897 746 */
AnnaBridge 125:2e9cc70d1897 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 125:2e9cc70d1897 748 {
AnnaBridge 125:2e9cc70d1897 749 uint32_t offset;
AnnaBridge 125:2e9cc70d1897 750 uint32_t entry;
AnnaBridge 125:2e9cc70d1897 751 uint32_t i;
AnnaBridge 125:2e9cc70d1897 752
AnnaBridge 125:2e9cc70d1897 753 offset = base_address >> 20;
AnnaBridge 125:2e9cc70d1897 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 125:2e9cc70d1897 755
AnnaBridge 125:2e9cc70d1897 756 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 757 ttb = ttb + offset;
AnnaBridge 125:2e9cc70d1897 758
AnnaBridge 125:2e9cc70d1897 759 for (i = 0; i < count; i++ )
AnnaBridge 125:2e9cc70d1897 760 {
AnnaBridge 125:2e9cc70d1897 761 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 762 *ttb++ = entry;
AnnaBridge 125:2e9cc70d1897 763 entry += OFFSET_1M;
AnnaBridge 125:2e9cc70d1897 764 }
AnnaBridge 125:2e9cc70d1897 765 }
AnnaBridge 125:2e9cc70d1897 766
AnnaBridge 125:2e9cc70d1897 767 /** \brief Create a 4k page entry
AnnaBridge 125:2e9cc70d1897 768
AnnaBridge 125:2e9cc70d1897 769 \param [in] ttb L1 table base address
AnnaBridge 125:2e9cc70d1897 770 \param [in] base_address 4k base address
AnnaBridge 125:2e9cc70d1897 771 \param [in] count Number of 4k pages to create
AnnaBridge 125:2e9cc70d1897 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 125:2e9cc70d1897 773 \param [in] ttb_l2 L2 table base address
AnnaBridge 125:2e9cc70d1897 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 125:2e9cc70d1897 775
AnnaBridge 125:2e9cc70d1897 776 */
AnnaBridge 125:2e9cc70d1897 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 125:2e9cc70d1897 778 {
AnnaBridge 125:2e9cc70d1897 779
AnnaBridge 125:2e9cc70d1897 780 uint32_t offset, offset2;
AnnaBridge 125:2e9cc70d1897 781 uint32_t entry, entry2;
AnnaBridge 125:2e9cc70d1897 782 uint32_t i;
AnnaBridge 125:2e9cc70d1897 783
AnnaBridge 125:2e9cc70d1897 784
AnnaBridge 125:2e9cc70d1897 785 offset = base_address >> 20;
AnnaBridge 125:2e9cc70d1897 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 125:2e9cc70d1897 787
AnnaBridge 125:2e9cc70d1897 788 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 789 ttb += offset;
AnnaBridge 125:2e9cc70d1897 790 //create l1_entry
AnnaBridge 125:2e9cc70d1897 791 *ttb = entry;
AnnaBridge 125:2e9cc70d1897 792
AnnaBridge 125:2e9cc70d1897 793 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 125:2e9cc70d1897 794 ttb_l2 += offset2;
AnnaBridge 125:2e9cc70d1897 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 125:2e9cc70d1897 796 for (i = 0; i < count; i++ )
AnnaBridge 125:2e9cc70d1897 797 {
AnnaBridge 125:2e9cc70d1897 798 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 799 *ttb_l2++ = entry2;
AnnaBridge 125:2e9cc70d1897 800 entry2 += OFFSET_4K;
AnnaBridge 125:2e9cc70d1897 801 }
AnnaBridge 125:2e9cc70d1897 802 }
AnnaBridge 125:2e9cc70d1897 803
AnnaBridge 125:2e9cc70d1897 804 /** \brief Create a 64k page entry
AnnaBridge 125:2e9cc70d1897 805
AnnaBridge 125:2e9cc70d1897 806 \param [in] ttb L1 table base address
AnnaBridge 125:2e9cc70d1897 807 \param [in] base_address 64k base address
AnnaBridge 125:2e9cc70d1897 808 \param [in] count Number of 64k pages to create
AnnaBridge 125:2e9cc70d1897 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 125:2e9cc70d1897 810 \param [in] ttb_l2 L2 table base address
AnnaBridge 125:2e9cc70d1897 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 125:2e9cc70d1897 812
AnnaBridge 125:2e9cc70d1897 813 */
AnnaBridge 125:2e9cc70d1897 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 125:2e9cc70d1897 815 {
AnnaBridge 125:2e9cc70d1897 816 uint32_t offset, offset2;
AnnaBridge 125:2e9cc70d1897 817 uint32_t entry, entry2;
AnnaBridge 125:2e9cc70d1897 818 uint32_t i,j;
AnnaBridge 125:2e9cc70d1897 819
AnnaBridge 125:2e9cc70d1897 820
AnnaBridge 125:2e9cc70d1897 821 offset = base_address >> 20;
AnnaBridge 125:2e9cc70d1897 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 125:2e9cc70d1897 823
AnnaBridge 125:2e9cc70d1897 824 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 825 ttb += offset;
AnnaBridge 125:2e9cc70d1897 826 //create l1_entry
AnnaBridge 125:2e9cc70d1897 827 *ttb = entry;
AnnaBridge 125:2e9cc70d1897 828
AnnaBridge 125:2e9cc70d1897 829 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 125:2e9cc70d1897 830 ttb_l2 += offset2;
AnnaBridge 125:2e9cc70d1897 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 125:2e9cc70d1897 832 for (i = 0; i < count; i++ )
AnnaBridge 125:2e9cc70d1897 833 {
AnnaBridge 125:2e9cc70d1897 834 //create 16 entries
AnnaBridge 125:2e9cc70d1897 835 for (j = 0; j < 16; j++)
AnnaBridge 125:2e9cc70d1897 836 //4 bytes aligned
AnnaBridge 125:2e9cc70d1897 837 *ttb_l2++ = entry2;
AnnaBridge 125:2e9cc70d1897 838 entry2 += OFFSET_64K;
AnnaBridge 125:2e9cc70d1897 839 }
AnnaBridge 125:2e9cc70d1897 840 }
AnnaBridge 125:2e9cc70d1897 841
AnnaBridge 125:2e9cc70d1897 842 /*@} end of MMU_Functions */
AnnaBridge 125:2e9cc70d1897 843 #endif
AnnaBridge 125:2e9cc70d1897 844
AnnaBridge 125:2e9cc70d1897 845 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 846 }
AnnaBridge 125:2e9cc70d1897 847 #endif