mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620HSP/core_ca9.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
125:2e9cc70d1897 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 /**************************************************************************//**
AnnaBridge 125:2e9cc70d1897 2 * @file core_ca9.h
AnnaBridge 125:2e9cc70d1897 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
AnnaBridge 125:2e9cc70d1897 4 * @version
AnnaBridge 125:2e9cc70d1897 5 * @date 25 March 2013
AnnaBridge 125:2e9cc70d1897 6 *
AnnaBridge 125:2e9cc70d1897 7 * @note
AnnaBridge 125:2e9cc70d1897 8 *
AnnaBridge 125:2e9cc70d1897 9 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
AnnaBridge 125:2e9cc70d1897 11
AnnaBridge 125:2e9cc70d1897 12 All rights reserved.
AnnaBridge 125:2e9cc70d1897 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 125:2e9cc70d1897 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 125:2e9cc70d1897 15 - Redistributions of source code must retain the above copyright
AnnaBridge 125:2e9cc70d1897 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 125:2e9cc70d1897 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 125:2e9cc70d1897 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 125:2e9cc70d1897 19 documentation and/or other materials provided with the distribution.
AnnaBridge 125:2e9cc70d1897 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 125:2e9cc70d1897 21 to endorse or promote products derived from this software without
AnnaBridge 125:2e9cc70d1897 22 specific prior written permission.
AnnaBridge 125:2e9cc70d1897 23 *
AnnaBridge 125:2e9cc70d1897 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 125:2e9cc70d1897 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 125:2e9cc70d1897 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 125:2e9cc70d1897 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 125:2e9cc70d1897 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 125:2e9cc70d1897 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 125:2e9cc70d1897 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 125:2e9cc70d1897 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 125:2e9cc70d1897 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 125:2e9cc70d1897 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 125:2e9cc70d1897 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 125:2e9cc70d1897 35 ---------------------------------------------------------------------------*/
AnnaBridge 125:2e9cc70d1897 36
AnnaBridge 125:2e9cc70d1897 37
AnnaBridge 125:2e9cc70d1897 38 #if defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 125:2e9cc70d1897 40 #endif
AnnaBridge 125:2e9cc70d1897 41
AnnaBridge 125:2e9cc70d1897 42 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 43 extern "C" {
AnnaBridge 125:2e9cc70d1897 44 #endif
AnnaBridge 125:2e9cc70d1897 45
AnnaBridge 125:2e9cc70d1897 46 #ifndef __CORE_CA9_H_GENERIC
AnnaBridge 125:2e9cc70d1897 47 #define __CORE_CA9_H_GENERIC
AnnaBridge 125:2e9cc70d1897 48
AnnaBridge 125:2e9cc70d1897 49
AnnaBridge 125:2e9cc70d1897 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 125:2e9cc70d1897 51 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 125:2e9cc70d1897 52
AnnaBridge 125:2e9cc70d1897 53 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 125:2e9cc70d1897 54 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 125:2e9cc70d1897 55
AnnaBridge 125:2e9cc70d1897 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 125:2e9cc70d1897 57 Unions are used for effective representation of core registers.
AnnaBridge 125:2e9cc70d1897 58
AnnaBridge 125:2e9cc70d1897 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 125:2e9cc70d1897 60 Function-like macros are used to allow more efficient code.
AnnaBridge 125:2e9cc70d1897 61 */
AnnaBridge 125:2e9cc70d1897 62
AnnaBridge 125:2e9cc70d1897 63
AnnaBridge 125:2e9cc70d1897 64 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 65 * CMSIS definitions
AnnaBridge 125:2e9cc70d1897 66 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 67 /** \ingroup Cortex_A9
AnnaBridge 125:2e9cc70d1897 68 @{
AnnaBridge 125:2e9cc70d1897 69 */
AnnaBridge 125:2e9cc70d1897 70
AnnaBridge 125:2e9cc70d1897 71 /* CMSIS CA9 definitions */
AnnaBridge 125:2e9cc70d1897 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 125:2e9cc70d1897 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 125:2e9cc70d1897 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 125:2e9cc70d1897 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 125:2e9cc70d1897 76
AnnaBridge 125:2e9cc70d1897 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
AnnaBridge 125:2e9cc70d1897 78
AnnaBridge 125:2e9cc70d1897 79
AnnaBridge 125:2e9cc70d1897 80 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 125:2e9cc70d1897 83 #define __STATIC_INLINE static __inline
AnnaBridge 125:2e9cc70d1897 84 #define __STATIC_ASM static __asm
AnnaBridge 125:2e9cc70d1897 85
AnnaBridge 125:2e9cc70d1897 86 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 125:2e9cc70d1897 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 125:2e9cc70d1897 89 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 90 #define __STATIC_ASM static __asm
AnnaBridge 125:2e9cc70d1897 91
AnnaBridge 125:2e9cc70d1897 92 #include <stdint.h>
AnnaBridge 125:2e9cc70d1897 93 inline uint32_t __get_PSR(void) {
AnnaBridge 125:2e9cc70d1897 94 __ASM("mrs r0, cpsr");
AnnaBridge 125:2e9cc70d1897 95 }
AnnaBridge 125:2e9cc70d1897 96
AnnaBridge 125:2e9cc70d1897 97 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 125:2e9cc70d1897 99 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 100 #define __STATIC_ASM static __asm
AnnaBridge 125:2e9cc70d1897 101
AnnaBridge 125:2e9cc70d1897 102 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 125:2e9cc70d1897 105 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 106 #define __STATIC_ASM static __asm
AnnaBridge 125:2e9cc70d1897 107
AnnaBridge 125:2e9cc70d1897 108 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 125:2e9cc70d1897 111 #define __STATIC_INLINE static inline
AnnaBridge 125:2e9cc70d1897 112 #define __STATIC_ASM static __asm
AnnaBridge 125:2e9cc70d1897 113
AnnaBridge 125:2e9cc70d1897 114 #endif
AnnaBridge 125:2e9cc70d1897 115
AnnaBridge 125:2e9cc70d1897 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge 125:2e9cc70d1897 117 */
AnnaBridge 125:2e9cc70d1897 118 #if defined ( __CC_ARM )
AnnaBridge 125:2e9cc70d1897 119 #if defined __TARGET_FPU_VFP
AnnaBridge 125:2e9cc70d1897 120 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 121 #define __FPU_USED 1
AnnaBridge 125:2e9cc70d1897 122 #else
AnnaBridge 125:2e9cc70d1897 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 124 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 125 #endif
AnnaBridge 125:2e9cc70d1897 126 #else
AnnaBridge 125:2e9cc70d1897 127 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 128 #endif
AnnaBridge 125:2e9cc70d1897 129
AnnaBridge 125:2e9cc70d1897 130 #elif defined ( __ICCARM__ )
AnnaBridge 125:2e9cc70d1897 131 #if defined __ARMVFP__
AnnaBridge 125:2e9cc70d1897 132 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 133 #define __FPU_USED 1
AnnaBridge 125:2e9cc70d1897 134 #else
AnnaBridge 125:2e9cc70d1897 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 136 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 137 #endif
AnnaBridge 125:2e9cc70d1897 138 #else
AnnaBridge 125:2e9cc70d1897 139 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 140 #endif
AnnaBridge 125:2e9cc70d1897 141
AnnaBridge 125:2e9cc70d1897 142 #elif defined ( __TMS470__ )
AnnaBridge 125:2e9cc70d1897 143 #if defined __TI_VFP_SUPPORT__
AnnaBridge 125:2e9cc70d1897 144 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 145 #define __FPU_USED 1
AnnaBridge 125:2e9cc70d1897 146 #else
AnnaBridge 125:2e9cc70d1897 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 148 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 149 #endif
AnnaBridge 125:2e9cc70d1897 150 #else
AnnaBridge 125:2e9cc70d1897 151 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 152 #endif
AnnaBridge 125:2e9cc70d1897 153
AnnaBridge 125:2e9cc70d1897 154 #elif defined ( __GNUC__ )
AnnaBridge 125:2e9cc70d1897 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 125:2e9cc70d1897 156 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 157 #define __FPU_USED 1
AnnaBridge 125:2e9cc70d1897 158 #else
AnnaBridge 125:2e9cc70d1897 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 160 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 161 #endif
AnnaBridge 125:2e9cc70d1897 162 #else
AnnaBridge 125:2e9cc70d1897 163 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 164 #endif
AnnaBridge 125:2e9cc70d1897 165
AnnaBridge 125:2e9cc70d1897 166 #elif defined ( __TASKING__ )
AnnaBridge 125:2e9cc70d1897 167 #if defined __FPU_VFP__
AnnaBridge 125:2e9cc70d1897 168 #if (__FPU_PRESENT == 1)
AnnaBridge 125:2e9cc70d1897 169 #define __FPU_USED 1
AnnaBridge 125:2e9cc70d1897 170 #else
AnnaBridge 125:2e9cc70d1897 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 125:2e9cc70d1897 172 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 173 #endif
AnnaBridge 125:2e9cc70d1897 174 #else
AnnaBridge 125:2e9cc70d1897 175 #define __FPU_USED 0
AnnaBridge 125:2e9cc70d1897 176 #endif
AnnaBridge 125:2e9cc70d1897 177 #endif
AnnaBridge 125:2e9cc70d1897 178
AnnaBridge 125:2e9cc70d1897 179 #include <stdint.h> /*!< standard types definitions */
AnnaBridge 125:2e9cc70d1897 180 #include "core_caInstr.h" /*!< Core Instruction Access */
AnnaBridge 125:2e9cc70d1897 181 #include "core_caFunc.h" /*!< Core Function Access */
AnnaBridge 125:2e9cc70d1897 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
AnnaBridge 125:2e9cc70d1897 183
AnnaBridge 125:2e9cc70d1897 184 #endif /* __CORE_CA9_H_GENERIC */
AnnaBridge 125:2e9cc70d1897 185
AnnaBridge 125:2e9cc70d1897 186 #ifndef __CMSIS_GENERIC
AnnaBridge 125:2e9cc70d1897 187
AnnaBridge 125:2e9cc70d1897 188 #ifndef __CORE_CA9_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 189 #define __CORE_CA9_H_DEPENDANT
AnnaBridge 125:2e9cc70d1897 190
AnnaBridge 125:2e9cc70d1897 191 /* check device defines and use defaults */
AnnaBridge 125:2e9cc70d1897 192 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 125:2e9cc70d1897 193 #ifndef __CA9_REV
AnnaBridge 125:2e9cc70d1897 194 #define __CA9_REV 0x0000
AnnaBridge 125:2e9cc70d1897 195 #warning "__CA9_REV not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 196 #endif
AnnaBridge 125:2e9cc70d1897 197
AnnaBridge 125:2e9cc70d1897 198 #ifndef __FPU_PRESENT
AnnaBridge 125:2e9cc70d1897 199 #define __FPU_PRESENT 1
AnnaBridge 125:2e9cc70d1897 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 125:2e9cc70d1897 201 #endif
AnnaBridge 125:2e9cc70d1897 202
AnnaBridge 125:2e9cc70d1897 203 #ifndef __Vendor_SysTickConfig
AnnaBridge 125:2e9cc70d1897 204 #define __Vendor_SysTickConfig 1
AnnaBridge 125:2e9cc70d1897 205 #endif
AnnaBridge 125:2e9cc70d1897 206
AnnaBridge 125:2e9cc70d1897 207 #if __Vendor_SysTickConfig == 0
AnnaBridge 125:2e9cc70d1897 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
AnnaBridge 125:2e9cc70d1897 209 #endif
AnnaBridge 125:2e9cc70d1897 210 #endif
AnnaBridge 125:2e9cc70d1897 211
AnnaBridge 125:2e9cc70d1897 212 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 125:2e9cc70d1897 213 /**
AnnaBridge 125:2e9cc70d1897 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 125:2e9cc70d1897 215
AnnaBridge 125:2e9cc70d1897 216 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 125:2e9cc70d1897 217 \li to specify the access to peripheral variables.
AnnaBridge 125:2e9cc70d1897 218 \li for automatic generation of peripheral register debug information.
AnnaBridge 125:2e9cc70d1897 219 */
AnnaBridge 125:2e9cc70d1897 220 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 221 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 222 #else
AnnaBridge 125:2e9cc70d1897 223 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 125:2e9cc70d1897 224 #endif
AnnaBridge 125:2e9cc70d1897 225 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 125:2e9cc70d1897 226 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 125:2e9cc70d1897 227
AnnaBridge 125:2e9cc70d1897 228 /*@} end of group Cortex_A9 */
AnnaBridge 125:2e9cc70d1897 229
AnnaBridge 125:2e9cc70d1897 230
AnnaBridge 125:2e9cc70d1897 231 /*******************************************************************************
AnnaBridge 125:2e9cc70d1897 232 * Register Abstraction
AnnaBridge 125:2e9cc70d1897 233 ******************************************************************************/
AnnaBridge 125:2e9cc70d1897 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 125:2e9cc70d1897 235 \brief Type definitions and defines for Cortex-A processor based devices.
AnnaBridge 125:2e9cc70d1897 236 */
AnnaBridge 125:2e9cc70d1897 237
AnnaBridge 125:2e9cc70d1897 238 /** \ingroup CMSIS_core_register
AnnaBridge 125:2e9cc70d1897 239 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 125:2e9cc70d1897 240 \brief Core Register type definitions.
AnnaBridge 125:2e9cc70d1897 241 @{
AnnaBridge 125:2e9cc70d1897 242 */
AnnaBridge 125:2e9cc70d1897 243
AnnaBridge 125:2e9cc70d1897 244 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 125:2e9cc70d1897 245 */
AnnaBridge 125:2e9cc70d1897 246 typedef union
AnnaBridge 125:2e9cc70d1897 247 {
AnnaBridge 125:2e9cc70d1897 248 struct
AnnaBridge 125:2e9cc70d1897 249 {
AnnaBridge 125:2e9cc70d1897 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
AnnaBridge 125:2e9cc70d1897 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 125:2e9cc70d1897 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
AnnaBridge 125:2e9cc70d1897 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 125:2e9cc70d1897 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 125:2e9cc70d1897 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 125:2e9cc70d1897 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 125:2e9cc70d1897 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 125:2e9cc70d1897 258 } b; /*!< Structure used for bit access */
AnnaBridge 125:2e9cc70d1897 259 uint32_t w; /*!< Type used for word access */
AnnaBridge 125:2e9cc70d1897 260 } APSR_Type;
AnnaBridge 125:2e9cc70d1897 261
AnnaBridge 125:2e9cc70d1897 262
AnnaBridge 125:2e9cc70d1897 263 /*@} end of group CMSIS_CORE */
AnnaBridge 125:2e9cc70d1897 264
AnnaBridge 125:2e9cc70d1897 265 /*@} end of CMSIS_Core_FPUFunctions */
AnnaBridge 125:2e9cc70d1897 266
AnnaBridge 125:2e9cc70d1897 267
AnnaBridge 125:2e9cc70d1897 268 #endif /* __CORE_CA9_H_GENERIC */
AnnaBridge 125:2e9cc70d1897 269
AnnaBridge 125:2e9cc70d1897 270 #endif /* __CMSIS_GENERIC */
AnnaBridge 125:2e9cc70d1897 271
AnnaBridge 125:2e9cc70d1897 272 #ifdef __cplusplus
AnnaBridge 125:2e9cc70d1897 273 }
AnnaBridge 125:2e9cc70d1897 274
AnnaBridge 125:2e9cc70d1897 275
AnnaBridge 125:2e9cc70d1897 276 #endif