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TARGET_LPC4337/core_cm4.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 12:05:23 2017 +0000
Revision:: 134:ad3be0349dc5
Parent:: 131:faff56e089b2
Child:: 145:64910690c574

Release 134 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	88:9327015d4013	1	/************************************************************************//
bogdanm	88:9327015d4013	2	* @file core_cm4.h
bogdanm	88:9327015d4013	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Kojto	110:165afa46840b	4	* @version V4.10
Kojto	110:165afa46840b	5	* @date 18. March 2015
bogdanm	88:9327015d4013	6	*
bogdanm	88:9327015d4013	7	* @note
bogdanm	88:9327015d4013	8	*
bogdanm	88:9327015d4013	9	******************************************************************************/
Kojto	110:165afa46840b	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm	88:9327015d4013	11
bogdanm	88:9327015d4013	12	All rights reserved.
bogdanm	88:9327015d4013	13	Redistribution and use in source and binary forms, with or without
bogdanm	88:9327015d4013	14	modification, are permitted provided that the following conditions are met:
bogdanm	88:9327015d4013	15	- Redistributions of source code must retain the above copyright
bogdanm	88:9327015d4013	16	notice, this list of conditions and the following disclaimer.
bogdanm	88:9327015d4013	17	- Redistributions in binary form must reproduce the above copyright
bogdanm	88:9327015d4013	18	notice, this list of conditions and the following disclaimer in the
bogdanm	88:9327015d4013	19	documentation and/or other materials provided with the distribution.
bogdanm	88:9327015d4013	20	- Neither the name of ARM nor the names of its contributors may be used
bogdanm	88:9327015d4013	21	to endorse or promote products derived from this software without
bogdanm	88:9327015d4013	22	specific prior written permission.
bogdanm	88:9327015d4013	23	*
bogdanm	88:9327015d4013	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	88:9327015d4013	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	88:9327015d4013	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm	88:9327015d4013	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm	88:9327015d4013	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm	88:9327015d4013	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm	88:9327015d4013	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	88:9327015d4013	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	88:9327015d4013	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm	88:9327015d4013	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm	88:9327015d4013	34	POSSIBILITY OF SUCH DAMAGE.
bogdanm	88:9327015d4013	35	---------------------------------------------------------------------------*/
bogdanm	88:9327015d4013	36
bogdanm	88:9327015d4013	37
bogdanm	88:9327015d4013	38	#if defined ( __ICCARM__ )
bogdanm	88:9327015d4013	39	#pragma system_include /* treat file as system include file for MISRA check */
bogdanm	88:9327015d4013	40	#endif
bogdanm	88:9327015d4013	41
Kojto	110:165afa46840b	42	#ifndef __CORE_CM4_H_GENERIC
Kojto	110:165afa46840b	43	#define __CORE_CM4_H_GENERIC
Kojto	110:165afa46840b	44
bogdanm	88:9327015d4013	45	#ifdef __cplusplus
bogdanm	88:9327015d4013	46	extern "C" {
bogdanm	88:9327015d4013	47	#endif
bogdanm	88:9327015d4013	48
bogdanm	88:9327015d4013	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm	88:9327015d4013	50	CMSIS violates the following MISRA-C:2004 rules:
bogdanm	88:9327015d4013	51
bogdanm	88:9327015d4013	52	\li Required Rule 8.5, object/function definition in header file.<br>
bogdanm	88:9327015d4013	53	Function definitions in header files are used to allow 'inlining'.
bogdanm	88:9327015d4013	54
bogdanm	88:9327015d4013	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm	88:9327015d4013	56	Unions are used for effective representation of core registers.
bogdanm	88:9327015d4013	57
bogdanm	88:9327015d4013	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm	88:9327015d4013	59	Function-like macros are used to allow more efficient code.
bogdanm	88:9327015d4013	60	*/
bogdanm	88:9327015d4013	61
bogdanm	88:9327015d4013	62
bogdanm	88:9327015d4013	63	/*******************************************************************************
bogdanm	88:9327015d4013	64	* CMSIS definitions
bogdanm	88:9327015d4013	65	******************************************************************************/
bogdanm	88:9327015d4013	66	/** \ingroup Cortex_M4
bogdanm	88:9327015d4013	67	@{
bogdanm	88:9327015d4013	68	*/
bogdanm	88:9327015d4013	69
bogdanm	88:9327015d4013	70	/* CMSIS CM4 definitions */
Kojto	110:165afa46840b	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	110:165afa46840b	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
bogdanm	88:9327015d4013	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
bogdanm	88:9327015d4013	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
bogdanm	88:9327015d4013	75
bogdanm	88:9327015d4013	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
bogdanm	88:9327015d4013	77
bogdanm	88:9327015d4013	78
bogdanm	88:9327015d4013	79	#if defined ( __CC_ARM )
bogdanm	88:9327015d4013	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
bogdanm	88:9327015d4013	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
bogdanm	88:9327015d4013	82	#define __STATIC_INLINE static __inline
bogdanm	88:9327015d4013	83
Kojto	110:165afa46840b	84	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	110:165afa46840b	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	110:165afa46840b	87	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	88
bogdanm	88:9327015d4013	89	#elif defined ( __ICCARM__ )
bogdanm	88:9327015d4013	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
bogdanm	88:9327015d4013	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
bogdanm	88:9327015d4013	92	#define __STATIC_INLINE static inline
bogdanm	88:9327015d4013	93
bogdanm	88:9327015d4013	94	#elif defined ( __TMS470__ )
bogdanm	88:9327015d4013	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
bogdanm	88:9327015d4013	96	#define __STATIC_INLINE static inline
bogdanm	88:9327015d4013	97
bogdanm	88:9327015d4013	98	#elif defined ( __TASKING__ )
bogdanm	88:9327015d4013	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
bogdanm	88:9327015d4013	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
bogdanm	88:9327015d4013	101	#define __STATIC_INLINE static inline
bogdanm	88:9327015d4013	102
Kojto	110:165afa46840b	103	#elif defined ( __CSMC__ )
Kojto	110:165afa46840b	104	#define __packed
Kojto	110:165afa46840b	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	110:165afa46840b	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	110:165afa46840b	107	#define __STATIC_INLINE static inline
Kojto	110:165afa46840b	108
bogdanm	88:9327015d4013	109	#endif
bogdanm	88:9327015d4013	110
Kojto	110:165afa46840b	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	110:165afa46840b	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
bogdanm	88:9327015d4013	113	*/
bogdanm	88:9327015d4013	114	#if defined ( __CC_ARM )
bogdanm	88:9327015d4013	115	#if defined __TARGET_FPU_VFP
bogdanm	88:9327015d4013	116	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	117	#define __FPU_USED 1
bogdanm	88:9327015d4013	118	#else
bogdanm	88:9327015d4013	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	88:9327015d4013	120	#define __FPU_USED 0
bogdanm	88:9327015d4013	121	#endif
bogdanm	88:9327015d4013	122	#else
bogdanm	88:9327015d4013	123	#define __FPU_USED 0
bogdanm	88:9327015d4013	124	#endif
bogdanm	88:9327015d4013	125
Kojto	110:165afa46840b	126	#elif defined ( __GNUC__ )
Kojto	110:165afa46840b	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	110:165afa46840b	128	#if (__FPU_PRESENT == 1)
Kojto	110:165afa46840b	129	#define __FPU_USED 1
Kojto	110:165afa46840b	130	#else
Kojto	110:165afa46840b	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	110:165afa46840b	132	#define __FPU_USED 0
Kojto	110:165afa46840b	133	#endif
Kojto	110:165afa46840b	134	#else
Kojto	110:165afa46840b	135	#define __FPU_USED 0
Kojto	110:165afa46840b	136	#endif
Kojto	110:165afa46840b	137
bogdanm	88:9327015d4013	138	#elif defined ( __ICCARM__ )
bogdanm	88:9327015d4013	139	#if defined __ARMVFP__
bogdanm	88:9327015d4013	140	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	141	#define __FPU_USED 1
bogdanm	88:9327015d4013	142	#else
bogdanm	88:9327015d4013	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	88:9327015d4013	144	#define __FPU_USED 0
bogdanm	88:9327015d4013	145	#endif
bogdanm	88:9327015d4013	146	#else
bogdanm	88:9327015d4013	147	#define __FPU_USED 0
bogdanm	88:9327015d4013	148	#endif
bogdanm	88:9327015d4013	149
bogdanm	88:9327015d4013	150	#elif defined ( __TMS470__ )
bogdanm	88:9327015d4013	151	#if defined __TI_VFP_SUPPORT__
bogdanm	88:9327015d4013	152	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	153	#define __FPU_USED 1
bogdanm	88:9327015d4013	154	#else
bogdanm	88:9327015d4013	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	88:9327015d4013	156	#define __FPU_USED 0
bogdanm	88:9327015d4013	157	#endif
bogdanm	88:9327015d4013	158	#else
bogdanm	88:9327015d4013	159	#define __FPU_USED 0
bogdanm	88:9327015d4013	160	#endif
bogdanm	88:9327015d4013	161
Kojto	110:165afa46840b	162	#elif defined ( __TASKING__ )
Kojto	110:165afa46840b	163	#if defined __FPU_VFP__
bogdanm	88:9327015d4013	164	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	165	#define __FPU_USED 1
bogdanm	88:9327015d4013	166	#else
Kojto	110:165afa46840b	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	88:9327015d4013	168	#define __FPU_USED 0
bogdanm	88:9327015d4013	169	#endif
bogdanm	88:9327015d4013	170	#else
bogdanm	88:9327015d4013	171	#define __FPU_USED 0
bogdanm	88:9327015d4013	172	#endif
bogdanm	88:9327015d4013	173
Kojto	110:165afa46840b	174	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	110:165afa46840b	175	#if ( __CSMC__ & 0x400) // FPU present for parser
bogdanm	88:9327015d4013	176	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	177	#define __FPU_USED 1
bogdanm	88:9327015d4013	178	#else
bogdanm	88:9327015d4013	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	88:9327015d4013	180	#define __FPU_USED 0
bogdanm	88:9327015d4013	181	#endif
bogdanm	88:9327015d4013	182	#else
bogdanm	88:9327015d4013	183	#define __FPU_USED 0
bogdanm	88:9327015d4013	184	#endif
bogdanm	88:9327015d4013	185	#endif
bogdanm	88:9327015d4013	186
bogdanm	88:9327015d4013	187	#include <stdint.h> /* standard types definitions */
bogdanm	88:9327015d4013	188	#include <core_cmInstr.h> /* Core Instruction Access */
bogdanm	88:9327015d4013	189	#include <core_cmFunc.h> /* Core Function Access */
Kojto	110:165afa46840b	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto	110:165afa46840b	191
Kojto	110:165afa46840b	192	#ifdef __cplusplus
Kojto	110:165afa46840b	193	}
Kojto	110:165afa46840b	194	#endif
bogdanm	88:9327015d4013	195
bogdanm	88:9327015d4013	196	#endif /* __CORE_CM4_H_GENERIC */
bogdanm	88:9327015d4013	197
bogdanm	88:9327015d4013	198	#ifndef __CMSIS_GENERIC
bogdanm	88:9327015d4013	199
bogdanm	88:9327015d4013	200	#ifndef __CORE_CM4_H_DEPENDANT
bogdanm	88:9327015d4013	201	#define __CORE_CM4_H_DEPENDANT
bogdanm	88:9327015d4013	202
Kojto	110:165afa46840b	203	#ifdef __cplusplus
Kojto	110:165afa46840b	204	extern "C" {
Kojto	110:165afa46840b	205	#endif
Kojto	110:165afa46840b	206
bogdanm	88:9327015d4013	207	/* check device defines and use defaults */
bogdanm	88:9327015d4013	208	#if defined __CHECK_DEVICE_DEFINES
bogdanm	88:9327015d4013	209	#ifndef __CM4_REV
bogdanm	88:9327015d4013	210	#define __CM4_REV 0x0000
bogdanm	88:9327015d4013	211	#warning "__CM4_REV not defined in device header file; using default!"
bogdanm	88:9327015d4013	212	#endif
bogdanm	88:9327015d4013	213
bogdanm	88:9327015d4013	214	#ifndef __FPU_PRESENT
bogdanm	88:9327015d4013	215	#define __FPU_PRESENT 0
bogdanm	88:9327015d4013	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
bogdanm	88:9327015d4013	217	#endif
bogdanm	88:9327015d4013	218
bogdanm	88:9327015d4013	219	#ifndef __MPU_PRESENT
bogdanm	88:9327015d4013	220	#define __MPU_PRESENT 0
bogdanm	88:9327015d4013	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm	88:9327015d4013	222	#endif
bogdanm	88:9327015d4013	223
bogdanm	88:9327015d4013	224	#ifndef __NVIC_PRIO_BITS
bogdanm	88:9327015d4013	225	#define __NVIC_PRIO_BITS 4
bogdanm	88:9327015d4013	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm	88:9327015d4013	227	#endif
bogdanm	88:9327015d4013	228
bogdanm	88:9327015d4013	229	#ifndef __Vendor_SysTickConfig
bogdanm	88:9327015d4013	230	#define __Vendor_SysTickConfig 0
bogdanm	88:9327015d4013	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm	88:9327015d4013	232	#endif
bogdanm	88:9327015d4013	233	#endif
bogdanm	88:9327015d4013	234
bogdanm	88:9327015d4013	235	/* IO definitions (access restrictions to peripheral registers) */
bogdanm	88:9327015d4013	236	/**
bogdanm	88:9327015d4013	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm	88:9327015d4013	238
bogdanm	88:9327015d4013	239	<strong>IO Type Qualifiers</strong> are used
bogdanm	88:9327015d4013	240	\li to specify the access to peripheral variables.
bogdanm	88:9327015d4013	241	\li for automatic generation of peripheral register debug information.
bogdanm	88:9327015d4013	242	*/
bogdanm	88:9327015d4013	243	#ifdef __cplusplus
bogdanm	88:9327015d4013	244	#define __I volatile /!< Defines 'read only' permissions /
bogdanm	88:9327015d4013	245	#else
bogdanm	88:9327015d4013	246	#define __I volatile const /!< Defines 'read only' permissions /
bogdanm	88:9327015d4013	247	#endif
bogdanm	88:9327015d4013	248	#define __O volatile /!< Defines 'write only' permissions /
bogdanm	88:9327015d4013	249	#define __IO volatile /!< Defines 'read / write' permissions /
bogdanm	88:9327015d4013	250
<>	128:9bcdf88f62b0	251	#ifdef __cplusplus
<>	128:9bcdf88f62b0	252	#define __IM volatile /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	253	#else
<>	128:9bcdf88f62b0	254	#define __IM volatile const /!< Defines 'read only' permissions /
<>	128:9bcdf88f62b0	255	#endif
<>	128:9bcdf88f62b0	256	#define __OM volatile /!< Defines 'write only' permissions /
<>	128:9bcdf88f62b0	257	#define __IOM volatile /!< Defines 'read / write' permissions /
<>	128:9bcdf88f62b0	258
bogdanm	88:9327015d4013	259	/@} end of group Cortex_M4 /
bogdanm	88:9327015d4013	260
bogdanm	88:9327015d4013	261
bogdanm	88:9327015d4013	262
bogdanm	88:9327015d4013	263	/*******************************************************************************
bogdanm	88:9327015d4013	264	* Register Abstraction
bogdanm	88:9327015d4013	265	Core Register contain:
bogdanm	88:9327015d4013	266	- Core Register
bogdanm	88:9327015d4013	267	- Core NVIC Register
bogdanm	88:9327015d4013	268	- Core SCB Register
bogdanm	88:9327015d4013	269	- Core SysTick Register
bogdanm	88:9327015d4013	270	- Core Debug Register
bogdanm	88:9327015d4013	271	- Core MPU Register
bogdanm	88:9327015d4013	272	- Core FPU Register
bogdanm	88:9327015d4013	273	******************************************************************************/
bogdanm	88:9327015d4013	274	/** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm	88:9327015d4013	275	\brief Type definitions and defines for Cortex-M processor based devices.
bogdanm	88:9327015d4013	276	*/
bogdanm	88:9327015d4013	277
bogdanm	88:9327015d4013	278	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	279	\defgroup CMSIS_CORE Status and Control Registers
bogdanm	88:9327015d4013	280	\brief Core Register type definitions.
bogdanm	88:9327015d4013	281	@{
bogdanm	88:9327015d4013	282	*/
bogdanm	88:9327015d4013	283
bogdanm	88:9327015d4013	284	/** \brief Union type to access the Application Program Status Register (APSR).
bogdanm	88:9327015d4013	285	*/
bogdanm	88:9327015d4013	286	typedef union
bogdanm	88:9327015d4013	287	{
bogdanm	88:9327015d4013	288	struct
bogdanm	88:9327015d4013	289	{
bogdanm	88:9327015d4013	290	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
bogdanm	88:9327015d4013	291	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
bogdanm	88:9327015d4013	292	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
bogdanm	88:9327015d4013	293	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
bogdanm	88:9327015d4013	294	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
bogdanm	88:9327015d4013	295	uint32_t C:1; /!< bit: 29 Carry condition code flag /
bogdanm	88:9327015d4013	296	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
bogdanm	88:9327015d4013	297	uint32_t N:1; /!< bit: 31 Negative condition code flag /
bogdanm	88:9327015d4013	298	} b; /!< Structure used for bit access /
bogdanm	88:9327015d4013	299	uint32_t w; /!< Type used for word access /
bogdanm	88:9327015d4013	300	} APSR_Type;
bogdanm	88:9327015d4013	301
Kojto	110:165afa46840b	302	/* APSR Register Definitions */
Kojto	110:165afa46840b	303	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	110:165afa46840b	304	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	110:165afa46840b	305
Kojto	110:165afa46840b	306	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	110:165afa46840b	307	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	110:165afa46840b	308
Kojto	110:165afa46840b	309	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	110:165afa46840b	310	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	110:165afa46840b	311
Kojto	110:165afa46840b	312	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	110:165afa46840b	313	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	110:165afa46840b	314
Kojto	110:165afa46840b	315	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	110:165afa46840b	316	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	110:165afa46840b	317
Kojto	110:165afa46840b	318	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Kojto	110:165afa46840b	319	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Kojto	110:165afa46840b	320
bogdanm	88:9327015d4013	321
bogdanm	88:9327015d4013	322	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm	88:9327015d4013	323	*/
bogdanm	88:9327015d4013	324	typedef union
bogdanm	88:9327015d4013	325	{
bogdanm	88:9327015d4013	326	struct
bogdanm	88:9327015d4013	327	{
bogdanm	88:9327015d4013	328	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
bogdanm	88:9327015d4013	329	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
bogdanm	88:9327015d4013	330	} b; /!< Structure used for bit access /
bogdanm	88:9327015d4013	331	uint32_t w; /!< Type used for word access /
bogdanm	88:9327015d4013	332	} IPSR_Type;
bogdanm	88:9327015d4013	333
Kojto	110:165afa46840b	334	/* IPSR Register Definitions */
Kojto	110:165afa46840b	335	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	110:165afa46840b	336	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	110:165afa46840b	337
bogdanm	88:9327015d4013	338
bogdanm	88:9327015d4013	339	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm	88:9327015d4013	340	*/
bogdanm	88:9327015d4013	341	typedef union
bogdanm	88:9327015d4013	342	{
bogdanm	88:9327015d4013	343	struct
bogdanm	88:9327015d4013	344	{
bogdanm	88:9327015d4013	345	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
bogdanm	88:9327015d4013	346	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
bogdanm	88:9327015d4013	347	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
bogdanm	88:9327015d4013	348	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
bogdanm	88:9327015d4013	349	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
bogdanm	88:9327015d4013	350	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
bogdanm	88:9327015d4013	351	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
bogdanm	88:9327015d4013	352	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
bogdanm	88:9327015d4013	353	uint32_t C:1; /!< bit: 29 Carry condition code flag /
bogdanm	88:9327015d4013	354	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
bogdanm	88:9327015d4013	355	uint32_t N:1; /!< bit: 31 Negative condition code flag /
bogdanm	88:9327015d4013	356	} b; /!< Structure used for bit access /
bogdanm	88:9327015d4013	357	uint32_t w; /!< Type used for word access /
bogdanm	88:9327015d4013	358	} xPSR_Type;
bogdanm	88:9327015d4013	359
Kojto	110:165afa46840b	360	/* xPSR Register Definitions */
Kojto	110:165afa46840b	361	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	110:165afa46840b	362	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	110:165afa46840b	363
Kojto	110:165afa46840b	364	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	110:165afa46840b	365	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	110:165afa46840b	366
Kojto	110:165afa46840b	367	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	110:165afa46840b	368	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	110:165afa46840b	369
Kojto	110:165afa46840b	370	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	110:165afa46840b	371	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	110:165afa46840b	372
Kojto	110:165afa46840b	373	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	110:165afa46840b	374	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	110:165afa46840b	375
Kojto	110:165afa46840b	376	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	110:165afa46840b	377	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	110:165afa46840b	378
Kojto	110:165afa46840b	379	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	110:165afa46840b	380	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	110:165afa46840b	381
Kojto	110:165afa46840b	382	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Kojto	110:165afa46840b	383	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Kojto	110:165afa46840b	384
Kojto	110:165afa46840b	385	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	110:165afa46840b	386	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	110:165afa46840b	387
bogdanm	88:9327015d4013	388
bogdanm	88:9327015d4013	389	/** \brief Union type to access the Control Registers (CONTROL).
bogdanm	88:9327015d4013	390	*/
bogdanm	88:9327015d4013	391	typedef union
bogdanm	88:9327015d4013	392	{
bogdanm	88:9327015d4013	393	struct
bogdanm	88:9327015d4013	394	{
bogdanm	88:9327015d4013	395	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
bogdanm	88:9327015d4013	396	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
bogdanm	88:9327015d4013	397	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
bogdanm	88:9327015d4013	398	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
bogdanm	88:9327015d4013	399	} b; /!< Structure used for bit access /
bogdanm	88:9327015d4013	400	uint32_t w; /!< Type used for word access /
bogdanm	88:9327015d4013	401	} CONTROL_Type;
bogdanm	88:9327015d4013	402
Kojto	110:165afa46840b	403	/* CONTROL Register Definitions */
Kojto	110:165afa46840b	404	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Kojto	110:165afa46840b	405	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Kojto	110:165afa46840b	406
Kojto	110:165afa46840b	407	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	110:165afa46840b	408	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	110:165afa46840b	409
Kojto	110:165afa46840b	410	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	110:165afa46840b	411	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	110:165afa46840b	412
bogdanm	88:9327015d4013	413	/@} end of group CMSIS_CORE /
bogdanm	88:9327015d4013	414
bogdanm	88:9327015d4013	415
bogdanm	88:9327015d4013	416	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	417	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm	88:9327015d4013	418	\brief Type definitions for the NVIC Registers
bogdanm	88:9327015d4013	419	@{
bogdanm	88:9327015d4013	420	*/
bogdanm	88:9327015d4013	421
bogdanm	88:9327015d4013	422	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm	88:9327015d4013	423	*/
bogdanm	88:9327015d4013	424	typedef struct
bogdanm	88:9327015d4013	425	{
bogdanm	88:9327015d4013	426	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
bogdanm	88:9327015d4013	427	uint32_t RESERVED0[24];
bogdanm	88:9327015d4013	428	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
bogdanm	88:9327015d4013	429	uint32_t RSERVED1[24];
bogdanm	88:9327015d4013	430	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
bogdanm	88:9327015d4013	431	uint32_t RESERVED2[24];
bogdanm	88:9327015d4013	432	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
bogdanm	88:9327015d4013	433	uint32_t RESERVED3[24];
bogdanm	88:9327015d4013	434	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
bogdanm	88:9327015d4013	435	uint32_t RESERVED4[56];
bogdanm	88:9327015d4013	436	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
bogdanm	88:9327015d4013	437	uint32_t RESERVED5[644];
bogdanm	88:9327015d4013	438	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
bogdanm	88:9327015d4013	439	} NVIC_Type;
bogdanm	88:9327015d4013	440
bogdanm	88:9327015d4013	441	/* Software Triggered Interrupt Register Definitions */
bogdanm	88:9327015d4013	442	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	110:165afa46840b	443	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
bogdanm	88:9327015d4013	444
bogdanm	88:9327015d4013	445	/@} end of group CMSIS_NVIC /
bogdanm	88:9327015d4013	446
bogdanm	88:9327015d4013	447
bogdanm	88:9327015d4013	448	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	449	\defgroup CMSIS_SCB System Control Block (SCB)
bogdanm	88:9327015d4013	450	\brief Type definitions for the System Control Block Registers
bogdanm	88:9327015d4013	451	@{
bogdanm	88:9327015d4013	452	*/
bogdanm	88:9327015d4013	453
bogdanm	88:9327015d4013	454	/** \brief Structure type to access the System Control Block (SCB).
bogdanm	88:9327015d4013	455	*/
bogdanm	88:9327015d4013	456	typedef struct
bogdanm	88:9327015d4013	457	{
bogdanm	88:9327015d4013	458	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
bogdanm	88:9327015d4013	459	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
bogdanm	88:9327015d4013	460	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
bogdanm	88:9327015d4013	461	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
bogdanm	88:9327015d4013	462	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
bogdanm	88:9327015d4013	463	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
bogdanm	88:9327015d4013	464	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
bogdanm	88:9327015d4013	465	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
bogdanm	88:9327015d4013	466	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
bogdanm	88:9327015d4013	467	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
bogdanm	88:9327015d4013	468	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
bogdanm	88:9327015d4013	469	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
bogdanm	88:9327015d4013	470	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
bogdanm	88:9327015d4013	471	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
bogdanm	88:9327015d4013	472	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
bogdanm	88:9327015d4013	473	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
bogdanm	88:9327015d4013	474	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
bogdanm	88:9327015d4013	475	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
bogdanm	88:9327015d4013	476	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
bogdanm	88:9327015d4013	477	uint32_t RESERVED0[5];
bogdanm	88:9327015d4013	478	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
bogdanm	88:9327015d4013	479	} SCB_Type;
bogdanm	88:9327015d4013	480
bogdanm	88:9327015d4013	481	/* SCB CPUID Register Definitions */
bogdanm	88:9327015d4013	482	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
bogdanm	88:9327015d4013	483	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
bogdanm	88:9327015d4013	484
bogdanm	88:9327015d4013	485	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
bogdanm	88:9327015d4013	486	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
bogdanm	88:9327015d4013	487
bogdanm	88:9327015d4013	488	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
bogdanm	88:9327015d4013	489	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
bogdanm	88:9327015d4013	490
bogdanm	88:9327015d4013	491	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
bogdanm	88:9327015d4013	492	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
bogdanm	88:9327015d4013	493
bogdanm	88:9327015d4013	494	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	110:165afa46840b	495	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
bogdanm	88:9327015d4013	496
bogdanm	88:9327015d4013	497	/* SCB Interrupt Control State Register Definitions */
bogdanm	88:9327015d4013	498	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
bogdanm	88:9327015d4013	499	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
bogdanm	88:9327015d4013	500
bogdanm	88:9327015d4013	501	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
bogdanm	88:9327015d4013	502	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
bogdanm	88:9327015d4013	503
bogdanm	88:9327015d4013	504	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
bogdanm	88:9327015d4013	505	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
bogdanm	88:9327015d4013	506
bogdanm	88:9327015d4013	507	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
bogdanm	88:9327015d4013	508	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
bogdanm	88:9327015d4013	509
bogdanm	88:9327015d4013	510	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
bogdanm	88:9327015d4013	511	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
bogdanm	88:9327015d4013	512
bogdanm	88:9327015d4013	513	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
bogdanm	88:9327015d4013	514	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
bogdanm	88:9327015d4013	515
bogdanm	88:9327015d4013	516	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
bogdanm	88:9327015d4013	517	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
bogdanm	88:9327015d4013	518
bogdanm	88:9327015d4013	519	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
bogdanm	88:9327015d4013	520	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
bogdanm	88:9327015d4013	521
bogdanm	88:9327015d4013	522	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
bogdanm	88:9327015d4013	523	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
bogdanm	88:9327015d4013	524
bogdanm	88:9327015d4013	525	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	110:165afa46840b	526	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
bogdanm	88:9327015d4013	527
bogdanm	88:9327015d4013	528	/* SCB Vector Table Offset Register Definitions */
bogdanm	88:9327015d4013	529	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
bogdanm	88:9327015d4013	530	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
bogdanm	88:9327015d4013	531
bogdanm	88:9327015d4013	532	/* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm	88:9327015d4013	533	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
bogdanm	88:9327015d4013	534	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
bogdanm	88:9327015d4013	535
bogdanm	88:9327015d4013	536	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
bogdanm	88:9327015d4013	537	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
bogdanm	88:9327015d4013	538
bogdanm	88:9327015d4013	539	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
bogdanm	88:9327015d4013	540	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
bogdanm	88:9327015d4013	541
bogdanm	88:9327015d4013	542	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
bogdanm	88:9327015d4013	543	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
bogdanm	88:9327015d4013	544
bogdanm	88:9327015d4013	545	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
bogdanm	88:9327015d4013	546	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
bogdanm	88:9327015d4013	547
bogdanm	88:9327015d4013	548	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
bogdanm	88:9327015d4013	549	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
bogdanm	88:9327015d4013	550
bogdanm	88:9327015d4013	551	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	110:165afa46840b	552	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
bogdanm	88:9327015d4013	553
bogdanm	88:9327015d4013	554	/* SCB System Control Register Definitions */
bogdanm	88:9327015d4013	555	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
bogdanm	88:9327015d4013	556	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
bogdanm	88:9327015d4013	557
bogdanm	88:9327015d4013	558	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
bogdanm	88:9327015d4013	559	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
bogdanm	88:9327015d4013	560
bogdanm	88:9327015d4013	561	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
bogdanm	88:9327015d4013	562	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
bogdanm	88:9327015d4013	563
bogdanm	88:9327015d4013	564	/* SCB Configuration Control Register Definitions */
bogdanm	88:9327015d4013	565	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
bogdanm	88:9327015d4013	566	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
bogdanm	88:9327015d4013	567
bogdanm	88:9327015d4013	568	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
bogdanm	88:9327015d4013	569	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
bogdanm	88:9327015d4013	570
bogdanm	88:9327015d4013	571	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
bogdanm	88:9327015d4013	572	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
bogdanm	88:9327015d4013	573
bogdanm	88:9327015d4013	574	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
bogdanm	88:9327015d4013	575	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
bogdanm	88:9327015d4013	576
bogdanm	88:9327015d4013	577	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
bogdanm	88:9327015d4013	578	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
bogdanm	88:9327015d4013	579
bogdanm	88:9327015d4013	580	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	110:165afa46840b	581	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
bogdanm	88:9327015d4013	582
bogdanm	88:9327015d4013	583	/* SCB System Handler Control and State Register Definitions */
bogdanm	88:9327015d4013	584	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
bogdanm	88:9327015d4013	585	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
bogdanm	88:9327015d4013	586
bogdanm	88:9327015d4013	587	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
bogdanm	88:9327015d4013	588	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
bogdanm	88:9327015d4013	589
bogdanm	88:9327015d4013	590	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
bogdanm	88:9327015d4013	591	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
bogdanm	88:9327015d4013	592
bogdanm	88:9327015d4013	593	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
bogdanm	88:9327015d4013	594	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
bogdanm	88:9327015d4013	595
bogdanm	88:9327015d4013	596	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
bogdanm	88:9327015d4013	597	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
bogdanm	88:9327015d4013	598
bogdanm	88:9327015d4013	599	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
bogdanm	88:9327015d4013	600	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
bogdanm	88:9327015d4013	601
bogdanm	88:9327015d4013	602	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
bogdanm	88:9327015d4013	603	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
bogdanm	88:9327015d4013	604
bogdanm	88:9327015d4013	605	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
bogdanm	88:9327015d4013	606	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
bogdanm	88:9327015d4013	607
bogdanm	88:9327015d4013	608	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
bogdanm	88:9327015d4013	609	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
bogdanm	88:9327015d4013	610
bogdanm	88:9327015d4013	611	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
bogdanm	88:9327015d4013	612	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
bogdanm	88:9327015d4013	613
bogdanm	88:9327015d4013	614	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
bogdanm	88:9327015d4013	615	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
bogdanm	88:9327015d4013	616
bogdanm	88:9327015d4013	617	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
bogdanm	88:9327015d4013	618	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
bogdanm	88:9327015d4013	619
bogdanm	88:9327015d4013	620	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
bogdanm	88:9327015d4013	621	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
bogdanm	88:9327015d4013	622
bogdanm	88:9327015d4013	623	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	110:165afa46840b	624	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
bogdanm	88:9327015d4013	625
bogdanm	88:9327015d4013	626	/* SCB Configurable Fault Status Registers Definitions */
bogdanm	88:9327015d4013	627	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
bogdanm	88:9327015d4013	628	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
bogdanm	88:9327015d4013	629
bogdanm	88:9327015d4013	630	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
bogdanm	88:9327015d4013	631	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
bogdanm	88:9327015d4013	632
bogdanm	88:9327015d4013	633	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	110:165afa46840b	634	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
bogdanm	88:9327015d4013	635
bogdanm	88:9327015d4013	636	/* SCB Hard Fault Status Registers Definitions */
bogdanm	88:9327015d4013	637	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
bogdanm	88:9327015d4013	638	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
bogdanm	88:9327015d4013	639
bogdanm	88:9327015d4013	640	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
bogdanm	88:9327015d4013	641	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
bogdanm	88:9327015d4013	642
bogdanm	88:9327015d4013	643	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
bogdanm	88:9327015d4013	644	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
bogdanm	88:9327015d4013	645
bogdanm	88:9327015d4013	646	/* SCB Debug Fault Status Register Definitions */
bogdanm	88:9327015d4013	647	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
bogdanm	88:9327015d4013	648	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
bogdanm	88:9327015d4013	649
bogdanm	88:9327015d4013	650	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
bogdanm	88:9327015d4013	651	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
bogdanm	88:9327015d4013	652
bogdanm	88:9327015d4013	653	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
bogdanm	88:9327015d4013	654	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
bogdanm	88:9327015d4013	655
bogdanm	88:9327015d4013	656	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
bogdanm	88:9327015d4013	657	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
bogdanm	88:9327015d4013	658
bogdanm	88:9327015d4013	659	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	110:165afa46840b	660	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
bogdanm	88:9327015d4013	661
bogdanm	88:9327015d4013	662	/@} end of group CMSIS_SCB /
bogdanm	88:9327015d4013	663
bogdanm	88:9327015d4013	664
bogdanm	88:9327015d4013	665	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	666	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm	88:9327015d4013	667	\brief Type definitions for the System Control and ID Register not in the SCB
bogdanm	88:9327015d4013	668	@{
bogdanm	88:9327015d4013	669	*/
bogdanm	88:9327015d4013	670
bogdanm	88:9327015d4013	671	/** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm	88:9327015d4013	672	*/
bogdanm	88:9327015d4013	673	typedef struct
bogdanm	88:9327015d4013	674	{
bogdanm	88:9327015d4013	675	uint32_t RESERVED0[1];
bogdanm	88:9327015d4013	676	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
bogdanm	88:9327015d4013	677	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
bogdanm	88:9327015d4013	678	} SCnSCB_Type;
bogdanm	88:9327015d4013	679
bogdanm	88:9327015d4013	680	/* Interrupt Controller Type Register Definitions */
bogdanm	88:9327015d4013	681	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	110:165afa46840b	682	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
bogdanm	88:9327015d4013	683
bogdanm	88:9327015d4013	684	/* Auxiliary Control Register Definitions */
bogdanm	88:9327015d4013	685	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
bogdanm	88:9327015d4013	686	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
bogdanm	88:9327015d4013	687
bogdanm	88:9327015d4013	688	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
bogdanm	88:9327015d4013	689	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
bogdanm	88:9327015d4013	690
bogdanm	88:9327015d4013	691	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
bogdanm	88:9327015d4013	692	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
bogdanm	88:9327015d4013	693
bogdanm	88:9327015d4013	694	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
bogdanm	88:9327015d4013	695	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
bogdanm	88:9327015d4013	696
bogdanm	88:9327015d4013	697	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	110:165afa46840b	698	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
bogdanm	88:9327015d4013	699
bogdanm	88:9327015d4013	700	/@} end of group CMSIS_SCnotSCB /
bogdanm	88:9327015d4013	701
bogdanm	88:9327015d4013	702
bogdanm	88:9327015d4013	703	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	704	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm	88:9327015d4013	705	\brief Type definitions for the System Timer Registers.
bogdanm	88:9327015d4013	706	@{
bogdanm	88:9327015d4013	707	*/
bogdanm	88:9327015d4013	708
bogdanm	88:9327015d4013	709	/** \brief Structure type to access the System Timer (SysTick).
bogdanm	88:9327015d4013	710	*/
bogdanm	88:9327015d4013	711	typedef struct
bogdanm	88:9327015d4013	712	{
bogdanm	88:9327015d4013	713	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
bogdanm	88:9327015d4013	714	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
bogdanm	88:9327015d4013	715	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
bogdanm	88:9327015d4013	716	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
bogdanm	88:9327015d4013	717	} SysTick_Type;
bogdanm	88:9327015d4013	718
bogdanm	88:9327015d4013	719	/* SysTick Control / Status Register Definitions */
bogdanm	88:9327015d4013	720	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
bogdanm	88:9327015d4013	721	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
bogdanm	88:9327015d4013	722
bogdanm	88:9327015d4013	723	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
bogdanm	88:9327015d4013	724	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
bogdanm	88:9327015d4013	725
bogdanm	88:9327015d4013	726	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
bogdanm	88:9327015d4013	727	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
bogdanm	88:9327015d4013	728
bogdanm	88:9327015d4013	729	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	110:165afa46840b	730	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
bogdanm	88:9327015d4013	731
bogdanm	88:9327015d4013	732	/* SysTick Reload Register Definitions */
bogdanm	88:9327015d4013	733	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	110:165afa46840b	734	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
bogdanm	88:9327015d4013	735
bogdanm	88:9327015d4013	736	/* SysTick Current Register Definitions */
bogdanm	88:9327015d4013	737	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	110:165afa46840b	738	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
bogdanm	88:9327015d4013	739
bogdanm	88:9327015d4013	740	/* SysTick Calibration Register Definitions */
bogdanm	88:9327015d4013	741	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
bogdanm	88:9327015d4013	742	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
bogdanm	88:9327015d4013	743
bogdanm	88:9327015d4013	744	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
bogdanm	88:9327015d4013	745	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
bogdanm	88:9327015d4013	746
bogdanm	88:9327015d4013	747	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	110:165afa46840b	748	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
bogdanm	88:9327015d4013	749
bogdanm	88:9327015d4013	750	/@} end of group CMSIS_SysTick /
bogdanm	88:9327015d4013	751
bogdanm	88:9327015d4013	752
bogdanm	88:9327015d4013	753	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	754	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm	88:9327015d4013	755	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm	88:9327015d4013	756	@{
bogdanm	88:9327015d4013	757	*/
bogdanm	88:9327015d4013	758
bogdanm	88:9327015d4013	759	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm	88:9327015d4013	760	*/
bogdanm	88:9327015d4013	761	typedef struct
bogdanm	88:9327015d4013	762	{
bogdanm	88:9327015d4013	763	__O union
bogdanm	88:9327015d4013	764	{
bogdanm	88:9327015d4013	765	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
bogdanm	88:9327015d4013	766	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
bogdanm	88:9327015d4013	767	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
bogdanm	88:9327015d4013	768	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
bogdanm	88:9327015d4013	769	uint32_t RESERVED0[864];
bogdanm	88:9327015d4013	770	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
bogdanm	88:9327015d4013	771	uint32_t RESERVED1[15];
bogdanm	88:9327015d4013	772	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
bogdanm	88:9327015d4013	773	uint32_t RESERVED2[15];
bogdanm	88:9327015d4013	774	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
bogdanm	88:9327015d4013	775	uint32_t RESERVED3[29];
bogdanm	88:9327015d4013	776	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
bogdanm	88:9327015d4013	777	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
bogdanm	88:9327015d4013	778	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
bogdanm	88:9327015d4013	779	uint32_t RESERVED4[43];
bogdanm	88:9327015d4013	780	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
bogdanm	88:9327015d4013	781	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
bogdanm	88:9327015d4013	782	uint32_t RESERVED5[6];
bogdanm	88:9327015d4013	783	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
bogdanm	88:9327015d4013	784	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
bogdanm	88:9327015d4013	785	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
bogdanm	88:9327015d4013	786	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
bogdanm	88:9327015d4013	787	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
bogdanm	88:9327015d4013	788	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
bogdanm	88:9327015d4013	789	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
bogdanm	88:9327015d4013	790	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
bogdanm	88:9327015d4013	791	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
bogdanm	88:9327015d4013	792	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
bogdanm	88:9327015d4013	793	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
bogdanm	88:9327015d4013	794	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
bogdanm	88:9327015d4013	795	} ITM_Type;
bogdanm	88:9327015d4013	796
bogdanm	88:9327015d4013	797	/* ITM Trace Privilege Register Definitions */
bogdanm	88:9327015d4013	798	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	110:165afa46840b	799	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
bogdanm	88:9327015d4013	800
bogdanm	88:9327015d4013	801	/* ITM Trace Control Register Definitions */
bogdanm	88:9327015d4013	802	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
bogdanm	88:9327015d4013	803	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
bogdanm	88:9327015d4013	804
bogdanm	88:9327015d4013	805	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
bogdanm	88:9327015d4013	806	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
bogdanm	88:9327015d4013	807
bogdanm	88:9327015d4013	808	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
bogdanm	88:9327015d4013	809	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
bogdanm	88:9327015d4013	810
bogdanm	88:9327015d4013	811	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
bogdanm	88:9327015d4013	812	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
bogdanm	88:9327015d4013	813
bogdanm	88:9327015d4013	814	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
bogdanm	88:9327015d4013	815	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
bogdanm	88:9327015d4013	816
bogdanm	88:9327015d4013	817	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
bogdanm	88:9327015d4013	818	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
bogdanm	88:9327015d4013	819
bogdanm	88:9327015d4013	820	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
bogdanm	88:9327015d4013	821	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
bogdanm	88:9327015d4013	822
bogdanm	88:9327015d4013	823	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
bogdanm	88:9327015d4013	824	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
bogdanm	88:9327015d4013	825
bogdanm	88:9327015d4013	826	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	110:165afa46840b	827	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
bogdanm	88:9327015d4013	828
bogdanm	88:9327015d4013	829	/* ITM Integration Write Register Definitions */
bogdanm	88:9327015d4013	830	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	110:165afa46840b	831	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
bogdanm	88:9327015d4013	832
bogdanm	88:9327015d4013	833	/* ITM Integration Read Register Definitions */
bogdanm	88:9327015d4013	834	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	110:165afa46840b	835	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
bogdanm	88:9327015d4013	836
bogdanm	88:9327015d4013	837	/* ITM Integration Mode Control Register Definitions */
bogdanm	88:9327015d4013	838	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	110:165afa46840b	839	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
bogdanm	88:9327015d4013	840
bogdanm	88:9327015d4013	841	/* ITM Lock Status Register Definitions */
bogdanm	88:9327015d4013	842	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
bogdanm	88:9327015d4013	843	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
bogdanm	88:9327015d4013	844
bogdanm	88:9327015d4013	845	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
bogdanm	88:9327015d4013	846	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
bogdanm	88:9327015d4013	847
bogdanm	88:9327015d4013	848	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	110:165afa46840b	849	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
bogdanm	88:9327015d4013	850
bogdanm	88:9327015d4013	851	/@}/ /* end of group CMSIS_ITM */
bogdanm	88:9327015d4013	852
bogdanm	88:9327015d4013	853
bogdanm	88:9327015d4013	854	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	855	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm	88:9327015d4013	856	\brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm	88:9327015d4013	857	@{
bogdanm	88:9327015d4013	858	*/
bogdanm	88:9327015d4013	859
bogdanm	88:9327015d4013	860	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm	88:9327015d4013	861	*/
bogdanm	88:9327015d4013	862	typedef struct
bogdanm	88:9327015d4013	863	{
bogdanm	88:9327015d4013	864	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
bogdanm	88:9327015d4013	865	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
bogdanm	88:9327015d4013	866	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
bogdanm	88:9327015d4013	867	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
bogdanm	88:9327015d4013	868	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
bogdanm	88:9327015d4013	869	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
bogdanm	88:9327015d4013	870	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
bogdanm	88:9327015d4013	871	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
bogdanm	88:9327015d4013	872	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
bogdanm	88:9327015d4013	873	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
bogdanm	88:9327015d4013	874	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
bogdanm	88:9327015d4013	875	uint32_t RESERVED0[1];
bogdanm	88:9327015d4013	876	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
bogdanm	88:9327015d4013	877	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
bogdanm	88:9327015d4013	878	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
bogdanm	88:9327015d4013	879	uint32_t RESERVED1[1];
bogdanm	88:9327015d4013	880	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
bogdanm	88:9327015d4013	881	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
bogdanm	88:9327015d4013	882	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
bogdanm	88:9327015d4013	883	uint32_t RESERVED2[1];
bogdanm	88:9327015d4013	884	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
bogdanm	88:9327015d4013	885	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
bogdanm	88:9327015d4013	886	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
bogdanm	88:9327015d4013	887	} DWT_Type;
bogdanm	88:9327015d4013	888
bogdanm	88:9327015d4013	889	/* DWT Control Register Definitions */
bogdanm	88:9327015d4013	890	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
bogdanm	88:9327015d4013	891	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
bogdanm	88:9327015d4013	892
bogdanm	88:9327015d4013	893	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
bogdanm	88:9327015d4013	894	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
bogdanm	88:9327015d4013	895
bogdanm	88:9327015d4013	896	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
bogdanm	88:9327015d4013	897	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
bogdanm	88:9327015d4013	898
bogdanm	88:9327015d4013	899	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
bogdanm	88:9327015d4013	900	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
bogdanm	88:9327015d4013	901
bogdanm	88:9327015d4013	902	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
bogdanm	88:9327015d4013	903	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
bogdanm	88:9327015d4013	904
bogdanm	88:9327015d4013	905	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
bogdanm	88:9327015d4013	906	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
bogdanm	88:9327015d4013	907
bogdanm	88:9327015d4013	908	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
bogdanm	88:9327015d4013	909	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
bogdanm	88:9327015d4013	910
bogdanm	88:9327015d4013	911	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
bogdanm	88:9327015d4013	912	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
bogdanm	88:9327015d4013	913
bogdanm	88:9327015d4013	914	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
bogdanm	88:9327015d4013	915	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
bogdanm	88:9327015d4013	916
bogdanm	88:9327015d4013	917	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
bogdanm	88:9327015d4013	918	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
bogdanm	88:9327015d4013	919
bogdanm	88:9327015d4013	920	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
bogdanm	88:9327015d4013	921	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
bogdanm	88:9327015d4013	922
bogdanm	88:9327015d4013	923	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
bogdanm	88:9327015d4013	924	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
bogdanm	88:9327015d4013	925
bogdanm	88:9327015d4013	926	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
bogdanm	88:9327015d4013	927	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
bogdanm	88:9327015d4013	928
bogdanm	88:9327015d4013	929	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
bogdanm	88:9327015d4013	930	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
bogdanm	88:9327015d4013	931
bogdanm	88:9327015d4013	932	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
bogdanm	88:9327015d4013	933	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
bogdanm	88:9327015d4013	934
bogdanm	88:9327015d4013	935	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
bogdanm	88:9327015d4013	936	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
bogdanm	88:9327015d4013	937
bogdanm	88:9327015d4013	938	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
bogdanm	88:9327015d4013	939	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
bogdanm	88:9327015d4013	940
bogdanm	88:9327015d4013	941	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	110:165afa46840b	942	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
bogdanm	88:9327015d4013	943
bogdanm	88:9327015d4013	944	/* DWT CPI Count Register Definitions */
bogdanm	88:9327015d4013	945	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	110:165afa46840b	946	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
bogdanm	88:9327015d4013	947
bogdanm	88:9327015d4013	948	/* DWT Exception Overhead Count Register Definitions */
bogdanm	88:9327015d4013	949	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	110:165afa46840b	950	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
bogdanm	88:9327015d4013	951
bogdanm	88:9327015d4013	952	/* DWT Sleep Count Register Definitions */
bogdanm	88:9327015d4013	953	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	110:165afa46840b	954	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
bogdanm	88:9327015d4013	955
bogdanm	88:9327015d4013	956	/* DWT LSU Count Register Definitions */
bogdanm	88:9327015d4013	957	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	110:165afa46840b	958	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
bogdanm	88:9327015d4013	959
bogdanm	88:9327015d4013	960	/* DWT Folded-instruction Count Register Definitions */
bogdanm	88:9327015d4013	961	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	110:165afa46840b	962	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
bogdanm	88:9327015d4013	963
bogdanm	88:9327015d4013	964	/* DWT Comparator Mask Register Definitions */
bogdanm	88:9327015d4013	965	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	110:165afa46840b	966	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
bogdanm	88:9327015d4013	967
bogdanm	88:9327015d4013	968	/* DWT Comparator Function Register Definitions */
bogdanm	88:9327015d4013	969	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
bogdanm	88:9327015d4013	970	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
bogdanm	88:9327015d4013	971
bogdanm	88:9327015d4013	972	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
bogdanm	88:9327015d4013	973	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
bogdanm	88:9327015d4013	974
bogdanm	88:9327015d4013	975	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
bogdanm	88:9327015d4013	976	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
bogdanm	88:9327015d4013	977
bogdanm	88:9327015d4013	978	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
bogdanm	88:9327015d4013	979	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
bogdanm	88:9327015d4013	980
bogdanm	88:9327015d4013	981	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
bogdanm	88:9327015d4013	982	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
bogdanm	88:9327015d4013	983
bogdanm	88:9327015d4013	984	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
bogdanm	88:9327015d4013	985	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
bogdanm	88:9327015d4013	986
bogdanm	88:9327015d4013	987	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
bogdanm	88:9327015d4013	988	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
bogdanm	88:9327015d4013	989
bogdanm	88:9327015d4013	990	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
bogdanm	88:9327015d4013	991	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
bogdanm	88:9327015d4013	992
bogdanm	88:9327015d4013	993	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	110:165afa46840b	994	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
bogdanm	88:9327015d4013	995
bogdanm	88:9327015d4013	996	/@}/ /* end of group CMSIS_DWT */
bogdanm	88:9327015d4013	997
bogdanm	88:9327015d4013	998
bogdanm	88:9327015d4013	999	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	1000	\defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm	88:9327015d4013	1001	\brief Type definitions for the Trace Port Interface (TPI)
bogdanm	88:9327015d4013	1002	@{
bogdanm	88:9327015d4013	1003	*/
bogdanm	88:9327015d4013	1004
bogdanm	88:9327015d4013	1005	/** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm	88:9327015d4013	1006	*/
bogdanm	88:9327015d4013	1007	typedef struct
bogdanm	88:9327015d4013	1008	{
bogdanm	88:9327015d4013	1009	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
bogdanm	88:9327015d4013	1010	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
bogdanm	88:9327015d4013	1011	uint32_t RESERVED0[2];
bogdanm	88:9327015d4013	1012	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
bogdanm	88:9327015d4013	1013	uint32_t RESERVED1[55];
bogdanm	88:9327015d4013	1014	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
bogdanm	88:9327015d4013	1015	uint32_t RESERVED2[131];
bogdanm	88:9327015d4013	1016	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
bogdanm	88:9327015d4013	1017	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
bogdanm	88:9327015d4013	1018	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
bogdanm	88:9327015d4013	1019	uint32_t RESERVED3[759];
bogdanm	88:9327015d4013	1020	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
bogdanm	88:9327015d4013	1021	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
bogdanm	88:9327015d4013	1022	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
bogdanm	88:9327015d4013	1023	uint32_t RESERVED4[1];
bogdanm	88:9327015d4013	1024	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
bogdanm	88:9327015d4013	1025	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
bogdanm	88:9327015d4013	1026	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
bogdanm	88:9327015d4013	1027	uint32_t RESERVED5[39];
bogdanm	88:9327015d4013	1028	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
bogdanm	88:9327015d4013	1029	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
bogdanm	88:9327015d4013	1030	uint32_t RESERVED7[8];
bogdanm	88:9327015d4013	1031	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
bogdanm	88:9327015d4013	1032	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
bogdanm	88:9327015d4013	1033	} TPI_Type;
bogdanm	88:9327015d4013	1034
bogdanm	88:9327015d4013	1035	/* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm	88:9327015d4013	1036	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	110:165afa46840b	1037	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
bogdanm	88:9327015d4013	1038
bogdanm	88:9327015d4013	1039	/* TPI Selected Pin Protocol Register Definitions */
bogdanm	88:9327015d4013	1040	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	110:165afa46840b	1041	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
bogdanm	88:9327015d4013	1042
bogdanm	88:9327015d4013	1043	/* TPI Formatter and Flush Status Register Definitions */
bogdanm	88:9327015d4013	1044	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
bogdanm	88:9327015d4013	1045	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
bogdanm	88:9327015d4013	1046
bogdanm	88:9327015d4013	1047	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
bogdanm	88:9327015d4013	1048	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
bogdanm	88:9327015d4013	1049
bogdanm	88:9327015d4013	1050	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
bogdanm	88:9327015d4013	1051	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
bogdanm	88:9327015d4013	1052
bogdanm	88:9327015d4013	1053	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	110:165afa46840b	1054	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
bogdanm	88:9327015d4013	1055
bogdanm	88:9327015d4013	1056	/* TPI Formatter and Flush Control Register Definitions */
bogdanm	88:9327015d4013	1057	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
bogdanm	88:9327015d4013	1058	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
bogdanm	88:9327015d4013	1059
bogdanm	88:9327015d4013	1060	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
bogdanm	88:9327015d4013	1061	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
bogdanm	88:9327015d4013	1062
bogdanm	88:9327015d4013	1063	/* TPI TRIGGER Register Definitions */
bogdanm	88:9327015d4013	1064	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	110:165afa46840b	1065	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
bogdanm	88:9327015d4013	1066
bogdanm	88:9327015d4013	1067	/* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm	88:9327015d4013	1068	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
bogdanm	88:9327015d4013	1069	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
bogdanm	88:9327015d4013	1070
bogdanm	88:9327015d4013	1071	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
bogdanm	88:9327015d4013	1072	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
bogdanm	88:9327015d4013	1073
bogdanm	88:9327015d4013	1074	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
bogdanm	88:9327015d4013	1075	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
bogdanm	88:9327015d4013	1076
bogdanm	88:9327015d4013	1077	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
bogdanm	88:9327015d4013	1078	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
bogdanm	88:9327015d4013	1079
bogdanm	88:9327015d4013	1080	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
bogdanm	88:9327015d4013	1081	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
bogdanm	88:9327015d4013	1082
bogdanm	88:9327015d4013	1083	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
bogdanm	88:9327015d4013	1084	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
bogdanm	88:9327015d4013	1085
bogdanm	88:9327015d4013	1086	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	110:165afa46840b	1087	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
bogdanm	88:9327015d4013	1088
bogdanm	88:9327015d4013	1089	/* TPI ITATBCTR2 Register Definitions */
bogdanm	88:9327015d4013	1090	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	110:165afa46840b	1091	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
bogdanm	88:9327015d4013	1092
bogdanm	88:9327015d4013	1093	/* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm	88:9327015d4013	1094	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
bogdanm	88:9327015d4013	1095	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
bogdanm	88:9327015d4013	1096
bogdanm	88:9327015d4013	1097	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
bogdanm	88:9327015d4013	1098	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
bogdanm	88:9327015d4013	1099
bogdanm	88:9327015d4013	1100	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
bogdanm	88:9327015d4013	1101	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
bogdanm	88:9327015d4013	1102
bogdanm	88:9327015d4013	1103	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
bogdanm	88:9327015d4013	1104	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
bogdanm	88:9327015d4013	1105
bogdanm	88:9327015d4013	1106	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
bogdanm	88:9327015d4013	1107	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
bogdanm	88:9327015d4013	1108
bogdanm	88:9327015d4013	1109	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
bogdanm	88:9327015d4013	1110	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
bogdanm	88:9327015d4013	1111
bogdanm	88:9327015d4013	1112	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	110:165afa46840b	1113	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
bogdanm	88:9327015d4013	1114
bogdanm	88:9327015d4013	1115	/* TPI ITATBCTR0 Register Definitions */
bogdanm	88:9327015d4013	1116	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	110:165afa46840b	1117	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
bogdanm	88:9327015d4013	1118
bogdanm	88:9327015d4013	1119	/* TPI Integration Mode Control Register Definitions */
bogdanm	88:9327015d4013	1120	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	110:165afa46840b	1121	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
bogdanm	88:9327015d4013	1122
bogdanm	88:9327015d4013	1123	/* TPI DEVID Register Definitions */
bogdanm	88:9327015d4013	1124	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
bogdanm	88:9327015d4013	1125	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
bogdanm	88:9327015d4013	1126
bogdanm	88:9327015d4013	1127	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
bogdanm	88:9327015d4013	1128	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
bogdanm	88:9327015d4013	1129
bogdanm	88:9327015d4013	1130	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
bogdanm	88:9327015d4013	1131	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
bogdanm	88:9327015d4013	1132
bogdanm	88:9327015d4013	1133	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
bogdanm	88:9327015d4013	1134	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
bogdanm	88:9327015d4013	1135
bogdanm	88:9327015d4013	1136	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
bogdanm	88:9327015d4013	1137	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
bogdanm	88:9327015d4013	1138
bogdanm	88:9327015d4013	1139	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	110:165afa46840b	1140	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
bogdanm	88:9327015d4013	1141
bogdanm	88:9327015d4013	1142	/* TPI DEVTYPE Register Definitions */
bogdanm	88:9327015d4013	1143	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
bogdanm	88:9327015d4013	1144	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
bogdanm	88:9327015d4013	1145
Kojto	110:165afa46840b	1146	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	110:165afa46840b	1147	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	110:165afa46840b	1148
bogdanm	88:9327015d4013	1149	/@}/ /* end of group CMSIS_TPI */
bogdanm	88:9327015d4013	1150
bogdanm	88:9327015d4013	1151
bogdanm	88:9327015d4013	1152	#if (__MPU_PRESENT == 1)
bogdanm	88:9327015d4013	1153	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	1154	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm	88:9327015d4013	1155	\brief Type definitions for the Memory Protection Unit (MPU)
bogdanm	88:9327015d4013	1156	@{
bogdanm	88:9327015d4013	1157	*/
bogdanm	88:9327015d4013	1158
bogdanm	88:9327015d4013	1159	/** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm	88:9327015d4013	1160	*/
bogdanm	88:9327015d4013	1161	typedef struct
bogdanm	88:9327015d4013	1162	{
bogdanm	88:9327015d4013	1163	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
bogdanm	88:9327015d4013	1164	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
bogdanm	88:9327015d4013	1165	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
bogdanm	88:9327015d4013	1166	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
bogdanm	88:9327015d4013	1167	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
bogdanm	88:9327015d4013	1168	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
bogdanm	88:9327015d4013	1169	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
bogdanm	88:9327015d4013	1170	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
bogdanm	88:9327015d4013	1171	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
bogdanm	88:9327015d4013	1172	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
bogdanm	88:9327015d4013	1173	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
bogdanm	88:9327015d4013	1174	} MPU_Type;
bogdanm	88:9327015d4013	1175
bogdanm	88:9327015d4013	1176	/* MPU Type Register */
bogdanm	88:9327015d4013	1177	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
bogdanm	88:9327015d4013	1178	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
bogdanm	88:9327015d4013	1179
bogdanm	88:9327015d4013	1180	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
bogdanm	88:9327015d4013	1181	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
bogdanm	88:9327015d4013	1182
bogdanm	88:9327015d4013	1183	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	110:165afa46840b	1184	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
bogdanm	88:9327015d4013	1185
bogdanm	88:9327015d4013	1186	/* MPU Control Register */
bogdanm	88:9327015d4013	1187	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
bogdanm	88:9327015d4013	1188	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
bogdanm	88:9327015d4013	1189
bogdanm	88:9327015d4013	1190	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
bogdanm	88:9327015d4013	1191	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
bogdanm	88:9327015d4013	1192
bogdanm	88:9327015d4013	1193	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	110:165afa46840b	1194	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
bogdanm	88:9327015d4013	1195
bogdanm	88:9327015d4013	1196	/* MPU Region Number Register */
bogdanm	88:9327015d4013	1197	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	110:165afa46840b	1198	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
bogdanm	88:9327015d4013	1199
bogdanm	88:9327015d4013	1200	/* MPU Region Base Address Register */
bogdanm	88:9327015d4013	1201	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
bogdanm	88:9327015d4013	1202	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
bogdanm	88:9327015d4013	1203
bogdanm	88:9327015d4013	1204	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
bogdanm	88:9327015d4013	1205	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
bogdanm	88:9327015d4013	1206
bogdanm	88:9327015d4013	1207	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	110:165afa46840b	1208	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
bogdanm	88:9327015d4013	1209
bogdanm	88:9327015d4013	1210	/* MPU Region Attribute and Size Register */
bogdanm	88:9327015d4013	1211	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
bogdanm	88:9327015d4013	1212	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
bogdanm	88:9327015d4013	1213
bogdanm	88:9327015d4013	1214	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
bogdanm	88:9327015d4013	1215	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
bogdanm	88:9327015d4013	1216
bogdanm	88:9327015d4013	1217	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
bogdanm	88:9327015d4013	1218	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
bogdanm	88:9327015d4013	1219
bogdanm	88:9327015d4013	1220	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
bogdanm	88:9327015d4013	1221	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
bogdanm	88:9327015d4013	1222
bogdanm	88:9327015d4013	1223	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
bogdanm	88:9327015d4013	1224	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
bogdanm	88:9327015d4013	1225
bogdanm	88:9327015d4013	1226	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
bogdanm	88:9327015d4013	1227	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
bogdanm	88:9327015d4013	1228
bogdanm	88:9327015d4013	1229	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
bogdanm	88:9327015d4013	1230	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
bogdanm	88:9327015d4013	1231
bogdanm	88:9327015d4013	1232	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
bogdanm	88:9327015d4013	1233	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
bogdanm	88:9327015d4013	1234
bogdanm	88:9327015d4013	1235	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
bogdanm	88:9327015d4013	1236	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
bogdanm	88:9327015d4013	1237
bogdanm	88:9327015d4013	1238	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	110:165afa46840b	1239	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
bogdanm	88:9327015d4013	1240
bogdanm	88:9327015d4013	1241	/@} end of group CMSIS_MPU /
bogdanm	88:9327015d4013	1242	#endif
bogdanm	88:9327015d4013	1243
bogdanm	88:9327015d4013	1244
bogdanm	88:9327015d4013	1245	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	1246	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	1247	\defgroup CMSIS_FPU Floating Point Unit (FPU)
bogdanm	88:9327015d4013	1248	\brief Type definitions for the Floating Point Unit (FPU)
bogdanm	88:9327015d4013	1249	@{
bogdanm	88:9327015d4013	1250	*/
bogdanm	88:9327015d4013	1251
bogdanm	88:9327015d4013	1252	/** \brief Structure type to access the Floating Point Unit (FPU).
bogdanm	88:9327015d4013	1253	*/
bogdanm	88:9327015d4013	1254	typedef struct
bogdanm	88:9327015d4013	1255	{
bogdanm	88:9327015d4013	1256	uint32_t RESERVED0[1];
bogdanm	88:9327015d4013	1257	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
bogdanm	88:9327015d4013	1258	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
bogdanm	88:9327015d4013	1259	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
bogdanm	88:9327015d4013	1260	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
bogdanm	88:9327015d4013	1261	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
bogdanm	88:9327015d4013	1262	} FPU_Type;
bogdanm	88:9327015d4013	1263
bogdanm	88:9327015d4013	1264	/* Floating-Point Context Control Register */
bogdanm	88:9327015d4013	1265	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
bogdanm	88:9327015d4013	1266	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
bogdanm	88:9327015d4013	1267
bogdanm	88:9327015d4013	1268	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
bogdanm	88:9327015d4013	1269	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
bogdanm	88:9327015d4013	1270
bogdanm	88:9327015d4013	1271	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
bogdanm	88:9327015d4013	1272	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
bogdanm	88:9327015d4013	1273
bogdanm	88:9327015d4013	1274	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
bogdanm	88:9327015d4013	1275	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
bogdanm	88:9327015d4013	1276
bogdanm	88:9327015d4013	1277	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
bogdanm	88:9327015d4013	1278	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
bogdanm	88:9327015d4013	1279
bogdanm	88:9327015d4013	1280	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
bogdanm	88:9327015d4013	1281	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
bogdanm	88:9327015d4013	1282
bogdanm	88:9327015d4013	1283	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
bogdanm	88:9327015d4013	1284	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
bogdanm	88:9327015d4013	1285
bogdanm	88:9327015d4013	1286	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
bogdanm	88:9327015d4013	1287	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
bogdanm	88:9327015d4013	1288
bogdanm	88:9327015d4013	1289	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Kojto	110:165afa46840b	1290	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
bogdanm	88:9327015d4013	1291
bogdanm	88:9327015d4013	1292	/* Floating-Point Context Address Register */
bogdanm	88:9327015d4013	1293	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
bogdanm	88:9327015d4013	1294	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
bogdanm	88:9327015d4013	1295
bogdanm	88:9327015d4013	1296	/* Floating-Point Default Status Control Register */
bogdanm	88:9327015d4013	1297	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
bogdanm	88:9327015d4013	1298	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
bogdanm	88:9327015d4013	1299
bogdanm	88:9327015d4013	1300	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
bogdanm	88:9327015d4013	1301	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
bogdanm	88:9327015d4013	1302
bogdanm	88:9327015d4013	1303	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
bogdanm	88:9327015d4013	1304	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
bogdanm	88:9327015d4013	1305
bogdanm	88:9327015d4013	1306	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
bogdanm	88:9327015d4013	1307	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
bogdanm	88:9327015d4013	1308
bogdanm	88:9327015d4013	1309	/* Media and FP Feature Register 0 */
bogdanm	88:9327015d4013	1310	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
bogdanm	88:9327015d4013	1311	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
bogdanm	88:9327015d4013	1312
bogdanm	88:9327015d4013	1313	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
bogdanm	88:9327015d4013	1314	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
bogdanm	88:9327015d4013	1315
bogdanm	88:9327015d4013	1316	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
bogdanm	88:9327015d4013	1317	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
bogdanm	88:9327015d4013	1318
bogdanm	88:9327015d4013	1319	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
bogdanm	88:9327015d4013	1320	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
bogdanm	88:9327015d4013	1321
bogdanm	88:9327015d4013	1322	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
bogdanm	88:9327015d4013	1323	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
bogdanm	88:9327015d4013	1324
bogdanm	88:9327015d4013	1325	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
bogdanm	88:9327015d4013	1326	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
bogdanm	88:9327015d4013	1327
bogdanm	88:9327015d4013	1328	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
bogdanm	88:9327015d4013	1329	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
bogdanm	88:9327015d4013	1330
bogdanm	88:9327015d4013	1331	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Kojto	110:165afa46840b	1332	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
bogdanm	88:9327015d4013	1333
bogdanm	88:9327015d4013	1334	/* Media and FP Feature Register 1 */
bogdanm	88:9327015d4013	1335	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
bogdanm	88:9327015d4013	1336	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
bogdanm	88:9327015d4013	1337
bogdanm	88:9327015d4013	1338	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
bogdanm	88:9327015d4013	1339	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
bogdanm	88:9327015d4013	1340
bogdanm	88:9327015d4013	1341	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
bogdanm	88:9327015d4013	1342	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
bogdanm	88:9327015d4013	1343
bogdanm	88:9327015d4013	1344	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Kojto	110:165afa46840b	1345	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
bogdanm	88:9327015d4013	1346
bogdanm	88:9327015d4013	1347	/@} end of group CMSIS_FPU /
bogdanm	88:9327015d4013	1348	#endif
bogdanm	88:9327015d4013	1349
bogdanm	88:9327015d4013	1350
bogdanm	88:9327015d4013	1351	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	1352	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm	88:9327015d4013	1353	\brief Type definitions for the Core Debug Registers
bogdanm	88:9327015d4013	1354	@{
bogdanm	88:9327015d4013	1355	*/
bogdanm	88:9327015d4013	1356
bogdanm	88:9327015d4013	1357	/** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm	88:9327015d4013	1358	*/
bogdanm	88:9327015d4013	1359	typedef struct
bogdanm	88:9327015d4013	1360	{
bogdanm	88:9327015d4013	1361	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
bogdanm	88:9327015d4013	1362	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
bogdanm	88:9327015d4013	1363	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
bogdanm	88:9327015d4013	1364	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
bogdanm	88:9327015d4013	1365	} CoreDebug_Type;
bogdanm	88:9327015d4013	1366
bogdanm	88:9327015d4013	1367	/* Debug Halting Control and Status Register */
bogdanm	88:9327015d4013	1368	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
bogdanm	88:9327015d4013	1369	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
bogdanm	88:9327015d4013	1370
bogdanm	88:9327015d4013	1371	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
bogdanm	88:9327015d4013	1372	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
bogdanm	88:9327015d4013	1373
bogdanm	88:9327015d4013	1374	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
bogdanm	88:9327015d4013	1375	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
bogdanm	88:9327015d4013	1376
bogdanm	88:9327015d4013	1377	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
bogdanm	88:9327015d4013	1378	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
bogdanm	88:9327015d4013	1379
bogdanm	88:9327015d4013	1380	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
bogdanm	88:9327015d4013	1381	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
bogdanm	88:9327015d4013	1382
bogdanm	88:9327015d4013	1383	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
bogdanm	88:9327015d4013	1384	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
bogdanm	88:9327015d4013	1385
bogdanm	88:9327015d4013	1386	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
bogdanm	88:9327015d4013	1387	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
bogdanm	88:9327015d4013	1388
bogdanm	88:9327015d4013	1389	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
bogdanm	88:9327015d4013	1390	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
bogdanm	88:9327015d4013	1391
bogdanm	88:9327015d4013	1392	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
bogdanm	88:9327015d4013	1393	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
bogdanm	88:9327015d4013	1394
bogdanm	88:9327015d4013	1395	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
bogdanm	88:9327015d4013	1396	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
bogdanm	88:9327015d4013	1397
bogdanm	88:9327015d4013	1398	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
bogdanm	88:9327015d4013	1399	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
bogdanm	88:9327015d4013	1400
bogdanm	88:9327015d4013	1401	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	110:165afa46840b	1402	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
bogdanm	88:9327015d4013	1403
bogdanm	88:9327015d4013	1404	/* Debug Core Register Selector Register */
bogdanm	88:9327015d4013	1405	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
bogdanm	88:9327015d4013	1406	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
bogdanm	88:9327015d4013	1407
bogdanm	88:9327015d4013	1408	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	110:165afa46840b	1409	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
bogdanm	88:9327015d4013	1410
bogdanm	88:9327015d4013	1411	/* Debug Exception and Monitor Control Register */
bogdanm	88:9327015d4013	1412	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
bogdanm	88:9327015d4013	1413	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
bogdanm	88:9327015d4013	1414
bogdanm	88:9327015d4013	1415	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
bogdanm	88:9327015d4013	1416	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
bogdanm	88:9327015d4013	1417
bogdanm	88:9327015d4013	1418	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
bogdanm	88:9327015d4013	1419	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
bogdanm	88:9327015d4013	1420
bogdanm	88:9327015d4013	1421	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
bogdanm	88:9327015d4013	1422	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
bogdanm	88:9327015d4013	1423
bogdanm	88:9327015d4013	1424	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
bogdanm	88:9327015d4013	1425	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
bogdanm	88:9327015d4013	1426
bogdanm	88:9327015d4013	1427	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
bogdanm	88:9327015d4013	1428	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
bogdanm	88:9327015d4013	1429
bogdanm	88:9327015d4013	1430	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
bogdanm	88:9327015d4013	1431	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
bogdanm	88:9327015d4013	1432
bogdanm	88:9327015d4013	1433	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
bogdanm	88:9327015d4013	1434	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
bogdanm	88:9327015d4013	1435
bogdanm	88:9327015d4013	1436	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
bogdanm	88:9327015d4013	1437	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
bogdanm	88:9327015d4013	1438
bogdanm	88:9327015d4013	1439	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
bogdanm	88:9327015d4013	1440	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
bogdanm	88:9327015d4013	1441
bogdanm	88:9327015d4013	1442	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
bogdanm	88:9327015d4013	1443	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
bogdanm	88:9327015d4013	1444
bogdanm	88:9327015d4013	1445	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
bogdanm	88:9327015d4013	1446	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
bogdanm	88:9327015d4013	1447
bogdanm	88:9327015d4013	1448	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	110:165afa46840b	1449	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
bogdanm	88:9327015d4013	1450
bogdanm	88:9327015d4013	1451	/@} end of group CMSIS_CoreDebug /
bogdanm	88:9327015d4013	1452
bogdanm	88:9327015d4013	1453
bogdanm	88:9327015d4013	1454	/** \ingroup CMSIS_core_register
bogdanm	88:9327015d4013	1455	\defgroup CMSIS_core_base Core Definitions
bogdanm	88:9327015d4013	1456	\brief Definitions for base addresses, unions, and structures.
bogdanm	88:9327015d4013	1457	@{
bogdanm	88:9327015d4013	1458	*/
bogdanm	88:9327015d4013	1459
bogdanm	88:9327015d4013	1460	/* Memory mapping of Cortex-M4 Hardware */
bogdanm	88:9327015d4013	1461	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
bogdanm	88:9327015d4013	1462	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
bogdanm	88:9327015d4013	1463	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
bogdanm	88:9327015d4013	1464	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
bogdanm	88:9327015d4013	1465	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
bogdanm	88:9327015d4013	1466	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
bogdanm	88:9327015d4013	1467	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
bogdanm	88:9327015d4013	1468	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
bogdanm	88:9327015d4013	1469
bogdanm	88:9327015d4013	1470	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
bogdanm	88:9327015d4013	1471	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
bogdanm	88:9327015d4013	1472	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
bogdanm	88:9327015d4013	1473	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
bogdanm	88:9327015d4013	1474	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
bogdanm	88:9327015d4013	1475	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
bogdanm	88:9327015d4013	1476	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
bogdanm	88:9327015d4013	1477	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
bogdanm	88:9327015d4013	1478
bogdanm	88:9327015d4013	1479	#if (__MPU_PRESENT == 1)
bogdanm	88:9327015d4013	1480	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
bogdanm	88:9327015d4013	1481	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
bogdanm	88:9327015d4013	1482	#endif
bogdanm	88:9327015d4013	1483
bogdanm	88:9327015d4013	1484	#if (__FPU_PRESENT == 1)
bogdanm	88:9327015d4013	1485	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
bogdanm	88:9327015d4013	1486	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
bogdanm	88:9327015d4013	1487	#endif
bogdanm	88:9327015d4013	1488
bogdanm	88:9327015d4013	1489	/@} /
bogdanm	88:9327015d4013	1490
bogdanm	88:9327015d4013	1491
bogdanm	88:9327015d4013	1492
bogdanm	88:9327015d4013	1493	/*******************************************************************************
bogdanm	88:9327015d4013	1494	* Hardware Abstraction Layer
bogdanm	88:9327015d4013	1495	Core Function Interface contains:
bogdanm	88:9327015d4013	1496	- Core NVIC Functions
bogdanm	88:9327015d4013	1497	- Core SysTick Functions
bogdanm	88:9327015d4013	1498	- Core Debug Functions
bogdanm	88:9327015d4013	1499	- Core Register Access Functions
bogdanm	88:9327015d4013	1500	******************************************************************************/
bogdanm	88:9327015d4013	1501	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm	88:9327015d4013	1502	*/
bogdanm	88:9327015d4013	1503
bogdanm	88:9327015d4013	1504
bogdanm	88:9327015d4013	1505
bogdanm	88:9327015d4013	1506	/* ########################## NVIC functions #################################### */
bogdanm	88:9327015d4013	1507	/** \ingroup CMSIS_Core_FunctionInterface
bogdanm	88:9327015d4013	1508	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm	88:9327015d4013	1509	\brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm	88:9327015d4013	1510	@{
bogdanm	88:9327015d4013	1511	*/
bogdanm	88:9327015d4013	1512
Kojto	122:f9eeca106725	1513	#ifdef CMSIS_NVIC_VIRTUAL
Kojto	122:f9eeca106725	1514	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1515	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto	122:f9eeca106725	1516	#endif
Kojto	122:f9eeca106725	1517	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1518	#else
Kojto	122:f9eeca106725	1519	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Kojto	122:f9eeca106725	1520	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Kojto	122:f9eeca106725	1521	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto	122:f9eeca106725	1522	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto	122:f9eeca106725	1523	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto	122:f9eeca106725	1524	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto	122:f9eeca106725	1525	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto	122:f9eeca106725	1526	#define NVIC_GetActive __NVIC_GetActive
Kojto	122:f9eeca106725	1527	#define NVIC_SetPriority __NVIC_SetPriority
Kojto	122:f9eeca106725	1528	#define NVIC_GetPriority __NVIC_GetPriority
<>	128:9bcdf88f62b0	1529	#define NVIC_SystemReset __NVIC_SystemReset
Kojto	122:f9eeca106725	1530	#endif /* CMSIS_NVIC_VIRTUAL */
Kojto	122:f9eeca106725	1531
Kojto	122:f9eeca106725	1532	#ifdef CMSIS_VECTAB_VIRTUAL
Kojto	122:f9eeca106725	1533	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1534	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto	122:f9eeca106725	1535	#endif
Kojto	122:f9eeca106725	1536	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	122:f9eeca106725	1537	#else
Kojto	122:f9eeca106725	1538	#define NVIC_SetVector __NVIC_SetVector
Kojto	122:f9eeca106725	1539	#define NVIC_GetVector __NVIC_GetVector
Kojto	122:f9eeca106725	1540	#endif /* CMSIS_VECTAB_VIRTUAL */
Kojto	122:f9eeca106725	1541
Kojto	122:f9eeca106725	1542
bogdanm	88:9327015d4013	1543	/** \brief Set Priority Grouping
bogdanm	88:9327015d4013	1544
bogdanm	88:9327015d4013	1545	The function sets the priority grouping field using the required unlock sequence.
bogdanm	88:9327015d4013	1546	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm	88:9327015d4013	1547	Only values from 0..7 are used.
bogdanm	88:9327015d4013	1548	In case of a conflict between priority grouping and available
bogdanm	88:9327015d4013	1549	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm	88:9327015d4013	1550
bogdanm	88:9327015d4013	1551	\param [in] PriorityGroup Priority grouping field.
bogdanm	88:9327015d4013	1552	*/
Kojto	122:f9eeca106725	1553	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm	88:9327015d4013	1554	{
bogdanm	88:9327015d4013	1555	uint32_t reg_value;
Kojto	110:165afa46840b	1556	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm	88:9327015d4013	1557
bogdanm	88:9327015d4013	1558	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	110:165afa46840b	1559	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	110:165afa46840b	1560	reg_value = (reg_value \|
Kojto	110:165afa46840b	1561	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1562	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
bogdanm	88:9327015d4013	1563	SCB->AIRCR = reg_value;
bogdanm	88:9327015d4013	1564	}
bogdanm	88:9327015d4013	1565
bogdanm	88:9327015d4013	1566
bogdanm	88:9327015d4013	1567	/** \brief Get Priority Grouping
bogdanm	88:9327015d4013	1568
bogdanm	88:9327015d4013	1569	The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm	88:9327015d4013	1570
bogdanm	88:9327015d4013	1571	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm	88:9327015d4013	1572	*/
Kojto	122:f9eeca106725	1573	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
bogdanm	88:9327015d4013	1574	{
Kojto	110:165afa46840b	1575	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
bogdanm	88:9327015d4013	1576	}
bogdanm	88:9327015d4013	1577
bogdanm	88:9327015d4013	1578
bogdanm	88:9327015d4013	1579	/** \brief Enable External Interrupt
bogdanm	88:9327015d4013	1580
bogdanm	88:9327015d4013	1581	The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm	88:9327015d4013	1582
bogdanm	88:9327015d4013	1583	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	88:9327015d4013	1584	*/
Kojto	122:f9eeca106725	1585	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1586	{
Kojto	110:165afa46840b	1587	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm	88:9327015d4013	1588	}
bogdanm	88:9327015d4013	1589
bogdanm	88:9327015d4013	1590
bogdanm	88:9327015d4013	1591	/** \brief Disable External Interrupt
bogdanm	88:9327015d4013	1592
bogdanm	88:9327015d4013	1593	The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm	88:9327015d4013	1594
bogdanm	88:9327015d4013	1595	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	88:9327015d4013	1596	*/
Kojto	122:f9eeca106725	1597	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1598	{
Kojto	110:165afa46840b	1599	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	131:faff56e089b2	1600	__DSB();
<>	131:faff56e089b2	1601	__ISB();
bogdanm	88:9327015d4013	1602	}
bogdanm	88:9327015d4013	1603
bogdanm	88:9327015d4013	1604
bogdanm	88:9327015d4013	1605	/** \brief Get Pending Interrupt
bogdanm	88:9327015d4013	1606
bogdanm	88:9327015d4013	1607	The function reads the pending register in the NVIC and returns the pending bit
bogdanm	88:9327015d4013	1608	for the specified interrupt.
bogdanm	88:9327015d4013	1609
bogdanm	88:9327015d4013	1610	\param [in] IRQn Interrupt number.
bogdanm	88:9327015d4013	1611
bogdanm	88:9327015d4013	1612	\return 0 Interrupt status is not pending.
bogdanm	88:9327015d4013	1613	\return 1 Interrupt status is pending.
bogdanm	88:9327015d4013	1614	*/
Kojto	122:f9eeca106725	1615	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1616	{
Kojto	110:165afa46840b	1617	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm	88:9327015d4013	1618	}
bogdanm	88:9327015d4013	1619
bogdanm	88:9327015d4013	1620
bogdanm	88:9327015d4013	1621	/** \brief Set Pending Interrupt
bogdanm	88:9327015d4013	1622
bogdanm	88:9327015d4013	1623	The function sets the pending bit of an external interrupt.
bogdanm	88:9327015d4013	1624
bogdanm	88:9327015d4013	1625	\param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm	88:9327015d4013	1626	*/
Kojto	122:f9eeca106725	1627	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1628	{
Kojto	110:165afa46840b	1629	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm	88:9327015d4013	1630	}
bogdanm	88:9327015d4013	1631
bogdanm	88:9327015d4013	1632
bogdanm	88:9327015d4013	1633	/** \brief Clear Pending Interrupt
bogdanm	88:9327015d4013	1634
bogdanm	88:9327015d4013	1635	The function clears the pending bit of an external interrupt.
bogdanm	88:9327015d4013	1636
bogdanm	88:9327015d4013	1637	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	88:9327015d4013	1638	*/
Kojto	122:f9eeca106725	1639	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1640	{
Kojto	110:165afa46840b	1641	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm	88:9327015d4013	1642	}
bogdanm	88:9327015d4013	1643
bogdanm	88:9327015d4013	1644
bogdanm	88:9327015d4013	1645	/** \brief Get Active Interrupt
bogdanm	88:9327015d4013	1646
bogdanm	88:9327015d4013	1647	The function reads the active register in NVIC and returns the active bit.
bogdanm	88:9327015d4013	1648
bogdanm	88:9327015d4013	1649	\param [in] IRQn Interrupt number.
bogdanm	88:9327015d4013	1650
bogdanm	88:9327015d4013	1651	\return 0 Interrupt status is not active.
bogdanm	88:9327015d4013	1652	\return 1 Interrupt status is active.
bogdanm	88:9327015d4013	1653	*/
Kojto	122:f9eeca106725	1654	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1655	{
Kojto	110:165afa46840b	1656	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm	88:9327015d4013	1657	}
bogdanm	88:9327015d4013	1658
bogdanm	88:9327015d4013	1659
bogdanm	88:9327015d4013	1660	/** \brief Set Interrupt Priority
bogdanm	88:9327015d4013	1661
bogdanm	88:9327015d4013	1662	The function sets the priority of an interrupt.
bogdanm	88:9327015d4013	1663
bogdanm	88:9327015d4013	1664	\note The priority cannot be set for every core interrupt.
bogdanm	88:9327015d4013	1665
bogdanm	88:9327015d4013	1666	\param [in] IRQn Interrupt number.
bogdanm	88:9327015d4013	1667	\param [in] priority Priority to set.
bogdanm	88:9327015d4013	1668	*/
Kojto	122:f9eeca106725	1669	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm	88:9327015d4013	1670	{
Kojto	110:165afa46840b	1671	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1672	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1673	}
bogdanm	88:9327015d4013	1674	else {
Kojto	110:165afa46840b	1675	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	110:165afa46840b	1676	}
bogdanm	88:9327015d4013	1677	}
bogdanm	88:9327015d4013	1678
bogdanm	88:9327015d4013	1679
bogdanm	88:9327015d4013	1680	/** \brief Get Interrupt Priority
bogdanm	88:9327015d4013	1681
bogdanm	88:9327015d4013	1682	The function reads the priority of an interrupt. The interrupt
bogdanm	88:9327015d4013	1683	number can be positive to specify an external (device specific)
bogdanm	88:9327015d4013	1684	interrupt, or negative to specify an internal (core) interrupt.
bogdanm	88:9327015d4013	1685
bogdanm	88:9327015d4013	1686
bogdanm	88:9327015d4013	1687	\param [in] IRQn Interrupt number.
bogdanm	88:9327015d4013	1688	\return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm	88:9327015d4013	1689	priority bits of the microcontroller.
bogdanm	88:9327015d4013	1690	*/
Kojto	122:f9eeca106725	1691	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
bogdanm	88:9327015d4013	1692	{
bogdanm	88:9327015d4013	1693
Kojto	110:165afa46840b	1694	if((int32_t)IRQn < 0) {
Kojto	110:165afa46840b	1695	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1696	}
bogdanm	88:9327015d4013	1697	else {
Kojto	110:165afa46840b	1698	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	110:165afa46840b	1699	}
bogdanm	88:9327015d4013	1700	}
bogdanm	88:9327015d4013	1701
bogdanm	88:9327015d4013	1702
bogdanm	88:9327015d4013	1703	/** \brief Encode Priority
bogdanm	88:9327015d4013	1704
bogdanm	88:9327015d4013	1705	The function encodes the priority for an interrupt with the given priority group,
bogdanm	88:9327015d4013	1706	preemptive priority value, and subpriority value.
bogdanm	88:9327015d4013	1707	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1708	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm	88:9327015d4013	1709
bogdanm	88:9327015d4013	1710	\param [in] PriorityGroup Used priority group.
bogdanm	88:9327015d4013	1711	\param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm	88:9327015d4013	1712	\param [in] SubPriority Subpriority value (starting from 0).
bogdanm	88:9327015d4013	1713	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm	88:9327015d4013	1714	*/
bogdanm	88:9327015d4013	1715	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm	88:9327015d4013	1716	{
Kojto	110:165afa46840b	1717	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm	88:9327015d4013	1718	uint32_t PreemptPriorityBits;
bogdanm	88:9327015d4013	1719	uint32_t SubPriorityBits;
bogdanm	88:9327015d4013	1720
Kojto	110:165afa46840b	1721	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1722	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm	88:9327015d4013	1723
bogdanm	88:9327015d4013	1724	return (
Kojto	110:165afa46840b	1725	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	110:165afa46840b	1726	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
bogdanm	88:9327015d4013	1727	);
bogdanm	88:9327015d4013	1728	}
bogdanm	88:9327015d4013	1729
bogdanm	88:9327015d4013	1730
bogdanm	88:9327015d4013	1731	/** \brief Decode Priority
bogdanm	88:9327015d4013	1732
bogdanm	88:9327015d4013	1733	The function decodes an interrupt priority value with a given priority group to
bogdanm	88:9327015d4013	1734	preemptive priority value and subpriority value.
bogdanm	88:9327015d4013	1735	In case of a conflict between priority grouping and available
Kojto	110:165afa46840b	1736	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
bogdanm	88:9327015d4013	1737
bogdanm	88:9327015d4013	1738	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm	88:9327015d4013	1739	\param [in] PriorityGroup Used priority group.
bogdanm	88:9327015d4013	1740	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm	88:9327015d4013	1741	\param [out] pSubPriority Subpriority value (starting from 0).
bogdanm	88:9327015d4013	1742	*/
bogdanm	88:9327015d4013	1743	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm	88:9327015d4013	1744	{
Kojto	110:165afa46840b	1745	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm	88:9327015d4013	1746	uint32_t PreemptPriorityBits;
bogdanm	88:9327015d4013	1747	uint32_t SubPriorityBits;
bogdanm	88:9327015d4013	1748
Kojto	110:165afa46840b	1749	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	110:165afa46840b	1750	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm	88:9327015d4013	1751
Kojto	110:165afa46840b	1752	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	110:165afa46840b	1753	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
bogdanm	88:9327015d4013	1754	}
bogdanm	88:9327015d4013	1755
bogdanm	88:9327015d4013	1756
bogdanm	88:9327015d4013	1757	/** \brief System Reset
bogdanm	88:9327015d4013	1758
bogdanm	88:9327015d4013	1759	The function initiates a system reset request to reset the MCU.
bogdanm	88:9327015d4013	1760	*/
<>	128:9bcdf88f62b0	1761	__STATIC_INLINE void __NVIC_SystemReset(void)
bogdanm	88:9327015d4013	1762	{
Kojto	110:165afa46840b	1763	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	110:165afa46840b	1764	buffered write are completed before reset */
Kojto	110:165afa46840b	1765	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	110:165afa46840b	1766	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	110:165afa46840b	1767	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	110:165afa46840b	1768	__DSB(); /* Ensure completion of memory access */
Kojto	110:165afa46840b	1769	while(1) { __NOP(); } /* wait until reset */
bogdanm	88:9327015d4013	1770	}
bogdanm	88:9327015d4013	1771
bogdanm	88:9327015d4013	1772	/@} end of CMSIS_Core_NVICFunctions /
bogdanm	88:9327015d4013	1773
bogdanm	88:9327015d4013	1774
bogdanm	88:9327015d4013	1775
bogdanm	88:9327015d4013	1776	/* ################################## SysTick function ############################################ */
bogdanm	88:9327015d4013	1777	/** \ingroup CMSIS_Core_FunctionInterface
bogdanm	88:9327015d4013	1778	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm	88:9327015d4013	1779	\brief Functions that configure the System.
bogdanm	88:9327015d4013	1780	@{
bogdanm	88:9327015d4013	1781	*/
bogdanm	88:9327015d4013	1782
bogdanm	88:9327015d4013	1783	#if (__Vendor_SysTickConfig == 0)
bogdanm	88:9327015d4013	1784
bogdanm	88:9327015d4013	1785	/** \brief System Tick Configuration
bogdanm	88:9327015d4013	1786
bogdanm	88:9327015d4013	1787	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm	88:9327015d4013	1788	Counter is in free running mode to generate periodic interrupts.
bogdanm	88:9327015d4013	1789
bogdanm	88:9327015d4013	1790	\param [in] ticks Number of ticks between two interrupts.
bogdanm	88:9327015d4013	1791
bogdanm	88:9327015d4013	1792	\return 0 Function succeeded.
bogdanm	88:9327015d4013	1793	\return 1 Function failed.
bogdanm	88:9327015d4013	1794
bogdanm	88:9327015d4013	1795	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm	88:9327015d4013	1796	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm	88:9327015d4013	1797	must contain a vendor-specific implementation of this function.
bogdanm	88:9327015d4013	1798
bogdanm	88:9327015d4013	1799	*/
bogdanm	88:9327015d4013	1800	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm	88:9327015d4013	1801	{
Kojto	110:165afa46840b	1802	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm	88:9327015d4013	1803
Kojto	110:165afa46840b	1804	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	110:165afa46840b	1805	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	110:165afa46840b	1806	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm	88:9327015d4013	1807	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
bogdanm	88:9327015d4013	1808	SysTick_CTRL_TICKINT_Msk \|
Kojto	110:165afa46840b	1809	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	110:165afa46840b	1810	return (0UL); /* Function successful */
bogdanm	88:9327015d4013	1811	}
bogdanm	88:9327015d4013	1812
bogdanm	88:9327015d4013	1813	#endif
bogdanm	88:9327015d4013	1814
bogdanm	88:9327015d4013	1815	/@} end of CMSIS_Core_SysTickFunctions /
bogdanm	88:9327015d4013	1816
bogdanm	88:9327015d4013	1817
bogdanm	88:9327015d4013	1818
bogdanm	88:9327015d4013	1819	/* ##################################### Debug In/Output function ########################################### */
bogdanm	88:9327015d4013	1820	/** \ingroup CMSIS_Core_FunctionInterface
bogdanm	88:9327015d4013	1821	\defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm	88:9327015d4013	1822	\brief Functions that access the ITM debug interface.
bogdanm	88:9327015d4013	1823	@{
bogdanm	88:9327015d4013	1824	*/
bogdanm	88:9327015d4013	1825
bogdanm	88:9327015d4013	1826	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
bogdanm	88:9327015d4013	1827	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
bogdanm	88:9327015d4013	1828
bogdanm	88:9327015d4013	1829
bogdanm	88:9327015d4013	1830	/** \brief ITM Send Character
bogdanm	88:9327015d4013	1831
bogdanm	88:9327015d4013	1832	The function transmits a character via the ITM channel 0, and
bogdanm	88:9327015d4013	1833	\li Just returns when no debugger is connected that has booked the output.
bogdanm	88:9327015d4013	1834	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm	88:9327015d4013	1835
bogdanm	88:9327015d4013	1836	\param [in] ch Character to transmit.
bogdanm	88:9327015d4013	1837
bogdanm	88:9327015d4013	1838	\returns Character to transmit.
bogdanm	88:9327015d4013	1839	*/
bogdanm	88:9327015d4013	1840	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm	88:9327015d4013	1841	{
Kojto	110:165afa46840b	1842	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	110:165afa46840b	1843	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
bogdanm	88:9327015d4013	1844	{
Kojto	110:165afa46840b	1845	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	110:165afa46840b	1846	ITM->PORT[0].u8 = (uint8_t)ch;
bogdanm	88:9327015d4013	1847	}
bogdanm	88:9327015d4013	1848	return (ch);
bogdanm	88:9327015d4013	1849	}
bogdanm	88:9327015d4013	1850
bogdanm	88:9327015d4013	1851
bogdanm	88:9327015d4013	1852	/** \brief ITM Receive Character
bogdanm	88:9327015d4013	1853
bogdanm	88:9327015d4013	1854	The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm	88:9327015d4013	1855
bogdanm	88:9327015d4013	1856	\return Received character.
bogdanm	88:9327015d4013	1857	\return -1 No character pending.
bogdanm	88:9327015d4013	1858	*/
bogdanm	88:9327015d4013	1859	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm	88:9327015d4013	1860	int32_t ch = -1; /* no character available */
bogdanm	88:9327015d4013	1861
bogdanm	88:9327015d4013	1862	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm	88:9327015d4013	1863	ch = ITM_RxBuffer;
bogdanm	88:9327015d4013	1864	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm	88:9327015d4013	1865	}
bogdanm	88:9327015d4013	1866
bogdanm	88:9327015d4013	1867	return (ch);
bogdanm	88:9327015d4013	1868	}
bogdanm	88:9327015d4013	1869
bogdanm	88:9327015d4013	1870
bogdanm	88:9327015d4013	1871	/** \brief ITM Check Character
bogdanm	88:9327015d4013	1872
bogdanm	88:9327015d4013	1873	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm	88:9327015d4013	1874
bogdanm	88:9327015d4013	1875	\return 0 No character available.
bogdanm	88:9327015d4013	1876	\return 1 Character available.
bogdanm	88:9327015d4013	1877	*/
bogdanm	88:9327015d4013	1878	__STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm	88:9327015d4013	1879
bogdanm	88:9327015d4013	1880	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm	88:9327015d4013	1881	return (0); /* no character available */
bogdanm	88:9327015d4013	1882	} else {
bogdanm	88:9327015d4013	1883	return (1); /* character available */
bogdanm	88:9327015d4013	1884	}
bogdanm	88:9327015d4013	1885	}
bogdanm	88:9327015d4013	1886
bogdanm	88:9327015d4013	1887	/@} end of CMSIS_core_DebugFunctions /
bogdanm	88:9327015d4013	1888
bogdanm	88:9327015d4013	1889
Kojto	110:165afa46840b	1890
bogdanm	88:9327015d4013	1891
bogdanm	88:9327015d4013	1892	#ifdef __cplusplus
bogdanm	88:9327015d4013	1893	}
bogdanm	88:9327015d4013	1894	#endif
Kojto	110:165afa46840b	1895
Kojto	110:165afa46840b	1896	#endif /* __CORE_CM4_H_DEPENDANT */
Kojto	110:165afa46840b	1897
Kojto	110:165afa46840b	1898	#endif /* __CMSIS_GENERIC */