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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K82F/core_cmInstr.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
129:0ab6a29f35bf 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 /**************************************************************************//**
<> 129:0ab6a29f35bf 2 * @file core_cmInstr.h
<> 129:0ab6a29f35bf 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 129:0ab6a29f35bf 4 * @version V4.10
<> 129:0ab6a29f35bf 5 * @date 18. March 2015
<> 129:0ab6a29f35bf 6 *
<> 129:0ab6a29f35bf 7 * @note
<> 129:0ab6a29f35bf 8 *
<> 129:0ab6a29f35bf 9 ******************************************************************************/
<> 129:0ab6a29f35bf 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 129:0ab6a29f35bf 11
<> 129:0ab6a29f35bf 12 All rights reserved.
<> 129:0ab6a29f35bf 13 Redistribution and use in source and binary forms, with or without
<> 129:0ab6a29f35bf 14 modification, are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 15 - Redistributions of source code must retain the above copyright
<> 129:0ab6a29f35bf 16 notice, this list of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 17 - Redistributions in binary form must reproduce the above copyright
<> 129:0ab6a29f35bf 18 notice, this list of conditions and the following disclaimer in the
<> 129:0ab6a29f35bf 19 documentation and/or other materials provided with the distribution.
<> 129:0ab6a29f35bf 20 - Neither the name of ARM nor the names of its contributors may be used
<> 129:0ab6a29f35bf 21 to endorse or promote products derived from this software without
<> 129:0ab6a29f35bf 22 specific prior written permission.
<> 129:0ab6a29f35bf 23 *
<> 129:0ab6a29f35bf 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 129:0ab6a29f35bf 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 129:0ab6a29f35bf 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 129:0ab6a29f35bf 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 129:0ab6a29f35bf 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 129:0ab6a29f35bf 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 129:0ab6a29f35bf 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 129:0ab6a29f35bf 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 129:0ab6a29f35bf 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 129:0ab6a29f35bf 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 129:0ab6a29f35bf 34 POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 35 ---------------------------------------------------------------------------*/
<> 129:0ab6a29f35bf 36
<> 129:0ab6a29f35bf 37
<> 129:0ab6a29f35bf 38 #ifndef __CORE_CMINSTR_H
<> 129:0ab6a29f35bf 39 #define __CORE_CMINSTR_H
<> 129:0ab6a29f35bf 40
<> 129:0ab6a29f35bf 41
<> 129:0ab6a29f35bf 42 /* ########################## Core Instruction Access ######################### */
<> 129:0ab6a29f35bf 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 129:0ab6a29f35bf 44 Access to dedicated instructions
<> 129:0ab6a29f35bf 45 @{
<> 129:0ab6a29f35bf 46 */
<> 129:0ab6a29f35bf 47
<> 129:0ab6a29f35bf 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 129:0ab6a29f35bf 49 /* ARM armcc specific functions */
<> 129:0ab6a29f35bf 50
<> 129:0ab6a29f35bf 51 #if (__ARMCC_VERSION < 400677)
<> 129:0ab6a29f35bf 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 129:0ab6a29f35bf 53 #endif
<> 129:0ab6a29f35bf 54
<> 129:0ab6a29f35bf 55
<> 129:0ab6a29f35bf 56 /** \brief No Operation
<> 129:0ab6a29f35bf 57
<> 129:0ab6a29f35bf 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 129:0ab6a29f35bf 59 */
<> 129:0ab6a29f35bf 60 #define __NOP __nop
<> 129:0ab6a29f35bf 61
<> 129:0ab6a29f35bf 62
<> 129:0ab6a29f35bf 63 /** \brief Wait For Interrupt
<> 129:0ab6a29f35bf 64
<> 129:0ab6a29f35bf 65 Wait For Interrupt is a hint instruction that suspends execution
<> 129:0ab6a29f35bf 66 until one of a number of events occurs.
<> 129:0ab6a29f35bf 67 */
<> 129:0ab6a29f35bf 68 #define __WFI __wfi
<> 129:0ab6a29f35bf 69
<> 129:0ab6a29f35bf 70
<> 129:0ab6a29f35bf 71 /** \brief Wait For Event
<> 129:0ab6a29f35bf 72
<> 129:0ab6a29f35bf 73 Wait For Event is a hint instruction that permits the processor to enter
<> 129:0ab6a29f35bf 74 a low-power state until one of a number of events occurs.
<> 129:0ab6a29f35bf 75 */
<> 129:0ab6a29f35bf 76 #define __WFE __wfe
<> 129:0ab6a29f35bf 77
<> 129:0ab6a29f35bf 78
<> 129:0ab6a29f35bf 79 /** \brief Send Event
<> 129:0ab6a29f35bf 80
<> 129:0ab6a29f35bf 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 129:0ab6a29f35bf 82 */
<> 129:0ab6a29f35bf 83 #define __SEV __sev
<> 129:0ab6a29f35bf 84
<> 129:0ab6a29f35bf 85
<> 129:0ab6a29f35bf 86 /** \brief Instruction Synchronization Barrier
<> 129:0ab6a29f35bf 87
<> 129:0ab6a29f35bf 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 129:0ab6a29f35bf 89 so that all instructions following the ISB are fetched from cache or
<> 129:0ab6a29f35bf 90 memory, after the instruction has been completed.
<> 129:0ab6a29f35bf 91 */
<> 129:0ab6a29f35bf 92 #define __ISB() do {\
<> 129:0ab6a29f35bf 93 __schedule_barrier();\
<> 129:0ab6a29f35bf 94 __isb(0xF);\
<> 129:0ab6a29f35bf 95 __schedule_barrier();\
<> 129:0ab6a29f35bf 96 } while (0)
<> 129:0ab6a29f35bf 97
<> 129:0ab6a29f35bf 98 /** \brief Data Synchronization Barrier
<> 129:0ab6a29f35bf 99
<> 129:0ab6a29f35bf 100 This function acts as a special kind of Data Memory Barrier.
<> 129:0ab6a29f35bf 101 It completes when all explicit memory accesses before this instruction complete.
<> 129:0ab6a29f35bf 102 */
<> 129:0ab6a29f35bf 103 #define __DSB() do {\
<> 129:0ab6a29f35bf 104 __schedule_barrier();\
<> 129:0ab6a29f35bf 105 __dsb(0xF);\
<> 129:0ab6a29f35bf 106 __schedule_barrier();\
<> 129:0ab6a29f35bf 107 } while (0)
<> 129:0ab6a29f35bf 108
<> 129:0ab6a29f35bf 109 /** \brief Data Memory Barrier
<> 129:0ab6a29f35bf 110
<> 129:0ab6a29f35bf 111 This function ensures the apparent order of the explicit memory operations before
<> 129:0ab6a29f35bf 112 and after the instruction, without ensuring their completion.
<> 129:0ab6a29f35bf 113 */
<> 129:0ab6a29f35bf 114 #define __DMB() do {\
<> 129:0ab6a29f35bf 115 __schedule_barrier();\
<> 129:0ab6a29f35bf 116 __dmb(0xF);\
<> 129:0ab6a29f35bf 117 __schedule_barrier();\
<> 129:0ab6a29f35bf 118 } while (0)
<> 129:0ab6a29f35bf 119
<> 129:0ab6a29f35bf 120 /** \brief Reverse byte order (32 bit)
<> 129:0ab6a29f35bf 121
<> 129:0ab6a29f35bf 122 This function reverses the byte order in integer value.
<> 129:0ab6a29f35bf 123
<> 129:0ab6a29f35bf 124 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 125 \return Reversed value
<> 129:0ab6a29f35bf 126 */
<> 129:0ab6a29f35bf 127 #define __REV __rev
<> 129:0ab6a29f35bf 128
<> 129:0ab6a29f35bf 129
<> 129:0ab6a29f35bf 130 /** \brief Reverse byte order (16 bit)
<> 129:0ab6a29f35bf 131
<> 129:0ab6a29f35bf 132 This function reverses the byte order in two unsigned short values.
<> 129:0ab6a29f35bf 133
<> 129:0ab6a29f35bf 134 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 135 \return Reversed value
<> 129:0ab6a29f35bf 136 */
<> 129:0ab6a29f35bf 137 #ifndef __NO_EMBEDDED_ASM
<> 129:0ab6a29f35bf 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 129:0ab6a29f35bf 139 {
<> 129:0ab6a29f35bf 140 rev16 r0, r0
<> 129:0ab6a29f35bf 141 bx lr
<> 129:0ab6a29f35bf 142 }
<> 129:0ab6a29f35bf 143 #endif
<> 129:0ab6a29f35bf 144
<> 129:0ab6a29f35bf 145 /** \brief Reverse byte order in signed short value
<> 129:0ab6a29f35bf 146
<> 129:0ab6a29f35bf 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 129:0ab6a29f35bf 148
<> 129:0ab6a29f35bf 149 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 150 \return Reversed value
<> 129:0ab6a29f35bf 151 */
<> 129:0ab6a29f35bf 152 #ifndef __NO_EMBEDDED_ASM
<> 129:0ab6a29f35bf 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 129:0ab6a29f35bf 154 {
<> 129:0ab6a29f35bf 155 revsh r0, r0
<> 129:0ab6a29f35bf 156 bx lr
<> 129:0ab6a29f35bf 157 }
<> 129:0ab6a29f35bf 158 #endif
<> 129:0ab6a29f35bf 159
<> 129:0ab6a29f35bf 160
<> 129:0ab6a29f35bf 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 129:0ab6a29f35bf 162
<> 129:0ab6a29f35bf 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 129:0ab6a29f35bf 164
<> 129:0ab6a29f35bf 165 \param [in] value Value to rotate
<> 129:0ab6a29f35bf 166 \param [in] value Number of Bits to rotate
<> 129:0ab6a29f35bf 167 \return Rotated value
<> 129:0ab6a29f35bf 168 */
<> 129:0ab6a29f35bf 169 #define __ROR __ror
<> 129:0ab6a29f35bf 170
<> 129:0ab6a29f35bf 171
<> 129:0ab6a29f35bf 172 /** \brief Breakpoint
<> 129:0ab6a29f35bf 173
<> 129:0ab6a29f35bf 174 This function causes the processor to enter Debug state.
<> 129:0ab6a29f35bf 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 129:0ab6a29f35bf 176
<> 129:0ab6a29f35bf 177 \param [in] value is ignored by the processor.
<> 129:0ab6a29f35bf 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 129:0ab6a29f35bf 179 */
<> 129:0ab6a29f35bf 180 #define __BKPT(value) __breakpoint(value)
<> 129:0ab6a29f35bf 181
<> 129:0ab6a29f35bf 182
<> 129:0ab6a29f35bf 183 /** \brief Reverse bit order of value
<> 129:0ab6a29f35bf 184
<> 129:0ab6a29f35bf 185 This function reverses the bit order of the given value.
<> 129:0ab6a29f35bf 186
<> 129:0ab6a29f35bf 187 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 188 \return Reversed value
<> 129:0ab6a29f35bf 189 */
<> 129:0ab6a29f35bf 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 129:0ab6a29f35bf 191 #define __RBIT __rbit
<> 129:0ab6a29f35bf 192 #else
<> 129:0ab6a29f35bf 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 129:0ab6a29f35bf 194 {
<> 129:0ab6a29f35bf 195 uint32_t result;
<> 129:0ab6a29f35bf 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 129:0ab6a29f35bf 197
<> 129:0ab6a29f35bf 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 129:0ab6a29f35bf 199 for (value >>= 1; value; value >>= 1)
<> 129:0ab6a29f35bf 200 {
<> 129:0ab6a29f35bf 201 result <<= 1;
<> 129:0ab6a29f35bf 202 result |= value & 1;
<> 129:0ab6a29f35bf 203 s--;
<> 129:0ab6a29f35bf 204 }
<> 129:0ab6a29f35bf 205 result <<= s; // shift when v's highest bits are zero
<> 129:0ab6a29f35bf 206 return(result);
<> 129:0ab6a29f35bf 207 }
<> 129:0ab6a29f35bf 208 #endif
<> 129:0ab6a29f35bf 209
<> 129:0ab6a29f35bf 210
<> 129:0ab6a29f35bf 211 /** \brief Count leading zeros
<> 129:0ab6a29f35bf 212
<> 129:0ab6a29f35bf 213 This function counts the number of leading zeros of a data value.
<> 129:0ab6a29f35bf 214
<> 129:0ab6a29f35bf 215 \param [in] value Value to count the leading zeros
<> 129:0ab6a29f35bf 216 \return number of leading zeros in value
<> 129:0ab6a29f35bf 217 */
<> 129:0ab6a29f35bf 218 #define __CLZ __clz
<> 129:0ab6a29f35bf 219
<> 129:0ab6a29f35bf 220
<> 129:0ab6a29f35bf 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 129:0ab6a29f35bf 222
<> 129:0ab6a29f35bf 223 /** \brief LDR Exclusive (8 bit)
<> 129:0ab6a29f35bf 224
<> 129:0ab6a29f35bf 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 129:0ab6a29f35bf 226
<> 129:0ab6a29f35bf 227 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 228 \return value of type uint8_t at (*ptr)
<> 129:0ab6a29f35bf 229 */
<> 129:0ab6a29f35bf 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 129:0ab6a29f35bf 231
<> 129:0ab6a29f35bf 232
<> 129:0ab6a29f35bf 233 /** \brief LDR Exclusive (16 bit)
<> 129:0ab6a29f35bf 234
<> 129:0ab6a29f35bf 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 129:0ab6a29f35bf 236
<> 129:0ab6a29f35bf 237 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 238 \return value of type uint16_t at (*ptr)
<> 129:0ab6a29f35bf 239 */
<> 129:0ab6a29f35bf 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 129:0ab6a29f35bf 241
<> 129:0ab6a29f35bf 242
<> 129:0ab6a29f35bf 243 /** \brief LDR Exclusive (32 bit)
<> 129:0ab6a29f35bf 244
<> 129:0ab6a29f35bf 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 129:0ab6a29f35bf 246
<> 129:0ab6a29f35bf 247 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 248 \return value of type uint32_t at (*ptr)
<> 129:0ab6a29f35bf 249 */
<> 129:0ab6a29f35bf 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 129:0ab6a29f35bf 251
<> 129:0ab6a29f35bf 252
<> 129:0ab6a29f35bf 253 /** \brief STR Exclusive (8 bit)
<> 129:0ab6a29f35bf 254
<> 129:0ab6a29f35bf 255 This function executes a exclusive STR instruction for 8 bit values.
<> 129:0ab6a29f35bf 256
<> 129:0ab6a29f35bf 257 \param [in] value Value to store
<> 129:0ab6a29f35bf 258 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 259 \return 0 Function succeeded
<> 129:0ab6a29f35bf 260 \return 1 Function failed
<> 129:0ab6a29f35bf 261 */
<> 129:0ab6a29f35bf 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 129:0ab6a29f35bf 263
<> 129:0ab6a29f35bf 264
<> 129:0ab6a29f35bf 265 /** \brief STR Exclusive (16 bit)
<> 129:0ab6a29f35bf 266
<> 129:0ab6a29f35bf 267 This function executes a exclusive STR instruction for 16 bit values.
<> 129:0ab6a29f35bf 268
<> 129:0ab6a29f35bf 269 \param [in] value Value to store
<> 129:0ab6a29f35bf 270 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 271 \return 0 Function succeeded
<> 129:0ab6a29f35bf 272 \return 1 Function failed
<> 129:0ab6a29f35bf 273 */
<> 129:0ab6a29f35bf 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 129:0ab6a29f35bf 275
<> 129:0ab6a29f35bf 276
<> 129:0ab6a29f35bf 277 /** \brief STR Exclusive (32 bit)
<> 129:0ab6a29f35bf 278
<> 129:0ab6a29f35bf 279 This function executes a exclusive STR instruction for 32 bit values.
<> 129:0ab6a29f35bf 280
<> 129:0ab6a29f35bf 281 \param [in] value Value to store
<> 129:0ab6a29f35bf 282 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 283 \return 0 Function succeeded
<> 129:0ab6a29f35bf 284 \return 1 Function failed
<> 129:0ab6a29f35bf 285 */
<> 129:0ab6a29f35bf 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 129:0ab6a29f35bf 287
<> 129:0ab6a29f35bf 288
<> 129:0ab6a29f35bf 289 /** \brief Remove the exclusive lock
<> 129:0ab6a29f35bf 290
<> 129:0ab6a29f35bf 291 This function removes the exclusive lock which is created by LDREX.
<> 129:0ab6a29f35bf 292
<> 129:0ab6a29f35bf 293 */
<> 129:0ab6a29f35bf 294 #define __CLREX __clrex
<> 129:0ab6a29f35bf 295
<> 129:0ab6a29f35bf 296
<> 129:0ab6a29f35bf 297 /** \brief Signed Saturate
<> 129:0ab6a29f35bf 298
<> 129:0ab6a29f35bf 299 This function saturates a signed value.
<> 129:0ab6a29f35bf 300
<> 129:0ab6a29f35bf 301 \param [in] value Value to be saturated
<> 129:0ab6a29f35bf 302 \param [in] sat Bit position to saturate to (1..32)
<> 129:0ab6a29f35bf 303 \return Saturated value
<> 129:0ab6a29f35bf 304 */
<> 129:0ab6a29f35bf 305 #define __SSAT __ssat
<> 129:0ab6a29f35bf 306
<> 129:0ab6a29f35bf 307
<> 129:0ab6a29f35bf 308 /** \brief Unsigned Saturate
<> 129:0ab6a29f35bf 309
<> 129:0ab6a29f35bf 310 This function saturates an unsigned value.
<> 129:0ab6a29f35bf 311
<> 129:0ab6a29f35bf 312 \param [in] value Value to be saturated
<> 129:0ab6a29f35bf 313 \param [in] sat Bit position to saturate to (0..31)
<> 129:0ab6a29f35bf 314 \return Saturated value
<> 129:0ab6a29f35bf 315 */
<> 129:0ab6a29f35bf 316 #define __USAT __usat
<> 129:0ab6a29f35bf 317
<> 129:0ab6a29f35bf 318
<> 129:0ab6a29f35bf 319 /** \brief Rotate Right with Extend (32 bit)
<> 129:0ab6a29f35bf 320
<> 129:0ab6a29f35bf 321 This function moves each bit of a bitstring right by one bit.
<> 129:0ab6a29f35bf 322 The carry input is shifted in at the left end of the bitstring.
<> 129:0ab6a29f35bf 323
<> 129:0ab6a29f35bf 324 \param [in] value Value to rotate
<> 129:0ab6a29f35bf 325 \return Rotated value
<> 129:0ab6a29f35bf 326 */
<> 129:0ab6a29f35bf 327 #ifndef __NO_EMBEDDED_ASM
<> 129:0ab6a29f35bf 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 129:0ab6a29f35bf 329 {
<> 129:0ab6a29f35bf 330 rrx r0, r0
<> 129:0ab6a29f35bf 331 bx lr
<> 129:0ab6a29f35bf 332 }
<> 129:0ab6a29f35bf 333 #endif
<> 129:0ab6a29f35bf 334
<> 129:0ab6a29f35bf 335
<> 129:0ab6a29f35bf 336 /** \brief LDRT Unprivileged (8 bit)
<> 129:0ab6a29f35bf 337
<> 129:0ab6a29f35bf 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 129:0ab6a29f35bf 339
<> 129:0ab6a29f35bf 340 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 341 \return value of type uint8_t at (*ptr)
<> 129:0ab6a29f35bf 342 */
<> 129:0ab6a29f35bf 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 129:0ab6a29f35bf 344
<> 129:0ab6a29f35bf 345
<> 129:0ab6a29f35bf 346 /** \brief LDRT Unprivileged (16 bit)
<> 129:0ab6a29f35bf 347
<> 129:0ab6a29f35bf 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 129:0ab6a29f35bf 349
<> 129:0ab6a29f35bf 350 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 351 \return value of type uint16_t at (*ptr)
<> 129:0ab6a29f35bf 352 */
<> 129:0ab6a29f35bf 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 129:0ab6a29f35bf 354
<> 129:0ab6a29f35bf 355
<> 129:0ab6a29f35bf 356 /** \brief LDRT Unprivileged (32 bit)
<> 129:0ab6a29f35bf 357
<> 129:0ab6a29f35bf 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 129:0ab6a29f35bf 359
<> 129:0ab6a29f35bf 360 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 361 \return value of type uint32_t at (*ptr)
<> 129:0ab6a29f35bf 362 */
<> 129:0ab6a29f35bf 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 129:0ab6a29f35bf 364
<> 129:0ab6a29f35bf 365
<> 129:0ab6a29f35bf 366 /** \brief STRT Unprivileged (8 bit)
<> 129:0ab6a29f35bf 367
<> 129:0ab6a29f35bf 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 129:0ab6a29f35bf 369
<> 129:0ab6a29f35bf 370 \param [in] value Value to store
<> 129:0ab6a29f35bf 371 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 372 */
<> 129:0ab6a29f35bf 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 129:0ab6a29f35bf 374
<> 129:0ab6a29f35bf 375
<> 129:0ab6a29f35bf 376 /** \brief STRT Unprivileged (16 bit)
<> 129:0ab6a29f35bf 377
<> 129:0ab6a29f35bf 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 129:0ab6a29f35bf 379
<> 129:0ab6a29f35bf 380 \param [in] value Value to store
<> 129:0ab6a29f35bf 381 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 382 */
<> 129:0ab6a29f35bf 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 129:0ab6a29f35bf 384
<> 129:0ab6a29f35bf 385
<> 129:0ab6a29f35bf 386 /** \brief STRT Unprivileged (32 bit)
<> 129:0ab6a29f35bf 387
<> 129:0ab6a29f35bf 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 129:0ab6a29f35bf 389
<> 129:0ab6a29f35bf 390 \param [in] value Value to store
<> 129:0ab6a29f35bf 391 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 392 */
<> 129:0ab6a29f35bf 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 129:0ab6a29f35bf 394
<> 129:0ab6a29f35bf 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 129:0ab6a29f35bf 396
<> 129:0ab6a29f35bf 397
<> 129:0ab6a29f35bf 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 129:0ab6a29f35bf 399 /* GNU gcc specific functions */
<> 129:0ab6a29f35bf 400
<> 129:0ab6a29f35bf 401 /* Define macros for porting to both thumb1 and thumb2.
<> 129:0ab6a29f35bf 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 129:0ab6a29f35bf 403 * Otherwise, use general registers, specified by constrant "r" */
<> 129:0ab6a29f35bf 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 129:0ab6a29f35bf 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 129:0ab6a29f35bf 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 129:0ab6a29f35bf 407 #else
<> 129:0ab6a29f35bf 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 129:0ab6a29f35bf 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 129:0ab6a29f35bf 410 #endif
<> 129:0ab6a29f35bf 411
<> 129:0ab6a29f35bf 412 /** \brief No Operation
<> 129:0ab6a29f35bf 413
<> 129:0ab6a29f35bf 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 129:0ab6a29f35bf 415 */
<> 129:0ab6a29f35bf 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 129:0ab6a29f35bf 417 {
<> 129:0ab6a29f35bf 418 __ASM volatile ("nop");
<> 129:0ab6a29f35bf 419 }
<> 129:0ab6a29f35bf 420
<> 129:0ab6a29f35bf 421
<> 129:0ab6a29f35bf 422 /** \brief Wait For Interrupt
<> 129:0ab6a29f35bf 423
<> 129:0ab6a29f35bf 424 Wait For Interrupt is a hint instruction that suspends execution
<> 129:0ab6a29f35bf 425 until one of a number of events occurs.
<> 129:0ab6a29f35bf 426 */
<> 129:0ab6a29f35bf 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 129:0ab6a29f35bf 428 {
<> 129:0ab6a29f35bf 429 __ASM volatile ("wfi");
<> 129:0ab6a29f35bf 430 }
<> 129:0ab6a29f35bf 431
<> 129:0ab6a29f35bf 432
<> 129:0ab6a29f35bf 433 /** \brief Wait For Event
<> 129:0ab6a29f35bf 434
<> 129:0ab6a29f35bf 435 Wait For Event is a hint instruction that permits the processor to enter
<> 129:0ab6a29f35bf 436 a low-power state until one of a number of events occurs.
<> 129:0ab6a29f35bf 437 */
<> 129:0ab6a29f35bf 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 129:0ab6a29f35bf 439 {
<> 129:0ab6a29f35bf 440 __ASM volatile ("wfe");
<> 129:0ab6a29f35bf 441 }
<> 129:0ab6a29f35bf 442
<> 129:0ab6a29f35bf 443
<> 129:0ab6a29f35bf 444 /** \brief Send Event
<> 129:0ab6a29f35bf 445
<> 129:0ab6a29f35bf 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 129:0ab6a29f35bf 447 */
<> 129:0ab6a29f35bf 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 129:0ab6a29f35bf 449 {
<> 129:0ab6a29f35bf 450 __ASM volatile ("sev");
<> 129:0ab6a29f35bf 451 }
<> 129:0ab6a29f35bf 452
<> 129:0ab6a29f35bf 453
<> 129:0ab6a29f35bf 454 /** \brief Instruction Synchronization Barrier
<> 129:0ab6a29f35bf 455
<> 129:0ab6a29f35bf 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 129:0ab6a29f35bf 457 so that all instructions following the ISB are fetched from cache or
<> 129:0ab6a29f35bf 458 memory, after the instruction has been completed.
<> 129:0ab6a29f35bf 459 */
<> 129:0ab6a29f35bf 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 129:0ab6a29f35bf 461 {
<> 129:0ab6a29f35bf 462 __ASM volatile ("isb 0xF":::"memory");
<> 129:0ab6a29f35bf 463 }
<> 129:0ab6a29f35bf 464
<> 129:0ab6a29f35bf 465
<> 129:0ab6a29f35bf 466 /** \brief Data Synchronization Barrier
<> 129:0ab6a29f35bf 467
<> 129:0ab6a29f35bf 468 This function acts as a special kind of Data Memory Barrier.
<> 129:0ab6a29f35bf 469 It completes when all explicit memory accesses before this instruction complete.
<> 129:0ab6a29f35bf 470 */
<> 129:0ab6a29f35bf 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 129:0ab6a29f35bf 472 {
<> 129:0ab6a29f35bf 473 __ASM volatile ("dsb 0xF":::"memory");
<> 129:0ab6a29f35bf 474 }
<> 129:0ab6a29f35bf 475
<> 129:0ab6a29f35bf 476
<> 129:0ab6a29f35bf 477 /** \brief Data Memory Barrier
<> 129:0ab6a29f35bf 478
<> 129:0ab6a29f35bf 479 This function ensures the apparent order of the explicit memory operations before
<> 129:0ab6a29f35bf 480 and after the instruction, without ensuring their completion.
<> 129:0ab6a29f35bf 481 */
<> 129:0ab6a29f35bf 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 129:0ab6a29f35bf 483 {
<> 129:0ab6a29f35bf 484 __ASM volatile ("dmb 0xF":::"memory");
<> 129:0ab6a29f35bf 485 }
<> 129:0ab6a29f35bf 486
<> 129:0ab6a29f35bf 487
<> 129:0ab6a29f35bf 488 /** \brief Reverse byte order (32 bit)
<> 129:0ab6a29f35bf 489
<> 129:0ab6a29f35bf 490 This function reverses the byte order in integer value.
<> 129:0ab6a29f35bf 491
<> 129:0ab6a29f35bf 492 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 493 \return Reversed value
<> 129:0ab6a29f35bf 494 */
<> 129:0ab6a29f35bf 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 129:0ab6a29f35bf 496 {
<> 129:0ab6a29f35bf 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 129:0ab6a29f35bf 498 return __builtin_bswap32(value);
<> 129:0ab6a29f35bf 499 #else
<> 129:0ab6a29f35bf 500 uint32_t result;
<> 129:0ab6a29f35bf 501
<> 129:0ab6a29f35bf 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 129:0ab6a29f35bf 503 return(result);
<> 129:0ab6a29f35bf 504 #endif
<> 129:0ab6a29f35bf 505 }
<> 129:0ab6a29f35bf 506
<> 129:0ab6a29f35bf 507
<> 129:0ab6a29f35bf 508 /** \brief Reverse byte order (16 bit)
<> 129:0ab6a29f35bf 509
<> 129:0ab6a29f35bf 510 This function reverses the byte order in two unsigned short values.
<> 129:0ab6a29f35bf 511
<> 129:0ab6a29f35bf 512 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 513 \return Reversed value
<> 129:0ab6a29f35bf 514 */
<> 129:0ab6a29f35bf 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 129:0ab6a29f35bf 516 {
<> 129:0ab6a29f35bf 517 uint32_t result;
<> 129:0ab6a29f35bf 518
<> 129:0ab6a29f35bf 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 129:0ab6a29f35bf 520 return(result);
<> 129:0ab6a29f35bf 521 }
<> 129:0ab6a29f35bf 522
<> 129:0ab6a29f35bf 523
<> 129:0ab6a29f35bf 524 /** \brief Reverse byte order in signed short value
<> 129:0ab6a29f35bf 525
<> 129:0ab6a29f35bf 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 129:0ab6a29f35bf 527
<> 129:0ab6a29f35bf 528 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 529 \return Reversed value
<> 129:0ab6a29f35bf 530 */
<> 129:0ab6a29f35bf 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 129:0ab6a29f35bf 532 {
<> 129:0ab6a29f35bf 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 129:0ab6a29f35bf 534 return (short)__builtin_bswap16(value);
<> 129:0ab6a29f35bf 535 #else
<> 129:0ab6a29f35bf 536 uint32_t result;
<> 129:0ab6a29f35bf 537
<> 129:0ab6a29f35bf 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 129:0ab6a29f35bf 539 return(result);
<> 129:0ab6a29f35bf 540 #endif
<> 129:0ab6a29f35bf 541 }
<> 129:0ab6a29f35bf 542
<> 129:0ab6a29f35bf 543
<> 129:0ab6a29f35bf 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 129:0ab6a29f35bf 545
<> 129:0ab6a29f35bf 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 129:0ab6a29f35bf 547
<> 129:0ab6a29f35bf 548 \param [in] value Value to rotate
<> 129:0ab6a29f35bf 549 \param [in] value Number of Bits to rotate
<> 129:0ab6a29f35bf 550 \return Rotated value
<> 129:0ab6a29f35bf 551 */
<> 129:0ab6a29f35bf 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 553 {
<> 129:0ab6a29f35bf 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 129:0ab6a29f35bf 555 }
<> 129:0ab6a29f35bf 556
<> 129:0ab6a29f35bf 557
<> 129:0ab6a29f35bf 558 /** \brief Breakpoint
<> 129:0ab6a29f35bf 559
<> 129:0ab6a29f35bf 560 This function causes the processor to enter Debug state.
<> 129:0ab6a29f35bf 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 129:0ab6a29f35bf 562
<> 129:0ab6a29f35bf 563 \param [in] value is ignored by the processor.
<> 129:0ab6a29f35bf 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 129:0ab6a29f35bf 565 */
<> 129:0ab6a29f35bf 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 129:0ab6a29f35bf 567
<> 129:0ab6a29f35bf 568
<> 129:0ab6a29f35bf 569 /** \brief Reverse bit order of value
<> 129:0ab6a29f35bf 570
<> 129:0ab6a29f35bf 571 This function reverses the bit order of the given value.
<> 129:0ab6a29f35bf 572
<> 129:0ab6a29f35bf 573 \param [in] value Value to reverse
<> 129:0ab6a29f35bf 574 \return Reversed value
<> 129:0ab6a29f35bf 575 */
<> 129:0ab6a29f35bf 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 129:0ab6a29f35bf 577 {
<> 129:0ab6a29f35bf 578 uint32_t result;
<> 129:0ab6a29f35bf 579
<> 129:0ab6a29f35bf 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 129:0ab6a29f35bf 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 129:0ab6a29f35bf 582 #else
<> 129:0ab6a29f35bf 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 129:0ab6a29f35bf 584
<> 129:0ab6a29f35bf 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 129:0ab6a29f35bf 586 for (value >>= 1; value; value >>= 1)
<> 129:0ab6a29f35bf 587 {
<> 129:0ab6a29f35bf 588 result <<= 1;
<> 129:0ab6a29f35bf 589 result |= value & 1;
<> 129:0ab6a29f35bf 590 s--;
<> 129:0ab6a29f35bf 591 }
<> 129:0ab6a29f35bf 592 result <<= s; // shift when v's highest bits are zero
<> 129:0ab6a29f35bf 593 #endif
<> 129:0ab6a29f35bf 594 return(result);
<> 129:0ab6a29f35bf 595 }
<> 129:0ab6a29f35bf 596
<> 129:0ab6a29f35bf 597
<> 129:0ab6a29f35bf 598 /** \brief Count leading zeros
<> 129:0ab6a29f35bf 599
<> 129:0ab6a29f35bf 600 This function counts the number of leading zeros of a data value.
<> 129:0ab6a29f35bf 601
<> 129:0ab6a29f35bf 602 \param [in] value Value to count the leading zeros
<> 129:0ab6a29f35bf 603 \return number of leading zeros in value
<> 129:0ab6a29f35bf 604 */
<> 129:0ab6a29f35bf 605 #define __CLZ __builtin_clz
<> 129:0ab6a29f35bf 606
<> 129:0ab6a29f35bf 607
<> 129:0ab6a29f35bf 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 129:0ab6a29f35bf 609
<> 129:0ab6a29f35bf 610 /** \brief LDR Exclusive (8 bit)
<> 129:0ab6a29f35bf 611
<> 129:0ab6a29f35bf 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 129:0ab6a29f35bf 613
<> 129:0ab6a29f35bf 614 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 615 \return value of type uint8_t at (*ptr)
<> 129:0ab6a29f35bf 616 */
<> 129:0ab6a29f35bf 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 129:0ab6a29f35bf 618 {
<> 129:0ab6a29f35bf 619 uint32_t result;
<> 129:0ab6a29f35bf 620
<> 129:0ab6a29f35bf 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 129:0ab6a29f35bf 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 623 #else
<> 129:0ab6a29f35bf 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 129:0ab6a29f35bf 625 accepted by assembler. So has to use following less efficient pattern.
<> 129:0ab6a29f35bf 626 */
<> 129:0ab6a29f35bf 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 129:0ab6a29f35bf 628 #endif
<> 129:0ab6a29f35bf 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 129:0ab6a29f35bf 630 }
<> 129:0ab6a29f35bf 631
<> 129:0ab6a29f35bf 632
<> 129:0ab6a29f35bf 633 /** \brief LDR Exclusive (16 bit)
<> 129:0ab6a29f35bf 634
<> 129:0ab6a29f35bf 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 129:0ab6a29f35bf 636
<> 129:0ab6a29f35bf 637 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 638 \return value of type uint16_t at (*ptr)
<> 129:0ab6a29f35bf 639 */
<> 129:0ab6a29f35bf 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 129:0ab6a29f35bf 641 {
<> 129:0ab6a29f35bf 642 uint32_t result;
<> 129:0ab6a29f35bf 643
<> 129:0ab6a29f35bf 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 129:0ab6a29f35bf 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 646 #else
<> 129:0ab6a29f35bf 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 129:0ab6a29f35bf 648 accepted by assembler. So has to use following less efficient pattern.
<> 129:0ab6a29f35bf 649 */
<> 129:0ab6a29f35bf 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 129:0ab6a29f35bf 651 #endif
<> 129:0ab6a29f35bf 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 129:0ab6a29f35bf 653 }
<> 129:0ab6a29f35bf 654
<> 129:0ab6a29f35bf 655
<> 129:0ab6a29f35bf 656 /** \brief LDR Exclusive (32 bit)
<> 129:0ab6a29f35bf 657
<> 129:0ab6a29f35bf 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 129:0ab6a29f35bf 659
<> 129:0ab6a29f35bf 660 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 661 \return value of type uint32_t at (*ptr)
<> 129:0ab6a29f35bf 662 */
<> 129:0ab6a29f35bf 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 129:0ab6a29f35bf 664 {
<> 129:0ab6a29f35bf 665 uint32_t result;
<> 129:0ab6a29f35bf 666
<> 129:0ab6a29f35bf 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 668 return(result);
<> 129:0ab6a29f35bf 669 }
<> 129:0ab6a29f35bf 670
<> 129:0ab6a29f35bf 671
<> 129:0ab6a29f35bf 672 /** \brief STR Exclusive (8 bit)
<> 129:0ab6a29f35bf 673
<> 129:0ab6a29f35bf 674 This function executes a exclusive STR instruction for 8 bit values.
<> 129:0ab6a29f35bf 675
<> 129:0ab6a29f35bf 676 \param [in] value Value to store
<> 129:0ab6a29f35bf 677 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 678 \return 0 Function succeeded
<> 129:0ab6a29f35bf 679 \return 1 Function failed
<> 129:0ab6a29f35bf 680 */
<> 129:0ab6a29f35bf 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 129:0ab6a29f35bf 682 {
<> 129:0ab6a29f35bf 683 uint32_t result;
<> 129:0ab6a29f35bf 684
<> 129:0ab6a29f35bf 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 129:0ab6a29f35bf 686 return(result);
<> 129:0ab6a29f35bf 687 }
<> 129:0ab6a29f35bf 688
<> 129:0ab6a29f35bf 689
<> 129:0ab6a29f35bf 690 /** \brief STR Exclusive (16 bit)
<> 129:0ab6a29f35bf 691
<> 129:0ab6a29f35bf 692 This function executes a exclusive STR instruction for 16 bit values.
<> 129:0ab6a29f35bf 693
<> 129:0ab6a29f35bf 694 \param [in] value Value to store
<> 129:0ab6a29f35bf 695 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 696 \return 0 Function succeeded
<> 129:0ab6a29f35bf 697 \return 1 Function failed
<> 129:0ab6a29f35bf 698 */
<> 129:0ab6a29f35bf 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 129:0ab6a29f35bf 700 {
<> 129:0ab6a29f35bf 701 uint32_t result;
<> 129:0ab6a29f35bf 702
<> 129:0ab6a29f35bf 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 129:0ab6a29f35bf 704 return(result);
<> 129:0ab6a29f35bf 705 }
<> 129:0ab6a29f35bf 706
<> 129:0ab6a29f35bf 707
<> 129:0ab6a29f35bf 708 /** \brief STR Exclusive (32 bit)
<> 129:0ab6a29f35bf 709
<> 129:0ab6a29f35bf 710 This function executes a exclusive STR instruction for 32 bit values.
<> 129:0ab6a29f35bf 711
<> 129:0ab6a29f35bf 712 \param [in] value Value to store
<> 129:0ab6a29f35bf 713 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 714 \return 0 Function succeeded
<> 129:0ab6a29f35bf 715 \return 1 Function failed
<> 129:0ab6a29f35bf 716 */
<> 129:0ab6a29f35bf 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 129:0ab6a29f35bf 718 {
<> 129:0ab6a29f35bf 719 uint32_t result;
<> 129:0ab6a29f35bf 720
<> 129:0ab6a29f35bf 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 129:0ab6a29f35bf 722 return(result);
<> 129:0ab6a29f35bf 723 }
<> 129:0ab6a29f35bf 724
<> 129:0ab6a29f35bf 725
<> 129:0ab6a29f35bf 726 /** \brief Remove the exclusive lock
<> 129:0ab6a29f35bf 727
<> 129:0ab6a29f35bf 728 This function removes the exclusive lock which is created by LDREX.
<> 129:0ab6a29f35bf 729
<> 129:0ab6a29f35bf 730 */
<> 129:0ab6a29f35bf 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 129:0ab6a29f35bf 732 {
<> 129:0ab6a29f35bf 733 __ASM volatile ("clrex" ::: "memory");
<> 129:0ab6a29f35bf 734 }
<> 129:0ab6a29f35bf 735
<> 129:0ab6a29f35bf 736
<> 129:0ab6a29f35bf 737 /** \brief Signed Saturate
<> 129:0ab6a29f35bf 738
<> 129:0ab6a29f35bf 739 This function saturates a signed value.
<> 129:0ab6a29f35bf 740
<> 129:0ab6a29f35bf 741 \param [in] value Value to be saturated
<> 129:0ab6a29f35bf 742 \param [in] sat Bit position to saturate to (1..32)
<> 129:0ab6a29f35bf 743 \return Saturated value
<> 129:0ab6a29f35bf 744 */
<> 129:0ab6a29f35bf 745 #define __SSAT(ARG1,ARG2) \
<> 129:0ab6a29f35bf 746 ({ \
<> 129:0ab6a29f35bf 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 129:0ab6a29f35bf 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 129:0ab6a29f35bf 749 __RES; \
<> 129:0ab6a29f35bf 750 })
<> 129:0ab6a29f35bf 751
<> 129:0ab6a29f35bf 752
<> 129:0ab6a29f35bf 753 /** \brief Unsigned Saturate
<> 129:0ab6a29f35bf 754
<> 129:0ab6a29f35bf 755 This function saturates an unsigned value.
<> 129:0ab6a29f35bf 756
<> 129:0ab6a29f35bf 757 \param [in] value Value to be saturated
<> 129:0ab6a29f35bf 758 \param [in] sat Bit position to saturate to (0..31)
<> 129:0ab6a29f35bf 759 \return Saturated value
<> 129:0ab6a29f35bf 760 */
<> 129:0ab6a29f35bf 761 #define __USAT(ARG1,ARG2) \
<> 129:0ab6a29f35bf 762 ({ \
<> 129:0ab6a29f35bf 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 129:0ab6a29f35bf 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 129:0ab6a29f35bf 765 __RES; \
<> 129:0ab6a29f35bf 766 })
<> 129:0ab6a29f35bf 767
<> 129:0ab6a29f35bf 768
<> 129:0ab6a29f35bf 769 /** \brief Rotate Right with Extend (32 bit)
<> 129:0ab6a29f35bf 770
<> 129:0ab6a29f35bf 771 This function moves each bit of a bitstring right by one bit.
<> 129:0ab6a29f35bf 772 The carry input is shifted in at the left end of the bitstring.
<> 129:0ab6a29f35bf 773
<> 129:0ab6a29f35bf 774 \param [in] value Value to rotate
<> 129:0ab6a29f35bf 775 \return Rotated value
<> 129:0ab6a29f35bf 776 */
<> 129:0ab6a29f35bf 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 129:0ab6a29f35bf 778 {
<> 129:0ab6a29f35bf 779 uint32_t result;
<> 129:0ab6a29f35bf 780
<> 129:0ab6a29f35bf 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 129:0ab6a29f35bf 782 return(result);
<> 129:0ab6a29f35bf 783 }
<> 129:0ab6a29f35bf 784
<> 129:0ab6a29f35bf 785
<> 129:0ab6a29f35bf 786 /** \brief LDRT Unprivileged (8 bit)
<> 129:0ab6a29f35bf 787
<> 129:0ab6a29f35bf 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 129:0ab6a29f35bf 789
<> 129:0ab6a29f35bf 790 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 791 \return value of type uint8_t at (*ptr)
<> 129:0ab6a29f35bf 792 */
<> 129:0ab6a29f35bf 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 129:0ab6a29f35bf 794 {
<> 129:0ab6a29f35bf 795 uint32_t result;
<> 129:0ab6a29f35bf 796
<> 129:0ab6a29f35bf 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 129:0ab6a29f35bf 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 799 #else
<> 129:0ab6a29f35bf 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 129:0ab6a29f35bf 801 accepted by assembler. So has to use following less efficient pattern.
<> 129:0ab6a29f35bf 802 */
<> 129:0ab6a29f35bf 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 129:0ab6a29f35bf 804 #endif
<> 129:0ab6a29f35bf 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 129:0ab6a29f35bf 806 }
<> 129:0ab6a29f35bf 807
<> 129:0ab6a29f35bf 808
<> 129:0ab6a29f35bf 809 /** \brief LDRT Unprivileged (16 bit)
<> 129:0ab6a29f35bf 810
<> 129:0ab6a29f35bf 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 129:0ab6a29f35bf 812
<> 129:0ab6a29f35bf 813 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 814 \return value of type uint16_t at (*ptr)
<> 129:0ab6a29f35bf 815 */
<> 129:0ab6a29f35bf 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 129:0ab6a29f35bf 817 {
<> 129:0ab6a29f35bf 818 uint32_t result;
<> 129:0ab6a29f35bf 819
<> 129:0ab6a29f35bf 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 129:0ab6a29f35bf 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 822 #else
<> 129:0ab6a29f35bf 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 129:0ab6a29f35bf 824 accepted by assembler. So has to use following less efficient pattern.
<> 129:0ab6a29f35bf 825 */
<> 129:0ab6a29f35bf 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 129:0ab6a29f35bf 827 #endif
<> 129:0ab6a29f35bf 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 129:0ab6a29f35bf 829 }
<> 129:0ab6a29f35bf 830
<> 129:0ab6a29f35bf 831
<> 129:0ab6a29f35bf 832 /** \brief LDRT Unprivileged (32 bit)
<> 129:0ab6a29f35bf 833
<> 129:0ab6a29f35bf 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 129:0ab6a29f35bf 835
<> 129:0ab6a29f35bf 836 \param [in] ptr Pointer to data
<> 129:0ab6a29f35bf 837 \return value of type uint32_t at (*ptr)
<> 129:0ab6a29f35bf 838 */
<> 129:0ab6a29f35bf 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 129:0ab6a29f35bf 840 {
<> 129:0ab6a29f35bf 841 uint32_t result;
<> 129:0ab6a29f35bf 842
<> 129:0ab6a29f35bf 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 129:0ab6a29f35bf 844 return(result);
<> 129:0ab6a29f35bf 845 }
<> 129:0ab6a29f35bf 846
<> 129:0ab6a29f35bf 847
<> 129:0ab6a29f35bf 848 /** \brief STRT Unprivileged (8 bit)
<> 129:0ab6a29f35bf 849
<> 129:0ab6a29f35bf 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 129:0ab6a29f35bf 851
<> 129:0ab6a29f35bf 852 \param [in] value Value to store
<> 129:0ab6a29f35bf 853 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 854 */
<> 129:0ab6a29f35bf 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 129:0ab6a29f35bf 856 {
<> 129:0ab6a29f35bf 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 129:0ab6a29f35bf 858 }
<> 129:0ab6a29f35bf 859
<> 129:0ab6a29f35bf 860
<> 129:0ab6a29f35bf 861 /** \brief STRT Unprivileged (16 bit)
<> 129:0ab6a29f35bf 862
<> 129:0ab6a29f35bf 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 129:0ab6a29f35bf 864
<> 129:0ab6a29f35bf 865 \param [in] value Value to store
<> 129:0ab6a29f35bf 866 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 867 */
<> 129:0ab6a29f35bf 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 129:0ab6a29f35bf 869 {
<> 129:0ab6a29f35bf 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 129:0ab6a29f35bf 871 }
<> 129:0ab6a29f35bf 872
<> 129:0ab6a29f35bf 873
<> 129:0ab6a29f35bf 874 /** \brief STRT Unprivileged (32 bit)
<> 129:0ab6a29f35bf 875
<> 129:0ab6a29f35bf 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 129:0ab6a29f35bf 877
<> 129:0ab6a29f35bf 878 \param [in] value Value to store
<> 129:0ab6a29f35bf 879 \param [in] ptr Pointer to location
<> 129:0ab6a29f35bf 880 */
<> 129:0ab6a29f35bf 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 129:0ab6a29f35bf 882 {
<> 129:0ab6a29f35bf 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 129:0ab6a29f35bf 884 }
<> 129:0ab6a29f35bf 885
<> 129:0ab6a29f35bf 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 129:0ab6a29f35bf 887
<> 129:0ab6a29f35bf 888
<> 129:0ab6a29f35bf 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 129:0ab6a29f35bf 890 /* IAR iccarm specific functions */
<> 129:0ab6a29f35bf 891 #include <cmsis_iar.h>
<> 129:0ab6a29f35bf 892
<> 129:0ab6a29f35bf 893
<> 129:0ab6a29f35bf 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 129:0ab6a29f35bf 895 /* TI CCS specific functions */
<> 129:0ab6a29f35bf 896 #include <cmsis_ccs.h>
<> 129:0ab6a29f35bf 897
<> 129:0ab6a29f35bf 898
<> 129:0ab6a29f35bf 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 129:0ab6a29f35bf 900 /* TASKING carm specific functions */
<> 129:0ab6a29f35bf 901 /*
<> 129:0ab6a29f35bf 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 129:0ab6a29f35bf 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 129:0ab6a29f35bf 904 * Including the CMSIS ones.
<> 129:0ab6a29f35bf 905 */
<> 129:0ab6a29f35bf 906
<> 129:0ab6a29f35bf 907
<> 129:0ab6a29f35bf 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 129:0ab6a29f35bf 909 /* Cosmic specific functions */
<> 129:0ab6a29f35bf 910 #include <cmsis_csm.h>
<> 129:0ab6a29f35bf 911
<> 129:0ab6a29f35bf 912 #endif
<> 129:0ab6a29f35bf 913
<> 129:0ab6a29f35bf 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 129:0ab6a29f35bf 915
<> 129:0ab6a29f35bf 916 #endif /* __CORE_CMINSTR_H */