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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K82F/core_ca_mmu.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
129:0ab6a29f35bf 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 ;/**************************************************************************//**
<> 129:0ab6a29f35bf 2 ; * @file core_ca_mmu.h
<> 129:0ab6a29f35bf 3 ; * @brief MMU Startup File for A9_MP Device Series
<> 129:0ab6a29f35bf 4 ; * @version V1.01
<> 129:0ab6a29f35bf 5 ; * @date 10 Sept 2014
<> 129:0ab6a29f35bf 6 ; *
<> 129:0ab6a29f35bf 7 ; * @note
<> 129:0ab6a29f35bf 8 ; *
<> 129:0ab6a29f35bf 9 ; ******************************************************************************/
<> 129:0ab6a29f35bf 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
<> 129:0ab6a29f35bf 11 ;
<> 129:0ab6a29f35bf 12 ; All rights reserved.
<> 129:0ab6a29f35bf 13 ; Redistribution and use in source and binary forms, with or without
<> 129:0ab6a29f35bf 14 ; modification, are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 15 ; - Redistributions of source code must retain the above copyright
<> 129:0ab6a29f35bf 16 ; notice, this list of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 17 ; - Redistributions in binary form must reproduce the above copyright
<> 129:0ab6a29f35bf 18 ; notice, this list of conditions and the following disclaimer in the
<> 129:0ab6a29f35bf 19 ; documentation and/or other materials provided with the distribution.
<> 129:0ab6a29f35bf 20 ; - Neither the name of ARM nor the names of its contributors may be used
<> 129:0ab6a29f35bf 21 ; to endorse or promote products derived from this software without
<> 129:0ab6a29f35bf 22 ; specific prior written permission.
<> 129:0ab6a29f35bf 23 ; *
<> 129:0ab6a29f35bf 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 129:0ab6a29f35bf 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 129:0ab6a29f35bf 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 129:0ab6a29f35bf 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 129:0ab6a29f35bf 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 129:0ab6a29f35bf 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 129:0ab6a29f35bf 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 129:0ab6a29f35bf 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 129:0ab6a29f35bf 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 129:0ab6a29f35bf 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 129:0ab6a29f35bf 34 ; POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 35 ; ---------------------------------------------------------------------------*/
<> 129:0ab6a29f35bf 36
<> 129:0ab6a29f35bf 37 #ifdef __cplusplus
<> 129:0ab6a29f35bf 38 extern "C" {
<> 129:0ab6a29f35bf 39 #endif
<> 129:0ab6a29f35bf 40
<> 129:0ab6a29f35bf 41 #ifndef _MMU_FUNC_H
<> 129:0ab6a29f35bf 42 #define _MMU_FUNC_H
<> 129:0ab6a29f35bf 43
<> 129:0ab6a29f35bf 44 #define SECTION_DESCRIPTOR (0x2)
<> 129:0ab6a29f35bf 45 #define SECTION_MASK (0xFFFFFFFC)
<> 129:0ab6a29f35bf 46
<> 129:0ab6a29f35bf 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
<> 129:0ab6a29f35bf 48 #define SECTION_B_SHIFT (2)
<> 129:0ab6a29f35bf 49 #define SECTION_C_SHIFT (3)
<> 129:0ab6a29f35bf 50 #define SECTION_TEX0_SHIFT (12)
<> 129:0ab6a29f35bf 51 #define SECTION_TEX1_SHIFT (13)
<> 129:0ab6a29f35bf 52 #define SECTION_TEX2_SHIFT (14)
<> 129:0ab6a29f35bf 53
<> 129:0ab6a29f35bf 54 #define SECTION_XN_MASK (0xFFFFFFEF)
<> 129:0ab6a29f35bf 55 #define SECTION_XN_SHIFT (4)
<> 129:0ab6a29f35bf 56
<> 129:0ab6a29f35bf 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
<> 129:0ab6a29f35bf 58 #define SECTION_DOMAIN_SHIFT (5)
<> 129:0ab6a29f35bf 59
<> 129:0ab6a29f35bf 60 #define SECTION_P_MASK (0xFFFFFDFF)
<> 129:0ab6a29f35bf 61 #define SECTION_P_SHIFT (9)
<> 129:0ab6a29f35bf 62
<> 129:0ab6a29f35bf 63 #define SECTION_AP_MASK (0xFFFF73FF)
<> 129:0ab6a29f35bf 64 #define SECTION_AP_SHIFT (10)
<> 129:0ab6a29f35bf 65 #define SECTION_AP2_SHIFT (15)
<> 129:0ab6a29f35bf 66
<> 129:0ab6a29f35bf 67 #define SECTION_S_MASK (0xFFFEFFFF)
<> 129:0ab6a29f35bf 68 #define SECTION_S_SHIFT (16)
<> 129:0ab6a29f35bf 69
<> 129:0ab6a29f35bf 70 #define SECTION_NG_MASK (0xFFFDFFFF)
<> 129:0ab6a29f35bf 71 #define SECTION_NG_SHIFT (17)
<> 129:0ab6a29f35bf 72
<> 129:0ab6a29f35bf 73 #define SECTION_NS_MASK (0xFFF7FFFF)
<> 129:0ab6a29f35bf 74 #define SECTION_NS_SHIFT (19)
<> 129:0ab6a29f35bf 75
<> 129:0ab6a29f35bf 76
<> 129:0ab6a29f35bf 77 #define PAGE_L1_DESCRIPTOR (0x1)
<> 129:0ab6a29f35bf 78 #define PAGE_L1_MASK (0xFFFFFFFC)
<> 129:0ab6a29f35bf 79
<> 129:0ab6a29f35bf 80 #define PAGE_L2_4K_DESC (0x2)
<> 129:0ab6a29f35bf 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
<> 129:0ab6a29f35bf 82
<> 129:0ab6a29f35bf 83 #define PAGE_L2_64K_DESC (0x1)
<> 129:0ab6a29f35bf 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
<> 129:0ab6a29f35bf 85
<> 129:0ab6a29f35bf 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
<> 129:0ab6a29f35bf 87 #define PAGE_4K_B_SHIFT (2)
<> 129:0ab6a29f35bf 88 #define PAGE_4K_C_SHIFT (3)
<> 129:0ab6a29f35bf 89 #define PAGE_4K_TEX0_SHIFT (6)
<> 129:0ab6a29f35bf 90 #define PAGE_4K_TEX1_SHIFT (7)
<> 129:0ab6a29f35bf 91 #define PAGE_4K_TEX2_SHIFT (8)
<> 129:0ab6a29f35bf 92
<> 129:0ab6a29f35bf 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
<> 129:0ab6a29f35bf 94 #define PAGE_64K_B_SHIFT (2)
<> 129:0ab6a29f35bf 95 #define PAGE_64K_C_SHIFT (3)
<> 129:0ab6a29f35bf 96 #define PAGE_64K_TEX0_SHIFT (12)
<> 129:0ab6a29f35bf 97 #define PAGE_64K_TEX1_SHIFT (13)
<> 129:0ab6a29f35bf 98 #define PAGE_64K_TEX2_SHIFT (14)
<> 129:0ab6a29f35bf 99
<> 129:0ab6a29f35bf 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
<> 129:0ab6a29f35bf 101 #define PAGE_B_SHIFT (2)
<> 129:0ab6a29f35bf 102 #define PAGE_C_SHIFT (3)
<> 129:0ab6a29f35bf 103 #define PAGE_TEX_SHIFT (12)
<> 129:0ab6a29f35bf 104
<> 129:0ab6a29f35bf 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
<> 129:0ab6a29f35bf 106 #define PAGE_XN_4K_SHIFT (0)
<> 129:0ab6a29f35bf 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
<> 129:0ab6a29f35bf 108 #define PAGE_XN_64K_SHIFT (15)
<> 129:0ab6a29f35bf 109
<> 129:0ab6a29f35bf 110
<> 129:0ab6a29f35bf 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
<> 129:0ab6a29f35bf 112 #define PAGE_DOMAIN_SHIFT (5)
<> 129:0ab6a29f35bf 113
<> 129:0ab6a29f35bf 114 #define PAGE_P_MASK (0xFFFFFDFF)
<> 129:0ab6a29f35bf 115 #define PAGE_P_SHIFT (9)
<> 129:0ab6a29f35bf 116
<> 129:0ab6a29f35bf 117 #define PAGE_AP_MASK (0xFFFFFDCF)
<> 129:0ab6a29f35bf 118 #define PAGE_AP_SHIFT (4)
<> 129:0ab6a29f35bf 119 #define PAGE_AP2_SHIFT (9)
<> 129:0ab6a29f35bf 120
<> 129:0ab6a29f35bf 121 #define PAGE_S_MASK (0xFFFFFBFF)
<> 129:0ab6a29f35bf 122 #define PAGE_S_SHIFT (10)
<> 129:0ab6a29f35bf 123
<> 129:0ab6a29f35bf 124 #define PAGE_NG_MASK (0xFFFFF7FF)
<> 129:0ab6a29f35bf 125 #define PAGE_NG_SHIFT (11)
<> 129:0ab6a29f35bf 126
<> 129:0ab6a29f35bf 127 #define PAGE_NS_MASK (0xFFFFFFF7)
<> 129:0ab6a29f35bf 128 #define PAGE_NS_SHIFT (3)
<> 129:0ab6a29f35bf 129
<> 129:0ab6a29f35bf 130 #define OFFSET_1M (0x00100000)
<> 129:0ab6a29f35bf 131 #define OFFSET_64K (0x00010000)
<> 129:0ab6a29f35bf 132 #define OFFSET_4K (0x00001000)
<> 129:0ab6a29f35bf 133
<> 129:0ab6a29f35bf 134 #define DESCRIPTOR_FAULT (0x00000000)
<> 129:0ab6a29f35bf 135
<> 129:0ab6a29f35bf 136 /* ########################### MMU Function Access ########################### */
<> 129:0ab6a29f35bf 137 /** \ingroup MMU_FunctionInterface
<> 129:0ab6a29f35bf 138 \defgroup MMU_Functions MMU Functions Interface
<> 129:0ab6a29f35bf 139 @{
<> 129:0ab6a29f35bf 140 */
<> 129:0ab6a29f35bf 141
<> 129:0ab6a29f35bf 142 /* Attributes enumerations */
<> 129:0ab6a29f35bf 143
<> 129:0ab6a29f35bf 144 /* Region size attributes */
<> 129:0ab6a29f35bf 145 typedef enum
<> 129:0ab6a29f35bf 146 {
<> 129:0ab6a29f35bf 147 SECTION,
<> 129:0ab6a29f35bf 148 PAGE_4k,
<> 129:0ab6a29f35bf 149 PAGE_64k,
<> 129:0ab6a29f35bf 150 } mmu_region_size_Type;
<> 129:0ab6a29f35bf 151
<> 129:0ab6a29f35bf 152 /* Region type attributes */
<> 129:0ab6a29f35bf 153 typedef enum
<> 129:0ab6a29f35bf 154 {
<> 129:0ab6a29f35bf 155 NORMAL,
<> 129:0ab6a29f35bf 156 DEVICE,
<> 129:0ab6a29f35bf 157 SHARED_DEVICE,
<> 129:0ab6a29f35bf 158 NON_SHARED_DEVICE,
<> 129:0ab6a29f35bf 159 STRONGLY_ORDERED
<> 129:0ab6a29f35bf 160 } mmu_memory_Type;
<> 129:0ab6a29f35bf 161
<> 129:0ab6a29f35bf 162 /* Region cacheability attributes */
<> 129:0ab6a29f35bf 163 typedef enum
<> 129:0ab6a29f35bf 164 {
<> 129:0ab6a29f35bf 165 NON_CACHEABLE,
<> 129:0ab6a29f35bf 166 WB_WA,
<> 129:0ab6a29f35bf 167 WT,
<> 129:0ab6a29f35bf 168 WB_NO_WA,
<> 129:0ab6a29f35bf 169 } mmu_cacheability_Type;
<> 129:0ab6a29f35bf 170
<> 129:0ab6a29f35bf 171 /* Region parity check attributes */
<> 129:0ab6a29f35bf 172 typedef enum
<> 129:0ab6a29f35bf 173 {
<> 129:0ab6a29f35bf 174 ECC_DISABLED,
<> 129:0ab6a29f35bf 175 ECC_ENABLED,
<> 129:0ab6a29f35bf 176 } mmu_ecc_check_Type;
<> 129:0ab6a29f35bf 177
<> 129:0ab6a29f35bf 178 /* Region execution attributes */
<> 129:0ab6a29f35bf 179 typedef enum
<> 129:0ab6a29f35bf 180 {
<> 129:0ab6a29f35bf 181 EXECUTE,
<> 129:0ab6a29f35bf 182 NON_EXECUTE,
<> 129:0ab6a29f35bf 183 } mmu_execute_Type;
<> 129:0ab6a29f35bf 184
<> 129:0ab6a29f35bf 185 /* Region global attributes */
<> 129:0ab6a29f35bf 186 typedef enum
<> 129:0ab6a29f35bf 187 {
<> 129:0ab6a29f35bf 188 GLOBAL,
<> 129:0ab6a29f35bf 189 NON_GLOBAL,
<> 129:0ab6a29f35bf 190 } mmu_global_Type;
<> 129:0ab6a29f35bf 191
<> 129:0ab6a29f35bf 192 /* Region shareability attributes */
<> 129:0ab6a29f35bf 193 typedef enum
<> 129:0ab6a29f35bf 194 {
<> 129:0ab6a29f35bf 195 NON_SHARED,
<> 129:0ab6a29f35bf 196 SHARED,
<> 129:0ab6a29f35bf 197 } mmu_shared_Type;
<> 129:0ab6a29f35bf 198
<> 129:0ab6a29f35bf 199 /* Region security attributes */
<> 129:0ab6a29f35bf 200 typedef enum
<> 129:0ab6a29f35bf 201 {
<> 129:0ab6a29f35bf 202 SECURE,
<> 129:0ab6a29f35bf 203 NON_SECURE,
<> 129:0ab6a29f35bf 204 } mmu_secure_Type;
<> 129:0ab6a29f35bf 205
<> 129:0ab6a29f35bf 206 /* Region access attributes */
<> 129:0ab6a29f35bf 207 typedef enum
<> 129:0ab6a29f35bf 208 {
<> 129:0ab6a29f35bf 209 NO_ACCESS,
<> 129:0ab6a29f35bf 210 RW,
<> 129:0ab6a29f35bf 211 READ,
<> 129:0ab6a29f35bf 212 } mmu_access_Type;
<> 129:0ab6a29f35bf 213
<> 129:0ab6a29f35bf 214 /* Memory Region definition */
<> 129:0ab6a29f35bf 215 typedef struct RegionStruct {
<> 129:0ab6a29f35bf 216 mmu_region_size_Type rg_t;
<> 129:0ab6a29f35bf 217 mmu_memory_Type mem_t;
<> 129:0ab6a29f35bf 218 uint8_t domain;
<> 129:0ab6a29f35bf 219 mmu_cacheability_Type inner_norm_t;
<> 129:0ab6a29f35bf 220 mmu_cacheability_Type outer_norm_t;
<> 129:0ab6a29f35bf 221 mmu_ecc_check_Type e_t;
<> 129:0ab6a29f35bf 222 mmu_execute_Type xn_t;
<> 129:0ab6a29f35bf 223 mmu_global_Type g_t;
<> 129:0ab6a29f35bf 224 mmu_secure_Type sec_t;
<> 129:0ab6a29f35bf 225 mmu_access_Type priv_t;
<> 129:0ab6a29f35bf 226 mmu_access_Type user_t;
<> 129:0ab6a29f35bf 227 mmu_shared_Type sh_t;
<> 129:0ab6a29f35bf 228
<> 129:0ab6a29f35bf 229 } mmu_region_attributes_Type;
<> 129:0ab6a29f35bf 230
<> 129:0ab6a29f35bf 231 /** \brief Set section execution-never attribute
<> 129:0ab6a29f35bf 232
<> 129:0ab6a29f35bf 233 The function sets section execution-never attribute
<> 129:0ab6a29f35bf 234
<> 129:0ab6a29f35bf 235 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
<> 129:0ab6a29f35bf 237
<> 129:0ab6a29f35bf 238 \return 0
<> 129:0ab6a29f35bf 239 */
<> 129:0ab6a29f35bf 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
<> 129:0ab6a29f35bf 241 {
<> 129:0ab6a29f35bf 242 *descriptor_l1 &= SECTION_XN_MASK;
<> 129:0ab6a29f35bf 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
<> 129:0ab6a29f35bf 244 return 0;
<> 129:0ab6a29f35bf 245 }
<> 129:0ab6a29f35bf 246
<> 129:0ab6a29f35bf 247 /** \brief Set section domain
<> 129:0ab6a29f35bf 248
<> 129:0ab6a29f35bf 249 The function sets section domain
<> 129:0ab6a29f35bf 250
<> 129:0ab6a29f35bf 251 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 252 \param [in] domain Section domain
<> 129:0ab6a29f35bf 253
<> 129:0ab6a29f35bf 254 \return 0
<> 129:0ab6a29f35bf 255 */
<> 129:0ab6a29f35bf 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
<> 129:0ab6a29f35bf 257 {
<> 129:0ab6a29f35bf 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
<> 129:0ab6a29f35bf 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
<> 129:0ab6a29f35bf 260 return 0;
<> 129:0ab6a29f35bf 261 }
<> 129:0ab6a29f35bf 262
<> 129:0ab6a29f35bf 263 /** \brief Set section parity check
<> 129:0ab6a29f35bf 264
<> 129:0ab6a29f35bf 265 The function sets section parity check
<> 129:0ab6a29f35bf 266
<> 129:0ab6a29f35bf 267 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 129:0ab6a29f35bf 269
<> 129:0ab6a29f35bf 270 \return 0
<> 129:0ab6a29f35bf 271 */
<> 129:0ab6a29f35bf 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 129:0ab6a29f35bf 273 {
<> 129:0ab6a29f35bf 274 *descriptor_l1 &= SECTION_P_MASK;
<> 129:0ab6a29f35bf 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 129:0ab6a29f35bf 276 return 0;
<> 129:0ab6a29f35bf 277 }
<> 129:0ab6a29f35bf 278
<> 129:0ab6a29f35bf 279 /** \brief Set section access privileges
<> 129:0ab6a29f35bf 280
<> 129:0ab6a29f35bf 281 The function sets section access privileges
<> 129:0ab6a29f35bf 282
<> 129:0ab6a29f35bf 283 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 129:0ab6a29f35bf 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 129:0ab6a29f35bf 286 \param [in] afe Access flag enable
<> 129:0ab6a29f35bf 287
<> 129:0ab6a29f35bf 288 \return 0
<> 129:0ab6a29f35bf 289 */
<> 129:0ab6a29f35bf 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 129:0ab6a29f35bf 291 {
<> 129:0ab6a29f35bf 292 uint32_t ap = 0;
<> 129:0ab6a29f35bf 293
<> 129:0ab6a29f35bf 294 if (afe == 0) { //full access
<> 129:0ab6a29f35bf 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 129:0ab6a29f35bf 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 129:0ab6a29f35bf 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 129:0ab6a29f35bf 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 129:0ab6a29f35bf 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 129:0ab6a29f35bf 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 129:0ab6a29f35bf 301 }
<> 129:0ab6a29f35bf 302
<> 129:0ab6a29f35bf 303 else { //Simplified access
<> 129:0ab6a29f35bf 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 129:0ab6a29f35bf 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 129:0ab6a29f35bf 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 129:0ab6a29f35bf 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 129:0ab6a29f35bf 308 }
<> 129:0ab6a29f35bf 309
<> 129:0ab6a29f35bf 310 *descriptor_l1 &= SECTION_AP_MASK;
<> 129:0ab6a29f35bf 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
<> 129:0ab6a29f35bf 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
<> 129:0ab6a29f35bf 313
<> 129:0ab6a29f35bf 314 return 0;
<> 129:0ab6a29f35bf 315 }
<> 129:0ab6a29f35bf 316
<> 129:0ab6a29f35bf 317 /** \brief Set section shareability
<> 129:0ab6a29f35bf 318
<> 129:0ab6a29f35bf 319 The function sets section shareability
<> 129:0ab6a29f35bf 320
<> 129:0ab6a29f35bf 321 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
<> 129:0ab6a29f35bf 323
<> 129:0ab6a29f35bf 324 \return 0
<> 129:0ab6a29f35bf 325 */
<> 129:0ab6a29f35bf 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
<> 129:0ab6a29f35bf 327 {
<> 129:0ab6a29f35bf 328 *descriptor_l1 &= SECTION_S_MASK;
<> 129:0ab6a29f35bf 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
<> 129:0ab6a29f35bf 330 return 0;
<> 129:0ab6a29f35bf 331 }
<> 129:0ab6a29f35bf 332
<> 129:0ab6a29f35bf 333 /** \brief Set section Global attribute
<> 129:0ab6a29f35bf 334
<> 129:0ab6a29f35bf 335 The function sets section Global attribute
<> 129:0ab6a29f35bf 336
<> 129:0ab6a29f35bf 337 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
<> 129:0ab6a29f35bf 339
<> 129:0ab6a29f35bf 340 \return 0
<> 129:0ab6a29f35bf 341 */
<> 129:0ab6a29f35bf 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
<> 129:0ab6a29f35bf 343 {
<> 129:0ab6a29f35bf 344 *descriptor_l1 &= SECTION_NG_MASK;
<> 129:0ab6a29f35bf 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
<> 129:0ab6a29f35bf 346 return 0;
<> 129:0ab6a29f35bf 347 }
<> 129:0ab6a29f35bf 348
<> 129:0ab6a29f35bf 349 /** \brief Set section Security attribute
<> 129:0ab6a29f35bf 350
<> 129:0ab6a29f35bf 351 The function sets section Global attribute
<> 129:0ab6a29f35bf 352
<> 129:0ab6a29f35bf 353 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
<> 129:0ab6a29f35bf 355
<> 129:0ab6a29f35bf 356 \return 0
<> 129:0ab6a29f35bf 357 */
<> 129:0ab6a29f35bf 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 129:0ab6a29f35bf 359 {
<> 129:0ab6a29f35bf 360 *descriptor_l1 &= SECTION_NS_MASK;
<> 129:0ab6a29f35bf 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
<> 129:0ab6a29f35bf 362 return 0;
<> 129:0ab6a29f35bf 363 }
<> 129:0ab6a29f35bf 364
<> 129:0ab6a29f35bf 365 /* Page 4k or 64k */
<> 129:0ab6a29f35bf 366 /** \brief Set 4k/64k page execution-never attribute
<> 129:0ab6a29f35bf 367
<> 129:0ab6a29f35bf 368 The function sets 4k/64k page execution-never attribute
<> 129:0ab6a29f35bf 369
<> 129:0ab6a29f35bf 370 \param [out] descriptor_l2 L2 descriptor.
<> 129:0ab6a29f35bf 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
<> 129:0ab6a29f35bf 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
<> 129:0ab6a29f35bf 373
<> 129:0ab6a29f35bf 374 \return 0
<> 129:0ab6a29f35bf 375 */
<> 129:0ab6a29f35bf 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
<> 129:0ab6a29f35bf 377 {
<> 129:0ab6a29f35bf 378 if (page == PAGE_4k)
<> 129:0ab6a29f35bf 379 {
<> 129:0ab6a29f35bf 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
<> 129:0ab6a29f35bf 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
<> 129:0ab6a29f35bf 382 }
<> 129:0ab6a29f35bf 383 else
<> 129:0ab6a29f35bf 384 {
<> 129:0ab6a29f35bf 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
<> 129:0ab6a29f35bf 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
<> 129:0ab6a29f35bf 387 }
<> 129:0ab6a29f35bf 388 return 0;
<> 129:0ab6a29f35bf 389 }
<> 129:0ab6a29f35bf 390
<> 129:0ab6a29f35bf 391 /** \brief Set 4k/64k page domain
<> 129:0ab6a29f35bf 392
<> 129:0ab6a29f35bf 393 The function sets 4k/64k page domain
<> 129:0ab6a29f35bf 394
<> 129:0ab6a29f35bf 395 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 396 \param [in] domain Page domain
<> 129:0ab6a29f35bf 397
<> 129:0ab6a29f35bf 398 \return 0
<> 129:0ab6a29f35bf 399 */
<> 129:0ab6a29f35bf 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
<> 129:0ab6a29f35bf 401 {
<> 129:0ab6a29f35bf 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
<> 129:0ab6a29f35bf 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
<> 129:0ab6a29f35bf 404 return 0;
<> 129:0ab6a29f35bf 405 }
<> 129:0ab6a29f35bf 406
<> 129:0ab6a29f35bf 407 /** \brief Set 4k/64k page parity check
<> 129:0ab6a29f35bf 408
<> 129:0ab6a29f35bf 409 The function sets 4k/64k page parity check
<> 129:0ab6a29f35bf 410
<> 129:0ab6a29f35bf 411 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 129:0ab6a29f35bf 413
<> 129:0ab6a29f35bf 414 \return 0
<> 129:0ab6a29f35bf 415 */
<> 129:0ab6a29f35bf 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 129:0ab6a29f35bf 417 {
<> 129:0ab6a29f35bf 418 *descriptor_l1 &= SECTION_P_MASK;
<> 129:0ab6a29f35bf 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 129:0ab6a29f35bf 420 return 0;
<> 129:0ab6a29f35bf 421 }
<> 129:0ab6a29f35bf 422
<> 129:0ab6a29f35bf 423 /** \brief Set 4k/64k page access privileges
<> 129:0ab6a29f35bf 424
<> 129:0ab6a29f35bf 425 The function sets 4k/64k page access privileges
<> 129:0ab6a29f35bf 426
<> 129:0ab6a29f35bf 427 \param [out] descriptor_l2 L2 descriptor.
<> 129:0ab6a29f35bf 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 129:0ab6a29f35bf 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 129:0ab6a29f35bf 430 \param [in] afe Access flag enable
<> 129:0ab6a29f35bf 431
<> 129:0ab6a29f35bf 432 \return 0
<> 129:0ab6a29f35bf 433 */
<> 129:0ab6a29f35bf 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 129:0ab6a29f35bf 435 {
<> 129:0ab6a29f35bf 436 uint32_t ap = 0;
<> 129:0ab6a29f35bf 437
<> 129:0ab6a29f35bf 438 if (afe == 0) { //full access
<> 129:0ab6a29f35bf 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 129:0ab6a29f35bf 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 129:0ab6a29f35bf 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 129:0ab6a29f35bf 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 129:0ab6a29f35bf 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 129:0ab6a29f35bf 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
<> 129:0ab6a29f35bf 445 }
<> 129:0ab6a29f35bf 446
<> 129:0ab6a29f35bf 447 else { //Simplified access
<> 129:0ab6a29f35bf 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 129:0ab6a29f35bf 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 129:0ab6a29f35bf 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 129:0ab6a29f35bf 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 129:0ab6a29f35bf 452 }
<> 129:0ab6a29f35bf 453
<> 129:0ab6a29f35bf 454 *descriptor_l2 &= PAGE_AP_MASK;
<> 129:0ab6a29f35bf 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
<> 129:0ab6a29f35bf 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
<> 129:0ab6a29f35bf 457
<> 129:0ab6a29f35bf 458 return 0;
<> 129:0ab6a29f35bf 459 }
<> 129:0ab6a29f35bf 460
<> 129:0ab6a29f35bf 461 /** \brief Set 4k/64k page shareability
<> 129:0ab6a29f35bf 462
<> 129:0ab6a29f35bf 463 The function sets 4k/64k page shareability
<> 129:0ab6a29f35bf 464
<> 129:0ab6a29f35bf 465 \param [out] descriptor_l2 L2 descriptor.
<> 129:0ab6a29f35bf 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
<> 129:0ab6a29f35bf 467
<> 129:0ab6a29f35bf 468 \return 0
<> 129:0ab6a29f35bf 469 */
<> 129:0ab6a29f35bf 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
<> 129:0ab6a29f35bf 471 {
<> 129:0ab6a29f35bf 472 *descriptor_l2 &= PAGE_S_MASK;
<> 129:0ab6a29f35bf 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
<> 129:0ab6a29f35bf 474 return 0;
<> 129:0ab6a29f35bf 475 }
<> 129:0ab6a29f35bf 476
<> 129:0ab6a29f35bf 477 /** \brief Set 4k/64k page Global attribute
<> 129:0ab6a29f35bf 478
<> 129:0ab6a29f35bf 479 The function sets 4k/64k page Global attribute
<> 129:0ab6a29f35bf 480
<> 129:0ab6a29f35bf 481 \param [out] descriptor_l2 L2 descriptor.
<> 129:0ab6a29f35bf 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
<> 129:0ab6a29f35bf 483
<> 129:0ab6a29f35bf 484 \return 0
<> 129:0ab6a29f35bf 485 */
<> 129:0ab6a29f35bf 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
<> 129:0ab6a29f35bf 487 {
<> 129:0ab6a29f35bf 488 *descriptor_l2 &= PAGE_NG_MASK;
<> 129:0ab6a29f35bf 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
<> 129:0ab6a29f35bf 490 return 0;
<> 129:0ab6a29f35bf 491 }
<> 129:0ab6a29f35bf 492
<> 129:0ab6a29f35bf 493 /** \brief Set 4k/64k page Security attribute
<> 129:0ab6a29f35bf 494
<> 129:0ab6a29f35bf 495 The function sets 4k/64k page Global attribute
<> 129:0ab6a29f35bf 496
<> 129:0ab6a29f35bf 497 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
<> 129:0ab6a29f35bf 499
<> 129:0ab6a29f35bf 500 \return 0
<> 129:0ab6a29f35bf 501 */
<> 129:0ab6a29f35bf 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 129:0ab6a29f35bf 503 {
<> 129:0ab6a29f35bf 504 *descriptor_l1 &= PAGE_NS_MASK;
<> 129:0ab6a29f35bf 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
<> 129:0ab6a29f35bf 506 return 0;
<> 129:0ab6a29f35bf 507 }
<> 129:0ab6a29f35bf 508
<> 129:0ab6a29f35bf 509
<> 129:0ab6a29f35bf 510 /** \brief Set Section memory attributes
<> 129:0ab6a29f35bf 511
<> 129:0ab6a29f35bf 512 The function sets section memory attributes
<> 129:0ab6a29f35bf 513
<> 129:0ab6a29f35bf 514 \param [out] descriptor_l1 L1 descriptor.
<> 129:0ab6a29f35bf 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 129:0ab6a29f35bf 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 129:0ab6a29f35bf 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 129:0ab6a29f35bf 518
<> 129:0ab6a29f35bf 519 \return 0
<> 129:0ab6a29f35bf 520 */
<> 129:0ab6a29f35bf 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
<> 129:0ab6a29f35bf 522 {
<> 129:0ab6a29f35bf 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
<> 129:0ab6a29f35bf 524
<> 129:0ab6a29f35bf 525 if (STRONGLY_ORDERED == mem)
<> 129:0ab6a29f35bf 526 {
<> 129:0ab6a29f35bf 527 return 0;
<> 129:0ab6a29f35bf 528 }
<> 129:0ab6a29f35bf 529 else if (SHARED_DEVICE == mem)
<> 129:0ab6a29f35bf 530 {
<> 129:0ab6a29f35bf 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 129:0ab6a29f35bf 532 }
<> 129:0ab6a29f35bf 533 else if (NON_SHARED_DEVICE == mem)
<> 129:0ab6a29f35bf 534 {
<> 129:0ab6a29f35bf 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
<> 129:0ab6a29f35bf 536 }
<> 129:0ab6a29f35bf 537 else if (NORMAL == mem)
<> 129:0ab6a29f35bf 538 {
<> 129:0ab6a29f35bf 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
<> 129:0ab6a29f35bf 540 switch(inner)
<> 129:0ab6a29f35bf 541 {
<> 129:0ab6a29f35bf 542 case NON_CACHEABLE:
<> 129:0ab6a29f35bf 543 break;
<> 129:0ab6a29f35bf 544 case WB_WA:
<> 129:0ab6a29f35bf 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 129:0ab6a29f35bf 546 break;
<> 129:0ab6a29f35bf 547 case WT:
<> 129:0ab6a29f35bf 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
<> 129:0ab6a29f35bf 549 break;
<> 129:0ab6a29f35bf 550 case WB_NO_WA:
<> 129:0ab6a29f35bf 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
<> 129:0ab6a29f35bf 552 break;
<> 129:0ab6a29f35bf 553 }
<> 129:0ab6a29f35bf 554 switch(outer)
<> 129:0ab6a29f35bf 555 {
<> 129:0ab6a29f35bf 556 case NON_CACHEABLE:
<> 129:0ab6a29f35bf 557 break;
<> 129:0ab6a29f35bf 558 case WB_WA:
<> 129:0ab6a29f35bf 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
<> 129:0ab6a29f35bf 560 break;
<> 129:0ab6a29f35bf 561 case WT:
<> 129:0ab6a29f35bf 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
<> 129:0ab6a29f35bf 563 break;
<> 129:0ab6a29f35bf 564 case WB_NO_WA:
<> 129:0ab6a29f35bf 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
<> 129:0ab6a29f35bf 566 break;
<> 129:0ab6a29f35bf 567 }
<> 129:0ab6a29f35bf 568 }
<> 129:0ab6a29f35bf 569
<> 129:0ab6a29f35bf 570 return 0;
<> 129:0ab6a29f35bf 571 }
<> 129:0ab6a29f35bf 572
<> 129:0ab6a29f35bf 573 /** \brief Set 4k/64k page memory attributes
<> 129:0ab6a29f35bf 574
<> 129:0ab6a29f35bf 575 The function sets 4k/64k page memory attributes
<> 129:0ab6a29f35bf 576
<> 129:0ab6a29f35bf 577 \param [out] descriptor_l2 L2 descriptor.
<> 129:0ab6a29f35bf 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 129:0ab6a29f35bf 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 129:0ab6a29f35bf 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 129:0ab6a29f35bf 581
<> 129:0ab6a29f35bf 582 \return 0
<> 129:0ab6a29f35bf 583 */
<> 129:0ab6a29f35bf 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
<> 129:0ab6a29f35bf 585 {
<> 129:0ab6a29f35bf 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
<> 129:0ab6a29f35bf 587
<> 129:0ab6a29f35bf 588 if (page == PAGE_64k)
<> 129:0ab6a29f35bf 589 {
<> 129:0ab6a29f35bf 590 //same as section
<> 129:0ab6a29f35bf 591 __memory_section(descriptor_l2, mem, outer, inner);
<> 129:0ab6a29f35bf 592 }
<> 129:0ab6a29f35bf 593 else
<> 129:0ab6a29f35bf 594 {
<> 129:0ab6a29f35bf 595 if (STRONGLY_ORDERED == mem)
<> 129:0ab6a29f35bf 596 {
<> 129:0ab6a29f35bf 597 return 0;
<> 129:0ab6a29f35bf 598 }
<> 129:0ab6a29f35bf 599 else if (SHARED_DEVICE == mem)
<> 129:0ab6a29f35bf 600 {
<> 129:0ab6a29f35bf 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 129:0ab6a29f35bf 602 }
<> 129:0ab6a29f35bf 603 else if (NON_SHARED_DEVICE == mem)
<> 129:0ab6a29f35bf 604 {
<> 129:0ab6a29f35bf 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
<> 129:0ab6a29f35bf 606 }
<> 129:0ab6a29f35bf 607 else if (NORMAL == mem)
<> 129:0ab6a29f35bf 608 {
<> 129:0ab6a29f35bf 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
<> 129:0ab6a29f35bf 610 switch(inner)
<> 129:0ab6a29f35bf 611 {
<> 129:0ab6a29f35bf 612 case NON_CACHEABLE:
<> 129:0ab6a29f35bf 613 break;
<> 129:0ab6a29f35bf 614 case WB_WA:
<> 129:0ab6a29f35bf 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 129:0ab6a29f35bf 616 break;
<> 129:0ab6a29f35bf 617 case WT:
<> 129:0ab6a29f35bf 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
<> 129:0ab6a29f35bf 619 break;
<> 129:0ab6a29f35bf 620 case WB_NO_WA:
<> 129:0ab6a29f35bf 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
<> 129:0ab6a29f35bf 622 break;
<> 129:0ab6a29f35bf 623 }
<> 129:0ab6a29f35bf 624 switch(outer)
<> 129:0ab6a29f35bf 625 {
<> 129:0ab6a29f35bf 626 case NON_CACHEABLE:
<> 129:0ab6a29f35bf 627 break;
<> 129:0ab6a29f35bf 628 case WB_WA:
<> 129:0ab6a29f35bf 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
<> 129:0ab6a29f35bf 630 break;
<> 129:0ab6a29f35bf 631 case WT:
<> 129:0ab6a29f35bf 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
<> 129:0ab6a29f35bf 633 break;
<> 129:0ab6a29f35bf 634 case WB_NO_WA:
<> 129:0ab6a29f35bf 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
<> 129:0ab6a29f35bf 636 break;
<> 129:0ab6a29f35bf 637 }
<> 129:0ab6a29f35bf 638 }
<> 129:0ab6a29f35bf 639 }
<> 129:0ab6a29f35bf 640
<> 129:0ab6a29f35bf 641 return 0;
<> 129:0ab6a29f35bf 642 }
<> 129:0ab6a29f35bf 643
<> 129:0ab6a29f35bf 644 /** \brief Create a L1 section descriptor
<> 129:0ab6a29f35bf 645
<> 129:0ab6a29f35bf 646 The function creates a section descriptor.
<> 129:0ab6a29f35bf 647
<> 129:0ab6a29f35bf 648 Assumptions:
<> 129:0ab6a29f35bf 649 - 16MB super sections not supported
<> 129:0ab6a29f35bf 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 129:0ab6a29f35bf 651 - Functions always return 0
<> 129:0ab6a29f35bf 652
<> 129:0ab6a29f35bf 653 \param [out] descriptor L1 descriptor
<> 129:0ab6a29f35bf 654 \param [out] descriptor2 L2 descriptor
<> 129:0ab6a29f35bf 655 \param [in] reg Section attributes
<> 129:0ab6a29f35bf 656
<> 129:0ab6a29f35bf 657 \return 0
<> 129:0ab6a29f35bf 658 */
<> 129:0ab6a29f35bf 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
<> 129:0ab6a29f35bf 660 {
<> 129:0ab6a29f35bf 661 *descriptor = 0;
<> 129:0ab6a29f35bf 662
<> 129:0ab6a29f35bf 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
<> 129:0ab6a29f35bf 664 __xn_section(descriptor,reg.xn_t);
<> 129:0ab6a29f35bf 665 __domain_section(descriptor, reg.domain);
<> 129:0ab6a29f35bf 666 __p_section(descriptor, reg.e_t);
<> 129:0ab6a29f35bf 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
<> 129:0ab6a29f35bf 668 __shared_section(descriptor,reg.sh_t);
<> 129:0ab6a29f35bf 669 __global_section(descriptor,reg.g_t);
<> 129:0ab6a29f35bf 670 __secure_section(descriptor,reg.sec_t);
<> 129:0ab6a29f35bf 671 *descriptor &= SECTION_MASK;
<> 129:0ab6a29f35bf 672 *descriptor |= SECTION_DESCRIPTOR;
<> 129:0ab6a29f35bf 673
<> 129:0ab6a29f35bf 674 return 0;
<> 129:0ab6a29f35bf 675
<> 129:0ab6a29f35bf 676 }
<> 129:0ab6a29f35bf 677
<> 129:0ab6a29f35bf 678
<> 129:0ab6a29f35bf 679 /** \brief Create a L1 and L2 4k/64k page descriptor
<> 129:0ab6a29f35bf 680
<> 129:0ab6a29f35bf 681 The function creates a 4k/64k page descriptor.
<> 129:0ab6a29f35bf 682 Assumptions:
<> 129:0ab6a29f35bf 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 129:0ab6a29f35bf 684 - Functions always return 0
<> 129:0ab6a29f35bf 685
<> 129:0ab6a29f35bf 686 \param [out] descriptor L1 descriptor
<> 129:0ab6a29f35bf 687 \param [out] descriptor2 L2 descriptor
<> 129:0ab6a29f35bf 688 \param [in] reg 4k/64k page attributes
<> 129:0ab6a29f35bf 689
<> 129:0ab6a29f35bf 690 \return 0
<> 129:0ab6a29f35bf 691 */
<> 129:0ab6a29f35bf 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
<> 129:0ab6a29f35bf 693 {
<> 129:0ab6a29f35bf 694 *descriptor = 0;
<> 129:0ab6a29f35bf 695 *descriptor2 = 0;
<> 129:0ab6a29f35bf 696
<> 129:0ab6a29f35bf 697 switch (reg.rg_t)
<> 129:0ab6a29f35bf 698 {
<> 129:0ab6a29f35bf 699 case PAGE_4k:
<> 129:0ab6a29f35bf 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
<> 129:0ab6a29f35bf 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
<> 129:0ab6a29f35bf 702 __domain_page(descriptor, reg.domain);
<> 129:0ab6a29f35bf 703 __p_page(descriptor, reg.e_t);
<> 129:0ab6a29f35bf 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 129:0ab6a29f35bf 705 __shared_page(descriptor2,reg.sh_t);
<> 129:0ab6a29f35bf 706 __global_page(descriptor2,reg.g_t);
<> 129:0ab6a29f35bf 707 __secure_page(descriptor,reg.sec_t);
<> 129:0ab6a29f35bf 708 *descriptor &= PAGE_L1_MASK;
<> 129:0ab6a29f35bf 709 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 129:0ab6a29f35bf 710 *descriptor2 &= PAGE_L2_4K_MASK;
<> 129:0ab6a29f35bf 711 *descriptor2 |= PAGE_L2_4K_DESC;
<> 129:0ab6a29f35bf 712 break;
<> 129:0ab6a29f35bf 713
<> 129:0ab6a29f35bf 714 case PAGE_64k:
<> 129:0ab6a29f35bf 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
<> 129:0ab6a29f35bf 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
<> 129:0ab6a29f35bf 717 __domain_page(descriptor, reg.domain);
<> 129:0ab6a29f35bf 718 __p_page(descriptor, reg.e_t);
<> 129:0ab6a29f35bf 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 129:0ab6a29f35bf 720 __shared_page(descriptor2,reg.sh_t);
<> 129:0ab6a29f35bf 721 __global_page(descriptor2,reg.g_t);
<> 129:0ab6a29f35bf 722 __secure_page(descriptor,reg.sec_t);
<> 129:0ab6a29f35bf 723 *descriptor &= PAGE_L1_MASK;
<> 129:0ab6a29f35bf 724 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 129:0ab6a29f35bf 725 *descriptor2 &= PAGE_L2_64K_MASK;
<> 129:0ab6a29f35bf 726 *descriptor2 |= PAGE_L2_64K_DESC;
<> 129:0ab6a29f35bf 727 break;
<> 129:0ab6a29f35bf 728
<> 129:0ab6a29f35bf 729 case SECTION:
<> 129:0ab6a29f35bf 730 //error
<> 129:0ab6a29f35bf 731 break;
<> 129:0ab6a29f35bf 732
<> 129:0ab6a29f35bf 733 }
<> 129:0ab6a29f35bf 734
<> 129:0ab6a29f35bf 735 return 0;
<> 129:0ab6a29f35bf 736
<> 129:0ab6a29f35bf 737 }
<> 129:0ab6a29f35bf 738
<> 129:0ab6a29f35bf 739 /** \brief Create a 1MB Section
<> 129:0ab6a29f35bf 740
<> 129:0ab6a29f35bf 741 \param [in] ttb Translation table base address
<> 129:0ab6a29f35bf 742 \param [in] base_address Section base address
<> 129:0ab6a29f35bf 743 \param [in] count Number of sections to create
<> 129:0ab6a29f35bf 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 129:0ab6a29f35bf 745
<> 129:0ab6a29f35bf 746 */
<> 129:0ab6a29f35bf 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
<> 129:0ab6a29f35bf 748 {
<> 129:0ab6a29f35bf 749 uint32_t offset;
<> 129:0ab6a29f35bf 750 uint32_t entry;
<> 129:0ab6a29f35bf 751 uint32_t i;
<> 129:0ab6a29f35bf 752
<> 129:0ab6a29f35bf 753 offset = base_address >> 20;
<> 129:0ab6a29f35bf 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
<> 129:0ab6a29f35bf 755
<> 129:0ab6a29f35bf 756 //4 bytes aligned
<> 129:0ab6a29f35bf 757 ttb = ttb + offset;
<> 129:0ab6a29f35bf 758
<> 129:0ab6a29f35bf 759 for (i = 0; i < count; i++ )
<> 129:0ab6a29f35bf 760 {
<> 129:0ab6a29f35bf 761 //4 bytes aligned
<> 129:0ab6a29f35bf 762 *ttb++ = entry;
<> 129:0ab6a29f35bf 763 entry += OFFSET_1M;
<> 129:0ab6a29f35bf 764 }
<> 129:0ab6a29f35bf 765 }
<> 129:0ab6a29f35bf 766
<> 129:0ab6a29f35bf 767 /** \brief Create a 4k page entry
<> 129:0ab6a29f35bf 768
<> 129:0ab6a29f35bf 769 \param [in] ttb L1 table base address
<> 129:0ab6a29f35bf 770 \param [in] base_address 4k base address
<> 129:0ab6a29f35bf 771 \param [in] count Number of 4k pages to create
<> 129:0ab6a29f35bf 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 129:0ab6a29f35bf 773 \param [in] ttb_l2 L2 table base address
<> 129:0ab6a29f35bf 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 129:0ab6a29f35bf 775
<> 129:0ab6a29f35bf 776 */
<> 129:0ab6a29f35bf 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 129:0ab6a29f35bf 778 {
<> 129:0ab6a29f35bf 779
<> 129:0ab6a29f35bf 780 uint32_t offset, offset2;
<> 129:0ab6a29f35bf 781 uint32_t entry, entry2;
<> 129:0ab6a29f35bf 782 uint32_t i;
<> 129:0ab6a29f35bf 783
<> 129:0ab6a29f35bf 784
<> 129:0ab6a29f35bf 785 offset = base_address >> 20;
<> 129:0ab6a29f35bf 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 129:0ab6a29f35bf 787
<> 129:0ab6a29f35bf 788 //4 bytes aligned
<> 129:0ab6a29f35bf 789 ttb += offset;
<> 129:0ab6a29f35bf 790 //create l1_entry
<> 129:0ab6a29f35bf 791 *ttb = entry;
<> 129:0ab6a29f35bf 792
<> 129:0ab6a29f35bf 793 offset2 = (base_address & 0xff000) >> 12;
<> 129:0ab6a29f35bf 794 ttb_l2 += offset2;
<> 129:0ab6a29f35bf 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
<> 129:0ab6a29f35bf 796 for (i = 0; i < count; i++ )
<> 129:0ab6a29f35bf 797 {
<> 129:0ab6a29f35bf 798 //4 bytes aligned
<> 129:0ab6a29f35bf 799 *ttb_l2++ = entry2;
<> 129:0ab6a29f35bf 800 entry2 += OFFSET_4K;
<> 129:0ab6a29f35bf 801 }
<> 129:0ab6a29f35bf 802 }
<> 129:0ab6a29f35bf 803
<> 129:0ab6a29f35bf 804 /** \brief Create a 64k page entry
<> 129:0ab6a29f35bf 805
<> 129:0ab6a29f35bf 806 \param [in] ttb L1 table base address
<> 129:0ab6a29f35bf 807 \param [in] base_address 64k base address
<> 129:0ab6a29f35bf 808 \param [in] count Number of 64k pages to create
<> 129:0ab6a29f35bf 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 129:0ab6a29f35bf 810 \param [in] ttb_l2 L2 table base address
<> 129:0ab6a29f35bf 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 129:0ab6a29f35bf 812
<> 129:0ab6a29f35bf 813 */
<> 129:0ab6a29f35bf 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 129:0ab6a29f35bf 815 {
<> 129:0ab6a29f35bf 816 uint32_t offset, offset2;
<> 129:0ab6a29f35bf 817 uint32_t entry, entry2;
<> 129:0ab6a29f35bf 818 uint32_t i,j;
<> 129:0ab6a29f35bf 819
<> 129:0ab6a29f35bf 820
<> 129:0ab6a29f35bf 821 offset = base_address >> 20;
<> 129:0ab6a29f35bf 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 129:0ab6a29f35bf 823
<> 129:0ab6a29f35bf 824 //4 bytes aligned
<> 129:0ab6a29f35bf 825 ttb += offset;
<> 129:0ab6a29f35bf 826 //create l1_entry
<> 129:0ab6a29f35bf 827 *ttb = entry;
<> 129:0ab6a29f35bf 828
<> 129:0ab6a29f35bf 829 offset2 = (base_address & 0xff000) >> 12;
<> 129:0ab6a29f35bf 830 ttb_l2 += offset2;
<> 129:0ab6a29f35bf 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
<> 129:0ab6a29f35bf 832 for (i = 0; i < count; i++ )
<> 129:0ab6a29f35bf 833 {
<> 129:0ab6a29f35bf 834 //create 16 entries
<> 129:0ab6a29f35bf 835 for (j = 0; j < 16; j++)
<> 129:0ab6a29f35bf 836 //4 bytes aligned
<> 129:0ab6a29f35bf 837 *ttb_l2++ = entry2;
<> 129:0ab6a29f35bf 838 entry2 += OFFSET_64K;
<> 129:0ab6a29f35bf 839 }
<> 129:0ab6a29f35bf 840 }
<> 129:0ab6a29f35bf 841
<> 129:0ab6a29f35bf 842 /*@} end of MMU_Functions */
<> 129:0ab6a29f35bf 843 #endif
<> 129:0ab6a29f35bf 844
<> 129:0ab6a29f35bf 845 #ifdef __cplusplus
<> 129:0ab6a29f35bf 846 }
<> 129:0ab6a29f35bf 847 #endif