mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K82F/TOOLCHAIN_ARM_STD/MK82FN256xxx15.sct@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
129:0ab6a29f35bf
Child:
141:794e51388b66
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 #! armcc -E
<> 129:0ab6a29f35bf 2 /*
<> 129:0ab6a29f35bf 3 ** ###################################################################
<> 129:0ab6a29f35bf 4 ** Processors: MK82FN256CAx15
<> 129:0ab6a29f35bf 5 ** MK82FN256VDC15
<> 129:0ab6a29f35bf 6 ** MK82FN256VLL15
<> 129:0ab6a29f35bf 7 ** MK82FN256VLQ15
<> 129:0ab6a29f35bf 8 **
<> 129:0ab6a29f35bf 9 ** Compiler: Keil ARM C/C++ Compiler
<> 129:0ab6a29f35bf 10 ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
<> 129:0ab6a29f35bf 11 ** Version: rev. 1.2, 2015-07-29
<> 129:0ab6a29f35bf 12 ** Build: b160406
<> 129:0ab6a29f35bf 13 **
<> 129:0ab6a29f35bf 14 ** Abstract:
<> 129:0ab6a29f35bf 15 ** Linker file for the Keil ARM C/C++ Compiler
<> 129:0ab6a29f35bf 16 **
<> 129:0ab6a29f35bf 17 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 129:0ab6a29f35bf 18 ** All rights reserved.
<> 129:0ab6a29f35bf 19 **
<> 129:0ab6a29f35bf 20 ** Redistribution and use in source and binary forms, with or without modification,
<> 129:0ab6a29f35bf 21 ** are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 22 **
<> 129:0ab6a29f35bf 23 ** o Redistributions of source code must retain the above copyright notice, this list
<> 129:0ab6a29f35bf 24 ** of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 25 **
<> 129:0ab6a29f35bf 26 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 129:0ab6a29f35bf 27 ** list of conditions and the following disclaimer in the documentation and/or
<> 129:0ab6a29f35bf 28 ** other materials provided with the distribution.
<> 129:0ab6a29f35bf 29 **
<> 129:0ab6a29f35bf 30 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 129:0ab6a29f35bf 31 ** contributors may be used to endorse or promote products derived from this
<> 129:0ab6a29f35bf 32 ** software without specific prior written permission.
<> 129:0ab6a29f35bf 33 **
<> 129:0ab6a29f35bf 34 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 129:0ab6a29f35bf 35 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 129:0ab6a29f35bf 36 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 129:0ab6a29f35bf 37 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 129:0ab6a29f35bf 38 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 129:0ab6a29f35bf 39 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 129:0ab6a29f35bf 40 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 129:0ab6a29f35bf 41 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 129:0ab6a29f35bf 42 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 129:0ab6a29f35bf 43 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 44 **
<> 129:0ab6a29f35bf 45 ** http: www.freescale.com
<> 129:0ab6a29f35bf 46 ** mail: support@freescale.com
<> 129:0ab6a29f35bf 47 **
<> 129:0ab6a29f35bf 48 ** ###################################################################
<> 129:0ab6a29f35bf 49 */
<> 129:0ab6a29f35bf 50
<> 129:0ab6a29f35bf 51 #define __ram_vector_table__ 1
<> 129:0ab6a29f35bf 52
<> 129:0ab6a29f35bf 53 /* Heap 1/4 of ram and stack 1/8 */
<> 129:0ab6a29f35bf 54 #define __stack_size__ 0x8000
<> 129:0ab6a29f35bf 55 #define __heap_size__ 0x10000
<> 129:0ab6a29f35bf 56
<> 129:0ab6a29f35bf 57 #if (defined(__ram_vector_table__))
<> 129:0ab6a29f35bf 58 #define __ram_vector_table_size__ 0x000003C0
<> 129:0ab6a29f35bf 59 #else
<> 129:0ab6a29f35bf 60 #define __ram_vector_table_size__ 0x00000000
<> 129:0ab6a29f35bf 61 #endif
<> 129:0ab6a29f35bf 62
<> 129:0ab6a29f35bf 63 #define m_interrupts_start 0x00000000
<> 129:0ab6a29f35bf 64 #define m_interrupts_size 0x000003C0
<> 129:0ab6a29f35bf 65
<> 129:0ab6a29f35bf 66 #define m_bootloader_config_start 0x000003C0
<> 129:0ab6a29f35bf 67 #define m_bootloader_config_size 0x00000040
<> 129:0ab6a29f35bf 68
<> 129:0ab6a29f35bf 69 #define m_flash_config_start 0x00000400
<> 129:0ab6a29f35bf 70 #define m_flash_config_size 0x00000010
<> 129:0ab6a29f35bf 71
<> 129:0ab6a29f35bf 72 #define m_text_start 0x00000410
<> 129:0ab6a29f35bf 73 #define m_text_size 0x0003FBF0
<> 129:0ab6a29f35bf 74
<> 129:0ab6a29f35bf 75 #define m_interrupts_ram_start 0x1FFF0000
<> 129:0ab6a29f35bf 76 #define m_interrupts_ram_size __ram_vector_table_size__
<> 129:0ab6a29f35bf 77
<> 129:0ab6a29f35bf 78 #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
<> 129:0ab6a29f35bf 79 #define m_data_size (0x00010000 - m_interrupts_ram_size)
<> 129:0ab6a29f35bf 80
<> 129:0ab6a29f35bf 81 #define m_data_2_start 0x20000000
<> 129:0ab6a29f35bf 82 #define m_data_2_size 0x00030000
<> 129:0ab6a29f35bf 83
<> 129:0ab6a29f35bf 84 /* Sizes */
<> 129:0ab6a29f35bf 85 #if (defined(__stack_size__))
<> 129:0ab6a29f35bf 86 #define Stack_Size __stack_size__
<> 129:0ab6a29f35bf 87 #else
<> 129:0ab6a29f35bf 88 #define Stack_Size 0x0400
<> 129:0ab6a29f35bf 89 #endif
<> 129:0ab6a29f35bf 90
<> 129:0ab6a29f35bf 91 #if (defined(__heap_size__))
<> 129:0ab6a29f35bf 92 #define Heap_Size __heap_size__
<> 129:0ab6a29f35bf 93 #else
<> 129:0ab6a29f35bf 94 #define Heap_Size 0x0400
<> 129:0ab6a29f35bf 95 #endif
<> 129:0ab6a29f35bf 96
<> 129:0ab6a29f35bf 97 LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
<> 129:0ab6a29f35bf 98 VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
<> 129:0ab6a29f35bf 99 * (RESET,+FIRST)
<> 129:0ab6a29f35bf 100 }
<> 129:0ab6a29f35bf 101 ER_m_bootloader_config m_bootloader_config_start FIXED m_bootloader_config_size { ; load address = execution address
<> 129:0ab6a29f35bf 102 * (BootloaderConfig)
<> 129:0ab6a29f35bf 103 }
<> 129:0ab6a29f35bf 104 ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
<> 129:0ab6a29f35bf 105 * (FlashConfig)
<> 129:0ab6a29f35bf 106 }
<> 129:0ab6a29f35bf 107 ER_m_text m_text_start m_text_size { ; load address = execution address
<> 129:0ab6a29f35bf 108 * (InRoot$$Sections)
<> 129:0ab6a29f35bf 109 .ANY (+RO)
<> 129:0ab6a29f35bf 110 }
<> 129:0ab6a29f35bf 111
<> 129:0ab6a29f35bf 112 #if (defined(__ram_vector_table__))
<> 129:0ab6a29f35bf 113 VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
<> 129:0ab6a29f35bf 114 }
<> 129:0ab6a29f35bf 115 #else
<> 129:0ab6a29f35bf 116 VECTOR_RAM m_interrupts_start EMPTY 0 {
<> 129:0ab6a29f35bf 117 }
<> 129:0ab6a29f35bf 118 #endif
<> 129:0ab6a29f35bf 119 RW_m_data m_data_start m_data_size { ; RW data
<> 129:0ab6a29f35bf 120 .ANY (+RW +ZI)
<> 129:0ab6a29f35bf 121 }
<> 129:0ab6a29f35bf 122 RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
<> 129:0ab6a29f35bf 123 .ANY (+RW +ZI)
<> 129:0ab6a29f35bf 124 }
<> 129:0ab6a29f35bf 125 RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up
<> 129:0ab6a29f35bf 126 }
<> 129:0ab6a29f35bf 127 }