mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K66F/core_sc300.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 124:2241e3a39974 1 /**************************************************************************//**
Kojto 124:2241e3a39974 2 * @file core_sc300.h
Kojto 124:2241e3a39974 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
Kojto 124:2241e3a39974 4 * @version V4.10
Kojto 124:2241e3a39974 5 * @date 18. March 2015
Kojto 124:2241e3a39974 6 *
Kojto 124:2241e3a39974 7 * @note
Kojto 124:2241e3a39974 8 *
Kojto 124:2241e3a39974 9 ******************************************************************************/
Kojto 124:2241e3a39974 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 124:2241e3a39974 11
Kojto 124:2241e3a39974 12 All rights reserved.
Kojto 124:2241e3a39974 13 Redistribution and use in source and binary forms, with or without
Kojto 124:2241e3a39974 14 modification, are permitted provided that the following conditions are met:
Kojto 124:2241e3a39974 15 - Redistributions of source code must retain the above copyright
Kojto 124:2241e3a39974 16 notice, this list of conditions and the following disclaimer.
Kojto 124:2241e3a39974 17 - Redistributions in binary form must reproduce the above copyright
Kojto 124:2241e3a39974 18 notice, this list of conditions and the following disclaimer in the
Kojto 124:2241e3a39974 19 documentation and/or other materials provided with the distribution.
Kojto 124:2241e3a39974 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 124:2241e3a39974 21 to endorse or promote products derived from this software without
Kojto 124:2241e3a39974 22 specific prior written permission.
Kojto 124:2241e3a39974 23 *
Kojto 124:2241e3a39974 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 124:2241e3a39974 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 124:2241e3a39974 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 124:2241e3a39974 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 124:2241e3a39974 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 124:2241e3a39974 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 124:2241e3a39974 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 124:2241e3a39974 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 124:2241e3a39974 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 124:2241e3a39974 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 124:2241e3a39974 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 124:2241e3a39974 35 ---------------------------------------------------------------------------*/
Kojto 124:2241e3a39974 36
Kojto 124:2241e3a39974 37
Kojto 124:2241e3a39974 38 #if defined ( __ICCARM__ )
Kojto 124:2241e3a39974 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 124:2241e3a39974 40 #endif
Kojto 124:2241e3a39974 41
Kojto 124:2241e3a39974 42 #ifndef __CORE_SC300_H_GENERIC
Kojto 124:2241e3a39974 43 #define __CORE_SC300_H_GENERIC
Kojto 124:2241e3a39974 44
Kojto 124:2241e3a39974 45 #ifdef __cplusplus
Kojto 124:2241e3a39974 46 extern "C" {
Kojto 124:2241e3a39974 47 #endif
Kojto 124:2241e3a39974 48
Kojto 124:2241e3a39974 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 124:2241e3a39974 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 124:2241e3a39974 51
Kojto 124:2241e3a39974 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 124:2241e3a39974 53 Function definitions in header files are used to allow 'inlining'.
Kojto 124:2241e3a39974 54
Kojto 124:2241e3a39974 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 124:2241e3a39974 56 Unions are used for effective representation of core registers.
Kojto 124:2241e3a39974 57
Kojto 124:2241e3a39974 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 124:2241e3a39974 59 Function-like macros are used to allow more efficient code.
Kojto 124:2241e3a39974 60 */
Kojto 124:2241e3a39974 61
Kojto 124:2241e3a39974 62
Kojto 124:2241e3a39974 63 /*******************************************************************************
Kojto 124:2241e3a39974 64 * CMSIS definitions
Kojto 124:2241e3a39974 65 ******************************************************************************/
Kojto 124:2241e3a39974 66 /** \ingroup SC3000
Kojto 124:2241e3a39974 67 @{
Kojto 124:2241e3a39974 68 */
Kojto 124:2241e3a39974 69
Kojto 124:2241e3a39974 70 /* CMSIS SC300 definitions */
Kojto 124:2241e3a39974 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 124:2241e3a39974 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 124:2241e3a39974 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
Kojto 124:2241e3a39974 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 124:2241e3a39974 75
Kojto 124:2241e3a39974 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
Kojto 124:2241e3a39974 77
Kojto 124:2241e3a39974 78
Kojto 124:2241e3a39974 79 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 124:2241e3a39974 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 124:2241e3a39974 82 #define __STATIC_INLINE static __inline
Kojto 124:2241e3a39974 83
Kojto 124:2241e3a39974 84 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 124:2241e3a39974 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 124:2241e3a39974 87 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 88
Kojto 124:2241e3a39974 89 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 124:2241e3a39974 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 124:2241e3a39974 92 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 93
Kojto 124:2241e3a39974 94 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 124:2241e3a39974 96 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 97
Kojto 124:2241e3a39974 98 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 124:2241e3a39974 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 124:2241e3a39974 101 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 102
Kojto 124:2241e3a39974 103 #elif defined ( __CSMC__ )
Kojto 124:2241e3a39974 104 #define __packed
Kojto 124:2241e3a39974 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 107 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 108
Kojto 124:2241e3a39974 109 #endif
Kojto 124:2241e3a39974 110
Kojto 124:2241e3a39974 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 124:2241e3a39974 112 This core does not support an FPU at all
Kojto 124:2241e3a39974 113 */
Kojto 124:2241e3a39974 114 #define __FPU_USED 0
Kojto 124:2241e3a39974 115
Kojto 124:2241e3a39974 116 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 117 #if defined __TARGET_FPU_VFP
Kojto 124:2241e3a39974 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 119 #endif
Kojto 124:2241e3a39974 120
Kojto 124:2241e3a39974 121 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 124:2241e3a39974 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 124 #endif
Kojto 124:2241e3a39974 125
Kojto 124:2241e3a39974 126 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 127 #if defined __ARMVFP__
Kojto 124:2241e3a39974 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 129 #endif
Kojto 124:2241e3a39974 130
Kojto 124:2241e3a39974 131 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 132 #if defined __TI__VFP_SUPPORT____
Kojto 124:2241e3a39974 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 134 #endif
Kojto 124:2241e3a39974 135
Kojto 124:2241e3a39974 136 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 137 #if defined __FPU_VFP__
Kojto 124:2241e3a39974 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 139 #endif
Kojto 124:2241e3a39974 140
Kojto 124:2241e3a39974 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 124:2241e3a39974 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 124:2241e3a39974 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 144 #endif
Kojto 124:2241e3a39974 145 #endif
Kojto 124:2241e3a39974 146
Kojto 124:2241e3a39974 147 #include <stdint.h> /* standard types definitions */
Kojto 124:2241e3a39974 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 124:2241e3a39974 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 124:2241e3a39974 150
Kojto 124:2241e3a39974 151 #ifdef __cplusplus
Kojto 124:2241e3a39974 152 }
Kojto 124:2241e3a39974 153 #endif
Kojto 124:2241e3a39974 154
Kojto 124:2241e3a39974 155 #endif /* __CORE_SC300_H_GENERIC */
Kojto 124:2241e3a39974 156
Kojto 124:2241e3a39974 157 #ifndef __CMSIS_GENERIC
Kojto 124:2241e3a39974 158
Kojto 124:2241e3a39974 159 #ifndef __CORE_SC300_H_DEPENDANT
Kojto 124:2241e3a39974 160 #define __CORE_SC300_H_DEPENDANT
Kojto 124:2241e3a39974 161
Kojto 124:2241e3a39974 162 #ifdef __cplusplus
Kojto 124:2241e3a39974 163 extern "C" {
Kojto 124:2241e3a39974 164 #endif
Kojto 124:2241e3a39974 165
Kojto 124:2241e3a39974 166 /* check device defines and use defaults */
Kojto 124:2241e3a39974 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 124:2241e3a39974 168 #ifndef __SC300_REV
Kojto 124:2241e3a39974 169 #define __SC300_REV 0x0000
Kojto 124:2241e3a39974 170 #warning "__SC300_REV not defined in device header file; using default!"
Kojto 124:2241e3a39974 171 #endif
Kojto 124:2241e3a39974 172
Kojto 124:2241e3a39974 173 #ifndef __MPU_PRESENT
Kojto 124:2241e3a39974 174 #define __MPU_PRESENT 0
Kojto 124:2241e3a39974 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 176 #endif
Kojto 124:2241e3a39974 177
Kojto 124:2241e3a39974 178 #ifndef __NVIC_PRIO_BITS
Kojto 124:2241e3a39974 179 #define __NVIC_PRIO_BITS 4
Kojto 124:2241e3a39974 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 124:2241e3a39974 181 #endif
Kojto 124:2241e3a39974 182
Kojto 124:2241e3a39974 183 #ifndef __Vendor_SysTickConfig
Kojto 124:2241e3a39974 184 #define __Vendor_SysTickConfig 0
Kojto 124:2241e3a39974 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 124:2241e3a39974 186 #endif
Kojto 124:2241e3a39974 187 #endif
Kojto 124:2241e3a39974 188
Kojto 124:2241e3a39974 189 /* IO definitions (access restrictions to peripheral registers) */
Kojto 124:2241e3a39974 190 /**
Kojto 124:2241e3a39974 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 124:2241e3a39974 192
Kojto 124:2241e3a39974 193 <strong>IO Type Qualifiers</strong> are used
Kojto 124:2241e3a39974 194 \li to specify the access to peripheral variables.
Kojto 124:2241e3a39974 195 \li for automatic generation of peripheral register debug information.
Kojto 124:2241e3a39974 196 */
Kojto 124:2241e3a39974 197 #ifdef __cplusplus
Kojto 124:2241e3a39974 198 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 199 #else
Kojto 124:2241e3a39974 200 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 201 #endif
Kojto 124:2241e3a39974 202 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 124:2241e3a39974 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 124:2241e3a39974 204
Kojto 124:2241e3a39974 205 /*@} end of group SC300 */
Kojto 124:2241e3a39974 206
Kojto 124:2241e3a39974 207
Kojto 124:2241e3a39974 208
Kojto 124:2241e3a39974 209 /*******************************************************************************
Kojto 124:2241e3a39974 210 * Register Abstraction
Kojto 124:2241e3a39974 211 Core Register contain:
Kojto 124:2241e3a39974 212 - Core Register
Kojto 124:2241e3a39974 213 - Core NVIC Register
Kojto 124:2241e3a39974 214 - Core SCB Register
Kojto 124:2241e3a39974 215 - Core SysTick Register
Kojto 124:2241e3a39974 216 - Core Debug Register
Kojto 124:2241e3a39974 217 - Core MPU Register
Kojto 124:2241e3a39974 218 ******************************************************************************/
Kojto 124:2241e3a39974 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 124:2241e3a39974 220 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 124:2241e3a39974 221 */
Kojto 124:2241e3a39974 222
Kojto 124:2241e3a39974 223 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 224 \defgroup CMSIS_CORE Status and Control Registers
Kojto 124:2241e3a39974 225 \brief Core Register type definitions.
Kojto 124:2241e3a39974 226 @{
Kojto 124:2241e3a39974 227 */
Kojto 124:2241e3a39974 228
Kojto 124:2241e3a39974 229 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 124:2241e3a39974 230 */
Kojto 124:2241e3a39974 231 typedef union
Kojto 124:2241e3a39974 232 {
Kojto 124:2241e3a39974 233 struct
Kojto 124:2241e3a39974 234 {
Kojto 124:2241e3a39974 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 124:2241e3a39974 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 124:2241e3a39974 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 241 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 242 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 243 } APSR_Type;
Kojto 124:2241e3a39974 244
Kojto 124:2241e3a39974 245 /* APSR Register Definitions */
Kojto 124:2241e3a39974 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 124:2241e3a39974 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 124:2241e3a39974 248
Kojto 124:2241e3a39974 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 124:2241e3a39974 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 124:2241e3a39974 251
Kojto 124:2241e3a39974 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 124:2241e3a39974 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 124:2241e3a39974 254
Kojto 124:2241e3a39974 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 124:2241e3a39974 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 124:2241e3a39974 257
Kojto 124:2241e3a39974 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 124:2241e3a39974 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 124:2241e3a39974 260
Kojto 124:2241e3a39974 261
Kojto 124:2241e3a39974 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 124:2241e3a39974 263 */
Kojto 124:2241e3a39974 264 typedef union
Kojto 124:2241e3a39974 265 {
Kojto 124:2241e3a39974 266 struct
Kojto 124:2241e3a39974 267 {
Kojto 124:2241e3a39974 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 124:2241e3a39974 270 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 271 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 272 } IPSR_Type;
Kojto 124:2241e3a39974 273
Kojto 124:2241e3a39974 274 /* IPSR Register Definitions */
Kojto 124:2241e3a39974 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 124:2241e3a39974 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 124:2241e3a39974 277
Kojto 124:2241e3a39974 278
Kojto 124:2241e3a39974 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 124:2241e3a39974 280 */
Kojto 124:2241e3a39974 281 typedef union
Kojto 124:2241e3a39974 282 {
Kojto 124:2241e3a39974 283 struct
Kojto 124:2241e3a39974 284 {
Kojto 124:2241e3a39974 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 124:2241e3a39974 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 124:2241e3a39974 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 124:2241e3a39974 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 124:2241e3a39974 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 294 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 295 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 296 } xPSR_Type;
Kojto 124:2241e3a39974 297
Kojto 124:2241e3a39974 298 /* xPSR Register Definitions */
Kojto 124:2241e3a39974 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 124:2241e3a39974 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 124:2241e3a39974 301
Kojto 124:2241e3a39974 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 124:2241e3a39974 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 124:2241e3a39974 304
Kojto 124:2241e3a39974 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 124:2241e3a39974 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 124:2241e3a39974 307
Kojto 124:2241e3a39974 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 124:2241e3a39974 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 124:2241e3a39974 310
Kojto 124:2241e3a39974 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 124:2241e3a39974 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 124:2241e3a39974 313
Kojto 124:2241e3a39974 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 124:2241e3a39974 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 124:2241e3a39974 316
Kojto 124:2241e3a39974 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 124:2241e3a39974 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 124:2241e3a39974 319
Kojto 124:2241e3a39974 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 124:2241e3a39974 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 124:2241e3a39974 322
Kojto 124:2241e3a39974 323
Kojto 124:2241e3a39974 324 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 124:2241e3a39974 325 */
Kojto 124:2241e3a39974 326 typedef union
Kojto 124:2241e3a39974 327 {
Kojto 124:2241e3a39974 328 struct
Kojto 124:2241e3a39974 329 {
Kojto 124:2241e3a39974 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 124:2241e3a39974 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 124:2241e3a39974 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 124:2241e3a39974 333 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 334 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 335 } CONTROL_Type;
Kojto 124:2241e3a39974 336
Kojto 124:2241e3a39974 337 /* CONTROL Register Definitions */
Kojto 124:2241e3a39974 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 124:2241e3a39974 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 124:2241e3a39974 340
Kojto 124:2241e3a39974 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 124:2241e3a39974 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 124:2241e3a39974 343
Kojto 124:2241e3a39974 344 /*@} end of group CMSIS_CORE */
Kojto 124:2241e3a39974 345
Kojto 124:2241e3a39974 346
Kojto 124:2241e3a39974 347 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 124:2241e3a39974 349 \brief Type definitions for the NVIC Registers
Kojto 124:2241e3a39974 350 @{
Kojto 124:2241e3a39974 351 */
Kojto 124:2241e3a39974 352
Kojto 124:2241e3a39974 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 124:2241e3a39974 354 */
Kojto 124:2241e3a39974 355 typedef struct
Kojto 124:2241e3a39974 356 {
Kojto 124:2241e3a39974 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 124:2241e3a39974 358 uint32_t RESERVED0[24];
Kojto 124:2241e3a39974 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 124:2241e3a39974 360 uint32_t RSERVED1[24];
Kojto 124:2241e3a39974 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 124:2241e3a39974 362 uint32_t RESERVED2[24];
Kojto 124:2241e3a39974 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 124:2241e3a39974 364 uint32_t RESERVED3[24];
Kojto 124:2241e3a39974 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 124:2241e3a39974 366 uint32_t RESERVED4[56];
Kojto 124:2241e3a39974 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 124:2241e3a39974 368 uint32_t RESERVED5[644];
Kojto 124:2241e3a39974 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 124:2241e3a39974 370 } NVIC_Type;
Kojto 124:2241e3a39974 371
Kojto 124:2241e3a39974 372 /* Software Triggered Interrupt Register Definitions */
Kojto 124:2241e3a39974 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 124:2241e3a39974 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 124:2241e3a39974 375
Kojto 124:2241e3a39974 376 /*@} end of group CMSIS_NVIC */
Kojto 124:2241e3a39974 377
Kojto 124:2241e3a39974 378
Kojto 124:2241e3a39974 379 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 380 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 124:2241e3a39974 381 \brief Type definitions for the System Control Block Registers
Kojto 124:2241e3a39974 382 @{
Kojto 124:2241e3a39974 383 */
Kojto 124:2241e3a39974 384
Kojto 124:2241e3a39974 385 /** \brief Structure type to access the System Control Block (SCB).
Kojto 124:2241e3a39974 386 */
Kojto 124:2241e3a39974 387 typedef struct
Kojto 124:2241e3a39974 388 {
Kojto 124:2241e3a39974 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 124:2241e3a39974 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 124:2241e3a39974 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 124:2241e3a39974 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 124:2241e3a39974 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 124:2241e3a39974 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 124:2241e3a39974 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 124:2241e3a39974 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 124:2241e3a39974 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 124:2241e3a39974 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 124:2241e3a39974 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 124:2241e3a39974 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 124:2241e3a39974 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 124:2241e3a39974 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 124:2241e3a39974 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 124:2241e3a39974 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 124:2241e3a39974 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 124:2241e3a39974 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 124:2241e3a39974 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 124:2241e3a39974 408 uint32_t RESERVED0[5];
Kojto 124:2241e3a39974 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 124:2241e3a39974 410 uint32_t RESERVED1[129];
Kojto 124:2241e3a39974 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Kojto 124:2241e3a39974 412 } SCB_Type;
Kojto 124:2241e3a39974 413
Kojto 124:2241e3a39974 414 /* SCB CPUID Register Definitions */
Kojto 124:2241e3a39974 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 124:2241e3a39974 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 124:2241e3a39974 417
Kojto 124:2241e3a39974 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 124:2241e3a39974 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 124:2241e3a39974 420
Kojto 124:2241e3a39974 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 124:2241e3a39974 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 124:2241e3a39974 423
Kojto 124:2241e3a39974 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 124:2241e3a39974 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 124:2241e3a39974 426
Kojto 124:2241e3a39974 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 124:2241e3a39974 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 124:2241e3a39974 429
Kojto 124:2241e3a39974 430 /* SCB Interrupt Control State Register Definitions */
Kojto 124:2241e3a39974 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 124:2241e3a39974 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 124:2241e3a39974 433
Kojto 124:2241e3a39974 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 124:2241e3a39974 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 124:2241e3a39974 436
Kojto 124:2241e3a39974 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 124:2241e3a39974 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 124:2241e3a39974 439
Kojto 124:2241e3a39974 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 124:2241e3a39974 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 124:2241e3a39974 442
Kojto 124:2241e3a39974 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 124:2241e3a39974 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 124:2241e3a39974 445
Kojto 124:2241e3a39974 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 124:2241e3a39974 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 124:2241e3a39974 448
Kojto 124:2241e3a39974 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 124:2241e3a39974 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 124:2241e3a39974 451
Kojto 124:2241e3a39974 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 124:2241e3a39974 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 124:2241e3a39974 454
Kojto 124:2241e3a39974 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 124:2241e3a39974 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 124:2241e3a39974 457
Kojto 124:2241e3a39974 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 124:2241e3a39974 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 124:2241e3a39974 460
Kojto 124:2241e3a39974 461 /* SCB Vector Table Offset Register Definitions */
Kojto 124:2241e3a39974 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kojto 124:2241e3a39974 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 124:2241e3a39974 464
Kojto 124:2241e3a39974 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 124:2241e3a39974 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 124:2241e3a39974 467
Kojto 124:2241e3a39974 468 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 124:2241e3a39974 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 124:2241e3a39974 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 124:2241e3a39974 471
Kojto 124:2241e3a39974 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 124:2241e3a39974 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 124:2241e3a39974 474
Kojto 124:2241e3a39974 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 124:2241e3a39974 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 124:2241e3a39974 477
Kojto 124:2241e3a39974 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 124:2241e3a39974 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 124:2241e3a39974 480
Kojto 124:2241e3a39974 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 124:2241e3a39974 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 124:2241e3a39974 483
Kojto 124:2241e3a39974 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 124:2241e3a39974 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 124:2241e3a39974 486
Kojto 124:2241e3a39974 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 124:2241e3a39974 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 124:2241e3a39974 489
Kojto 124:2241e3a39974 490 /* SCB System Control Register Definitions */
Kojto 124:2241e3a39974 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 124:2241e3a39974 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 124:2241e3a39974 493
Kojto 124:2241e3a39974 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 124:2241e3a39974 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 124:2241e3a39974 496
Kojto 124:2241e3a39974 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 124:2241e3a39974 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 124:2241e3a39974 499
Kojto 124:2241e3a39974 500 /* SCB Configuration Control Register Definitions */
Kojto 124:2241e3a39974 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 124:2241e3a39974 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 124:2241e3a39974 503
Kojto 124:2241e3a39974 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 124:2241e3a39974 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 124:2241e3a39974 506
Kojto 124:2241e3a39974 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 124:2241e3a39974 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 124:2241e3a39974 509
Kojto 124:2241e3a39974 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 124:2241e3a39974 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 124:2241e3a39974 512
Kojto 124:2241e3a39974 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 124:2241e3a39974 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 124:2241e3a39974 515
Kojto 124:2241e3a39974 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 124:2241e3a39974 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 124:2241e3a39974 518
Kojto 124:2241e3a39974 519 /* SCB System Handler Control and State Register Definitions */
Kojto 124:2241e3a39974 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 124:2241e3a39974 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 124:2241e3a39974 522
Kojto 124:2241e3a39974 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 124:2241e3a39974 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 124:2241e3a39974 525
Kojto 124:2241e3a39974 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 124:2241e3a39974 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 124:2241e3a39974 528
Kojto 124:2241e3a39974 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 124:2241e3a39974 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 124:2241e3a39974 531
Kojto 124:2241e3a39974 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 124:2241e3a39974 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 124:2241e3a39974 534
Kojto 124:2241e3a39974 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 124:2241e3a39974 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 124:2241e3a39974 537
Kojto 124:2241e3a39974 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 124:2241e3a39974 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 124:2241e3a39974 540
Kojto 124:2241e3a39974 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 124:2241e3a39974 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 124:2241e3a39974 543
Kojto 124:2241e3a39974 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 124:2241e3a39974 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 124:2241e3a39974 546
Kojto 124:2241e3a39974 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 124:2241e3a39974 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 124:2241e3a39974 549
Kojto 124:2241e3a39974 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 124:2241e3a39974 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 124:2241e3a39974 552
Kojto 124:2241e3a39974 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 124:2241e3a39974 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 124:2241e3a39974 555
Kojto 124:2241e3a39974 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 124:2241e3a39974 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 124:2241e3a39974 558
Kojto 124:2241e3a39974 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 124:2241e3a39974 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 124:2241e3a39974 561
Kojto 124:2241e3a39974 562 /* SCB Configurable Fault Status Registers Definitions */
Kojto 124:2241e3a39974 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 124:2241e3a39974 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 124:2241e3a39974 565
Kojto 124:2241e3a39974 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 124:2241e3a39974 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 124:2241e3a39974 568
Kojto 124:2241e3a39974 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 124:2241e3a39974 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 124:2241e3a39974 571
Kojto 124:2241e3a39974 572 /* SCB Hard Fault Status Registers Definitions */
Kojto 124:2241e3a39974 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 124:2241e3a39974 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 124:2241e3a39974 575
Kojto 124:2241e3a39974 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 124:2241e3a39974 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 124:2241e3a39974 578
Kojto 124:2241e3a39974 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 124:2241e3a39974 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 124:2241e3a39974 581
Kojto 124:2241e3a39974 582 /* SCB Debug Fault Status Register Definitions */
Kojto 124:2241e3a39974 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 124:2241e3a39974 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 124:2241e3a39974 585
Kojto 124:2241e3a39974 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 124:2241e3a39974 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 124:2241e3a39974 588
Kojto 124:2241e3a39974 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 124:2241e3a39974 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 124:2241e3a39974 591
Kojto 124:2241e3a39974 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 124:2241e3a39974 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 124:2241e3a39974 594
Kojto 124:2241e3a39974 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 124:2241e3a39974 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 124:2241e3a39974 597
Kojto 124:2241e3a39974 598 /*@} end of group CMSIS_SCB */
Kojto 124:2241e3a39974 599
Kojto 124:2241e3a39974 600
Kojto 124:2241e3a39974 601 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 124:2241e3a39974 603 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 124:2241e3a39974 604 @{
Kojto 124:2241e3a39974 605 */
Kojto 124:2241e3a39974 606
Kojto 124:2241e3a39974 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 124:2241e3a39974 608 */
Kojto 124:2241e3a39974 609 typedef struct
Kojto 124:2241e3a39974 610 {
Kojto 124:2241e3a39974 611 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 124:2241e3a39974 613 uint32_t RESERVED1[1];
Kojto 124:2241e3a39974 614 } SCnSCB_Type;
Kojto 124:2241e3a39974 615
Kojto 124:2241e3a39974 616 /* Interrupt Controller Type Register Definitions */
Kojto 124:2241e3a39974 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 124:2241e3a39974 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 124:2241e3a39974 619
Kojto 124:2241e3a39974 620 /*@} end of group CMSIS_SCnotSCB */
Kojto 124:2241e3a39974 621
Kojto 124:2241e3a39974 622
Kojto 124:2241e3a39974 623 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 124:2241e3a39974 625 \brief Type definitions for the System Timer Registers.
Kojto 124:2241e3a39974 626 @{
Kojto 124:2241e3a39974 627 */
Kojto 124:2241e3a39974 628
Kojto 124:2241e3a39974 629 /** \brief Structure type to access the System Timer (SysTick).
Kojto 124:2241e3a39974 630 */
Kojto 124:2241e3a39974 631 typedef struct
Kojto 124:2241e3a39974 632 {
Kojto 124:2241e3a39974 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 124:2241e3a39974 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 124:2241e3a39974 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 124:2241e3a39974 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 124:2241e3a39974 637 } SysTick_Type;
Kojto 124:2241e3a39974 638
Kojto 124:2241e3a39974 639 /* SysTick Control / Status Register Definitions */
Kojto 124:2241e3a39974 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 124:2241e3a39974 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 124:2241e3a39974 642
Kojto 124:2241e3a39974 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 124:2241e3a39974 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 124:2241e3a39974 645
Kojto 124:2241e3a39974 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 124:2241e3a39974 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 124:2241e3a39974 648
Kojto 124:2241e3a39974 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 124:2241e3a39974 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 124:2241e3a39974 651
Kojto 124:2241e3a39974 652 /* SysTick Reload Register Definitions */
Kojto 124:2241e3a39974 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 124:2241e3a39974 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 124:2241e3a39974 655
Kojto 124:2241e3a39974 656 /* SysTick Current Register Definitions */
Kojto 124:2241e3a39974 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 124:2241e3a39974 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 124:2241e3a39974 659
Kojto 124:2241e3a39974 660 /* SysTick Calibration Register Definitions */
Kojto 124:2241e3a39974 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 124:2241e3a39974 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 124:2241e3a39974 663
Kojto 124:2241e3a39974 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 124:2241e3a39974 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 124:2241e3a39974 666
Kojto 124:2241e3a39974 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 124:2241e3a39974 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 124:2241e3a39974 669
Kojto 124:2241e3a39974 670 /*@} end of group CMSIS_SysTick */
Kojto 124:2241e3a39974 671
Kojto 124:2241e3a39974 672
Kojto 124:2241e3a39974 673 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 124:2241e3a39974 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 124:2241e3a39974 676 @{
Kojto 124:2241e3a39974 677 */
Kojto 124:2241e3a39974 678
Kojto 124:2241e3a39974 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 124:2241e3a39974 680 */
Kojto 124:2241e3a39974 681 typedef struct
Kojto 124:2241e3a39974 682 {
Kojto 124:2241e3a39974 683 __O union
Kojto 124:2241e3a39974 684 {
Kojto 124:2241e3a39974 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 124:2241e3a39974 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 124:2241e3a39974 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 124:2241e3a39974 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 124:2241e3a39974 689 uint32_t RESERVED0[864];
Kojto 124:2241e3a39974 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 124:2241e3a39974 691 uint32_t RESERVED1[15];
Kojto 124:2241e3a39974 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 124:2241e3a39974 693 uint32_t RESERVED2[15];
Kojto 124:2241e3a39974 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 124:2241e3a39974 695 uint32_t RESERVED3[29];
Kojto 124:2241e3a39974 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 124:2241e3a39974 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 124:2241e3a39974 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 124:2241e3a39974 699 uint32_t RESERVED4[43];
Kojto 124:2241e3a39974 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 124:2241e3a39974 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 124:2241e3a39974 702 uint32_t RESERVED5[6];
Kojto 124:2241e3a39974 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 124:2241e3a39974 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 124:2241e3a39974 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 124:2241e3a39974 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 124:2241e3a39974 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 124:2241e3a39974 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 124:2241e3a39974 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 124:2241e3a39974 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 124:2241e3a39974 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 124:2241e3a39974 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 124:2241e3a39974 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 124:2241e3a39974 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 124:2241e3a39974 715 } ITM_Type;
Kojto 124:2241e3a39974 716
Kojto 124:2241e3a39974 717 /* ITM Trace Privilege Register Definitions */
Kojto 124:2241e3a39974 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 124:2241e3a39974 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 124:2241e3a39974 720
Kojto 124:2241e3a39974 721 /* ITM Trace Control Register Definitions */
Kojto 124:2241e3a39974 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 124:2241e3a39974 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 124:2241e3a39974 724
Kojto 124:2241e3a39974 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 124:2241e3a39974 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 124:2241e3a39974 727
Kojto 124:2241e3a39974 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 124:2241e3a39974 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 124:2241e3a39974 730
Kojto 124:2241e3a39974 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 124:2241e3a39974 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 124:2241e3a39974 733
Kojto 124:2241e3a39974 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 124:2241e3a39974 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 124:2241e3a39974 736
Kojto 124:2241e3a39974 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 124:2241e3a39974 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 124:2241e3a39974 739
Kojto 124:2241e3a39974 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 124:2241e3a39974 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 124:2241e3a39974 742
Kojto 124:2241e3a39974 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 124:2241e3a39974 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 124:2241e3a39974 745
Kojto 124:2241e3a39974 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 124:2241e3a39974 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 124:2241e3a39974 748
Kojto 124:2241e3a39974 749 /* ITM Integration Write Register Definitions */
Kojto 124:2241e3a39974 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 124:2241e3a39974 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 124:2241e3a39974 752
Kojto 124:2241e3a39974 753 /* ITM Integration Read Register Definitions */
Kojto 124:2241e3a39974 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 124:2241e3a39974 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 124:2241e3a39974 756
Kojto 124:2241e3a39974 757 /* ITM Integration Mode Control Register Definitions */
Kojto 124:2241e3a39974 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 124:2241e3a39974 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 124:2241e3a39974 760
Kojto 124:2241e3a39974 761 /* ITM Lock Status Register Definitions */
Kojto 124:2241e3a39974 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 124:2241e3a39974 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 124:2241e3a39974 764
Kojto 124:2241e3a39974 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 124:2241e3a39974 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 124:2241e3a39974 767
Kojto 124:2241e3a39974 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 124:2241e3a39974 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 124:2241e3a39974 770
Kojto 124:2241e3a39974 771 /*@}*/ /* end of group CMSIS_ITM */
Kojto 124:2241e3a39974 772
Kojto 124:2241e3a39974 773
Kojto 124:2241e3a39974 774 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 124:2241e3a39974 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 124:2241e3a39974 777 @{
Kojto 124:2241e3a39974 778 */
Kojto 124:2241e3a39974 779
Kojto 124:2241e3a39974 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 124:2241e3a39974 781 */
Kojto 124:2241e3a39974 782 typedef struct
Kojto 124:2241e3a39974 783 {
Kojto 124:2241e3a39974 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 124:2241e3a39974 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 124:2241e3a39974 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 124:2241e3a39974 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 124:2241e3a39974 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 124:2241e3a39974 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 124:2241e3a39974 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 124:2241e3a39974 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 124:2241e3a39974 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 124:2241e3a39974 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 124:2241e3a39974 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 124:2241e3a39974 795 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 124:2241e3a39974 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 124:2241e3a39974 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 124:2241e3a39974 799 uint32_t RESERVED1[1];
Kojto 124:2241e3a39974 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 124:2241e3a39974 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 124:2241e3a39974 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 124:2241e3a39974 803 uint32_t RESERVED2[1];
Kojto 124:2241e3a39974 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 124:2241e3a39974 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 124:2241e3a39974 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 124:2241e3a39974 807 } DWT_Type;
Kojto 124:2241e3a39974 808
Kojto 124:2241e3a39974 809 /* DWT Control Register Definitions */
Kojto 124:2241e3a39974 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 124:2241e3a39974 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 124:2241e3a39974 812
Kojto 124:2241e3a39974 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 124:2241e3a39974 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 124:2241e3a39974 815
Kojto 124:2241e3a39974 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 124:2241e3a39974 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 124:2241e3a39974 818
Kojto 124:2241e3a39974 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 124:2241e3a39974 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 124:2241e3a39974 821
Kojto 124:2241e3a39974 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 124:2241e3a39974 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 124:2241e3a39974 824
Kojto 124:2241e3a39974 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 124:2241e3a39974 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 124:2241e3a39974 827
Kojto 124:2241e3a39974 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 124:2241e3a39974 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 124:2241e3a39974 830
Kojto 124:2241e3a39974 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 124:2241e3a39974 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 124:2241e3a39974 833
Kojto 124:2241e3a39974 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 124:2241e3a39974 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 124:2241e3a39974 836
Kojto 124:2241e3a39974 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 124:2241e3a39974 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 124:2241e3a39974 839
Kojto 124:2241e3a39974 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 124:2241e3a39974 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 124:2241e3a39974 842
Kojto 124:2241e3a39974 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 124:2241e3a39974 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 124:2241e3a39974 845
Kojto 124:2241e3a39974 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 124:2241e3a39974 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 124:2241e3a39974 848
Kojto 124:2241e3a39974 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 124:2241e3a39974 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 124:2241e3a39974 851
Kojto 124:2241e3a39974 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 124:2241e3a39974 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 124:2241e3a39974 854
Kojto 124:2241e3a39974 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 124:2241e3a39974 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 124:2241e3a39974 857
Kojto 124:2241e3a39974 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 124:2241e3a39974 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 124:2241e3a39974 860
Kojto 124:2241e3a39974 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 124:2241e3a39974 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 124:2241e3a39974 863
Kojto 124:2241e3a39974 864 /* DWT CPI Count Register Definitions */
Kojto 124:2241e3a39974 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 124:2241e3a39974 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 124:2241e3a39974 867
Kojto 124:2241e3a39974 868 /* DWT Exception Overhead Count Register Definitions */
Kojto 124:2241e3a39974 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 124:2241e3a39974 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 124:2241e3a39974 871
Kojto 124:2241e3a39974 872 /* DWT Sleep Count Register Definitions */
Kojto 124:2241e3a39974 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 124:2241e3a39974 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 124:2241e3a39974 875
Kojto 124:2241e3a39974 876 /* DWT LSU Count Register Definitions */
Kojto 124:2241e3a39974 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 124:2241e3a39974 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 124:2241e3a39974 879
Kojto 124:2241e3a39974 880 /* DWT Folded-instruction Count Register Definitions */
Kojto 124:2241e3a39974 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 124:2241e3a39974 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 124:2241e3a39974 883
Kojto 124:2241e3a39974 884 /* DWT Comparator Mask Register Definitions */
Kojto 124:2241e3a39974 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 124:2241e3a39974 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 124:2241e3a39974 887
Kojto 124:2241e3a39974 888 /* DWT Comparator Function Register Definitions */
Kojto 124:2241e3a39974 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 124:2241e3a39974 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 124:2241e3a39974 891
Kojto 124:2241e3a39974 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 124:2241e3a39974 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 124:2241e3a39974 894
Kojto 124:2241e3a39974 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 124:2241e3a39974 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 124:2241e3a39974 897
Kojto 124:2241e3a39974 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 124:2241e3a39974 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 124:2241e3a39974 900
Kojto 124:2241e3a39974 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 124:2241e3a39974 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 124:2241e3a39974 903
Kojto 124:2241e3a39974 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 124:2241e3a39974 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 124:2241e3a39974 906
Kojto 124:2241e3a39974 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 124:2241e3a39974 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 124:2241e3a39974 909
Kojto 124:2241e3a39974 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 124:2241e3a39974 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 124:2241e3a39974 912
Kojto 124:2241e3a39974 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 124:2241e3a39974 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 124:2241e3a39974 915
Kojto 124:2241e3a39974 916 /*@}*/ /* end of group CMSIS_DWT */
Kojto 124:2241e3a39974 917
Kojto 124:2241e3a39974 918
Kojto 124:2241e3a39974 919 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 124:2241e3a39974 921 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 124:2241e3a39974 922 @{
Kojto 124:2241e3a39974 923 */
Kojto 124:2241e3a39974 924
Kojto 124:2241e3a39974 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 124:2241e3a39974 926 */
Kojto 124:2241e3a39974 927 typedef struct
Kojto 124:2241e3a39974 928 {
Kojto 124:2241e3a39974 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 124:2241e3a39974 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 124:2241e3a39974 931 uint32_t RESERVED0[2];
Kojto 124:2241e3a39974 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 124:2241e3a39974 933 uint32_t RESERVED1[55];
Kojto 124:2241e3a39974 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 124:2241e3a39974 935 uint32_t RESERVED2[131];
Kojto 124:2241e3a39974 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 124:2241e3a39974 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 124:2241e3a39974 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 124:2241e3a39974 939 uint32_t RESERVED3[759];
Kojto 124:2241e3a39974 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 124:2241e3a39974 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 124:2241e3a39974 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 124:2241e3a39974 943 uint32_t RESERVED4[1];
Kojto 124:2241e3a39974 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 124:2241e3a39974 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 124:2241e3a39974 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 124:2241e3a39974 947 uint32_t RESERVED5[39];
Kojto 124:2241e3a39974 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 124:2241e3a39974 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 124:2241e3a39974 950 uint32_t RESERVED7[8];
Kojto 124:2241e3a39974 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 124:2241e3a39974 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 124:2241e3a39974 953 } TPI_Type;
Kojto 124:2241e3a39974 954
Kojto 124:2241e3a39974 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 124:2241e3a39974 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 124:2241e3a39974 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 124:2241e3a39974 958
Kojto 124:2241e3a39974 959 /* TPI Selected Pin Protocol Register Definitions */
Kojto 124:2241e3a39974 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 124:2241e3a39974 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 124:2241e3a39974 962
Kojto 124:2241e3a39974 963 /* TPI Formatter and Flush Status Register Definitions */
Kojto 124:2241e3a39974 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 124:2241e3a39974 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 124:2241e3a39974 966
Kojto 124:2241e3a39974 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 124:2241e3a39974 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 124:2241e3a39974 969
Kojto 124:2241e3a39974 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 124:2241e3a39974 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 124:2241e3a39974 972
Kojto 124:2241e3a39974 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 124:2241e3a39974 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 124:2241e3a39974 975
Kojto 124:2241e3a39974 976 /* TPI Formatter and Flush Control Register Definitions */
Kojto 124:2241e3a39974 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 124:2241e3a39974 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 124:2241e3a39974 979
Kojto 124:2241e3a39974 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 124:2241e3a39974 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 124:2241e3a39974 982
Kojto 124:2241e3a39974 983 /* TPI TRIGGER Register Definitions */
Kojto 124:2241e3a39974 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 124:2241e3a39974 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 124:2241e3a39974 986
Kojto 124:2241e3a39974 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 124:2241e3a39974 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 124:2241e3a39974 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 124:2241e3a39974 990
Kojto 124:2241e3a39974 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 124:2241e3a39974 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 124:2241e3a39974 993
Kojto 124:2241e3a39974 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 124:2241e3a39974 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 124:2241e3a39974 996
Kojto 124:2241e3a39974 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 124:2241e3a39974 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 124:2241e3a39974 999
Kojto 124:2241e3a39974 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 124:2241e3a39974 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 124:2241e3a39974 1002
Kojto 124:2241e3a39974 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 124:2241e3a39974 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 124:2241e3a39974 1005
Kojto 124:2241e3a39974 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 124:2241e3a39974 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 124:2241e3a39974 1008
Kojto 124:2241e3a39974 1009 /* TPI ITATBCTR2 Register Definitions */
Kojto 124:2241e3a39974 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 124:2241e3a39974 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 124:2241e3a39974 1012
Kojto 124:2241e3a39974 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 124:2241e3a39974 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 124:2241e3a39974 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 124:2241e3a39974 1016
Kojto 124:2241e3a39974 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 124:2241e3a39974 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 124:2241e3a39974 1019
Kojto 124:2241e3a39974 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 124:2241e3a39974 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 124:2241e3a39974 1022
Kojto 124:2241e3a39974 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 124:2241e3a39974 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 124:2241e3a39974 1025
Kojto 124:2241e3a39974 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 124:2241e3a39974 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 124:2241e3a39974 1028
Kojto 124:2241e3a39974 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 124:2241e3a39974 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 124:2241e3a39974 1031
Kojto 124:2241e3a39974 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 124:2241e3a39974 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 124:2241e3a39974 1034
Kojto 124:2241e3a39974 1035 /* TPI ITATBCTR0 Register Definitions */
Kojto 124:2241e3a39974 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 124:2241e3a39974 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 124:2241e3a39974 1038
Kojto 124:2241e3a39974 1039 /* TPI Integration Mode Control Register Definitions */
Kojto 124:2241e3a39974 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 124:2241e3a39974 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 124:2241e3a39974 1042
Kojto 124:2241e3a39974 1043 /* TPI DEVID Register Definitions */
Kojto 124:2241e3a39974 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 124:2241e3a39974 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 124:2241e3a39974 1046
Kojto 124:2241e3a39974 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 124:2241e3a39974 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 124:2241e3a39974 1049
Kojto 124:2241e3a39974 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 124:2241e3a39974 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 124:2241e3a39974 1052
Kojto 124:2241e3a39974 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 124:2241e3a39974 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 124:2241e3a39974 1055
Kojto 124:2241e3a39974 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 124:2241e3a39974 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 124:2241e3a39974 1058
Kojto 124:2241e3a39974 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 124:2241e3a39974 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 124:2241e3a39974 1061
Kojto 124:2241e3a39974 1062 /* TPI DEVTYPE Register Definitions */
Kojto 124:2241e3a39974 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 124:2241e3a39974 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 124:2241e3a39974 1065
Kojto 124:2241e3a39974 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 124:2241e3a39974 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 124:2241e3a39974 1068
Kojto 124:2241e3a39974 1069 /*@}*/ /* end of group CMSIS_TPI */
Kojto 124:2241e3a39974 1070
Kojto 124:2241e3a39974 1071
Kojto 124:2241e3a39974 1072 #if (__MPU_PRESENT == 1)
Kojto 124:2241e3a39974 1073 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 124:2241e3a39974 1075 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 124:2241e3a39974 1076 @{
Kojto 124:2241e3a39974 1077 */
Kojto 124:2241e3a39974 1078
Kojto 124:2241e3a39974 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 124:2241e3a39974 1080 */
Kojto 124:2241e3a39974 1081 typedef struct
Kojto 124:2241e3a39974 1082 {
Kojto 124:2241e3a39974 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 124:2241e3a39974 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 124:2241e3a39974 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 124:2241e3a39974 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 124:2241e3a39974 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 124:2241e3a39974 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 124:2241e3a39974 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 124:2241e3a39974 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 124:2241e3a39974 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1094 } MPU_Type;
Kojto 124:2241e3a39974 1095
Kojto 124:2241e3a39974 1096 /* MPU Type Register */
Kojto 124:2241e3a39974 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 124:2241e3a39974 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 124:2241e3a39974 1099
Kojto 124:2241e3a39974 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 124:2241e3a39974 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 124:2241e3a39974 1102
Kojto 124:2241e3a39974 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 124:2241e3a39974 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 124:2241e3a39974 1105
Kojto 124:2241e3a39974 1106 /* MPU Control Register */
Kojto 124:2241e3a39974 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 124:2241e3a39974 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 124:2241e3a39974 1109
Kojto 124:2241e3a39974 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 124:2241e3a39974 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 124:2241e3a39974 1112
Kojto 124:2241e3a39974 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 124:2241e3a39974 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 124:2241e3a39974 1115
Kojto 124:2241e3a39974 1116 /* MPU Region Number Register */
Kojto 124:2241e3a39974 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 124:2241e3a39974 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 124:2241e3a39974 1119
Kojto 124:2241e3a39974 1120 /* MPU Region Base Address Register */
Kojto 124:2241e3a39974 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 124:2241e3a39974 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 124:2241e3a39974 1123
Kojto 124:2241e3a39974 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 124:2241e3a39974 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 124:2241e3a39974 1126
Kojto 124:2241e3a39974 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 124:2241e3a39974 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 124:2241e3a39974 1129
Kojto 124:2241e3a39974 1130 /* MPU Region Attribute and Size Register */
Kojto 124:2241e3a39974 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 124:2241e3a39974 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 124:2241e3a39974 1133
Kojto 124:2241e3a39974 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 124:2241e3a39974 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 124:2241e3a39974 1136
Kojto 124:2241e3a39974 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 124:2241e3a39974 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 124:2241e3a39974 1139
Kojto 124:2241e3a39974 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 124:2241e3a39974 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 124:2241e3a39974 1142
Kojto 124:2241e3a39974 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 124:2241e3a39974 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 124:2241e3a39974 1145
Kojto 124:2241e3a39974 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 124:2241e3a39974 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 124:2241e3a39974 1148
Kojto 124:2241e3a39974 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 124:2241e3a39974 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 124:2241e3a39974 1151
Kojto 124:2241e3a39974 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 124:2241e3a39974 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 124:2241e3a39974 1154
Kojto 124:2241e3a39974 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 124:2241e3a39974 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 124:2241e3a39974 1157
Kojto 124:2241e3a39974 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 124:2241e3a39974 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 124:2241e3a39974 1160
Kojto 124:2241e3a39974 1161 /*@} end of group CMSIS_MPU */
Kojto 124:2241e3a39974 1162 #endif
Kojto 124:2241e3a39974 1163
Kojto 124:2241e3a39974 1164
Kojto 124:2241e3a39974 1165 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 124:2241e3a39974 1167 \brief Type definitions for the Core Debug Registers
Kojto 124:2241e3a39974 1168 @{
Kojto 124:2241e3a39974 1169 */
Kojto 124:2241e3a39974 1170
Kojto 124:2241e3a39974 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 124:2241e3a39974 1172 */
Kojto 124:2241e3a39974 1173 typedef struct
Kojto 124:2241e3a39974 1174 {
Kojto 124:2241e3a39974 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 124:2241e3a39974 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 124:2241e3a39974 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 124:2241e3a39974 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 124:2241e3a39974 1179 } CoreDebug_Type;
Kojto 124:2241e3a39974 1180
Kojto 124:2241e3a39974 1181 /* Debug Halting Control and Status Register */
Kojto 124:2241e3a39974 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 124:2241e3a39974 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 124:2241e3a39974 1184
Kojto 124:2241e3a39974 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 124:2241e3a39974 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 124:2241e3a39974 1187
Kojto 124:2241e3a39974 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 124:2241e3a39974 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 124:2241e3a39974 1190
Kojto 124:2241e3a39974 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 124:2241e3a39974 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 124:2241e3a39974 1193
Kojto 124:2241e3a39974 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 124:2241e3a39974 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 124:2241e3a39974 1196
Kojto 124:2241e3a39974 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 124:2241e3a39974 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 124:2241e3a39974 1199
Kojto 124:2241e3a39974 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 124:2241e3a39974 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 124:2241e3a39974 1202
Kojto 124:2241e3a39974 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 124:2241e3a39974 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 124:2241e3a39974 1205
Kojto 124:2241e3a39974 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 124:2241e3a39974 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 124:2241e3a39974 1208
Kojto 124:2241e3a39974 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 124:2241e3a39974 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 124:2241e3a39974 1211
Kojto 124:2241e3a39974 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 124:2241e3a39974 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 124:2241e3a39974 1214
Kojto 124:2241e3a39974 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 124:2241e3a39974 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 124:2241e3a39974 1217
Kojto 124:2241e3a39974 1218 /* Debug Core Register Selector Register */
Kojto 124:2241e3a39974 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 124:2241e3a39974 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 124:2241e3a39974 1221
Kojto 124:2241e3a39974 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 124:2241e3a39974 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 124:2241e3a39974 1224
Kojto 124:2241e3a39974 1225 /* Debug Exception and Monitor Control Register */
Kojto 124:2241e3a39974 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 124:2241e3a39974 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 124:2241e3a39974 1228
Kojto 124:2241e3a39974 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 124:2241e3a39974 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 124:2241e3a39974 1231
Kojto 124:2241e3a39974 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 124:2241e3a39974 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 124:2241e3a39974 1234
Kojto 124:2241e3a39974 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 124:2241e3a39974 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 124:2241e3a39974 1237
Kojto 124:2241e3a39974 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 124:2241e3a39974 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 124:2241e3a39974 1240
Kojto 124:2241e3a39974 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 124:2241e3a39974 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 124:2241e3a39974 1243
Kojto 124:2241e3a39974 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 124:2241e3a39974 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 124:2241e3a39974 1246
Kojto 124:2241e3a39974 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 124:2241e3a39974 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 124:2241e3a39974 1249
Kojto 124:2241e3a39974 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 124:2241e3a39974 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 124:2241e3a39974 1252
Kojto 124:2241e3a39974 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 124:2241e3a39974 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 124:2241e3a39974 1255
Kojto 124:2241e3a39974 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 124:2241e3a39974 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 124:2241e3a39974 1258
Kojto 124:2241e3a39974 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 124:2241e3a39974 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 124:2241e3a39974 1261
Kojto 124:2241e3a39974 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 124:2241e3a39974 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 124:2241e3a39974 1264
Kojto 124:2241e3a39974 1265 /*@} end of group CMSIS_CoreDebug */
Kojto 124:2241e3a39974 1266
Kojto 124:2241e3a39974 1267
Kojto 124:2241e3a39974 1268 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1269 \defgroup CMSIS_core_base Core Definitions
Kojto 124:2241e3a39974 1270 \brief Definitions for base addresses, unions, and structures.
Kojto 124:2241e3a39974 1271 @{
Kojto 124:2241e3a39974 1272 */
Kojto 124:2241e3a39974 1273
Kojto 124:2241e3a39974 1274 /* Memory mapping of Cortex-M3 Hardware */
Kojto 124:2241e3a39974 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 124:2241e3a39974 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 124:2241e3a39974 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 124:2241e3a39974 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 124:2241e3a39974 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 124:2241e3a39974 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 124:2241e3a39974 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 124:2241e3a39974 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 124:2241e3a39974 1283
Kojto 124:2241e3a39974 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 124:2241e3a39974 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 124:2241e3a39974 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 124:2241e3a39974 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 124:2241e3a39974 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 124:2241e3a39974 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 124:2241e3a39974 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 124:2241e3a39974 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 124:2241e3a39974 1292
Kojto 124:2241e3a39974 1293 #if (__MPU_PRESENT == 1)
Kojto 124:2241e3a39974 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 124:2241e3a39974 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 124:2241e3a39974 1296 #endif
Kojto 124:2241e3a39974 1297
Kojto 124:2241e3a39974 1298 /*@} */
Kojto 124:2241e3a39974 1299
Kojto 124:2241e3a39974 1300
Kojto 124:2241e3a39974 1301
Kojto 124:2241e3a39974 1302 /*******************************************************************************
Kojto 124:2241e3a39974 1303 * Hardware Abstraction Layer
Kojto 124:2241e3a39974 1304 Core Function Interface contains:
Kojto 124:2241e3a39974 1305 - Core NVIC Functions
Kojto 124:2241e3a39974 1306 - Core SysTick Functions
Kojto 124:2241e3a39974 1307 - Core Debug Functions
Kojto 124:2241e3a39974 1308 - Core Register Access Functions
Kojto 124:2241e3a39974 1309 ******************************************************************************/
Kojto 124:2241e3a39974 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 124:2241e3a39974 1311 */
Kojto 124:2241e3a39974 1312
Kojto 124:2241e3a39974 1313
Kojto 124:2241e3a39974 1314
Kojto 124:2241e3a39974 1315 /* ########################## NVIC functions #################################### */
Kojto 124:2241e3a39974 1316 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 124:2241e3a39974 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 124:2241e3a39974 1319 @{
Kojto 124:2241e3a39974 1320 */
Kojto 124:2241e3a39974 1321
Kojto 124:2241e3a39974 1322 /** \brief Set Priority Grouping
Kojto 124:2241e3a39974 1323
Kojto 124:2241e3a39974 1324 The function sets the priority grouping field using the required unlock sequence.
Kojto 124:2241e3a39974 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 124:2241e3a39974 1326 Only values from 0..7 are used.
Kojto 124:2241e3a39974 1327 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 124:2241e3a39974 1329
Kojto 124:2241e3a39974 1330 \param [in] PriorityGroup Priority grouping field.
Kojto 124:2241e3a39974 1331 */
Kojto 124:2241e3a39974 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 124:2241e3a39974 1333 {
Kojto 124:2241e3a39974 1334 uint32_t reg_value;
Kojto 124:2241e3a39974 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1336
Kojto 124:2241e3a39974 1337 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 124:2241e3a39974 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 124:2241e3a39974 1339 reg_value = (reg_value |
Kojto 124:2241e3a39974 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 124:2241e3a39974 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 124:2241e3a39974 1342 SCB->AIRCR = reg_value;
Kojto 124:2241e3a39974 1343 }
Kojto 124:2241e3a39974 1344
Kojto 124:2241e3a39974 1345
Kojto 124:2241e3a39974 1346 /** \brief Get Priority Grouping
Kojto 124:2241e3a39974 1347
Kojto 124:2241e3a39974 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 124:2241e3a39974 1349
Kojto 124:2241e3a39974 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 124:2241e3a39974 1351 */
Kojto 124:2241e3a39974 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 124:2241e3a39974 1353 {
Kojto 124:2241e3a39974 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 124:2241e3a39974 1355 }
Kojto 124:2241e3a39974 1356
Kojto 124:2241e3a39974 1357
Kojto 124:2241e3a39974 1358 /** \brief Enable External Interrupt
Kojto 124:2241e3a39974 1359
Kojto 124:2241e3a39974 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 1361
Kojto 124:2241e3a39974 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1363 */
Kojto 124:2241e3a39974 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1365 {
Kojto 124:2241e3a39974 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1367 }
Kojto 124:2241e3a39974 1368
Kojto 124:2241e3a39974 1369
Kojto 124:2241e3a39974 1370 /** \brief Disable External Interrupt
Kojto 124:2241e3a39974 1371
Kojto 124:2241e3a39974 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 1373
Kojto 124:2241e3a39974 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1375 */
Kojto 124:2241e3a39974 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1377 {
Kojto 124:2241e3a39974 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1379 __DSB();
<> 131:faff56e089b2 1380 __ISB();
Kojto 124:2241e3a39974 1381 }
Kojto 124:2241e3a39974 1382
Kojto 124:2241e3a39974 1383
Kojto 124:2241e3a39974 1384 /** \brief Get Pending Interrupt
Kojto 124:2241e3a39974 1385
Kojto 124:2241e3a39974 1386 The function reads the pending register in the NVIC and returns the pending bit
Kojto 124:2241e3a39974 1387 for the specified interrupt.
Kojto 124:2241e3a39974 1388
Kojto 124:2241e3a39974 1389 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1390
Kojto 124:2241e3a39974 1391 \return 0 Interrupt status is not pending.
Kojto 124:2241e3a39974 1392 \return 1 Interrupt status is pending.
Kojto 124:2241e3a39974 1393 */
Kojto 124:2241e3a39974 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1395 {
Kojto 124:2241e3a39974 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 124:2241e3a39974 1397 }
Kojto 124:2241e3a39974 1398
Kojto 124:2241e3a39974 1399
Kojto 124:2241e3a39974 1400 /** \brief Set Pending Interrupt
Kojto 124:2241e3a39974 1401
Kojto 124:2241e3a39974 1402 The function sets the pending bit of an external interrupt.
Kojto 124:2241e3a39974 1403
Kojto 124:2241e3a39974 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1405 */
Kojto 124:2241e3a39974 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1407 {
Kojto 124:2241e3a39974 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1409 }
Kojto 124:2241e3a39974 1410
Kojto 124:2241e3a39974 1411
Kojto 124:2241e3a39974 1412 /** \brief Clear Pending Interrupt
Kojto 124:2241e3a39974 1413
Kojto 124:2241e3a39974 1414 The function clears the pending bit of an external interrupt.
Kojto 124:2241e3a39974 1415
Kojto 124:2241e3a39974 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1417 */
Kojto 124:2241e3a39974 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1419 {
Kojto 124:2241e3a39974 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1421 }
Kojto 124:2241e3a39974 1422
Kojto 124:2241e3a39974 1423
Kojto 124:2241e3a39974 1424 /** \brief Get Active Interrupt
Kojto 124:2241e3a39974 1425
Kojto 124:2241e3a39974 1426 The function reads the active register in NVIC and returns the active bit.
Kojto 124:2241e3a39974 1427
Kojto 124:2241e3a39974 1428 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1429
Kojto 124:2241e3a39974 1430 \return 0 Interrupt status is not active.
Kojto 124:2241e3a39974 1431 \return 1 Interrupt status is active.
Kojto 124:2241e3a39974 1432 */
Kojto 124:2241e3a39974 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1434 {
Kojto 124:2241e3a39974 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 124:2241e3a39974 1436 }
Kojto 124:2241e3a39974 1437
Kojto 124:2241e3a39974 1438
Kojto 124:2241e3a39974 1439 /** \brief Set Interrupt Priority
Kojto 124:2241e3a39974 1440
Kojto 124:2241e3a39974 1441 The function sets the priority of an interrupt.
Kojto 124:2241e3a39974 1442
Kojto 124:2241e3a39974 1443 \note The priority cannot be set for every core interrupt.
Kojto 124:2241e3a39974 1444
Kojto 124:2241e3a39974 1445 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1446 \param [in] priority Priority to set.
Kojto 124:2241e3a39974 1447 */
Kojto 124:2241e3a39974 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 124:2241e3a39974 1449 {
Kojto 124:2241e3a39974 1450 if((int32_t)IRQn < 0) {
Kojto 124:2241e3a39974 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 124:2241e3a39974 1452 }
Kojto 124:2241e3a39974 1453 else {
Kojto 124:2241e3a39974 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 124:2241e3a39974 1455 }
Kojto 124:2241e3a39974 1456 }
Kojto 124:2241e3a39974 1457
Kojto 124:2241e3a39974 1458
Kojto 124:2241e3a39974 1459 /** \brief Get Interrupt Priority
Kojto 124:2241e3a39974 1460
Kojto 124:2241e3a39974 1461 The function reads the priority of an interrupt. The interrupt
Kojto 124:2241e3a39974 1462 number can be positive to specify an external (device specific)
Kojto 124:2241e3a39974 1463 interrupt, or negative to specify an internal (core) interrupt.
Kojto 124:2241e3a39974 1464
Kojto 124:2241e3a39974 1465
Kojto 124:2241e3a39974 1466 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 124:2241e3a39974 1468 priority bits of the microcontroller.
Kojto 124:2241e3a39974 1469 */
Kojto 124:2241e3a39974 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1471 {
Kojto 124:2241e3a39974 1472
Kojto 124:2241e3a39974 1473 if((int32_t)IRQn < 0) {
Kojto 124:2241e3a39974 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 1475 }
Kojto 124:2241e3a39974 1476 else {
Kojto 124:2241e3a39974 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 1478 }
Kojto 124:2241e3a39974 1479 }
Kojto 124:2241e3a39974 1480
Kojto 124:2241e3a39974 1481
Kojto 124:2241e3a39974 1482 /** \brief Encode Priority
Kojto 124:2241e3a39974 1483
Kojto 124:2241e3a39974 1484 The function encodes the priority for an interrupt with the given priority group,
Kojto 124:2241e3a39974 1485 preemptive priority value, and subpriority value.
Kojto 124:2241e3a39974 1486 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 124:2241e3a39974 1488
Kojto 124:2241e3a39974 1489 \param [in] PriorityGroup Used priority group.
Kojto 124:2241e3a39974 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 124:2241e3a39974 1491 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 124:2241e3a39974 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 124:2241e3a39974 1493 */
Kojto 124:2241e3a39974 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 124:2241e3a39974 1495 {
Kojto 124:2241e3a39974 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1497 uint32_t PreemptPriorityBits;
Kojto 124:2241e3a39974 1498 uint32_t SubPriorityBits;
Kojto 124:2241e3a39974 1499
Kojto 124:2241e3a39974 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 124:2241e3a39974 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 124:2241e3a39974 1502
Kojto 124:2241e3a39974 1503 return (
Kojto 124:2241e3a39974 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 124:2241e3a39974 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 124:2241e3a39974 1506 );
Kojto 124:2241e3a39974 1507 }
Kojto 124:2241e3a39974 1508
Kojto 124:2241e3a39974 1509
Kojto 124:2241e3a39974 1510 /** \brief Decode Priority
Kojto 124:2241e3a39974 1511
Kojto 124:2241e3a39974 1512 The function decodes an interrupt priority value with a given priority group to
Kojto 124:2241e3a39974 1513 preemptive priority value and subpriority value.
Kojto 124:2241e3a39974 1514 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 124:2241e3a39974 1516
Kojto 124:2241e3a39974 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 124:2241e3a39974 1518 \param [in] PriorityGroup Used priority group.
Kojto 124:2241e3a39974 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 124:2241e3a39974 1520 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 124:2241e3a39974 1521 */
Kojto 124:2241e3a39974 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 124:2241e3a39974 1523 {
Kojto 124:2241e3a39974 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1525 uint32_t PreemptPriorityBits;
Kojto 124:2241e3a39974 1526 uint32_t SubPriorityBits;
Kojto 124:2241e3a39974 1527
Kojto 124:2241e3a39974 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 124:2241e3a39974 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 124:2241e3a39974 1530
Kojto 124:2241e3a39974 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 124:2241e3a39974 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 124:2241e3a39974 1533 }
Kojto 124:2241e3a39974 1534
Kojto 124:2241e3a39974 1535
Kojto 124:2241e3a39974 1536 /** \brief System Reset
Kojto 124:2241e3a39974 1537
Kojto 124:2241e3a39974 1538 The function initiates a system reset request to reset the MCU.
Kojto 124:2241e3a39974 1539 */
Kojto 124:2241e3a39974 1540 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 124:2241e3a39974 1541 {
Kojto 124:2241e3a39974 1542 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 124:2241e3a39974 1543 buffered write are completed before reset */
Kojto 124:2241e3a39974 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 124:2241e3a39974 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 124:2241e3a39974 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 124:2241e3a39974 1547 __DSB(); /* Ensure completion of memory access */
Kojto 124:2241e3a39974 1548 while(1) { __NOP(); } /* wait until reset */
Kojto 124:2241e3a39974 1549 }
Kojto 124:2241e3a39974 1550
Kojto 124:2241e3a39974 1551 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 124:2241e3a39974 1552
Kojto 124:2241e3a39974 1553
Kojto 124:2241e3a39974 1554
Kojto 124:2241e3a39974 1555 /* ################################## SysTick function ############################################ */
Kojto 124:2241e3a39974 1556 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 124:2241e3a39974 1558 \brief Functions that configure the System.
Kojto 124:2241e3a39974 1559 @{
Kojto 124:2241e3a39974 1560 */
Kojto 124:2241e3a39974 1561
Kojto 124:2241e3a39974 1562 #if (__Vendor_SysTickConfig == 0)
Kojto 124:2241e3a39974 1563
Kojto 124:2241e3a39974 1564 /** \brief System Tick Configuration
Kojto 124:2241e3a39974 1565
Kojto 124:2241e3a39974 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 124:2241e3a39974 1567 Counter is in free running mode to generate periodic interrupts.
Kojto 124:2241e3a39974 1568
Kojto 124:2241e3a39974 1569 \param [in] ticks Number of ticks between two interrupts.
Kojto 124:2241e3a39974 1570
Kojto 124:2241e3a39974 1571 \return 0 Function succeeded.
Kojto 124:2241e3a39974 1572 \return 1 Function failed.
Kojto 124:2241e3a39974 1573
Kojto 124:2241e3a39974 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 124:2241e3a39974 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 124:2241e3a39974 1576 must contain a vendor-specific implementation of this function.
Kojto 124:2241e3a39974 1577
Kojto 124:2241e3a39974 1578 */
Kojto 124:2241e3a39974 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 124:2241e3a39974 1580 {
Kojto 124:2241e3a39974 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 124:2241e3a39974 1582
Kojto 124:2241e3a39974 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 124:2241e3a39974 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 124:2241e3a39974 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 124:2241e3a39974 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 124:2241e3a39974 1587 SysTick_CTRL_TICKINT_Msk |
Kojto 124:2241e3a39974 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 124:2241e3a39974 1589 return (0UL); /* Function successful */
Kojto 124:2241e3a39974 1590 }
Kojto 124:2241e3a39974 1591
Kojto 124:2241e3a39974 1592 #endif
Kojto 124:2241e3a39974 1593
Kojto 124:2241e3a39974 1594 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 124:2241e3a39974 1595
Kojto 124:2241e3a39974 1596
Kojto 124:2241e3a39974 1597
Kojto 124:2241e3a39974 1598 /* ##################################### Debug In/Output function ########################################### */
Kojto 124:2241e3a39974 1599 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 124:2241e3a39974 1601 \brief Functions that access the ITM debug interface.
Kojto 124:2241e3a39974 1602 @{
Kojto 124:2241e3a39974 1603 */
Kojto 124:2241e3a39974 1604
Kojto 124:2241e3a39974 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 124:2241e3a39974 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 124:2241e3a39974 1607
Kojto 124:2241e3a39974 1608
Kojto 124:2241e3a39974 1609 /** \brief ITM Send Character
Kojto 124:2241e3a39974 1610
Kojto 124:2241e3a39974 1611 The function transmits a character via the ITM channel 0, and
Kojto 124:2241e3a39974 1612 \li Just returns when no debugger is connected that has booked the output.
Kojto 124:2241e3a39974 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 124:2241e3a39974 1614
Kojto 124:2241e3a39974 1615 \param [in] ch Character to transmit.
Kojto 124:2241e3a39974 1616
Kojto 124:2241e3a39974 1617 \returns Character to transmit.
Kojto 124:2241e3a39974 1618 */
Kojto 124:2241e3a39974 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 124:2241e3a39974 1620 {
Kojto 124:2241e3a39974 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 124:2241e3a39974 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 124:2241e3a39974 1623 {
Kojto 124:2241e3a39974 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 124:2241e3a39974 1625 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 124:2241e3a39974 1626 }
Kojto 124:2241e3a39974 1627 return (ch);
Kojto 124:2241e3a39974 1628 }
Kojto 124:2241e3a39974 1629
Kojto 124:2241e3a39974 1630
Kojto 124:2241e3a39974 1631 /** \brief ITM Receive Character
Kojto 124:2241e3a39974 1632
Kojto 124:2241e3a39974 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 124:2241e3a39974 1634
Kojto 124:2241e3a39974 1635 \return Received character.
Kojto 124:2241e3a39974 1636 \return -1 No character pending.
Kojto 124:2241e3a39974 1637 */
Kojto 124:2241e3a39974 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 124:2241e3a39974 1639 int32_t ch = -1; /* no character available */
Kojto 124:2241e3a39974 1640
Kojto 124:2241e3a39974 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 124:2241e3a39974 1642 ch = ITM_RxBuffer;
Kojto 124:2241e3a39974 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 124:2241e3a39974 1644 }
Kojto 124:2241e3a39974 1645
Kojto 124:2241e3a39974 1646 return (ch);
Kojto 124:2241e3a39974 1647 }
Kojto 124:2241e3a39974 1648
Kojto 124:2241e3a39974 1649
Kojto 124:2241e3a39974 1650 /** \brief ITM Check Character
Kojto 124:2241e3a39974 1651
Kojto 124:2241e3a39974 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 124:2241e3a39974 1653
Kojto 124:2241e3a39974 1654 \return 0 No character available.
Kojto 124:2241e3a39974 1655 \return 1 Character available.
Kojto 124:2241e3a39974 1656 */
Kojto 124:2241e3a39974 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 124:2241e3a39974 1658
Kojto 124:2241e3a39974 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 124:2241e3a39974 1660 return (0); /* no character available */
Kojto 124:2241e3a39974 1661 } else {
Kojto 124:2241e3a39974 1662 return (1); /* character available */
Kojto 124:2241e3a39974 1663 }
Kojto 124:2241e3a39974 1664 }
Kojto 124:2241e3a39974 1665
Kojto 124:2241e3a39974 1666 /*@} end of CMSIS_core_DebugFunctions */
Kojto 124:2241e3a39974 1667
Kojto 124:2241e3a39974 1668
Kojto 124:2241e3a39974 1669
Kojto 124:2241e3a39974 1670
Kojto 124:2241e3a39974 1671 #ifdef __cplusplus
Kojto 124:2241e3a39974 1672 }
Kojto 124:2241e3a39974 1673 #endif
Kojto 124:2241e3a39974 1674
Kojto 124:2241e3a39974 1675 #endif /* __CORE_SC300_H_DEPENDANT */
Kojto 124:2241e3a39974 1676
Kojto 124:2241e3a39974 1677 #endif /* __CMSIS_GENERIC */