mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K66F/core_cm0.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 124:2241e3a39974 1 /**************************************************************************//**
Kojto 124:2241e3a39974 2 * @file core_cm0.h
Kojto 124:2241e3a39974 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 124:2241e3a39974 4 * @version V4.10
Kojto 124:2241e3a39974 5 * @date 18. March 2015
Kojto 124:2241e3a39974 6 *
Kojto 124:2241e3a39974 7 * @note
Kojto 124:2241e3a39974 8 *
Kojto 124:2241e3a39974 9 ******************************************************************************/
Kojto 124:2241e3a39974 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 124:2241e3a39974 11
Kojto 124:2241e3a39974 12 All rights reserved.
Kojto 124:2241e3a39974 13 Redistribution and use in source and binary forms, with or without
Kojto 124:2241e3a39974 14 modification, are permitted provided that the following conditions are met:
Kojto 124:2241e3a39974 15 - Redistributions of source code must retain the above copyright
Kojto 124:2241e3a39974 16 notice, this list of conditions and the following disclaimer.
Kojto 124:2241e3a39974 17 - Redistributions in binary form must reproduce the above copyright
Kojto 124:2241e3a39974 18 notice, this list of conditions and the following disclaimer in the
Kojto 124:2241e3a39974 19 documentation and/or other materials provided with the distribution.
Kojto 124:2241e3a39974 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 124:2241e3a39974 21 to endorse or promote products derived from this software without
Kojto 124:2241e3a39974 22 specific prior written permission.
Kojto 124:2241e3a39974 23 *
Kojto 124:2241e3a39974 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 124:2241e3a39974 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 124:2241e3a39974 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 124:2241e3a39974 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 124:2241e3a39974 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 124:2241e3a39974 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 124:2241e3a39974 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 124:2241e3a39974 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 124:2241e3a39974 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 124:2241e3a39974 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 124:2241e3a39974 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 124:2241e3a39974 35 ---------------------------------------------------------------------------*/
Kojto 124:2241e3a39974 36
Kojto 124:2241e3a39974 37
Kojto 124:2241e3a39974 38 #if defined ( __ICCARM__ )
Kojto 124:2241e3a39974 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 124:2241e3a39974 40 #endif
Kojto 124:2241e3a39974 41
Kojto 124:2241e3a39974 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 124:2241e3a39974 43 #define __CORE_CM0_H_GENERIC
Kojto 124:2241e3a39974 44
Kojto 124:2241e3a39974 45 #ifdef __cplusplus
Kojto 124:2241e3a39974 46 extern "C" {
Kojto 124:2241e3a39974 47 #endif
Kojto 124:2241e3a39974 48
Kojto 124:2241e3a39974 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 124:2241e3a39974 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 124:2241e3a39974 51
Kojto 124:2241e3a39974 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 124:2241e3a39974 53 Function definitions in header files are used to allow 'inlining'.
Kojto 124:2241e3a39974 54
Kojto 124:2241e3a39974 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 124:2241e3a39974 56 Unions are used for effective representation of core registers.
Kojto 124:2241e3a39974 57
Kojto 124:2241e3a39974 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 124:2241e3a39974 59 Function-like macros are used to allow more efficient code.
Kojto 124:2241e3a39974 60 */
Kojto 124:2241e3a39974 61
Kojto 124:2241e3a39974 62
Kojto 124:2241e3a39974 63 /*******************************************************************************
Kojto 124:2241e3a39974 64 * CMSIS definitions
Kojto 124:2241e3a39974 65 ******************************************************************************/
Kojto 124:2241e3a39974 66 /** \ingroup Cortex_M0
Kojto 124:2241e3a39974 67 @{
Kojto 124:2241e3a39974 68 */
Kojto 124:2241e3a39974 69
Kojto 124:2241e3a39974 70 /* CMSIS CM0 definitions */
Kojto 124:2241e3a39974 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 124:2241e3a39974 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 124:2241e3a39974 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 124:2241e3a39974 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 124:2241e3a39974 75
Kojto 124:2241e3a39974 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 124:2241e3a39974 77
Kojto 124:2241e3a39974 78
Kojto 124:2241e3a39974 79 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 124:2241e3a39974 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 124:2241e3a39974 82 #define __STATIC_INLINE static __inline
Kojto 124:2241e3a39974 83
Kojto 124:2241e3a39974 84 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 124:2241e3a39974 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 124:2241e3a39974 87 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 88
Kojto 124:2241e3a39974 89 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 124:2241e3a39974 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 124:2241e3a39974 92 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 93
Kojto 124:2241e3a39974 94 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 124:2241e3a39974 96 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 97
Kojto 124:2241e3a39974 98 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 124:2241e3a39974 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 124:2241e3a39974 101 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 102
Kojto 124:2241e3a39974 103 #elif defined ( __CSMC__ )
Kojto 124:2241e3a39974 104 #define __packed
Kojto 124:2241e3a39974 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 107 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 108
Kojto 124:2241e3a39974 109 #endif
Kojto 124:2241e3a39974 110
Kojto 124:2241e3a39974 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 124:2241e3a39974 112 This core does not support an FPU at all
Kojto 124:2241e3a39974 113 */
Kojto 124:2241e3a39974 114 #define __FPU_USED 0
Kojto 124:2241e3a39974 115
Kojto 124:2241e3a39974 116 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 117 #if defined __TARGET_FPU_VFP
Kojto 124:2241e3a39974 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 119 #endif
Kojto 124:2241e3a39974 120
Kojto 124:2241e3a39974 121 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 124:2241e3a39974 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 124 #endif
Kojto 124:2241e3a39974 125
Kojto 124:2241e3a39974 126 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 127 #if defined __ARMVFP__
Kojto 124:2241e3a39974 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 129 #endif
Kojto 124:2241e3a39974 130
Kojto 124:2241e3a39974 131 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 132 #if defined __TI__VFP_SUPPORT____
Kojto 124:2241e3a39974 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 134 #endif
Kojto 124:2241e3a39974 135
Kojto 124:2241e3a39974 136 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 137 #if defined __FPU_VFP__
Kojto 124:2241e3a39974 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 139 #endif
Kojto 124:2241e3a39974 140
Kojto 124:2241e3a39974 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 124:2241e3a39974 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 124:2241e3a39974 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 144 #endif
Kojto 124:2241e3a39974 145 #endif
Kojto 124:2241e3a39974 146
Kojto 124:2241e3a39974 147 #include <stdint.h> /* standard types definitions */
Kojto 124:2241e3a39974 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 124:2241e3a39974 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 124:2241e3a39974 150
Kojto 124:2241e3a39974 151 #ifdef __cplusplus
Kojto 124:2241e3a39974 152 }
Kojto 124:2241e3a39974 153 #endif
Kojto 124:2241e3a39974 154
Kojto 124:2241e3a39974 155 #endif /* __CORE_CM0_H_GENERIC */
Kojto 124:2241e3a39974 156
Kojto 124:2241e3a39974 157 #ifndef __CMSIS_GENERIC
Kojto 124:2241e3a39974 158
Kojto 124:2241e3a39974 159 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 124:2241e3a39974 160 #define __CORE_CM0_H_DEPENDANT
Kojto 124:2241e3a39974 161
Kojto 124:2241e3a39974 162 #ifdef __cplusplus
Kojto 124:2241e3a39974 163 extern "C" {
Kojto 124:2241e3a39974 164 #endif
Kojto 124:2241e3a39974 165
Kojto 124:2241e3a39974 166 /* check device defines and use defaults */
Kojto 124:2241e3a39974 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 124:2241e3a39974 168 #ifndef __CM0_REV
Kojto 124:2241e3a39974 169 #define __CM0_REV 0x0000
Kojto 124:2241e3a39974 170 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 124:2241e3a39974 171 #endif
Kojto 124:2241e3a39974 172
Kojto 124:2241e3a39974 173 #ifndef __NVIC_PRIO_BITS
Kojto 124:2241e3a39974 174 #define __NVIC_PRIO_BITS 2
Kojto 124:2241e3a39974 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 124:2241e3a39974 176 #endif
Kojto 124:2241e3a39974 177
Kojto 124:2241e3a39974 178 #ifndef __Vendor_SysTickConfig
Kojto 124:2241e3a39974 179 #define __Vendor_SysTickConfig 0
Kojto 124:2241e3a39974 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 124:2241e3a39974 181 #endif
Kojto 124:2241e3a39974 182 #endif
Kojto 124:2241e3a39974 183
Kojto 124:2241e3a39974 184 /* IO definitions (access restrictions to peripheral registers) */
Kojto 124:2241e3a39974 185 /**
Kojto 124:2241e3a39974 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 124:2241e3a39974 187
Kojto 124:2241e3a39974 188 <strong>IO Type Qualifiers</strong> are used
Kojto 124:2241e3a39974 189 \li to specify the access to peripheral variables.
Kojto 124:2241e3a39974 190 \li for automatic generation of peripheral register debug information.
Kojto 124:2241e3a39974 191 */
Kojto 124:2241e3a39974 192 #ifdef __cplusplus
Kojto 124:2241e3a39974 193 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 194 #else
Kojto 124:2241e3a39974 195 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 196 #endif
Kojto 124:2241e3a39974 197 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 124:2241e3a39974 198 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 124:2241e3a39974 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
Kojto 124:2241e3a39974 208 /*@} end of group Cortex_M0 */
Kojto 124:2241e3a39974 209
Kojto 124:2241e3a39974 210
Kojto 124:2241e3a39974 211
Kojto 124:2241e3a39974 212 /*******************************************************************************
Kojto 124:2241e3a39974 213 * Register Abstraction
Kojto 124:2241e3a39974 214 Core Register contain:
Kojto 124:2241e3a39974 215 - Core Register
Kojto 124:2241e3a39974 216 - Core NVIC Register
Kojto 124:2241e3a39974 217 - Core SCB Register
Kojto 124:2241e3a39974 218 - Core SysTick Register
Kojto 124:2241e3a39974 219 ******************************************************************************/
Kojto 124:2241e3a39974 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 124:2241e3a39974 221 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 124:2241e3a39974 222 */
Kojto 124:2241e3a39974 223
Kojto 124:2241e3a39974 224 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 225 \defgroup CMSIS_CORE Status and Control Registers
Kojto 124:2241e3a39974 226 \brief Core Register type definitions.
Kojto 124:2241e3a39974 227 @{
Kojto 124:2241e3a39974 228 */
Kojto 124:2241e3a39974 229
Kojto 124:2241e3a39974 230 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 124:2241e3a39974 231 */
Kojto 124:2241e3a39974 232 typedef union
Kojto 124:2241e3a39974 233 {
Kojto 124:2241e3a39974 234 struct
Kojto 124:2241e3a39974 235 {
Kojto 124:2241e3a39974 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 124:2241e3a39974 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 241 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 242 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 243 } APSR_Type;
Kojto 124:2241e3a39974 244
Kojto 124:2241e3a39974 245 /* APSR Register Definitions */
Kojto 124:2241e3a39974 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 124:2241e3a39974 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 124:2241e3a39974 248
Kojto 124:2241e3a39974 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 124:2241e3a39974 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 124:2241e3a39974 251
Kojto 124:2241e3a39974 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 124:2241e3a39974 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 124:2241e3a39974 254
Kojto 124:2241e3a39974 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 124:2241e3a39974 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 124:2241e3a39974 257
Kojto 124:2241e3a39974 258
Kojto 124:2241e3a39974 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 124:2241e3a39974 260 */
Kojto 124:2241e3a39974 261 typedef union
Kojto 124:2241e3a39974 262 {
Kojto 124:2241e3a39974 263 struct
Kojto 124:2241e3a39974 264 {
Kojto 124:2241e3a39974 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 124:2241e3a39974 267 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 268 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 269 } IPSR_Type;
Kojto 124:2241e3a39974 270
Kojto 124:2241e3a39974 271 /* IPSR Register Definitions */
Kojto 124:2241e3a39974 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 124:2241e3a39974 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 124:2241e3a39974 274
Kojto 124:2241e3a39974 275
Kojto 124:2241e3a39974 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 124:2241e3a39974 277 */
Kojto 124:2241e3a39974 278 typedef union
Kojto 124:2241e3a39974 279 {
Kojto 124:2241e3a39974 280 struct
Kojto 124:2241e3a39974 281 {
Kojto 124:2241e3a39974 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 124:2241e3a39974 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 124:2241e3a39974 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 124:2241e3a39974 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 290 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 291 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 292 } xPSR_Type;
Kojto 124:2241e3a39974 293
Kojto 124:2241e3a39974 294 /* xPSR Register Definitions */
Kojto 124:2241e3a39974 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 124:2241e3a39974 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 124:2241e3a39974 297
Kojto 124:2241e3a39974 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 124:2241e3a39974 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 124:2241e3a39974 300
Kojto 124:2241e3a39974 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 124:2241e3a39974 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 124:2241e3a39974 303
Kojto 124:2241e3a39974 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 124:2241e3a39974 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 124:2241e3a39974 306
Kojto 124:2241e3a39974 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 124:2241e3a39974 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 124:2241e3a39974 309
Kojto 124:2241e3a39974 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 124:2241e3a39974 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 124:2241e3a39974 312
Kojto 124:2241e3a39974 313
Kojto 124:2241e3a39974 314 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 124:2241e3a39974 315 */
Kojto 124:2241e3a39974 316 typedef union
Kojto 124:2241e3a39974 317 {
Kojto 124:2241e3a39974 318 struct
Kojto 124:2241e3a39974 319 {
Kojto 124:2241e3a39974 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 124:2241e3a39974 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 124:2241e3a39974 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 124:2241e3a39974 323 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 324 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 325 } CONTROL_Type;
Kojto 124:2241e3a39974 326
Kojto 124:2241e3a39974 327 /* CONTROL Register Definitions */
Kojto 124:2241e3a39974 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 124:2241e3a39974 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 124:2241e3a39974 330
Kojto 124:2241e3a39974 331 /*@} end of group CMSIS_CORE */
Kojto 124:2241e3a39974 332
Kojto 124:2241e3a39974 333
Kojto 124:2241e3a39974 334 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 124:2241e3a39974 336 \brief Type definitions for the NVIC Registers
Kojto 124:2241e3a39974 337 @{
Kojto 124:2241e3a39974 338 */
Kojto 124:2241e3a39974 339
Kojto 124:2241e3a39974 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 124:2241e3a39974 341 */
Kojto 124:2241e3a39974 342 typedef struct
Kojto 124:2241e3a39974 343 {
Kojto 124:2241e3a39974 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 124:2241e3a39974 345 uint32_t RESERVED0[31];
Kojto 124:2241e3a39974 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 124:2241e3a39974 347 uint32_t RSERVED1[31];
Kojto 124:2241e3a39974 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 124:2241e3a39974 349 uint32_t RESERVED2[31];
Kojto 124:2241e3a39974 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 124:2241e3a39974 351 uint32_t RESERVED3[31];
Kojto 124:2241e3a39974 352 uint32_t RESERVED4[64];
Kojto 124:2241e3a39974 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 124:2241e3a39974 354 } NVIC_Type;
Kojto 124:2241e3a39974 355
Kojto 124:2241e3a39974 356 /*@} end of group CMSIS_NVIC */
Kojto 124:2241e3a39974 357
Kojto 124:2241e3a39974 358
Kojto 124:2241e3a39974 359 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 360 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 124:2241e3a39974 361 \brief Type definitions for the System Control Block Registers
Kojto 124:2241e3a39974 362 @{
Kojto 124:2241e3a39974 363 */
Kojto 124:2241e3a39974 364
Kojto 124:2241e3a39974 365 /** \brief Structure type to access the System Control Block (SCB).
Kojto 124:2241e3a39974 366 */
Kojto 124:2241e3a39974 367 typedef struct
Kojto 124:2241e3a39974 368 {
Kojto 124:2241e3a39974 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 124:2241e3a39974 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 124:2241e3a39974 371 uint32_t RESERVED0;
Kojto 124:2241e3a39974 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 124:2241e3a39974 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 124:2241e3a39974 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 124:2241e3a39974 375 uint32_t RESERVED1;
Kojto 124:2241e3a39974 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 124:2241e3a39974 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 124:2241e3a39974 378 } SCB_Type;
Kojto 124:2241e3a39974 379
Kojto 124:2241e3a39974 380 /* SCB CPUID Register Definitions */
Kojto 124:2241e3a39974 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 124:2241e3a39974 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 124:2241e3a39974 383
Kojto 124:2241e3a39974 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 124:2241e3a39974 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 124:2241e3a39974 386
Kojto 124:2241e3a39974 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 124:2241e3a39974 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 124:2241e3a39974 389
Kojto 124:2241e3a39974 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 124:2241e3a39974 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 124:2241e3a39974 392
Kojto 124:2241e3a39974 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 124:2241e3a39974 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 124:2241e3a39974 395
Kojto 124:2241e3a39974 396 /* SCB Interrupt Control State Register Definitions */
Kojto 124:2241e3a39974 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 124:2241e3a39974 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 124:2241e3a39974 399
Kojto 124:2241e3a39974 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 124:2241e3a39974 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 124:2241e3a39974 402
Kojto 124:2241e3a39974 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 124:2241e3a39974 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 124:2241e3a39974 405
Kojto 124:2241e3a39974 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 124:2241e3a39974 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 124:2241e3a39974 408
Kojto 124:2241e3a39974 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 124:2241e3a39974 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 124:2241e3a39974 411
Kojto 124:2241e3a39974 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 124:2241e3a39974 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 124:2241e3a39974 414
Kojto 124:2241e3a39974 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 124:2241e3a39974 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 124:2241e3a39974 417
Kojto 124:2241e3a39974 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 124:2241e3a39974 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 124:2241e3a39974 420
Kojto 124:2241e3a39974 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 124:2241e3a39974 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 124:2241e3a39974 423
Kojto 124:2241e3a39974 424 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 124:2241e3a39974 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 124:2241e3a39974 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 124:2241e3a39974 427
Kojto 124:2241e3a39974 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 124:2241e3a39974 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 124:2241e3a39974 430
Kojto 124:2241e3a39974 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 124:2241e3a39974 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 124:2241e3a39974 433
Kojto 124:2241e3a39974 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 124:2241e3a39974 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 124:2241e3a39974 436
Kojto 124:2241e3a39974 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 124:2241e3a39974 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 124:2241e3a39974 439
Kojto 124:2241e3a39974 440 /* SCB System Control Register Definitions */
Kojto 124:2241e3a39974 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 124:2241e3a39974 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 124:2241e3a39974 443
Kojto 124:2241e3a39974 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 124:2241e3a39974 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 124:2241e3a39974 446
Kojto 124:2241e3a39974 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 124:2241e3a39974 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 124:2241e3a39974 449
Kojto 124:2241e3a39974 450 /* SCB Configuration Control Register Definitions */
Kojto 124:2241e3a39974 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 124:2241e3a39974 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 124:2241e3a39974 453
Kojto 124:2241e3a39974 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 124:2241e3a39974 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 124:2241e3a39974 456
Kojto 124:2241e3a39974 457 /* SCB System Handler Control and State Register Definitions */
Kojto 124:2241e3a39974 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 124:2241e3a39974 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 124:2241e3a39974 460
Kojto 124:2241e3a39974 461 /*@} end of group CMSIS_SCB */
Kojto 124:2241e3a39974 462
Kojto 124:2241e3a39974 463
Kojto 124:2241e3a39974 464 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 124:2241e3a39974 466 \brief Type definitions for the System Timer Registers.
Kojto 124:2241e3a39974 467 @{
Kojto 124:2241e3a39974 468 */
Kojto 124:2241e3a39974 469
Kojto 124:2241e3a39974 470 /** \brief Structure type to access the System Timer (SysTick).
Kojto 124:2241e3a39974 471 */
Kojto 124:2241e3a39974 472 typedef struct
Kojto 124:2241e3a39974 473 {
Kojto 124:2241e3a39974 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 124:2241e3a39974 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 124:2241e3a39974 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 124:2241e3a39974 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 124:2241e3a39974 478 } SysTick_Type;
Kojto 124:2241e3a39974 479
Kojto 124:2241e3a39974 480 /* SysTick Control / Status Register Definitions */
Kojto 124:2241e3a39974 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 124:2241e3a39974 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 124:2241e3a39974 483
Kojto 124:2241e3a39974 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 124:2241e3a39974 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 124:2241e3a39974 486
Kojto 124:2241e3a39974 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 124:2241e3a39974 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 124:2241e3a39974 489
Kojto 124:2241e3a39974 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 124:2241e3a39974 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 124:2241e3a39974 492
Kojto 124:2241e3a39974 493 /* SysTick Reload Register Definitions */
Kojto 124:2241e3a39974 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 124:2241e3a39974 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 124:2241e3a39974 496
Kojto 124:2241e3a39974 497 /* SysTick Current Register Definitions */
Kojto 124:2241e3a39974 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 124:2241e3a39974 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 124:2241e3a39974 500
Kojto 124:2241e3a39974 501 /* SysTick Calibration Register Definitions */
Kojto 124:2241e3a39974 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 124:2241e3a39974 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 124:2241e3a39974 504
Kojto 124:2241e3a39974 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 124:2241e3a39974 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 124:2241e3a39974 507
Kojto 124:2241e3a39974 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 124:2241e3a39974 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 124:2241e3a39974 510
Kojto 124:2241e3a39974 511 /*@} end of group CMSIS_SysTick */
Kojto 124:2241e3a39974 512
Kojto 124:2241e3a39974 513
Kojto 124:2241e3a39974 514 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 124:2241e3a39974 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 124:2241e3a39974 517 are only accessible over DAP and not via processor. Therefore
Kojto 124:2241e3a39974 518 they are not covered by the Cortex-M0 header file.
Kojto 124:2241e3a39974 519 @{
Kojto 124:2241e3a39974 520 */
Kojto 124:2241e3a39974 521 /*@} end of group CMSIS_CoreDebug */
Kojto 124:2241e3a39974 522
Kojto 124:2241e3a39974 523
Kojto 124:2241e3a39974 524 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 525 \defgroup CMSIS_core_base Core Definitions
Kojto 124:2241e3a39974 526 \brief Definitions for base addresses, unions, and structures.
Kojto 124:2241e3a39974 527 @{
Kojto 124:2241e3a39974 528 */
Kojto 124:2241e3a39974 529
Kojto 124:2241e3a39974 530 /* Memory mapping of Cortex-M0 Hardware */
Kojto 124:2241e3a39974 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 124:2241e3a39974 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 124:2241e3a39974 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 124:2241e3a39974 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 124:2241e3a39974 535
Kojto 124:2241e3a39974 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 124:2241e3a39974 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 124:2241e3a39974 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 124:2241e3a39974 539
Kojto 124:2241e3a39974 540
Kojto 124:2241e3a39974 541 /*@} */
Kojto 124:2241e3a39974 542
Kojto 124:2241e3a39974 543
Kojto 124:2241e3a39974 544
Kojto 124:2241e3a39974 545 /*******************************************************************************
Kojto 124:2241e3a39974 546 * Hardware Abstraction Layer
Kojto 124:2241e3a39974 547 Core Function Interface contains:
Kojto 124:2241e3a39974 548 - Core NVIC Functions
Kojto 124:2241e3a39974 549 - Core SysTick Functions
Kojto 124:2241e3a39974 550 - Core Register Access Functions
Kojto 124:2241e3a39974 551 ******************************************************************************/
Kojto 124:2241e3a39974 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 124:2241e3a39974 553 */
Kojto 124:2241e3a39974 554
Kojto 124:2241e3a39974 555
Kojto 124:2241e3a39974 556
Kojto 124:2241e3a39974 557 /* ########################## NVIC functions #################################### */
Kojto 124:2241e3a39974 558 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 124:2241e3a39974 560 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 124:2241e3a39974 561 @{
Kojto 124:2241e3a39974 562 */
Kojto 124:2241e3a39974 563
Kojto 124:2241e3a39974 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 124:2241e3a39974 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 124:2241e3a39974 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 124:2241e3a39974 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 124:2241e3a39974 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 124:2241e3a39974 569
Kojto 124:2241e3a39974 570
Kojto 124:2241e3a39974 571 /** \brief Enable External Interrupt
Kojto 124:2241e3a39974 572
Kojto 124:2241e3a39974 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 574
Kojto 124:2241e3a39974 575 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 576 */
Kojto 124:2241e3a39974 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 578 {
Kojto 124:2241e3a39974 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 580 }
Kojto 124:2241e3a39974 581
Kojto 124:2241e3a39974 582
Kojto 124:2241e3a39974 583 /** \brief Disable External Interrupt
Kojto 124:2241e3a39974 584
Kojto 124:2241e3a39974 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 586
Kojto 124:2241e3a39974 587 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 588 */
Kojto 124:2241e3a39974 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 590 {
Kojto 124:2241e3a39974 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
Kojto 124:2241e3a39974 594 }
Kojto 124:2241e3a39974 595
Kojto 124:2241e3a39974 596
Kojto 124:2241e3a39974 597 /** \brief Get Pending Interrupt
Kojto 124:2241e3a39974 598
Kojto 124:2241e3a39974 599 The function reads the pending register in the NVIC and returns the pending bit
Kojto 124:2241e3a39974 600 for the specified interrupt.
Kojto 124:2241e3a39974 601
Kojto 124:2241e3a39974 602 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 603
Kojto 124:2241e3a39974 604 \return 0 Interrupt status is not pending.
Kojto 124:2241e3a39974 605 \return 1 Interrupt status is pending.
Kojto 124:2241e3a39974 606 */
Kojto 124:2241e3a39974 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 608 {
Kojto 124:2241e3a39974 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 124:2241e3a39974 610 }
Kojto 124:2241e3a39974 611
Kojto 124:2241e3a39974 612
Kojto 124:2241e3a39974 613 /** \brief Set Pending Interrupt
Kojto 124:2241e3a39974 614
Kojto 124:2241e3a39974 615 The function sets the pending bit of an external interrupt.
Kojto 124:2241e3a39974 616
Kojto 124:2241e3a39974 617 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 618 */
Kojto 124:2241e3a39974 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 620 {
Kojto 124:2241e3a39974 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 622 }
Kojto 124:2241e3a39974 623
Kojto 124:2241e3a39974 624
Kojto 124:2241e3a39974 625 /** \brief Clear Pending Interrupt
Kojto 124:2241e3a39974 626
Kojto 124:2241e3a39974 627 The function clears the pending bit of an external interrupt.
Kojto 124:2241e3a39974 628
Kojto 124:2241e3a39974 629 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 630 */
Kojto 124:2241e3a39974 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 632 {
Kojto 124:2241e3a39974 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 634 }
Kojto 124:2241e3a39974 635
Kojto 124:2241e3a39974 636
Kojto 124:2241e3a39974 637 /** \brief Set Interrupt Priority
Kojto 124:2241e3a39974 638
Kojto 124:2241e3a39974 639 The function sets the priority of an interrupt.
Kojto 124:2241e3a39974 640
Kojto 124:2241e3a39974 641 \note The priority cannot be set for every core interrupt.
Kojto 124:2241e3a39974 642
Kojto 124:2241e3a39974 643 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 644 \param [in] priority Priority to set.
Kojto 124:2241e3a39974 645 */
Kojto 124:2241e3a39974 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 124:2241e3a39974 647 {
Kojto 124:2241e3a39974 648 if((int32_t)(IRQn) < 0) {
Kojto 124:2241e3a39974 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 124:2241e3a39974 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 124:2241e3a39974 651 }
Kojto 124:2241e3a39974 652 else {
Kojto 124:2241e3a39974 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 124:2241e3a39974 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 124:2241e3a39974 655 }
Kojto 124:2241e3a39974 656 }
Kojto 124:2241e3a39974 657
Kojto 124:2241e3a39974 658
Kojto 124:2241e3a39974 659 /** \brief Get Interrupt Priority
Kojto 124:2241e3a39974 660
Kojto 124:2241e3a39974 661 The function reads the priority of an interrupt. The interrupt
Kojto 124:2241e3a39974 662 number can be positive to specify an external (device specific)
Kojto 124:2241e3a39974 663 interrupt, or negative to specify an internal (core) interrupt.
Kojto 124:2241e3a39974 664
Kojto 124:2241e3a39974 665
Kojto 124:2241e3a39974 666 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 667 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 124:2241e3a39974 668 priority bits of the microcontroller.
Kojto 124:2241e3a39974 669 */
Kojto 124:2241e3a39974 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 124:2241e3a39974 671 {
Kojto 124:2241e3a39974 672
Kojto 124:2241e3a39974 673 if((int32_t)(IRQn) < 0) {
Kojto 124:2241e3a39974 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 675 }
Kojto 124:2241e3a39974 676 else {
Kojto 124:2241e3a39974 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 678 }
Kojto 124:2241e3a39974 679 }
Kojto 124:2241e3a39974 680
Kojto 124:2241e3a39974 681
Kojto 124:2241e3a39974 682 /** \brief System Reset
Kojto 124:2241e3a39974 683
Kojto 124:2241e3a39974 684 The function initiates a system reset request to reset the MCU.
Kojto 124:2241e3a39974 685 */
Kojto 124:2241e3a39974 686 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 124:2241e3a39974 687 {
Kojto 124:2241e3a39974 688 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 124:2241e3a39974 689 buffered write are completed before reset */
Kojto 124:2241e3a39974 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 124:2241e3a39974 691 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 124:2241e3a39974 692 __DSB(); /* Ensure completion of memory access */
Kojto 124:2241e3a39974 693 while(1) { __NOP(); } /* wait until reset */
Kojto 124:2241e3a39974 694 }
Kojto 124:2241e3a39974 695
Kojto 124:2241e3a39974 696 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 124:2241e3a39974 697
Kojto 124:2241e3a39974 698
Kojto 124:2241e3a39974 699
Kojto 124:2241e3a39974 700 /* ################################## SysTick function ############################################ */
Kojto 124:2241e3a39974 701 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 124:2241e3a39974 703 \brief Functions that configure the System.
Kojto 124:2241e3a39974 704 @{
Kojto 124:2241e3a39974 705 */
Kojto 124:2241e3a39974 706
Kojto 124:2241e3a39974 707 #if (__Vendor_SysTickConfig == 0)
Kojto 124:2241e3a39974 708
Kojto 124:2241e3a39974 709 /** \brief System Tick Configuration
Kojto 124:2241e3a39974 710
Kojto 124:2241e3a39974 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 124:2241e3a39974 712 Counter is in free running mode to generate periodic interrupts.
Kojto 124:2241e3a39974 713
Kojto 124:2241e3a39974 714 \param [in] ticks Number of ticks between two interrupts.
Kojto 124:2241e3a39974 715
Kojto 124:2241e3a39974 716 \return 0 Function succeeded.
Kojto 124:2241e3a39974 717 \return 1 Function failed.
Kojto 124:2241e3a39974 718
Kojto 124:2241e3a39974 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 124:2241e3a39974 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 124:2241e3a39974 721 must contain a vendor-specific implementation of this function.
Kojto 124:2241e3a39974 722
Kojto 124:2241e3a39974 723 */
Kojto 124:2241e3a39974 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 124:2241e3a39974 725 {
Kojto 124:2241e3a39974 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 124:2241e3a39974 727
Kojto 124:2241e3a39974 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 124:2241e3a39974 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 124:2241e3a39974 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 124:2241e3a39974 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 124:2241e3a39974 732 SysTick_CTRL_TICKINT_Msk |
Kojto 124:2241e3a39974 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 124:2241e3a39974 734 return (0UL); /* Function successful */
Kojto 124:2241e3a39974 735 }
Kojto 124:2241e3a39974 736
Kojto 124:2241e3a39974 737 #endif
Kojto 124:2241e3a39974 738
Kojto 124:2241e3a39974 739 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 124:2241e3a39974 740
Kojto 124:2241e3a39974 741
Kojto 124:2241e3a39974 742
Kojto 124:2241e3a39974 743
Kojto 124:2241e3a39974 744 #ifdef __cplusplus
Kojto 124:2241e3a39974 745 }
Kojto 124:2241e3a39974 746 #endif
Kojto 124:2241e3a39974 747
Kojto 124:2241e3a39974 748 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 124:2241e3a39974 749
Kojto 124:2241e3a39974 750 #endif /* __CMSIS_GENERIC */