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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_BEETLE_SOC/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
122:f9eeca106725 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /* mbed Microcontroller Library
Kojto 122:f9eeca106725 2 * Copyright (c) 2015 ARM Limited
Kojto 122:f9eeca106725 3 *
Kojto 122:f9eeca106725 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 122:f9eeca106725 5 * you may not use this file except in compliance with the License.
Kojto 122:f9eeca106725 6 * You may obtain a copy of the License at
Kojto 122:f9eeca106725 7 *
Kojto 122:f9eeca106725 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 122:f9eeca106725 9 *
Kojto 122:f9eeca106725 10 * Unless required by applicable law or agreed to in writing, software
Kojto 122:f9eeca106725 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 122:f9eeca106725 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 122:f9eeca106725 13 * See the License for the specific language governing permissions and
Kojto 122:f9eeca106725 14 * limitations under the License.
Kojto 122:f9eeca106725 15 */
Kojto 122:f9eeca106725 16 /*
Kojto 122:f9eeca106725 17 * SSP interface Support
Kojto 122:f9eeca106725 18 * =====================
Kojto 122:f9eeca106725 19 */
Kojto 122:f9eeca106725 20
Kojto 122:f9eeca106725 21 #ifndef MBED_SPI_DEF_H
Kojto 122:f9eeca106725 22 #define MBED_SPI_DEF_H
Kojto 122:f9eeca106725 23
Kojto 122:f9eeca106725 24 #include <stdint.h> /* standard types definitions */
Kojto 122:f9eeca106725 25
Kojto 122:f9eeca106725 26 #define Module_ID 0x00090108
Kojto 122:f9eeca106725 27
Kojto 122:f9eeca106725 28 typedef struct beetle_spi
Kojto 122:f9eeca106725 29 {
Kojto 122:f9eeca106725 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
Kojto 122:f9eeca106725 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
Kojto 122:f9eeca106725 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
Kojto 122:f9eeca106725 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
Kojto 122:f9eeca106725 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
Kojto 122:f9eeca106725 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
Kojto 122:f9eeca106725 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
Kojto 122:f9eeca106725 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
Kojto 122:f9eeca106725 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
Kojto 122:f9eeca106725 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
Kojto 122:f9eeca106725 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
Kojto 122:f9eeca106725 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
Kojto 122:f9eeca106725 42 uint32_t reserved[208];
Kojto 122:f9eeca106725 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
Kojto 122:f9eeca106725 44 }SPI_TypeDef;
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46
Kojto 122:f9eeca106725 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
Kojto 122:f9eeca106725 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
Kojto 122:f9eeca106725 49
Kojto 122:f9eeca106725 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
Kojto 122:f9eeca106725 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /* Configuration Register Bit Masks */
Kojto 122:f9eeca106725 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
Kojto 122:f9eeca106725 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
Kojto 122:f9eeca106725 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
Kojto 122:f9eeca106725 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
Kojto 122:f9eeca106725 58 #define CONFIG_MBRD_0 0x00008
Kojto 122:f9eeca106725 59 #define CONFIG_MBRD_1 0x00010
Kojto 122:f9eeca106725 60 #define CONFIG_MBRD_2 0x00020
Kojto 122:f9eeca106725 61 #define CONFIG_MBRD_SHIFT 3
Kojto 122:f9eeca106725 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
Kojto 122:f9eeca106725 63 #define CONFIG_TWS_0 0x00000
Kojto 122:f9eeca106725 64 #define CONFIG_TWS_1 0x00040
Kojto 122:f9eeca106725 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
Kojto 122:f9eeca106725 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
Kojto 122:f9eeca106725 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
Kojto 122:f9eeca106725 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
Kojto 122:f9eeca106725 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
Kojto 122:f9eeca106725 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
Kojto 122:f9eeca106725 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
Kojto 122:f9eeca106725 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
Kojto 122:f9eeca106725 73
Kojto 122:f9eeca106725 74 /* Interrupt Status Register Bit Masks */
Kojto 122:f9eeca106725 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
Kojto 122:f9eeca106725 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
Kojto 122:f9eeca106725 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
Kojto 122:f9eeca106725 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
Kojto 122:f9eeca106725 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
Kojto 122:f9eeca106725 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
Kojto 122:f9eeca106725 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
Kojto 122:f9eeca106725 82
Kojto 122:f9eeca106725 83 /* Interrupt Enable Register Bit Masks */
Kojto 122:f9eeca106725 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
Kojto 122:f9eeca106725 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
Kojto 122:f9eeca106725 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
Kojto 122:f9eeca106725 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
Kojto 122:f9eeca106725 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
Kojto 122:f9eeca106725 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
Kojto 122:f9eeca106725 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
Kojto 122:f9eeca106725 91
Kojto 122:f9eeca106725 92 /* Interrupt Disable Register Bit Masks */
Kojto 122:f9eeca106725 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
Kojto 122:f9eeca106725 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
Kojto 122:f9eeca106725 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
Kojto 122:f9eeca106725 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
Kojto 122:f9eeca106725 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
Kojto 122:f9eeca106725 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
Kojto 122:f9eeca106725 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
Kojto 122:f9eeca106725 100
Kojto 122:f9eeca106725 101 /* Interrupt Mask Register Bit Masks */
Kojto 122:f9eeca106725 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
Kojto 122:f9eeca106725 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
Kojto 122:f9eeca106725 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
Kojto 122:f9eeca106725 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
Kojto 122:f9eeca106725 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
Kojto 122:f9eeca106725 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
Kojto 122:f9eeca106725 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
Kojto 122:f9eeca106725 109
Kojto 122:f9eeca106725 110 /* SPI Enable Register Bit Masks */
Kojto 122:f9eeca106725 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
Kojto 122:f9eeca106725 112
Kojto 122:f9eeca106725 113 /* Delay Register Bit Masks */
Kojto 122:f9eeca106725 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
Kojto 122:f9eeca106725 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
Kojto 122:f9eeca106725 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
Kojto 122:f9eeca106725 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
Kojto 122:f9eeca106725 118
Kojto 122:f9eeca106725 119 /* Transmit Data Register Bit Masks */
Kojto 122:f9eeca106725 120 #define TX_DATA_TDATA 0xFF
Kojto 122:f9eeca106725 121
Kojto 122:f9eeca106725 122 /* Receive Data Register Bit Masks */
Kojto 122:f9eeca106725 123 #define RX_DATA_RDATA 0xFF
Kojto 122:f9eeca106725 124
Kojto 122:f9eeca106725 125 /* Slave Idle Count Register Bit Masks */
Kojto 122:f9eeca106725 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
Kojto 122:f9eeca106725 127
Kojto 122:f9eeca106725 128 /* TX Threshold Register Bit Masks */
Kojto 122:f9eeca106725 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 /* RX Threshold Register Bit Masks */
Kojto 122:f9eeca106725 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
Kojto 122:f9eeca106725 133
Kojto 122:f9eeca106725 134 #endif