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TARGET_TB_SENSE_12/core_sc000.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file core_sc000.h
Anna Bridge 142:4eea097334d6 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 142:4eea097334d6 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 142:4eea097334d6 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
Anna Bridge 142:4eea097334d6 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 142:4eea097334d6 29 #endif
Anna Bridge 142:4eea097334d6 30
Anna Bridge 142:4eea097334d6 31 #ifndef __CORE_SC000_H_GENERIC
Anna Bridge 142:4eea097334d6 32 #define __CORE_SC000_H_GENERIC
Anna Bridge 142:4eea097334d6 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
Anna Bridge 142:4eea097334d6 36 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 37 extern "C" {
Anna Bridge 142:4eea097334d6 38 #endif
Anna Bridge 142:4eea097334d6 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 142:4eea097334d6 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 142:4eea097334d6 43
Anna Bridge 142:4eea097334d6 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 142:4eea097334d6 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 142:4eea097334d6 46
Anna Bridge 142:4eea097334d6 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 142:4eea097334d6 48 Unions are used for effective representation of core registers.
Anna Bridge 142:4eea097334d6 49
Anna Bridge 142:4eea097334d6 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 142:4eea097334d6 51 Function-like macros are used to allow more efficient code.
Anna Bridge 142:4eea097334d6 52 */
Anna Bridge 142:4eea097334d6 53
Anna Bridge 142:4eea097334d6 54
Anna Bridge 142:4eea097334d6 55 /*******************************************************************************
Anna Bridge 142:4eea097334d6 56 * CMSIS definitions
Anna Bridge 142:4eea097334d6 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup SC000
Anna Bridge 142:4eea097334d6 60 @{
Anna Bridge 142:4eea097334d6 61 */
Anna Bridge 142:4eea097334d6 62
Anna Bridge 142:4eea097334d6 63 /* CMSIS SC000 definitions */
AnnaBridge 145:64910690c574 64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Anna Bridge 142:4eea097334d6 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
Anna Bridge 142:4eea097334d6 70
Anna Bridge 142:4eea097334d6 71 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 142:4eea097334d6 72 This core does not support an FPU at all
Anna Bridge 142:4eea097334d6 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
Anna Bridge 142:4eea097334d6 75
Anna Bridge 142:4eea097334d6 76 #if defined ( __CC_ARM )
Anna Bridge 142:4eea097334d6 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 84 #endif
Anna Bridge 142:4eea097334d6 85
Anna Bridge 142:4eea097334d6 86 #elif defined ( __GNUC__ )
Anna Bridge 142:4eea097334d6 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 89 #endif
Anna Bridge 142:4eea097334d6 90
Anna Bridge 142:4eea097334d6 91 #elif defined ( __ICCARM__ )
Anna Bridge 142:4eea097334d6 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 94 #endif
Anna Bridge 142:4eea097334d6 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 99 #endif
Anna Bridge 142:4eea097334d6 100
Anna Bridge 142:4eea097334d6 101 #elif defined ( __TASKING__ )
Anna Bridge 142:4eea097334d6 102 #if defined __FPU_VFP__
Anna Bridge 142:4eea097334d6 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 104 #endif
Anna Bridge 142:4eea097334d6 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
Anna Bridge 142:4eea097334d6 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 142:4eea097334d6 109 #endif
AnnaBridge 145:64910690c574 110
Anna Bridge 142:4eea097334d6 111 #endif
Anna Bridge 142:4eea097334d6 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
Anna Bridge 142:4eea097334d6 115
Anna Bridge 142:4eea097334d6 116 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 117 }
Anna Bridge 142:4eea097334d6 118 #endif
Anna Bridge 142:4eea097334d6 119
Anna Bridge 142:4eea097334d6 120 #endif /* __CORE_SC000_H_GENERIC */
Anna Bridge 142:4eea097334d6 121
Anna Bridge 142:4eea097334d6 122 #ifndef __CMSIS_GENERIC
Anna Bridge 142:4eea097334d6 123
Anna Bridge 142:4eea097334d6 124 #ifndef __CORE_SC000_H_DEPENDANT
Anna Bridge 142:4eea097334d6 125 #define __CORE_SC000_H_DEPENDANT
Anna Bridge 142:4eea097334d6 126
Anna Bridge 142:4eea097334d6 127 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 128 extern "C" {
Anna Bridge 142:4eea097334d6 129 #endif
Anna Bridge 142:4eea097334d6 130
Anna Bridge 142:4eea097334d6 131 /* check device defines and use defaults */
Anna Bridge 142:4eea097334d6 132 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 142:4eea097334d6 133 #ifndef __SC000_REV
AnnaBridge 145:64910690c574 134 #define __SC000_REV 0x0000U
Anna Bridge 142:4eea097334d6 135 #warning "__SC000_REV not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 136 #endif
Anna Bridge 142:4eea097334d6 137
Anna Bridge 142:4eea097334d6 138 #ifndef __MPU_PRESENT
AnnaBridge 145:64910690c574 139 #define __MPU_PRESENT 0U
Anna Bridge 142:4eea097334d6 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 141 #endif
Anna Bridge 142:4eea097334d6 142
Anna Bridge 142:4eea097334d6 143 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 144 #define __NVIC_PRIO_BITS 2U
Anna Bridge 142:4eea097334d6 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 146 #endif
Anna Bridge 142:4eea097334d6 147
Anna Bridge 142:4eea097334d6 148 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 149 #define __Vendor_SysTickConfig 0U
Anna Bridge 142:4eea097334d6 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 142:4eea097334d6 151 #endif
Anna Bridge 142:4eea097334d6 152 #endif
Anna Bridge 142:4eea097334d6 153
Anna Bridge 142:4eea097334d6 154 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 142:4eea097334d6 155 /**
Anna Bridge 142:4eea097334d6 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 142:4eea097334d6 157
Anna Bridge 142:4eea097334d6 158 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 142:4eea097334d6 159 \li to specify the access to peripheral variables.
Anna Bridge 142:4eea097334d6 160 \li for automatic generation of peripheral register debug information.
Anna Bridge 142:4eea097334d6 161 */
Anna Bridge 142:4eea097334d6 162 #ifdef __cplusplus
AnnaBridge 145:64910690c574 163 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 164 #else
AnnaBridge 145:64910690c574 165 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 142:4eea097334d6 166 #endif
AnnaBridge 145:64910690c574 167 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 168 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 145:64910690c574 169
AnnaBridge 145:64910690c574 170 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 142:4eea097334d6 174
Anna Bridge 142:4eea097334d6 175 /*@} end of group SC000 */
Anna Bridge 142:4eea097334d6 176
Anna Bridge 142:4eea097334d6 177
Anna Bridge 142:4eea097334d6 178
Anna Bridge 142:4eea097334d6 179 /*******************************************************************************
Anna Bridge 142:4eea097334d6 180 * Register Abstraction
Anna Bridge 142:4eea097334d6 181 Core Register contain:
Anna Bridge 142:4eea097334d6 182 - Core Register
Anna Bridge 142:4eea097334d6 183 - Core NVIC Register
Anna Bridge 142:4eea097334d6 184 - Core SCB Register
Anna Bridge 142:4eea097334d6 185 - Core SysTick Register
Anna Bridge 142:4eea097334d6 186 - Core MPU Register
Anna Bridge 142:4eea097334d6 187 ******************************************************************************/
AnnaBridge 145:64910690c574 188 /**
AnnaBridge 145:64910690c574 189 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 190 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 142:4eea097334d6 191 */
Anna Bridge 142:4eea097334d6 192
AnnaBridge 145:64910690c574 193 /**
AnnaBridge 145:64910690c574 194 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 195 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 196 \brief Core Register type definitions.
Anna Bridge 142:4eea097334d6 197 @{
Anna Bridge 142:4eea097334d6 198 */
Anna Bridge 142:4eea097334d6 199
AnnaBridge 145:64910690c574 200 /**
AnnaBridge 145:64910690c574 201 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 142:4eea097334d6 202 */
Anna Bridge 142:4eea097334d6 203 typedef union
Anna Bridge 142:4eea097334d6 204 {
Anna Bridge 142:4eea097334d6 205 struct
Anna Bridge 142:4eea097334d6 206 {
AnnaBridge 145:64910690c574 207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 145:64910690c574 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 212 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 213 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 214 } APSR_Type;
Anna Bridge 142:4eea097334d6 215
Anna Bridge 142:4eea097334d6 216 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 217 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 142:4eea097334d6 218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 142:4eea097334d6 219
AnnaBridge 145:64910690c574 220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 142:4eea097334d6 221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 142:4eea097334d6 222
AnnaBridge 145:64910690c574 223 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 142:4eea097334d6 224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 142:4eea097334d6 225
AnnaBridge 145:64910690c574 226 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 142:4eea097334d6 227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 142:4eea097334d6 228
Anna Bridge 142:4eea097334d6 229
AnnaBridge 145:64910690c574 230 /**
AnnaBridge 145:64910690c574 231 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 142:4eea097334d6 232 */
Anna Bridge 142:4eea097334d6 233 typedef union
Anna Bridge 142:4eea097334d6 234 {
Anna Bridge 142:4eea097334d6 235 struct
Anna Bridge 142:4eea097334d6 236 {
AnnaBridge 145:64910690c574 237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 239 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 240 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 241 } IPSR_Type;
Anna Bridge 142:4eea097334d6 242
Anna Bridge 142:4eea097334d6 243 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 142:4eea097334d6 245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 142:4eea097334d6 246
Anna Bridge 142:4eea097334d6 247
AnnaBridge 145:64910690c574 248 /**
AnnaBridge 145:64910690c574 249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 142:4eea097334d6 250 */
Anna Bridge 142:4eea097334d6 251 typedef union
Anna Bridge 142:4eea097334d6 252 {
Anna Bridge 142:4eea097334d6 253 struct
Anna Bridge 142:4eea097334d6 254 {
AnnaBridge 145:64910690c574 255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 145:64910690c574 257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 145:64910690c574 258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 145:64910690c574 259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 263 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 264 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 265 } xPSR_Type;
Anna Bridge 142:4eea097334d6 266
Anna Bridge 142:4eea097334d6 267 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 142:4eea097334d6 269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 142:4eea097334d6 270
AnnaBridge 145:64910690c574 271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 142:4eea097334d6 272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 142:4eea097334d6 273
AnnaBridge 145:64910690c574 274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 142:4eea097334d6 275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 142:4eea097334d6 276
AnnaBridge 145:64910690c574 277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 142:4eea097334d6 278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 142:4eea097334d6 279
AnnaBridge 145:64910690c574 280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 142:4eea097334d6 281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 142:4eea097334d6 282
AnnaBridge 145:64910690c574 283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 142:4eea097334d6 284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 142:4eea097334d6 285
Anna Bridge 142:4eea097334d6 286
AnnaBridge 145:64910690c574 287 /**
AnnaBridge 145:64910690c574 288 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 142:4eea097334d6 289 */
Anna Bridge 142:4eea097334d6 290 typedef union
Anna Bridge 142:4eea097334d6 291 {
Anna Bridge 142:4eea097334d6 292 struct
Anna Bridge 142:4eea097334d6 293 {
AnnaBridge 145:64910690c574 294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 145:64910690c574 295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 145:64910690c574 296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 297 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 298 uint32_t w; /*!< Type used for word access */
Anna Bridge 142:4eea097334d6 299 } CONTROL_Type;
Anna Bridge 142:4eea097334d6 300
Anna Bridge 142:4eea097334d6 301 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 142:4eea097334d6 303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 142:4eea097334d6 304
Anna Bridge 142:4eea097334d6 305 /*@} end of group CMSIS_CORE */
Anna Bridge 142:4eea097334d6 306
Anna Bridge 142:4eea097334d6 307
AnnaBridge 145:64910690c574 308 /**
AnnaBridge 145:64910690c574 309 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 311 \brief Type definitions for the NVIC Registers
Anna Bridge 142:4eea097334d6 312 @{
Anna Bridge 142:4eea097334d6 313 */
Anna Bridge 142:4eea097334d6 314
AnnaBridge 145:64910690c574 315 /**
AnnaBridge 145:64910690c574 316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 142:4eea097334d6 317 */
Anna Bridge 142:4eea097334d6 318 typedef struct
Anna Bridge 142:4eea097334d6 319 {
AnnaBridge 145:64910690c574 320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 321 uint32_t RESERVED0[31U];
AnnaBridge 145:64910690c574 322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 323 uint32_t RSERVED1[31U];
AnnaBridge 145:64910690c574 324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 325 uint32_t RESERVED2[31U];
AnnaBridge 145:64910690c574 326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 327 uint32_t RESERVED3[31U];
AnnaBridge 145:64910690c574 328 uint32_t RESERVED4[64U];
AnnaBridge 145:64910690c574 329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 142:4eea097334d6 330 } NVIC_Type;
Anna Bridge 142:4eea097334d6 331
Anna Bridge 142:4eea097334d6 332 /*@} end of group CMSIS_NVIC */
Anna Bridge 142:4eea097334d6 333
Anna Bridge 142:4eea097334d6 334
AnnaBridge 145:64910690c574 335 /**
AnnaBridge 145:64910690c574 336 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 337 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 338 \brief Type definitions for the System Control Block Registers
Anna Bridge 142:4eea097334d6 339 @{
Anna Bridge 142:4eea097334d6 340 */
Anna Bridge 142:4eea097334d6 341
AnnaBridge 145:64910690c574 342 /**
AnnaBridge 145:64910690c574 343 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 142:4eea097334d6 344 */
Anna Bridge 142:4eea097334d6 345 typedef struct
Anna Bridge 142:4eea097334d6 346 {
AnnaBridge 145:64910690c574 347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 145:64910690c574 350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 353 uint32_t RESERVED0[1U];
AnnaBridge 145:64910690c574 354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 145:64910690c574 355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 145:64910690c574 356 uint32_t RESERVED1[154U];
AnnaBridge 145:64910690c574 357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Anna Bridge 142:4eea097334d6 358 } SCB_Type;
Anna Bridge 142:4eea097334d6 359
Anna Bridge 142:4eea097334d6 360 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 142:4eea097334d6 362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 142:4eea097334d6 363
AnnaBridge 145:64910690c574 364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 142:4eea097334d6 365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 142:4eea097334d6 366
AnnaBridge 145:64910690c574 367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 142:4eea097334d6 368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 142:4eea097334d6 369
AnnaBridge 145:64910690c574 370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 142:4eea097334d6 371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 142:4eea097334d6 372
AnnaBridge 145:64910690c574 373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 142:4eea097334d6 374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 142:4eea097334d6 375
Anna Bridge 142:4eea097334d6 376 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 142:4eea097334d6 378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 142:4eea097334d6 379
AnnaBridge 145:64910690c574 380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 142:4eea097334d6 381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 142:4eea097334d6 382
AnnaBridge 145:64910690c574 383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 142:4eea097334d6 384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 142:4eea097334d6 385
AnnaBridge 145:64910690c574 386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 142:4eea097334d6 387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 142:4eea097334d6 388
AnnaBridge 145:64910690c574 389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 142:4eea097334d6 390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 142:4eea097334d6 391
AnnaBridge 145:64910690c574 392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 142:4eea097334d6 393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 142:4eea097334d6 394
AnnaBridge 145:64910690c574 395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 142:4eea097334d6 396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 142:4eea097334d6 397
AnnaBridge 145:64910690c574 398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 142:4eea097334d6 399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 142:4eea097334d6 400
AnnaBridge 145:64910690c574 401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 142:4eea097334d6 402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 142:4eea097334d6 403
Anna Bridge 142:4eea097334d6 404 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 142:4eea097334d6 406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 142:4eea097334d6 407
Anna Bridge 142:4eea097334d6 408 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 142:4eea097334d6 410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 142:4eea097334d6 411
AnnaBridge 145:64910690c574 412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 142:4eea097334d6 413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 142:4eea097334d6 414
AnnaBridge 145:64910690c574 415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 142:4eea097334d6 416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 142:4eea097334d6 417
AnnaBridge 145:64910690c574 418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 142:4eea097334d6 419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 142:4eea097334d6 420
AnnaBridge 145:64910690c574 421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 142:4eea097334d6 422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 142:4eea097334d6 423
Anna Bridge 142:4eea097334d6 424 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 142:4eea097334d6 426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 142:4eea097334d6 427
AnnaBridge 145:64910690c574 428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 142:4eea097334d6 429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 142:4eea097334d6 430
AnnaBridge 145:64910690c574 431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 142:4eea097334d6 432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 142:4eea097334d6 433
Anna Bridge 142:4eea097334d6 434 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 142:4eea097334d6 436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 142:4eea097334d6 437
AnnaBridge 145:64910690c574 438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 142:4eea097334d6 439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 142:4eea097334d6 440
Anna Bridge 142:4eea097334d6 441 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 142:4eea097334d6 443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 142:4eea097334d6 444
Anna Bridge 142:4eea097334d6 445 /*@} end of group CMSIS_SCB */
Anna Bridge 142:4eea097334d6 446
Anna Bridge 142:4eea097334d6 447
AnnaBridge 145:64910690c574 448 /**
AnnaBridge 145:64910690c574 449 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 145:64910690c574 451 \brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge 142:4eea097334d6 452 @{
Anna Bridge 142:4eea097334d6 453 */
Anna Bridge 142:4eea097334d6 454
AnnaBridge 145:64910690c574 455 /**
AnnaBridge 145:64910690c574 456 \brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge 142:4eea097334d6 457 */
Anna Bridge 142:4eea097334d6 458 typedef struct
Anna Bridge 142:4eea097334d6 459 {
AnnaBridge 145:64910690c574 460 uint32_t RESERVED0[2U];
AnnaBridge 145:64910690c574 461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Anna Bridge 142:4eea097334d6 462 } SCnSCB_Type;
Anna Bridge 142:4eea097334d6 463
Anna Bridge 142:4eea097334d6 464 /* Auxiliary Control Register Definitions */
AnnaBridge 145:64910690c574 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Anna Bridge 142:4eea097334d6 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Anna Bridge 142:4eea097334d6 467
Anna Bridge 142:4eea097334d6 468 /*@} end of group CMSIS_SCnotSCB */
Anna Bridge 142:4eea097334d6 469
Anna Bridge 142:4eea097334d6 470
AnnaBridge 145:64910690c574 471 /**
AnnaBridge 145:64910690c574 472 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 474 \brief Type definitions for the System Timer Registers.
Anna Bridge 142:4eea097334d6 475 @{
Anna Bridge 142:4eea097334d6 476 */
Anna Bridge 142:4eea097334d6 477
AnnaBridge 145:64910690c574 478 /**
AnnaBridge 145:64910690c574 479 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 142:4eea097334d6 480 */
Anna Bridge 142:4eea097334d6 481 typedef struct
Anna Bridge 142:4eea097334d6 482 {
AnnaBridge 145:64910690c574 483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 142:4eea097334d6 487 } SysTick_Type;
Anna Bridge 142:4eea097334d6 488
Anna Bridge 142:4eea097334d6 489 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 142:4eea097334d6 491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 142:4eea097334d6 492
AnnaBridge 145:64910690c574 493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 142:4eea097334d6 494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 142:4eea097334d6 495
AnnaBridge 145:64910690c574 496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 142:4eea097334d6 497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 142:4eea097334d6 498
AnnaBridge 145:64910690c574 499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 142:4eea097334d6 500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 142:4eea097334d6 501
Anna Bridge 142:4eea097334d6 502 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 142:4eea097334d6 504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 142:4eea097334d6 505
Anna Bridge 142:4eea097334d6 506 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 142:4eea097334d6 508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 142:4eea097334d6 509
Anna Bridge 142:4eea097334d6 510 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 142:4eea097334d6 512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 142:4eea097334d6 513
AnnaBridge 145:64910690c574 514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 142:4eea097334d6 515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 142:4eea097334d6 516
AnnaBridge 145:64910690c574 517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 142:4eea097334d6 518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 142:4eea097334d6 519
Anna Bridge 142:4eea097334d6 520 /*@} end of group CMSIS_SysTick */
Anna Bridge 142:4eea097334d6 521
AnnaBridge 145:64910690c574 522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 523 /**
AnnaBridge 145:64910690c574 524 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 526 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 142:4eea097334d6 527 @{
Anna Bridge 142:4eea097334d6 528 */
Anna Bridge 142:4eea097334d6 529
AnnaBridge 145:64910690c574 530 /**
AnnaBridge 145:64910690c574 531 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 142:4eea097334d6 532 */
Anna Bridge 142:4eea097334d6 533 typedef struct
Anna Bridge 142:4eea097334d6 534 {
AnnaBridge 145:64910690c574 535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 145:64910690c574 536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 145:64910690c574 537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 145:64910690c574 538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 145:64910690c574 539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 142:4eea097334d6 540 } MPU_Type;
Anna Bridge 142:4eea097334d6 541
AnnaBridge 145:64910690c574 542 /* MPU Type Register Definitions */
AnnaBridge 145:64910690c574 543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 142:4eea097334d6 544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 142:4eea097334d6 545
AnnaBridge 145:64910690c574 546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 142:4eea097334d6 547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 142:4eea097334d6 548
AnnaBridge 145:64910690c574 549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 142:4eea097334d6 550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 142:4eea097334d6 551
AnnaBridge 145:64910690c574 552 /* MPU Control Register Definitions */
AnnaBridge 145:64910690c574 553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 142:4eea097334d6 554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 142:4eea097334d6 555
AnnaBridge 145:64910690c574 556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 142:4eea097334d6 557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 142:4eea097334d6 558
AnnaBridge 145:64910690c574 559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 142:4eea097334d6 560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 142:4eea097334d6 561
AnnaBridge 145:64910690c574 562 /* MPU Region Number Register Definitions */
AnnaBridge 145:64910690c574 563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 142:4eea097334d6 564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 142:4eea097334d6 565
AnnaBridge 145:64910690c574 566 /* MPU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Anna Bridge 142:4eea097334d6 568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 142:4eea097334d6 569
AnnaBridge 145:64910690c574 570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 142:4eea097334d6 571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 142:4eea097334d6 572
AnnaBridge 145:64910690c574 573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 142:4eea097334d6 574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 142:4eea097334d6 575
AnnaBridge 145:64910690c574 576 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 145:64910690c574 577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 142:4eea097334d6 578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 142:4eea097334d6 579
AnnaBridge 145:64910690c574 580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 142:4eea097334d6 581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 142:4eea097334d6 582
AnnaBridge 145:64910690c574 583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 142:4eea097334d6 584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 142:4eea097334d6 585
AnnaBridge 145:64910690c574 586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 142:4eea097334d6 587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 142:4eea097334d6 588
AnnaBridge 145:64910690c574 589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 142:4eea097334d6 590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 142:4eea097334d6 591
AnnaBridge 145:64910690c574 592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 142:4eea097334d6 593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 142:4eea097334d6 594
AnnaBridge 145:64910690c574 595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 142:4eea097334d6 596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 142:4eea097334d6 597
AnnaBridge 145:64910690c574 598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 142:4eea097334d6 599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 142:4eea097334d6 600
AnnaBridge 145:64910690c574 601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 142:4eea097334d6 602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 142:4eea097334d6 603
AnnaBridge 145:64910690c574 604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 142:4eea097334d6 605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 142:4eea097334d6 606
Anna Bridge 142:4eea097334d6 607 /*@} end of group CMSIS_MPU */
Anna Bridge 142:4eea097334d6 608 #endif
Anna Bridge 142:4eea097334d6 609
Anna Bridge 142:4eea097334d6 610
AnnaBridge 145:64910690c574 611 /**
AnnaBridge 145:64910690c574 612 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 145:64910690c574 615 Therefore they are not covered by the SC000 header file.
Anna Bridge 142:4eea097334d6 616 @{
Anna Bridge 142:4eea097334d6 617 */
Anna Bridge 142:4eea097334d6 618 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 142:4eea097334d6 619
Anna Bridge 142:4eea097334d6 620
AnnaBridge 145:64910690c574 621 /**
AnnaBridge 145:64910690c574 622 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 623 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 142:4eea097334d6 625 @{
Anna Bridge 142:4eea097334d6 626 */
Anna Bridge 142:4eea097334d6 627
AnnaBridge 145:64910690c574 628 /**
AnnaBridge 145:64910690c574 629 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 630 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 632 \return Masked and shifted value.
AnnaBridge 145:64910690c574 633 */
AnnaBridge 145:64910690c574 634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 635
AnnaBridge 145:64910690c574 636 /**
AnnaBridge 145:64910690c574 637 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 638 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 640 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 641 */
AnnaBridge 145:64910690c574 642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 643
AnnaBridge 145:64910690c574 644 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 645
AnnaBridge 145:64910690c574 646
AnnaBridge 145:64910690c574 647 /**
AnnaBridge 145:64910690c574 648 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 649 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 650 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 651 @{
AnnaBridge 145:64910690c574 652 */
AnnaBridge 145:64910690c574 653
AnnaBridge 145:64910690c574 654 /* Memory mapping of Core Hardware */
Anna Bridge 142:4eea097334d6 655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 142:4eea097334d6 658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 142:4eea097334d6 659
Anna Bridge 142:4eea097334d6 660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 145:64910690c574 661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 142:4eea097334d6 664
AnnaBridge 145:64910690c574 665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 142:4eea097334d6 668 #endif
Anna Bridge 142:4eea097334d6 669
Anna Bridge 142:4eea097334d6 670 /*@} */
Anna Bridge 142:4eea097334d6 671
Anna Bridge 142:4eea097334d6 672
Anna Bridge 142:4eea097334d6 673
Anna Bridge 142:4eea097334d6 674 /*******************************************************************************
Anna Bridge 142:4eea097334d6 675 * Hardware Abstraction Layer
Anna Bridge 142:4eea097334d6 676 Core Function Interface contains:
Anna Bridge 142:4eea097334d6 677 - Core NVIC Functions
Anna Bridge 142:4eea097334d6 678 - Core SysTick Functions
Anna Bridge 142:4eea097334d6 679 - Core Register Access Functions
Anna Bridge 142:4eea097334d6 680 ******************************************************************************/
AnnaBridge 145:64910690c574 681 /**
AnnaBridge 145:64910690c574 682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 142:4eea097334d6 683 */
Anna Bridge 142:4eea097334d6 684
Anna Bridge 142:4eea097334d6 685
Anna Bridge 142:4eea097334d6 686
Anna Bridge 142:4eea097334d6 687 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 688 /**
AnnaBridge 145:64910690c574 689 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 691 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 692 @{
Anna Bridge 142:4eea097334d6 693 */
Anna Bridge 142:4eea097334d6 694
AnnaBridge 145:64910690c574 695 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 145:64910690c574 696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 145:64910690c574 698 #endif
AnnaBridge 145:64910690c574 699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 700 #else
AnnaBridge 145:64910690c574 701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 145:64910690c574 702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 145:64910690c574 703 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 145:64910690c574 705 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 145:64910690c574 706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 145:64910690c574 707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 145:64910690c574 708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 145:64910690c574 709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 145:64910690c574 710 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 145:64910690c574 711 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 145:64910690c574 712 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 145:64910690c574 713 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 145:64910690c574 714
AnnaBridge 145:64910690c574 715 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 145:64910690c574 716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 145:64910690c574 718 #endif
AnnaBridge 145:64910690c574 719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 720 #else
AnnaBridge 145:64910690c574 721 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 145:64910690c574 722 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 723 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 145:64910690c574 724
AnnaBridge 145:64910690c574 725 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 726
AnnaBridge 145:64910690c574 727
Anna Bridge 142:4eea097334d6 728 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Anna Bridge 142:4eea097334d6 729 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 142:4eea097334d6 730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 142:4eea097334d6 731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 142:4eea097334d6 732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 142:4eea097334d6 733
Anna Bridge 142:4eea097334d6 734
AnnaBridge 145:64910690c574 735 /**
AnnaBridge 145:64910690c574 736 \brief Enable Interrupt
AnnaBridge 145:64910690c574 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 738 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 739 \note IRQn must not be negative.
Anna Bridge 142:4eea097334d6 740 */
AnnaBridge 145:64910690c574 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 742 {
AnnaBridge 145:64910690c574 743 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 744 {
AnnaBridge 145:64910690c574 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 746 }
Anna Bridge 142:4eea097334d6 747 }
Anna Bridge 142:4eea097334d6 748
Anna Bridge 142:4eea097334d6 749
AnnaBridge 145:64910690c574 750 /**
AnnaBridge 145:64910690c574 751 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 753 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 754 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 755 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 756 \note IRQn must not be negative.
Anna Bridge 142:4eea097334d6 757 */
AnnaBridge 145:64910690c574 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 759 {
AnnaBridge 145:64910690c574 760 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 761 {
AnnaBridge 145:64910690c574 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 763 }
AnnaBridge 145:64910690c574 764 else
AnnaBridge 145:64910690c574 765 {
AnnaBridge 145:64910690c574 766 return(0U);
AnnaBridge 145:64910690c574 767 }
Anna Bridge 142:4eea097334d6 768 }
Anna Bridge 142:4eea097334d6 769
Anna Bridge 142:4eea097334d6 770
AnnaBridge 145:64910690c574 771 /**
AnnaBridge 145:64910690c574 772 \brief Disable Interrupt
AnnaBridge 145:64910690c574 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 774 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 775 \note IRQn must not be negative.
Anna Bridge 142:4eea097334d6 776 */
AnnaBridge 145:64910690c574 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 778 {
AnnaBridge 145:64910690c574 779 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 780 {
AnnaBridge 145:64910690c574 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 782 __DSB();
AnnaBridge 145:64910690c574 783 __ISB();
AnnaBridge 145:64910690c574 784 }
Anna Bridge 142:4eea097334d6 785 }
Anna Bridge 142:4eea097334d6 786
Anna Bridge 142:4eea097334d6 787
AnnaBridge 145:64910690c574 788 /**
AnnaBridge 145:64910690c574 789 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 791 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 792 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 793 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 794 \note IRQn must not be negative.
Anna Bridge 142:4eea097334d6 795 */
AnnaBridge 145:64910690c574 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 797 {
AnnaBridge 145:64910690c574 798 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 799 {
AnnaBridge 145:64910690c574 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 801 }
AnnaBridge 145:64910690c574 802 else
AnnaBridge 145:64910690c574 803 {
AnnaBridge 145:64910690c574 804 return(0U);
AnnaBridge 145:64910690c574 805 }
Anna Bridge 142:4eea097334d6 806 }
Anna Bridge 142:4eea097334d6 807
Anna Bridge 142:4eea097334d6 808
AnnaBridge 145:64910690c574 809 /**
AnnaBridge 145:64910690c574 810 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 812 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 813 \note IRQn must not be negative.
Anna Bridge 142:4eea097334d6 814 */
AnnaBridge 145:64910690c574 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 142:4eea097334d6 816 {
AnnaBridge 145:64910690c574 817 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 818 {
AnnaBridge 145:64910690c574 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Anna Bridge 142:4eea097334d6 820 }
Anna Bridge 142:4eea097334d6 821 }
Anna Bridge 142:4eea097334d6 822
Anna Bridge 142:4eea097334d6 823
AnnaBridge 145:64910690c574 824 /**
AnnaBridge 145:64910690c574 825 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 827 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 828 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 829 */
AnnaBridge 145:64910690c574 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 831 {
AnnaBridge 145:64910690c574 832 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 833 {
AnnaBridge 145:64910690c574 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 835 }
AnnaBridge 145:64910690c574 836 }
Anna Bridge 142:4eea097334d6 837
Anna Bridge 142:4eea097334d6 838
AnnaBridge 145:64910690c574 839 /**
AnnaBridge 145:64910690c574 840 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 841 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 842 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 843 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 844 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 845 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 846 \note The priority cannot be set for every processor exception.
Anna Bridge 142:4eea097334d6 847 */
AnnaBridge 145:64910690c574 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 142:4eea097334d6 849 {
AnnaBridge 145:64910690c574 850 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 851 {
AnnaBridge 145:64910690c574 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 142:4eea097334d6 854 }
AnnaBridge 145:64910690c574 855 else
AnnaBridge 145:64910690c574 856 {
AnnaBridge 145:64910690c574 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 142:4eea097334d6 859 }
Anna Bridge 142:4eea097334d6 860 }
Anna Bridge 142:4eea097334d6 861
Anna Bridge 142:4eea097334d6 862
AnnaBridge 145:64910690c574 863 /**
AnnaBridge 145:64910690c574 864 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 865 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 866 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 867 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 868 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 869 \return Interrupt Priority.
AnnaBridge 145:64910690c574 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 142:4eea097334d6 871 */
AnnaBridge 145:64910690c574 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 873 {
AnnaBridge 145:64910690c574 874
AnnaBridge 145:64910690c574 875 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 876 {
AnnaBridge 145:64910690c574 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 878 }
AnnaBridge 145:64910690c574 879 else
AnnaBridge 145:64910690c574 880 {
AnnaBridge 145:64910690c574 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 882 }
AnnaBridge 145:64910690c574 883 }
AnnaBridge 145:64910690c574 884
AnnaBridge 145:64910690c574 885
AnnaBridge 145:64910690c574 886 /**
AnnaBridge 145:64910690c574 887 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 888 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 889 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 890 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 891 VTOR must been relocated to SRAM before.
AnnaBridge 145:64910690c574 892 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 893 \param [in] vector Address of interrupt handler function
AnnaBridge 145:64910690c574 894 */
AnnaBridge 145:64910690c574 895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 142:4eea097334d6 896 {
AnnaBridge 145:64910690c574 897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 899 }
AnnaBridge 145:64910690c574 900
AnnaBridge 145:64910690c574 901
AnnaBridge 145:64910690c574 902 /**
AnnaBridge 145:64910690c574 903 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 904 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 905 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 906 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 907 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 908 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 909 */
AnnaBridge 145:64910690c574 910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 911 {
AnnaBridge 145:64910690c574 912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 914 }
AnnaBridge 145:64910690c574 915
AnnaBridge 145:64910690c574 916
AnnaBridge 145:64910690c574 917 /**
AnnaBridge 145:64910690c574 918 \brief System Reset
AnnaBridge 145:64910690c574 919 \details Initiates a system reset request to reset the MCU.
AnnaBridge 145:64910690c574 920 */
AnnaBridge 145:64910690c574 921 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 145:64910690c574 922 {
AnnaBridge 145:64910690c574 923 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 145:64910690c574 924 buffered write are completed before reset */
Anna Bridge 142:4eea097334d6 925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 142:4eea097334d6 926 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 145:64910690c574 927 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 928
AnnaBridge 145:64910690c574 929 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 930 {
AnnaBridge 145:64910690c574 931 __NOP();
AnnaBridge 145:64910690c574 932 }
Anna Bridge 142:4eea097334d6 933 }
Anna Bridge 142:4eea097334d6 934
Anna Bridge 142:4eea097334d6 935 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 142:4eea097334d6 936
Anna Bridge 142:4eea097334d6 937
AnnaBridge 145:64910690c574 938 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 939 /**
AnnaBridge 145:64910690c574 940 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 941 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 942 \brief Function that provides FPU type.
Anna Bridge 142:4eea097334d6 943 @{
Anna Bridge 142:4eea097334d6 944 */
Anna Bridge 142:4eea097334d6 945
AnnaBridge 145:64910690c574 946 /**
AnnaBridge 145:64910690c574 947 \brief get FPU type
AnnaBridge 145:64910690c574 948 \details returns the FPU type
AnnaBridge 145:64910690c574 949 \returns
AnnaBridge 145:64910690c574 950 - \b 0: No FPU
AnnaBridge 145:64910690c574 951 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 952 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 953 */
AnnaBridge 145:64910690c574 954 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 955 {
AnnaBridge 145:64910690c574 956 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 957 }
Anna Bridge 142:4eea097334d6 958
Anna Bridge 142:4eea097334d6 959
AnnaBridge 145:64910690c574 960 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 961
AnnaBridge 145:64910690c574 962
Anna Bridge 142:4eea097334d6 963
AnnaBridge 145:64910690c574 964 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 965 /**
AnnaBridge 145:64910690c574 966 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 968 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 969 @{
AnnaBridge 145:64910690c574 970 */
Anna Bridge 142:4eea097334d6 971
AnnaBridge 145:64910690c574 972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 142:4eea097334d6 973
AnnaBridge 145:64910690c574 974 /**
AnnaBridge 145:64910690c574 975 \brief System Tick Configuration
AnnaBridge 145:64910690c574 976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 977 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 978 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 979 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 980 \return 1 Function failed.
AnnaBridge 145:64910690c574 981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 983 must contain a vendor-specific implementation of this function.
Anna Bridge 142:4eea097334d6 984 */
Anna Bridge 142:4eea097334d6 985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 142:4eea097334d6 986 {
AnnaBridge 145:64910690c574 987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 988 {
AnnaBridge 145:64910690c574 989 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 990 }
Anna Bridge 142:4eea097334d6 991
Anna Bridge 142:4eea097334d6 992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 142:4eea097334d6 993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 142:4eea097334d6 994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 142:4eea097334d6 995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 142:4eea097334d6 996 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 142:4eea097334d6 997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 142:4eea097334d6 998 return (0UL); /* Function successful */
Anna Bridge 142:4eea097334d6 999 }
Anna Bridge 142:4eea097334d6 1000
Anna Bridge 142:4eea097334d6 1001 #endif
Anna Bridge 142:4eea097334d6 1002
Anna Bridge 142:4eea097334d6 1003 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 142:4eea097334d6 1004
Anna Bridge 142:4eea097334d6 1005
Anna Bridge 142:4eea097334d6 1006
Anna Bridge 142:4eea097334d6 1007
Anna Bridge 142:4eea097334d6 1008 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 1009 }
Anna Bridge 142:4eea097334d6 1010 #endif
Anna Bridge 142:4eea097334d6 1011
Anna Bridge 142:4eea097334d6 1012 #endif /* __CORE_SC000_H_DEPENDANT */
Anna Bridge 142:4eea097334d6 1013
Anna Bridge 142:4eea097334d6 1014 #endif /* __CMSIS_GENERIC */