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TARGET_RZ_A1H/core_ca.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:: Kojto
Date:: Wed Jul 19 16:46:19 2017 +0100
Revision:: 147:a97add6d7e64
Parent:: 145:64910690c574
Child:: 160:5571c4ff569f

Release 147 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/************************************************************************//
AnnaBridge	145:64910690c574	2	* @file core_ca.h
AnnaBridge	145:64910690c574	3	* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge	145:64910690c574	4	* @version V1.00
AnnaBridge	145:64910690c574	5	* @date 22. Feb 2017
AnnaBridge	145:64910690c574	6	******************************************************************************/
AnnaBridge	145:64910690c574	7	/*
AnnaBridge	145:64910690c574	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	145:64910690c574	9	*
AnnaBridge	145:64910690c574	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	145:64910690c574	11	*
AnnaBridge	145:64910690c574	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	145:64910690c574	13	* not use this file except in compliance with the License.
AnnaBridge	145:64910690c574	14	* You may obtain a copy of the License at
AnnaBridge	145:64910690c574	15	*
AnnaBridge	145:64910690c574	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	145:64910690c574	17	*
AnnaBridge	145:64910690c574	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	145:64910690c574	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	145:64910690c574	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	145:64910690c574	21	* See the License for the specific language governing permissions and
AnnaBridge	145:64910690c574	22	* limitations under the License.
AnnaBridge	145:64910690c574	23	*/
AnnaBridge	145:64910690c574	24
AnnaBridge	145:64910690c574	25	#if defined ( __ICCARM__ )
AnnaBridge	145:64910690c574	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	145:64910690c574	27	#endif
AnnaBridge	145:64910690c574	28
AnnaBridge	145:64910690c574	29	#ifdef __cplusplus
AnnaBridge	145:64910690c574	30	extern "C" {
AnnaBridge	145:64910690c574	31	#endif
AnnaBridge	145:64910690c574	32
AnnaBridge	145:64910690c574	33	#ifndef __CORE_CA_H_GENERIC
AnnaBridge	145:64910690c574	34	#define __CORE_CA_H_GENERIC
AnnaBridge	145:64910690c574	35
AnnaBridge	145:64910690c574	36
AnnaBridge	145:64910690c574	37	/*******************************************************************************
AnnaBridge	145:64910690c574	38	* CMSIS definitions
AnnaBridge	145:64910690c574	39	******************************************************************************/
AnnaBridge	145:64910690c574	40
AnnaBridge	145:64910690c574	41	/* CMSIS CA definitions */
AnnaBridge	145:64910690c574	42	#define __CA_CMSIS_VERSION_MAIN (1U) /!< \brief [31:16] CMSIS HAL main version /
AnnaBridge	145:64910690c574	43	#define __CA_CMSIS_VERSION_SUB (0U) /!< \brief [15:0] CMSIS HAL sub version /
AnnaBridge	145:64910690c574	44	#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	145:64910690c574	45	__CA_CMSIS_VERSION_SUB ) /!< \brief CMSIS HAL version number /
AnnaBridge	145:64910690c574	46
AnnaBridge	145:64910690c574	47	#if defined ( __CC_ARM )
AnnaBridge	145:64910690c574	48	#if defined __TARGET_FPU_VFP
AnnaBridge	145:64910690c574	49	#if (__FPU_PRESENT == 1)
AnnaBridge	145:64910690c574	50	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	51	#else
AnnaBridge	145:64910690c574	52	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	53	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	54	#endif
AnnaBridge	145:64910690c574	55	#else
AnnaBridge	145:64910690c574	56	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	57	#endif
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	#elif defined ( __ICCARM__ )
AnnaBridge	145:64910690c574	60	#if defined __ARMVFP__
AnnaBridge	145:64910690c574	61	#if (__FPU_PRESENT == 1)
AnnaBridge	145:64910690c574	62	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	63	#else
AnnaBridge	145:64910690c574	64	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	65	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	66	#endif
AnnaBridge	145:64910690c574	67	#else
AnnaBridge	145:64910690c574	68	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	69	#endif
AnnaBridge	145:64910690c574	70
AnnaBridge	145:64910690c574	71	#elif defined ( __TMS470__ )
AnnaBridge	145:64910690c574	72	#if defined __TI_VFP_SUPPORT__
AnnaBridge	145:64910690c574	73	#if (__FPU_PRESENT == 1)
AnnaBridge	145:64910690c574	74	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	75	#else
AnnaBridge	145:64910690c574	76	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	77	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	78	#endif
AnnaBridge	145:64910690c574	79	#else
AnnaBridge	145:64910690c574	80	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	81	#endif
AnnaBridge	145:64910690c574	82
AnnaBridge	145:64910690c574	83	#elif defined ( __GNUC__ )
AnnaBridge	145:64910690c574	84	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	145:64910690c574	85	#if (__FPU_PRESENT == 1)
AnnaBridge	145:64910690c574	86	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	87	#else
AnnaBridge	145:64910690c574	88	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	89	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	90	#endif
AnnaBridge	145:64910690c574	91	#else
AnnaBridge	145:64910690c574	92	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	93	#endif
AnnaBridge	145:64910690c574	94
AnnaBridge	145:64910690c574	95	#elif defined ( __TASKING__ )
AnnaBridge	145:64910690c574	96	#if defined __FPU_VFP__
AnnaBridge	145:64910690c574	97	#if (__FPU_PRESENT == 1)
AnnaBridge	145:64910690c574	98	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	99	#else
AnnaBridge	145:64910690c574	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	101	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	102	#endif
AnnaBridge	145:64910690c574	103	#else
AnnaBridge	145:64910690c574	104	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	105	#endif
AnnaBridge	145:64910690c574	106	#endif
AnnaBridge	145:64910690c574	107
AnnaBridge	145:64910690c574	108	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	145:64910690c574	109
AnnaBridge	145:64910690c574	110	#ifdef __cplusplus
AnnaBridge	145:64910690c574	111	}
AnnaBridge	145:64910690c574	112	#endif
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114	#endif /* __CORE_CA_H_GENERIC */
AnnaBridge	145:64910690c574	115
AnnaBridge	145:64910690c574	116	#ifndef __CMSIS_GENERIC
AnnaBridge	145:64910690c574	117
AnnaBridge	145:64910690c574	118	#ifndef __CORE_CA_H_DEPENDANT
AnnaBridge	145:64910690c574	119	#define __CORE_CA_H_DEPENDANT
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	#ifdef __cplusplus
AnnaBridge	145:64910690c574	122	extern "C" {
AnnaBridge	145:64910690c574	123	#endif
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	/* check device defines and use defaults */
AnnaBridge	145:64910690c574	126	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	145:64910690c574	127	#ifndef __CA_REV
AnnaBridge	145:64910690c574	128	#define __CA_REV 0x0000U
AnnaBridge	145:64910690c574	129	#warning "__CA_REV not defined in device header file; using default!"
AnnaBridge	145:64910690c574	130	#endif
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	#ifndef __FPU_PRESENT
AnnaBridge	145:64910690c574	133	#define __FPU_PRESENT 0U
AnnaBridge	145:64910690c574	134	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	145:64910690c574	135	#endif
AnnaBridge	145:64910690c574	136
AnnaBridge	145:64910690c574	137	#ifndef __MPU_PRESENT
AnnaBridge	145:64910690c574	138	#define __MPU_PRESENT 0U
AnnaBridge	145:64910690c574	139	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	145:64910690c574	140	#endif
AnnaBridge	145:64910690c574	141
AnnaBridge	145:64910690c574	142	#ifndef __GIC_PRESENT
AnnaBridge	145:64910690c574	143	#define __GIC_PRESENT 1U
AnnaBridge	145:64910690c574	144	#warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge	145:64910690c574	145	#endif
AnnaBridge	145:64910690c574	146
AnnaBridge	145:64910690c574	147	#ifndef __TIM_PRESENT
AnnaBridge	145:64910690c574	148	#define __TIM_PRESENT 1U
AnnaBridge	145:64910690c574	149	#warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge	145:64910690c574	150	#endif
AnnaBridge	145:64910690c574	151
AnnaBridge	145:64910690c574	152	#ifndef __L2C_PRESENT
AnnaBridge	145:64910690c574	153	#define __L2C_PRESENT 0U
AnnaBridge	145:64910690c574	154	#warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge	145:64910690c574	155	#endif
AnnaBridge	145:64910690c574	156	#endif
AnnaBridge	145:64910690c574	157
AnnaBridge	145:64910690c574	158	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	145:64910690c574	159	#ifdef __cplusplus
AnnaBridge	145:64910690c574	160	#define __I volatile /!< \brief Defines 'read only' permissions /
AnnaBridge	145:64910690c574	161	#else
AnnaBridge	145:64910690c574	162	#define __I volatile const /!< \brief Defines 'read only' permissions /
AnnaBridge	145:64910690c574	163	#endif
AnnaBridge	145:64910690c574	164	#define __O volatile /!< \brief Defines 'write only' permissions /
AnnaBridge	145:64910690c574	165	#define __IO volatile /!< \brief Defines 'read / write' permissions /
AnnaBridge	145:64910690c574	166
AnnaBridge	145:64910690c574	167	/* following defines should be used for structure members */
AnnaBridge	145:64910690c574	168	#define __IM volatile const /!< \brief Defines 'read only' structure member permissions /
AnnaBridge	145:64910690c574	169	#define __OM volatile /!< \brief Defines 'write only' structure member permissions /
AnnaBridge	145:64910690c574	170	#define __IOM volatile /!< \brief Defines 'read / write' structure member permissions /
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172
AnnaBridge	145:64910690c574	173	/*******************************************************************************
AnnaBridge	145:64910690c574	174	* Register Abstraction
AnnaBridge	145:64910690c574	175	Core Register contain:
AnnaBridge	145:64910690c574	176	- CPSR
AnnaBridge	145:64910690c574	177	- CP15 Registers
AnnaBridge	145:64910690c574	178	- L2C-310 Cache Controller
AnnaBridge	145:64910690c574	179	- Generic Interrupt Controller Distributor
AnnaBridge	145:64910690c574	180	- Generic Interrupt Controller Interface
AnnaBridge	145:64910690c574	181	******************************************************************************/
AnnaBridge	145:64910690c574	182
AnnaBridge	145:64910690c574	183	/* Core Register CPSR */
AnnaBridge	145:64910690c574	184	typedef union
AnnaBridge	145:64910690c574	185	{
AnnaBridge	145:64910690c574	186	struct
AnnaBridge	145:64910690c574	187	{
AnnaBridge	145:64910690c574	188	uint32_t M:5; /!< \brief bit: 0.. 4 Mode field /
AnnaBridge	145:64910690c574	189	uint32_t T:1; /!< \brief bit: 5 Thumb execution state bit /
AnnaBridge	145:64910690c574	190	uint32_t F:1; /!< \brief bit: 6 FIQ mask bit /
AnnaBridge	145:64910690c574	191	uint32_t I:1; /!< \brief bit: 7 IRQ mask bit /
AnnaBridge	145:64910690c574	192	uint32_t A:1; /!< \brief bit: 8 Asynchronous abort mask bit /
AnnaBridge	145:64910690c574	193	uint32_t E:1; /!< \brief bit: 9 Endianness execution state bit /
AnnaBridge	145:64910690c574	194	uint32_t IT1:6; /!< \brief bit: 10..15 If-Then execution state bits 2-7 /
AnnaBridge	145:64910690c574	195	uint32_t GE:4; /!< \brief bit: 16..19 Greater than or Equal flags /
AnnaBridge	145:64910690c574	196	uint32_t _reserved0:4; /!< \brief bit: 20..23 Reserved /
AnnaBridge	145:64910690c574	197	uint32_t J:1; /!< \brief bit: 24 Jazelle bit /
AnnaBridge	145:64910690c574	198	uint32_t IT0:2; /!< \brief bit: 25..26 If-Then execution state bits 0-1 /
AnnaBridge	145:64910690c574	199	uint32_t Q:1; /!< \brief bit: 27 Saturation condition flag /
AnnaBridge	145:64910690c574	200	uint32_t V:1; /!< \brief bit: 28 Overflow condition code flag /
AnnaBridge	145:64910690c574	201	uint32_t C:1; /!< \brief bit: 29 Carry condition code flag /
AnnaBridge	145:64910690c574	202	uint32_t Z:1; /!< \brief bit: 30 Zero condition code flag /
AnnaBridge	145:64910690c574	203	uint32_t N:1; /!< \brief bit: 31 Negative condition code flag /
AnnaBridge	145:64910690c574	204	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	205	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	206	} CPSR_Type;
AnnaBridge	145:64910690c574	207
AnnaBridge	145:64910690c574	208	/* CPSR Register Definitions */
AnnaBridge	145:64910690c574	209	#define CPSR_N_Pos 31U /!< \brief CPSR: N Position /
AnnaBridge	145:64910690c574	210	#define CPSR_N_Msk (1UL << CPSR_N_Pos) /!< \brief CPSR: N Mask /
AnnaBridge	145:64910690c574	211
AnnaBridge	145:64910690c574	212	#define CPSR_Z_Pos 30U /!< \brief CPSR: Z Position /
AnnaBridge	145:64910690c574	213	#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /!< \brief CPSR: Z Mask /
AnnaBridge	145:64910690c574	214
AnnaBridge	145:64910690c574	215	#define CPSR_C_Pos 29U /!< \brief CPSR: C Position /
AnnaBridge	145:64910690c574	216	#define CPSR_C_Msk (1UL << CPSR_C_Pos) /!< \brief CPSR: C Mask /
AnnaBridge	145:64910690c574	217
AnnaBridge	145:64910690c574	218	#define CPSR_V_Pos 28U /!< \brief CPSR: V Position /
AnnaBridge	145:64910690c574	219	#define CPSR_V_Msk (1UL << CPSR_V_Pos) /!< \brief CPSR: V Mask /
AnnaBridge	145:64910690c574	220
AnnaBridge	145:64910690c574	221	#define CPSR_Q_Pos 27U /!< \brief CPSR: Q Position /
AnnaBridge	145:64910690c574	222	#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /!< \brief CPSR: Q Mask /
AnnaBridge	145:64910690c574	223
AnnaBridge	145:64910690c574	224	#define CPSR_IT0_Pos 25U /!< \brief CPSR: IT0 Position /
AnnaBridge	145:64910690c574	225	#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /!< \brief CPSR: IT0 Mask /
AnnaBridge	145:64910690c574	226
AnnaBridge	145:64910690c574	227	#define CPSR_J_Pos 24U /!< \brief CPSR: J Position /
AnnaBridge	145:64910690c574	228	#define CPSR_J_Msk (1UL << CPSR_J_Pos) /!< \brief CPSR: J Mask /
AnnaBridge	145:64910690c574	229
AnnaBridge	145:64910690c574	230	#define CPSR_GE_Pos 16U /!< \brief CPSR: GE Position /
AnnaBridge	145:64910690c574	231	#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /!< \brief CPSR: GE Mask /
AnnaBridge	145:64910690c574	232
AnnaBridge	145:64910690c574	233	#define CPSR_IT1_Pos 10U /!< \brief CPSR: IT1 Position /
AnnaBridge	145:64910690c574	234	#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /!< \brief CPSR: IT1 Mask /
AnnaBridge	145:64910690c574	235
AnnaBridge	145:64910690c574	236	#define CPSR_E_Pos 9U /!< \brief CPSR: E Position /
AnnaBridge	145:64910690c574	237	#define CPSR_E_Msk (1UL << CPSR_E_Pos) /!< \brief CPSR: E Mask /
AnnaBridge	145:64910690c574	238
AnnaBridge	145:64910690c574	239	#define CPSR_A_Pos 8U /!< \brief CPSR: A Position /
AnnaBridge	145:64910690c574	240	#define CPSR_A_Msk (1UL << CPSR_A_Pos) /!< \brief CPSR: A Mask /
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	#define CPSR_I_Pos 7U /!< \brief CPSR: I Position /
AnnaBridge	145:64910690c574	243	#define CPSR_I_Msk (1UL << CPSR_I_Pos) /!< \brief CPSR: I Mask /
AnnaBridge	145:64910690c574	244
AnnaBridge	145:64910690c574	245	#define CPSR_F_Pos 6U /!< \brief CPSR: F Position /
AnnaBridge	145:64910690c574	246	#define CPSR_F_Msk (1UL << CPSR_F_Pos) /!< \brief CPSR: F Mask /
AnnaBridge	145:64910690c574	247
AnnaBridge	145:64910690c574	248	#define CPSR_T_Pos 5U /!< \brief CPSR: T Position /
AnnaBridge	145:64910690c574	249	#define CPSR_T_Msk (1UL << CPSR_T_Pos) /!< \brief CPSR: T Mask /
AnnaBridge	145:64910690c574	250
AnnaBridge	145:64910690c574	251	#define CPSR_M_Pos 0U /!< \brief CPSR: M Position /
AnnaBridge	145:64910690c574	252	#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /!< \brief CPSR: M Mask /
AnnaBridge	145:64910690c574	253
AnnaBridge	145:64910690c574	254	/* CP15 Register SCTLR */
AnnaBridge	145:64910690c574	255	typedef union
AnnaBridge	145:64910690c574	256	{
AnnaBridge	145:64910690c574	257	struct
AnnaBridge	145:64910690c574	258	{
AnnaBridge	145:64910690c574	259	uint32_t M:1; /!< \brief bit: 0 MMU enable /
AnnaBridge	145:64910690c574	260	uint32_t A:1; /!< \brief bit: 1 Alignment check enable /
AnnaBridge	145:64910690c574	261	uint32_t C:1; /!< \brief bit: 2 Cache enable /
AnnaBridge	145:64910690c574	262	uint32_t _reserved0:2; /!< \brief bit: 3.. 4 Reserved /
AnnaBridge	145:64910690c574	263	uint32_t CP15BEN:1; /!< \brief bit: 5 CP15 barrier enable /
AnnaBridge	145:64910690c574	264	uint32_t _reserved1:1; /!< \brief bit: 6 Reserved /
AnnaBridge	145:64910690c574	265	uint32_t B:1; /!< \brief bit: 7 Endianness model /
AnnaBridge	145:64910690c574	266	uint32_t _reserved2:2; /!< \brief bit: 8.. 9 Reserved /
AnnaBridge	145:64910690c574	267	uint32_t SW:1; /!< \brief bit: 10 SWP and SWPB enable /
AnnaBridge	145:64910690c574	268	uint32_t Z:1; /!< \brief bit: 11 Branch prediction enable /
AnnaBridge	145:64910690c574	269	uint32_t I:1; /!< \brief bit: 12 Instruction cache enable /
AnnaBridge	145:64910690c574	270	uint32_t V:1; /!< \brief bit: 13 Vectors bit /
AnnaBridge	145:64910690c574	271	uint32_t RR:1; /!< \brief bit: 14 Round Robin select /
AnnaBridge	145:64910690c574	272	uint32_t _reserved3:2; /!< \brief bit:15..16 Reserved /
AnnaBridge	145:64910690c574	273	uint32_t HA:1; /!< \brief bit: 17 Hardware Access flag enable /
AnnaBridge	145:64910690c574	274	uint32_t _reserved4:1; /!< \brief bit: 18 Reserved /
AnnaBridge	145:64910690c574	275	uint32_t WXN:1; /!< \brief bit: 19 Write permission implies XN /
AnnaBridge	145:64910690c574	276	uint32_t UWXN:1; /!< \brief bit: 20 Unprivileged write permission implies PL1 XN /
AnnaBridge	145:64910690c574	277	uint32_t FI:1; /!< \brief bit: 21 Fast interrupts configuration enable /
AnnaBridge	145:64910690c574	278	uint32_t U:1; /!< \brief bit: 22 Alignment model /
AnnaBridge	145:64910690c574	279	uint32_t _reserved5:1; /!< \brief bit: 23 Reserved /
AnnaBridge	145:64910690c574	280	uint32_t VE:1; /!< \brief bit: 24 Interrupt Vectors Enable /
AnnaBridge	145:64910690c574	281	uint32_t EE:1; /!< \brief bit: 25 Exception Endianness /
AnnaBridge	145:64910690c574	282	uint32_t _reserved6:1; /!< \brief bit: 26 Reserved /
AnnaBridge	145:64910690c574	283	uint32_t NMFI:1; /!< \brief bit: 27 Non-maskable FIQ (NMFI) support /
AnnaBridge	145:64910690c574	284	uint32_t TRE:1; /!< \brief bit: 28 TEX remap enable. /
AnnaBridge	145:64910690c574	285	uint32_t AFE:1; /!< \brief bit: 29 Access flag enable /
AnnaBridge	145:64910690c574	286	uint32_t TE:1; /!< \brief bit: 30 Thumb Exception enable /
AnnaBridge	145:64910690c574	287	uint32_t _reserved7:1; /!< \brief bit: 31 Reserved /
AnnaBridge	145:64910690c574	288	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	289	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	290	} SCTLR_Type;
AnnaBridge	145:64910690c574	291
AnnaBridge	145:64910690c574	292	#define SCTLR_TE_Pos 30U /!< \brief SCTLR: TE Position /
AnnaBridge	145:64910690c574	293	#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /!< \brief SCTLR: TE Mask /
AnnaBridge	145:64910690c574	294
AnnaBridge	145:64910690c574	295	#define SCTLR_AFE_Pos 29U /!< \brief SCTLR: AFE Position /
AnnaBridge	145:64910690c574	296	#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /!< \brief SCTLR: AFE Mask /
AnnaBridge	145:64910690c574	297
AnnaBridge	145:64910690c574	298	#define SCTLR_TRE_Pos 28U /!< \brief SCTLR: TRE Position /
AnnaBridge	145:64910690c574	299	#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /!< \brief SCTLR: TRE Mask /
AnnaBridge	145:64910690c574	300
AnnaBridge	145:64910690c574	301	#define SCTLR_NMFI_Pos 27U /!< \brief SCTLR: NMFI Position /
AnnaBridge	145:64910690c574	302	#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /!< \brief SCTLR: NMFI Mask /
AnnaBridge	145:64910690c574	303
AnnaBridge	145:64910690c574	304	#define SCTLR_EE_Pos 25U /!< \brief SCTLR: EE Position /
AnnaBridge	145:64910690c574	305	#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /!< \brief SCTLR: EE Mask /
AnnaBridge	145:64910690c574	306
AnnaBridge	145:64910690c574	307	#define SCTLR_VE_Pos 24U /!< \brief SCTLR: VE Position /
AnnaBridge	145:64910690c574	308	#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /!< \brief SCTLR: VE Mask /
AnnaBridge	145:64910690c574	309
AnnaBridge	145:64910690c574	310	#define SCTLR_U_Pos 22U /!< \brief SCTLR: U Position /
AnnaBridge	145:64910690c574	311	#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /!< \brief SCTLR: U Mask /
AnnaBridge	145:64910690c574	312
AnnaBridge	145:64910690c574	313	#define SCTLR_FI_Pos 21U /!< \brief SCTLR: FI Position /
AnnaBridge	145:64910690c574	314	#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /!< \brief SCTLR: FI Mask /
AnnaBridge	145:64910690c574	315
AnnaBridge	145:64910690c574	316	#define SCTLR_UWXN_Pos 20U /!< \brief SCTLR: UWXN Position /
AnnaBridge	145:64910690c574	317	#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /!< \brief SCTLR: UWXN Mask /
AnnaBridge	145:64910690c574	318
AnnaBridge	145:64910690c574	319	#define SCTLR_WXN_Pos 19U /!< \brief SCTLR: WXN Position /
AnnaBridge	145:64910690c574	320	#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /!< \brief SCTLR: WXN Mask /
AnnaBridge	145:64910690c574	321
AnnaBridge	145:64910690c574	322	#define SCTLR_HA_Pos 17U /!< \brief SCTLR: HA Position /
AnnaBridge	145:64910690c574	323	#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /!< \brief SCTLR: HA Mask /
AnnaBridge	145:64910690c574	324
AnnaBridge	145:64910690c574	325	#define SCTLR_RR_Pos 14U /!< \brief SCTLR: RR Position /
AnnaBridge	145:64910690c574	326	#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /!< \brief SCTLR: RR Mask /
AnnaBridge	145:64910690c574	327
AnnaBridge	145:64910690c574	328	#define SCTLR_V_Pos 13U /!< \brief SCTLR: V Position /
AnnaBridge	145:64910690c574	329	#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /!< \brief SCTLR: V Mask /
AnnaBridge	145:64910690c574	330
AnnaBridge	145:64910690c574	331	#define SCTLR_I_Pos 12U /!< \brief SCTLR: I Position /
AnnaBridge	145:64910690c574	332	#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /!< \brief SCTLR: I Mask /
AnnaBridge	145:64910690c574	333
AnnaBridge	145:64910690c574	334	#define SCTLR_Z_Pos 11U /!< \brief SCTLR: Z Position /
AnnaBridge	145:64910690c574	335	#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /!< \brief SCTLR: Z Mask /
AnnaBridge	145:64910690c574	336
AnnaBridge	145:64910690c574	337	#define SCTLR_SW_Pos 10U /!< \brief SCTLR: SW Position /
AnnaBridge	145:64910690c574	338	#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /!< \brief SCTLR: SW Mask /
AnnaBridge	145:64910690c574	339
AnnaBridge	145:64910690c574	340	#define SCTLR_B_Pos 7U /!< \brief SCTLR: B Position /
AnnaBridge	145:64910690c574	341	#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /!< \brief SCTLR: B Mask /
AnnaBridge	145:64910690c574	342
AnnaBridge	145:64910690c574	343	#define SCTLR_CP15BEN_Pos 5U /!< \brief SCTLR: CP15BEN Position /
AnnaBridge	145:64910690c574	344	#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /!< \brief SCTLR: CP15BEN Mask /
AnnaBridge	145:64910690c574	345
AnnaBridge	145:64910690c574	346	#define SCTLR_C_Pos 2U /!< \brief SCTLR: C Position /
AnnaBridge	145:64910690c574	347	#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /!< \brief SCTLR: C Mask /
AnnaBridge	145:64910690c574	348
AnnaBridge	145:64910690c574	349	#define SCTLR_A_Pos 1U /!< \brief SCTLR: A Position /
AnnaBridge	145:64910690c574	350	#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /!< \brief SCTLR: A Mask /
AnnaBridge	145:64910690c574	351
AnnaBridge	145:64910690c574	352	#define SCTLR_M_Pos 0U /!< \brief SCTLR: M Position /
AnnaBridge	145:64910690c574	353	#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /!< \brief SCTLR: M Mask /
AnnaBridge	145:64910690c574	354
AnnaBridge	145:64910690c574	355	/* CP15 Register CPACR */
AnnaBridge	145:64910690c574	356	typedef union
AnnaBridge	145:64910690c574	357	{
AnnaBridge	145:64910690c574	358	struct
AnnaBridge	145:64910690c574	359	{
AnnaBridge	145:64910690c574	360	uint32_t _reserved0:20; /!< \brief bit: 0..19 Reserved /
AnnaBridge	145:64910690c574	361	uint32_t cp10:2; /!< \brief bit:20..21 Access rights for coprocessor 10 /
AnnaBridge	145:64910690c574	362	uint32_t cp11:2; /!< \brief bit:22..23 Access rights for coprocessor 11 /
AnnaBridge	145:64910690c574	363	uint32_t _reserved1:6; /!< \brief bit:24..29 Reserved /
AnnaBridge	145:64910690c574	364	uint32_t D32DIS:1; /!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file /
AnnaBridge	145:64910690c574	365	uint32_t ASEDIS:1; /!< \brief bit: 31 Disable Advanced SIMD Functionality /
AnnaBridge	145:64910690c574	366	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	367	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	368	} CPACR_Type;
AnnaBridge	145:64910690c574	369
AnnaBridge	145:64910690c574	370	#define CPACR_ASEDIS_Pos 31U /!< \brief CPACR: ASEDIS Position /
AnnaBridge	145:64910690c574	371	#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /!< \brief CPACR: ASEDIS Mask /
AnnaBridge	145:64910690c574	372
AnnaBridge	145:64910690c574	373	#define CPACR_D32DIS_Pos 30U /!< \brief CPACR: D32DIS Position /
AnnaBridge	145:64910690c574	374	#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
AnnaBridge	145:64910690c574	375
AnnaBridge	145:64910690c574	376	#define CPACR_cp11_Pos 22U /!< \brief CPACR: cp11 Position /
AnnaBridge	145:64910690c574	377	#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /!< \brief CPACR: cp11 Mask /
AnnaBridge	145:64910690c574	378
AnnaBridge	145:64910690c574	379	#define CPACR_cp10_Pos 20U /!< \brief CPACR: cp10 Position /
AnnaBridge	145:64910690c574	380	#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /!< \brief CPACR: cp10 Mask /
AnnaBridge	145:64910690c574	381
AnnaBridge	145:64910690c574	382	/* CP15 Register DFSR */
AnnaBridge	145:64910690c574	383	typedef union
AnnaBridge	145:64910690c574	384	{
AnnaBridge	145:64910690c574	385	struct
AnnaBridge	145:64910690c574	386	{
AnnaBridge	145:64910690c574	387	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	145:64910690c574	388	uint32_t Domain:4; /!< \brief bit: 4.. 7 Fault on which domain /
AnnaBridge	145:64910690c574	389	uint32_t _reserved0:2; /!< \brief bit: 8.. 9 Reserved /
AnnaBridge	145:64910690c574	390	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	145:64910690c574	391	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
AnnaBridge	145:64910690c574	392	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	145:64910690c574	393	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
AnnaBridge	145:64910690c574	394	uint32_t _reserved1:18; /!< \brief bit:14..31 Reserved /
AnnaBridge	145:64910690c574	395	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	396	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	397	} DFSR_Type;
AnnaBridge	145:64910690c574	398
AnnaBridge	145:64910690c574	399	#define DFSR_CM_Pos 13U /!< \brief DFSR: CM Position /
AnnaBridge	145:64910690c574	400	#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /!< \brief DFSR: CM Mask /
AnnaBridge	145:64910690c574	401
AnnaBridge	145:64910690c574	402	#define DFSR_Ext_Pos 12U /!< \brief DFSR: Ext Position /
AnnaBridge	145:64910690c574	403	#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /!< \brief DFSR: Ext Mask /
AnnaBridge	145:64910690c574	404
AnnaBridge	145:64910690c574	405	#define DFSR_WnR_Pos 11U /!< \brief DFSR: WnR Position /
AnnaBridge	145:64910690c574	406	#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /!< \brief DFSR: WnR Mask /
AnnaBridge	145:64910690c574	407
AnnaBridge	145:64910690c574	408	#define DFSR_FS1_Pos 10U /!< \brief DFSR: FS1 Position /
AnnaBridge	145:64910690c574	409	#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /!< \brief DFSR: FS1 Mask /
AnnaBridge	145:64910690c574	410
AnnaBridge	145:64910690c574	411	#define DFSR_Domain_Pos 4U /!< \brief DFSR: Domain Position /
AnnaBridge	145:64910690c574	412	#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /!< \brief DFSR: Domain Mask /
AnnaBridge	145:64910690c574	413
AnnaBridge	145:64910690c574	414	#define DFSR_FS0_Pos 0U /!< \brief DFSR: FS0 Position /
AnnaBridge	145:64910690c574	415	#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /!< \brief DFSR: FS0 Mask /
AnnaBridge	145:64910690c574	416
AnnaBridge	145:64910690c574	417	/* CP15 Register IFSR */
AnnaBridge	145:64910690c574	418	typedef union
AnnaBridge	145:64910690c574	419	{
AnnaBridge	145:64910690c574	420	struct
AnnaBridge	145:64910690c574	421	{
AnnaBridge	145:64910690c574	422	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	145:64910690c574	423	uint32_t _reserved0:6; /!< \brief bit: 4.. 9 Reserved /
AnnaBridge	145:64910690c574	424	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	145:64910690c574	425	uint32_t _reserved1:1; /!< \brief bit: 11 Reserved /
AnnaBridge	145:64910690c574	426	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	145:64910690c574	427	uint32_t _reserved2:19; /!< \brief bit:13..31 Reserved /
AnnaBridge	145:64910690c574	428	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	429	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	430	} IFSR_Type;
AnnaBridge	145:64910690c574	431
AnnaBridge	145:64910690c574	432	#define IFSR_ExT_Pos 12U /!< \brief IFSR: ExT Position /
AnnaBridge	145:64910690c574	433	#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /!< \brief IFSR: ExT Mask /
AnnaBridge	145:64910690c574	434
AnnaBridge	145:64910690c574	435	#define IFSR_FS1_Pos 10U /!< \brief IFSR: FS1 Position /
AnnaBridge	145:64910690c574	436	#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /!< \brief IFSR: FS1 Mask /
AnnaBridge	145:64910690c574	437
AnnaBridge	145:64910690c574	438	#define IFSR_FS0_Pos 0U /!< \brief IFSR: FS0 Position /
AnnaBridge	145:64910690c574	439	#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /!< \brief IFSR: FS0 Mask /
AnnaBridge	145:64910690c574	440
AnnaBridge	145:64910690c574	441	/* CP15 Register ISR */
AnnaBridge	145:64910690c574	442	typedef union
AnnaBridge	145:64910690c574	443	{
AnnaBridge	145:64910690c574	444	struct
AnnaBridge	145:64910690c574	445	{
AnnaBridge	145:64910690c574	446	uint32_t _reserved0:6; /!< \brief bit: 0.. 5 Reserved /
AnnaBridge	145:64910690c574	447	uint32_t F:1; /!< \brief bit: 6 FIQ pending bit /
AnnaBridge	145:64910690c574	448	uint32_t I:1; /!< \brief bit: 7 IRQ pending bit /
AnnaBridge	145:64910690c574	449	uint32_t A:1; /!< \brief bit: 8 External abort pending bit /
AnnaBridge	145:64910690c574	450	uint32_t _reserved1:23; /!< \brief bit:14..31 Reserved /
AnnaBridge	145:64910690c574	451	} b; /!< \brief Structure used for bit access /
AnnaBridge	145:64910690c574	452	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	145:64910690c574	453	} ISR_Type;
AnnaBridge	145:64910690c574	454
AnnaBridge	145:64910690c574	455	#define ISR_A_Pos 13U /!< \brief ISR: A Position /
AnnaBridge	145:64910690c574	456	#define ISR_A_Msk (1UL << ISR_A_Pos) /!< \brief ISR: A Mask /
AnnaBridge	145:64910690c574	457
AnnaBridge	145:64910690c574	458	#define ISR_I_Pos 12U /!< \brief ISR: I Position /
AnnaBridge	145:64910690c574	459	#define ISR_I_Msk (1UL << ISR_I_Pos) /!< \brief ISR: I Mask /
AnnaBridge	145:64910690c574	460
AnnaBridge	145:64910690c574	461	#define ISR_F_Pos 11U /!< \brief ISR: F Position /
AnnaBridge	145:64910690c574	462	#define ISR_F_Msk (1UL << ISR_F_Pos) /!< \brief ISR: F Mask /
AnnaBridge	145:64910690c574	463
AnnaBridge	145:64910690c574	464
AnnaBridge	145:64910690c574	465	/**
AnnaBridge	145:64910690c574	466	\brief Union type to access the L2C_310 Cache Controller.
AnnaBridge	145:64910690c574	467	*/
AnnaBridge	145:64910690c574	468	#if (__L2C_PRESENT == 1U)
AnnaBridge	145:64910690c574	469	typedef struct
AnnaBridge	145:64910690c574	470	{
AnnaBridge	145:64910690c574	471	__I uint32_t CACHE_ID; /!< \brief Offset: 0x0000 Cache ID Register /
AnnaBridge	145:64910690c574	472	__I uint32_t CACHE_TYPE; /!< \brief Offset: 0x0004 Cache Type Register /
AnnaBridge	145:64910690c574	473	uint32_t RESERVED0[0x3e];
AnnaBridge	145:64910690c574	474	__IO uint32_t CONTROL; /!< \brief Offset: 0x0100 Control Register /
AnnaBridge	145:64910690c574	475	__IO uint32_t AUX_CNT; /!< \brief Offset: 0x0104 Auxiliary Control /
AnnaBridge	145:64910690c574	476	uint32_t RESERVED1[0x3e];
AnnaBridge	145:64910690c574	477	__IO uint32_t EVENT_CONTROL; /!< \brief Offset: 0x0200 Event Counter Control /
AnnaBridge	145:64910690c574	478	__IO uint32_t EVENT_COUNTER1_CONF; /!< \brief Offset: 0x0204 Event Counter 1 Configuration /
AnnaBridge	145:64910690c574	479	__IO uint32_t EVENT_COUNTER0_CONF; /!< \brief Offset: 0x0208 Event Counter 1 Configuration /
AnnaBridge	145:64910690c574	480	uint32_t RESERVED2[0x2];
AnnaBridge	145:64910690c574	481	__IO uint32_t INTERRUPT_MASK; /!< \brief Offset: 0x0214 Interrupt Mask /
AnnaBridge	145:64910690c574	482	__I uint32_t MASKED_INT_STATUS; /!< \brief Offset: 0x0218 Masked Interrupt Status /
AnnaBridge	145:64910690c574	483	__I uint32_t RAW_INT_STATUS; /!< \brief Offset: 0x021c Raw Interrupt Status /
AnnaBridge	145:64910690c574	484	__O uint32_t INTERRUPT_CLEAR; /!< \brief Offset: 0x0220 Interrupt Clear /
AnnaBridge	145:64910690c574	485	uint32_t RESERVED3[0x143];
AnnaBridge	145:64910690c574	486	__IO uint32_t CACHE_SYNC; /!< \brief Offset: 0x0730 Cache Sync /
AnnaBridge	145:64910690c574	487	uint32_t RESERVED4[0xf];
AnnaBridge	145:64910690c574	488	__IO uint32_t INV_LINE_PA; /!< \brief Offset: 0x0770 Invalidate Line By PA /
AnnaBridge	145:64910690c574	489	uint32_t RESERVED6[2];
AnnaBridge	145:64910690c574	490	__IO uint32_t INV_WAY; /!< \brief Offset: 0x077c Invalidate by Way /
AnnaBridge	145:64910690c574	491	uint32_t RESERVED5[0xc];
AnnaBridge	145:64910690c574	492	__IO uint32_t CLEAN_LINE_PA; /!< \brief Offset: 0x07b0 Clean Line by PA /
AnnaBridge	145:64910690c574	493	uint32_t RESERVED7[1];
AnnaBridge	145:64910690c574	494	__IO uint32_t CLEAN_LINE_INDEX_WAY; /!< \brief Offset: 0x07b8 Clean Line by Index/Way /
AnnaBridge	145:64910690c574	495	__IO uint32_t CLEAN_WAY; /!< \brief Offset: 0x07bc Clean by Way /
AnnaBridge	145:64910690c574	496	uint32_t RESERVED8[0xc];
AnnaBridge	145:64910690c574	497	__IO uint32_t CLEAN_INV_LINE_PA; /!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA /
AnnaBridge	145:64910690c574	498	uint32_t RESERVED9[1];
AnnaBridge	145:64910690c574	499	__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way /
AnnaBridge	145:64910690c574	500	__IO uint32_t CLEAN_INV_WAY; /!< \brief Offset: 0x07fc Clean and Invalidate by Way /
AnnaBridge	145:64910690c574	501	uint32_t RESERVED10[0x40];
AnnaBridge	145:64910690c574	502	__IO uint32_t DATA_LOCK_0_WAY; /!< \brief Offset: 0x0900 Data Lockdown 0 by Way /
AnnaBridge	145:64910690c574	503	__IO uint32_t INST_LOCK_0_WAY; /!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way /
AnnaBridge	145:64910690c574	504	__IO uint32_t DATA_LOCK_1_WAY; /!< \brief Offset: 0x0908 Data Lockdown 1 by Way /
AnnaBridge	145:64910690c574	505	__IO uint32_t INST_LOCK_1_WAY; /!< \brief Offset: 0x090c Instruction Lockdown 1 by Way /
AnnaBridge	145:64910690c574	506	__IO uint32_t DATA_LOCK_2_WAY; /!< \brief Offset: 0x0910 Data Lockdown 2 by Way /
AnnaBridge	145:64910690c574	507	__IO uint32_t INST_LOCK_2_WAY; /!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way /
AnnaBridge	145:64910690c574	508	__IO uint32_t DATA_LOCK_3_WAY; /!< \brief Offset: 0x0918 Data Lockdown 3 by Way /
AnnaBridge	145:64910690c574	509	__IO uint32_t INST_LOCK_3_WAY; /!< \brief Offset: 0x091c Instruction Lockdown 3 by Way /
AnnaBridge	145:64910690c574	510	__IO uint32_t DATA_LOCK_4_WAY; /!< \brief Offset: 0x0920 Data Lockdown 4 by Way /
AnnaBridge	145:64910690c574	511	__IO uint32_t INST_LOCK_4_WAY; /!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way /
AnnaBridge	145:64910690c574	512	__IO uint32_t DATA_LOCK_5_WAY; /!< \brief Offset: 0x0928 Data Lockdown 5 by Way /
AnnaBridge	145:64910690c574	513	__IO uint32_t INST_LOCK_5_WAY; /!< \brief Offset: 0x092c Instruction Lockdown 5 by Way /
AnnaBridge	145:64910690c574	514	__IO uint32_t DATA_LOCK_6_WAY; /!< \brief Offset: 0x0930 Data Lockdown 5 by Way /
AnnaBridge	145:64910690c574	515	__IO uint32_t INST_LOCK_6_WAY; /!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way /
AnnaBridge	145:64910690c574	516	__IO uint32_t DATA_LOCK_7_WAY; /!< \brief Offset: 0x0938 Data Lockdown 6 by Way /
AnnaBridge	145:64910690c574	517	__IO uint32_t INST_LOCK_7_WAY; /!< \brief Offset: 0x093c Instruction Lockdown 6 by Way /
AnnaBridge	145:64910690c574	518	uint32_t RESERVED11[0x4];
AnnaBridge	145:64910690c574	519	__IO uint32_t LOCK_LINE_EN; /!< \brief Offset: 0x0950 Lockdown by Line Enable /
AnnaBridge	145:64910690c574	520	__IO uint32_t UNLOCK_ALL_BY_WAY; /!< \brief Offset: 0x0954 Unlock All Lines by Way /
AnnaBridge	145:64910690c574	521	uint32_t RESERVED12[0xaa];
AnnaBridge	145:64910690c574	522	__IO uint32_t ADDRESS_FILTER_START; /!< \brief Offset: 0x0c00 Address Filtering Start /
AnnaBridge	145:64910690c574	523	__IO uint32_t ADDRESS_FILTER_END; /!< \brief Offset: 0x0c04 Address Filtering End /
AnnaBridge	145:64910690c574	524	uint32_t RESERVED13[0xce];
AnnaBridge	145:64910690c574	525	__IO uint32_t DEBUG_CONTROL; /!< \brief Offset: 0x0f40 Debug Control Register /
AnnaBridge	145:64910690c574	526	} L2C_310_TypeDef;
AnnaBridge	145:64910690c574	527
AnnaBridge	145:64910690c574	528	#define L2C_310 ((L2C_310_TypeDef )L2C_310_BASE) /!< \brief L2C_310 Declaration */
AnnaBridge	145:64910690c574	529	#endif
AnnaBridge	145:64910690c574	530
AnnaBridge	145:64910690c574	531	#if (__GIC_PRESENT == 1U)
AnnaBridge	145:64910690c574	532	/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge	145:64910690c574	533	*/
AnnaBridge	145:64910690c574	534	typedef struct
AnnaBridge	145:64910690c574	535	{
AnnaBridge	145:64910690c574	536	__IO uint32_t ICDDCR;
AnnaBridge	145:64910690c574	537	__I uint32_t ICDICTR;
AnnaBridge	145:64910690c574	538	__I uint32_t ICDIIDR;
AnnaBridge	145:64910690c574	539	uint32_t RESERVED0[29];
AnnaBridge	145:64910690c574	540	__IO uint32_t ICDISR[32];
AnnaBridge	145:64910690c574	541	__IO uint32_t ICDISER[32];
AnnaBridge	145:64910690c574	542	__IO uint32_t ICDICER[32];
AnnaBridge	145:64910690c574	543	__IO uint32_t ICDISPR[32];
AnnaBridge	145:64910690c574	544	__IO uint32_t ICDICPR[32];
AnnaBridge	145:64910690c574	545	__I uint32_t ICDABR[32];
AnnaBridge	145:64910690c574	546	uint32_t RESERVED1[32];
AnnaBridge	145:64910690c574	547	__IO uint32_t ICDIPR[256];
AnnaBridge	145:64910690c574	548	__IO uint32_t ICDIPTR[256];
AnnaBridge	145:64910690c574	549	__IO uint32_t ICDICFR[64];
AnnaBridge	145:64910690c574	550	uint32_t RESERVED2[128];
AnnaBridge	145:64910690c574	551	__IO uint32_t ICDSGIR;
AnnaBridge	145:64910690c574	552	} GICDistributor_Type;
AnnaBridge	145:64910690c574	553
AnnaBridge	145:64910690c574	554	#define GICDistributor ((GICDistributor_Type ) GIC_DISTRIBUTOR_BASE ) /!< GIC Distributor configuration struct */
AnnaBridge	145:64910690c574	555
AnnaBridge	145:64910690c574	556	/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge	145:64910690c574	557	*/
AnnaBridge	145:64910690c574	558	typedef struct
AnnaBridge	145:64910690c574	559	{
AnnaBridge	145:64910690c574	560	__IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
AnnaBridge	145:64910690c574	561	__IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
AnnaBridge	145:64910690c574	562	__IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
AnnaBridge	145:64910690c574	563	__I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
AnnaBridge	145:64910690c574	564	__IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
AnnaBridge	145:64910690c574	565	__I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
AnnaBridge	145:64910690c574	566	__I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
AnnaBridge	145:64910690c574	567	__IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
AnnaBridge	145:64910690c574	568	uint32_t RESERVED[55];
AnnaBridge	145:64910690c574	569	__I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
AnnaBridge	145:64910690c574	570	} GICInterface_Type;
AnnaBridge	145:64910690c574	571
AnnaBridge	145:64910690c574	572	#define GICInterface ((GICInterface_Type ) GIC_INTERFACE_BASE ) /!< GIC Interface configuration struct */
AnnaBridge	145:64910690c574	573	#endif
AnnaBridge	145:64910690c574	574
AnnaBridge	145:64910690c574	575	#if (__TIM_PRESENT == 1U)
AnnaBridge	145:64910690c574	576	#if ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
AnnaBridge	145:64910690c574	577	/** \brief Structure type to access the Private Timer
AnnaBridge	145:64910690c574	578	*/
AnnaBridge	145:64910690c574	579	typedef struct
AnnaBridge	145:64910690c574	580	{
AnnaBridge	145:64910690c574	581	__IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
AnnaBridge	145:64910690c574	582	__IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
AnnaBridge	145:64910690c574	583	__IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
AnnaBridge	145:64910690c574	584	__IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
AnnaBridge	145:64910690c574	585	uint32_t RESERVED[8];
AnnaBridge	145:64910690c574	586	__IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
AnnaBridge	145:64910690c574	587	__IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
AnnaBridge	145:64910690c574	588	__IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
AnnaBridge	145:64910690c574	589	__IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
AnnaBridge	145:64910690c574	590	__IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
AnnaBridge	145:64910690c574	591	__I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
AnnaBridge	145:64910690c574	592	} Timer_Type;
AnnaBridge	145:64910690c574	593	#define PTIM ((Timer_Type ) TIMER_BASE ) /!< \brief Timer configuration struct */
AnnaBridge	145:64910690c574	594	#endif
AnnaBridge	145:64910690c574	595	#endif
AnnaBridge	145:64910690c574	596
AnnaBridge	145:64910690c574	597	/*******************************************************************************
AnnaBridge	145:64910690c574	598	* Hardware Abstraction Layer
AnnaBridge	145:64910690c574	599	Core Function Interface contains:
AnnaBridge	145:64910690c574	600	- L1 Cache Functions
AnnaBridge	145:64910690c574	601	- L2C-310 Cache Controller Functions
AnnaBridge	145:64910690c574	602	- PL1 Timer Functions
AnnaBridge	145:64910690c574	603	- GIC Functions
AnnaBridge	145:64910690c574	604	- MMU Functions
AnnaBridge	145:64910690c574	605	******************************************************************************/
AnnaBridge	145:64910690c574	606
AnnaBridge	145:64910690c574	607	/* ########################## L1 Cache functions ################################# */
AnnaBridge	145:64910690c574	608
AnnaBridge	145:64910690c574	609	/** \brief Enable Caches
AnnaBridge	145:64910690c574	610
AnnaBridge	145:64910690c574	611	Enable Caches
AnnaBridge	145:64910690c574	612	*/
AnnaBridge	145:64910690c574	613	__STATIC_INLINE void L1C_EnableCaches(void) {
AnnaBridge	145:64910690c574	614	// Set I bit 12 to enable I Cache
AnnaBridge	145:64910690c574	615	// Set C bit 2 to enable D Cache
AnnaBridge	145:64910690c574	616	__set_SCTLR( __get_SCTLR() \| (1 << 12) \| (1 << 2));
AnnaBridge	145:64910690c574	617	}
AnnaBridge	145:64910690c574	618
AnnaBridge	145:64910690c574	619	/** \brief Disable Caches
AnnaBridge	145:64910690c574	620
AnnaBridge	145:64910690c574	621	Disable Caches
AnnaBridge	145:64910690c574	622	*/
AnnaBridge	145:64910690c574	623	__STATIC_INLINE void L1C_DisableCaches(void) {
AnnaBridge	145:64910690c574	624	// Clear I bit 12 to disable I Cache
AnnaBridge	145:64910690c574	625	// Clear C bit 2 to disable D Cache
AnnaBridge	145:64910690c574	626	__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge	145:64910690c574	627	__ISB();
AnnaBridge	145:64910690c574	628	}
AnnaBridge	145:64910690c574	629
AnnaBridge	145:64910690c574	630	/** \brief Enable BTAC
AnnaBridge	145:64910690c574	631
AnnaBridge	145:64910690c574	632	Enable BTAC
AnnaBridge	145:64910690c574	633	*/
AnnaBridge	145:64910690c574	634	__STATIC_INLINE void L1C_EnableBTAC(void) {
AnnaBridge	145:64910690c574	635	// Set Z bit 11 to enable branch prediction
AnnaBridge	145:64910690c574	636	__set_SCTLR( __get_SCTLR() \| (1 << 11));
AnnaBridge	145:64910690c574	637	__ISB();
AnnaBridge	145:64910690c574	638	}
AnnaBridge	145:64910690c574	639
AnnaBridge	145:64910690c574	640	/** \brief Disable BTAC
AnnaBridge	145:64910690c574	641
AnnaBridge	145:64910690c574	642	Disable BTAC
AnnaBridge	145:64910690c574	643	*/
AnnaBridge	145:64910690c574	644	__STATIC_INLINE void L1C_DisableBTAC(void) {
AnnaBridge	145:64910690c574	645	// Clear Z bit 11 to disable branch prediction
AnnaBridge	145:64910690c574	646	__set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge	145:64910690c574	647	}
AnnaBridge	145:64910690c574	648
AnnaBridge	145:64910690c574	649	/** \brief Invalidate entire branch predictor array
AnnaBridge	145:64910690c574	650
AnnaBridge	145:64910690c574	651	BPIALL. Branch Predictor Invalidate All.
AnnaBridge	145:64910690c574	652	*/
AnnaBridge	145:64910690c574	653
AnnaBridge	145:64910690c574	654	__STATIC_INLINE void L1C_InvalidateBTAC(void) {
AnnaBridge	145:64910690c574	655	__set_BPIALL(0);
AnnaBridge	145:64910690c574	656	__DSB(); //ensure completion of the invalidation
AnnaBridge	145:64910690c574	657	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	145:64910690c574	658	}
AnnaBridge	145:64910690c574	659
AnnaBridge	145:64910690c574	660	/** \brief Invalidate the whole I$
AnnaBridge	145:64910690c574	661
AnnaBridge	145:64910690c574	662	ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge	145:64910690c574	663	*/
AnnaBridge	145:64910690c574	664	__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge	145:64910690c574	665	__set_ICIALLU(0);
AnnaBridge	145:64910690c574	666	__DSB(); //ensure completion of the invalidation
AnnaBridge	145:64910690c574	667	__ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge	145:64910690c574	668	}
AnnaBridge	145:64910690c574	669
AnnaBridge	145:64910690c574	670	/** \brief Clean D$ by MVA
AnnaBridge	145:64910690c574	671
AnnaBridge	145:64910690c574	672	DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge	145:64910690c574	673	*/
AnnaBridge	145:64910690c574	674	__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge	145:64910690c574	675	__set_DCCMVAC((uint32_t)va);
AnnaBridge	145:64910690c574	676	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	145:64910690c574	677	}
AnnaBridge	145:64910690c574	678
AnnaBridge	145:64910690c574	679	/** \brief Invalidate D$ by MVA
AnnaBridge	145:64910690c574	680
AnnaBridge	145:64910690c574	681	DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge	145:64910690c574	682	*/
AnnaBridge	145:64910690c574	683	__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge	145:64910690c574	684	__set_DCIMVAC((uint32_t)va);
AnnaBridge	145:64910690c574	685	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	145:64910690c574	686	}
AnnaBridge	145:64910690c574	687
AnnaBridge	145:64910690c574	688	/** \brief Clean and Invalidate D$ by MVA
AnnaBridge	145:64910690c574	689
AnnaBridge	145:64910690c574	690	DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge	145:64910690c574	691	*/
AnnaBridge	145:64910690c574	692	__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge	145:64910690c574	693	__set_DCCIMVAC((uint32_t)va);
AnnaBridge	145:64910690c574	694	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	145:64910690c574	695	}
AnnaBridge	145:64910690c574	696
AnnaBridge	145:64910690c574	697	/** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge	145:64910690c574	698
AnnaBridge	145:64910690c574	699	Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge	145:64910690c574	700	*/
AnnaBridge	145:64910690c574	701	__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge	145:64910690c574	702	__L1C_CleanInvalidateCache(op); // compiler specific call
AnnaBridge	145:64910690c574	703	}
AnnaBridge	145:64910690c574	704
AnnaBridge	145:64910690c574	705
AnnaBridge	145:64910690c574	706	/** \brief Invalidate the whole D$
AnnaBridge	145:64910690c574	707
AnnaBridge	145:64910690c574	708	DCISW. Invalidate by Set/Way
AnnaBridge	145:64910690c574	709	*/
AnnaBridge	145:64910690c574	710
AnnaBridge	145:64910690c574	711	__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge	145:64910690c574	712	L1C_CleanInvalidateCache(0);
AnnaBridge	145:64910690c574	713	}
AnnaBridge	145:64910690c574	714
AnnaBridge	145:64910690c574	715	/** \brief Clean the whole D$
AnnaBridge	145:64910690c574	716
AnnaBridge	145:64910690c574	717	DCCSW. Clean by Set/Way
AnnaBridge	145:64910690c574	718	*/
AnnaBridge	145:64910690c574	719
AnnaBridge	145:64910690c574	720	__STATIC_INLINE void L1C_CleanDCacheAll(void) {
AnnaBridge	145:64910690c574	721	L1C_CleanInvalidateCache(1);
AnnaBridge	145:64910690c574	722	}
AnnaBridge	145:64910690c574	723
AnnaBridge	145:64910690c574	724	/** \brief Clean and invalidate the whole D$
AnnaBridge	145:64910690c574	725
AnnaBridge	145:64910690c574	726	DCCISW. Clean and Invalidate by Set/Way
AnnaBridge	145:64910690c574	727	*/
AnnaBridge	145:64910690c574	728
AnnaBridge	145:64910690c574	729	__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge	145:64910690c574	730	L1C_CleanInvalidateCache(2);
AnnaBridge	145:64910690c574	731	}
AnnaBridge	145:64910690c574	732
AnnaBridge	145:64910690c574	733
AnnaBridge	145:64910690c574	734	/* ########################## L2 Cache functions ################################# */
AnnaBridge	145:64910690c574	735	#if (__L2C_PRESENT == 1U)
AnnaBridge	145:64910690c574	736	//Cache Sync operation
AnnaBridge	145:64910690c574	737	__STATIC_INLINE void L2C_Sync(void)
AnnaBridge	145:64910690c574	738	{
AnnaBridge	145:64910690c574	739	L2C_310->CACHE_SYNC = 0x0;
AnnaBridge	145:64910690c574	740	}
AnnaBridge	145:64910690c574	741
AnnaBridge	145:64910690c574	742	//return Cache controller cache ID
AnnaBridge	145:64910690c574	743	__STATIC_INLINE int L2C_GetID (void)
AnnaBridge	145:64910690c574	744	{
AnnaBridge	145:64910690c574	745	return L2C_310->CACHE_ID;
AnnaBridge	145:64910690c574	746	}
AnnaBridge	145:64910690c574	747
AnnaBridge	145:64910690c574	748	//return Cache controller cache Type
AnnaBridge	145:64910690c574	749	__STATIC_INLINE int L2C_GetType (void)
AnnaBridge	145:64910690c574	750	{
AnnaBridge	145:64910690c574	751	return L2C_310->CACHE_TYPE;
AnnaBridge	145:64910690c574	752	}
AnnaBridge	145:64910690c574	753
AnnaBridge	145:64910690c574	754	//Invalidate all cache by way
AnnaBridge	145:64910690c574	755	__STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge	145:64910690c574	756	{
AnnaBridge	145:64910690c574	757	unsigned int assoc;
AnnaBridge	145:64910690c574	758
AnnaBridge	145:64910690c574	759	if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge	145:64910690c574	760	assoc = 16;
AnnaBridge	145:64910690c574	761	else
AnnaBridge	145:64910690c574	762	assoc = 8;
AnnaBridge	145:64910690c574	763
AnnaBridge	145:64910690c574	764	L2C_310->INV_WAY = (1 << assoc) - 1;
AnnaBridge	145:64910690c574	765	while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge	145:64910690c574	766
AnnaBridge	145:64910690c574	767	L2C_Sync();
AnnaBridge	145:64910690c574	768	}
AnnaBridge	145:64910690c574	769
AnnaBridge	145:64910690c574	770	//Clean and Invalidate all cache by way
AnnaBridge	145:64910690c574	771	__STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge	145:64910690c574	772	{
AnnaBridge	145:64910690c574	773	unsigned int assoc;
AnnaBridge	145:64910690c574	774
AnnaBridge	145:64910690c574	775	if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge	145:64910690c574	776	assoc = 16;
AnnaBridge	145:64910690c574	777	else
AnnaBridge	145:64910690c574	778	assoc = 8;
AnnaBridge	145:64910690c574	779
AnnaBridge	145:64910690c574	780	L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
AnnaBridge	145:64910690c574	781	while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge	145:64910690c574	782
AnnaBridge	145:64910690c574	783	L2C_Sync();
AnnaBridge	145:64910690c574	784	}
AnnaBridge	145:64910690c574	785
AnnaBridge	145:64910690c574	786	//Enable Cache
AnnaBridge	145:64910690c574	787	__STATIC_INLINE void L2C_Enable(void)
AnnaBridge	145:64910690c574	788	{
AnnaBridge	145:64910690c574	789	L2C_310->CONTROL = 0;
AnnaBridge	145:64910690c574	790	L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge	145:64910690c574	791	L2C_310->DEBUG_CONTROL = 0;
AnnaBridge	145:64910690c574	792	L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge	145:64910690c574	793	L2C_310->CACHE_SYNC = 0;
AnnaBridge	145:64910690c574	794	L2C_310->CONTROL = 0x01;
AnnaBridge	145:64910690c574	795	L2C_Sync();
AnnaBridge	145:64910690c574	796	}
AnnaBridge	145:64910690c574	797	//Disable Cache
AnnaBridge	145:64910690c574	798	__STATIC_INLINE void L2C_Disable(void)
AnnaBridge	145:64910690c574	799	{
AnnaBridge	145:64910690c574	800	L2C_310->CONTROL = 0x00;
AnnaBridge	145:64910690c574	801	L2C_Sync();
AnnaBridge	145:64910690c574	802	}
AnnaBridge	145:64910690c574	803
AnnaBridge	145:64910690c574	804	//Invalidate cache by physical address
AnnaBridge	145:64910690c574	805	__STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge	145:64910690c574	806	{
AnnaBridge	145:64910690c574	807	L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge	145:64910690c574	808	L2C_Sync();
AnnaBridge	145:64910690c574	809	}
AnnaBridge	145:64910690c574	810
AnnaBridge	145:64910690c574	811	//Clean cache by physical address
AnnaBridge	145:64910690c574	812	__STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge	145:64910690c574	813	{
AnnaBridge	145:64910690c574	814	L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge	145:64910690c574	815	L2C_Sync();
AnnaBridge	145:64910690c574	816	}
AnnaBridge	145:64910690c574	817
AnnaBridge	145:64910690c574	818	//Clean and invalidate cache by physical address
AnnaBridge	145:64910690c574	819	__STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge	145:64910690c574	820	{
AnnaBridge	145:64910690c574	821	L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge	145:64910690c574	822	L2C_Sync();
AnnaBridge	145:64910690c574	823	}
AnnaBridge	145:64910690c574	824	#endif
AnnaBridge	145:64910690c574	825
AnnaBridge	145:64910690c574	826	/* ########################## GIC functions ###################################### */
AnnaBridge	145:64910690c574	827	#if (__GIC_PRESENT == 1U)
AnnaBridge	145:64910690c574	828
AnnaBridge	145:64910690c574	829	__STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge	145:64910690c574	830	{
AnnaBridge	145:64910690c574	831	GICDistributor->ICDDCR \|= 1; //enable distributor
AnnaBridge	145:64910690c574	832	}
AnnaBridge	145:64910690c574	833
AnnaBridge	145:64910690c574	834	__STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge	145:64910690c574	835	{
AnnaBridge	145:64910690c574	836	GICDistributor->ICDDCR &=~1; //disable distributor
AnnaBridge	145:64910690c574	837	}
AnnaBridge	145:64910690c574	838
AnnaBridge	145:64910690c574	839	__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge	145:64910690c574	840	{
AnnaBridge	145:64910690c574	841	return (uint32_t)(GICDistributor->ICDICTR);
AnnaBridge	145:64910690c574	842	}
AnnaBridge	145:64910690c574	843
AnnaBridge	145:64910690c574	844	__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge	145:64910690c574	845	{
AnnaBridge	145:64910690c574	846	return (uint32_t)(GICDistributor->ICDIIDR);
AnnaBridge	145:64910690c574	847	}
AnnaBridge	145:64910690c574	848
AnnaBridge	145:64910690c574	849	__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge	145:64910690c574	850	{
AnnaBridge	145:64910690c574	851	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge	145:64910690c574	852	field += IRQn % 4;
AnnaBridge	145:64910690c574	853	*field = (char)cpu_target & 0xf;
AnnaBridge	145:64910690c574	854	}
AnnaBridge	145:64910690c574	855
AnnaBridge	145:64910690c574	856	__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
AnnaBridge	145:64910690c574	857	{
AnnaBridge	145:64910690c574	858	uint32_t i, num_irq;
AnnaBridge	145:64910690c574	859
AnnaBridge	145:64910690c574	860	//Get the maximum number of interrupts that the GIC supports
AnnaBridge	145:64910690c574	861	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge	145:64910690c574	862
AnnaBridge	145:64910690c574	863	for (i = 0; i < (num_irq/16); i++)
AnnaBridge	145:64910690c574	864	{
AnnaBridge	145:64910690c574	865	GICDistributor->ICDISPR[i] = *ICDICFRn++;
AnnaBridge	145:64910690c574	866	}
AnnaBridge	145:64910690c574	867	}
AnnaBridge	145:64910690c574	868
AnnaBridge	145:64910690c574	869	__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	870	{
AnnaBridge	145:64910690c574	871	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge	145:64910690c574	872	field += IRQn % 4;
AnnaBridge	145:64910690c574	873	return ((uint32_t)*field & 0xf);
AnnaBridge	145:64910690c574	874	}
AnnaBridge	145:64910690c574	875
AnnaBridge	145:64910690c574	876	__STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge	145:64910690c574	877	{
AnnaBridge	145:64910690c574	878	GICInterface->ICCICR \|= 1; //enable interface
AnnaBridge	145:64910690c574	879	}
AnnaBridge	145:64910690c574	880
AnnaBridge	145:64910690c574	881	__STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge	145:64910690c574	882	{
AnnaBridge	145:64910690c574	883	GICInterface->ICCICR &=~1; //disable distributor
AnnaBridge	145:64910690c574	884	}
AnnaBridge	145:64910690c574	885
AnnaBridge	145:64910690c574	886	__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge	145:64910690c574	887	{
AnnaBridge	145:64910690c574	888	return (IRQn_Type)(GICInterface->ICCIAR);
AnnaBridge	145:64910690c574	889	}
AnnaBridge	145:64910690c574	890
AnnaBridge	145:64910690c574	891	__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	892	{
AnnaBridge	145:64910690c574	893	GICInterface->ICCEOIR = IRQn;
AnnaBridge	145:64910690c574	894	}
AnnaBridge	145:64910690c574	895
AnnaBridge	145:64910690c574	896	__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	897	{
AnnaBridge	145:64910690c574	898	GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	145:64910690c574	899	}
AnnaBridge	145:64910690c574	900
AnnaBridge	145:64910690c574	901	__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	902	{
AnnaBridge	145:64910690c574	903	GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	145:64910690c574	904	}
AnnaBridge	145:64910690c574	905
AnnaBridge	145:64910690c574	906	__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	907	{
AnnaBridge	145:64910690c574	908	GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	145:64910690c574	909	}
AnnaBridge	145:64910690c574	910
AnnaBridge	145:64910690c574	911	__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	912	{
AnnaBridge	145:64910690c574	913	GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	145:64910690c574	914	}
AnnaBridge	145:64910690c574	915
AnnaBridge	145:64910690c574	916	__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
AnnaBridge	145:64910690c574	917	{
AnnaBridge	145:64910690c574	918	// Word-size read/writes must be used to access this register
AnnaBridge	145:64910690c574	919	volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
AnnaBridge	145:64910690c574	920	unsigned bit_shift = (IRQn % 16)<<1;
AnnaBridge	145:64910690c574	921	unsigned int save_word;
AnnaBridge	145:64910690c574	922
AnnaBridge	145:64910690c574	923	save_word = *field;
AnnaBridge	145:64910690c574	924	save_word &= (~(3 << bit_shift));
AnnaBridge	145:64910690c574	925
AnnaBridge	145:64910690c574	926	*field = (save_word \| (((edge_level<<1) \| model) << bit_shift));
AnnaBridge	145:64910690c574	927	}
AnnaBridge	145:64910690c574	928
AnnaBridge	145:64910690c574	929	__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	145:64910690c574	930	{
AnnaBridge	145:64910690c574	931	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge	145:64910690c574	932	field += IRQn % 4;
AnnaBridge	145:64910690c574	933	*field = (char)priority;
AnnaBridge	145:64910690c574	934	}
AnnaBridge	145:64910690c574	935
AnnaBridge	145:64910690c574	936	__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	937	{
AnnaBridge	145:64910690c574	938	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge	145:64910690c574	939	field += IRQn % 4;
AnnaBridge	145:64910690c574	940	return (uint32_t)*field;
AnnaBridge	145:64910690c574	941	}
AnnaBridge	145:64910690c574	942
AnnaBridge	145:64910690c574	943	__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
AnnaBridge	145:64910690c574	944	{
AnnaBridge	145:64910690c574	945	GICInterface->ICCPMR = priority & 0xff; //set priority mask
AnnaBridge	145:64910690c574	946	}
AnnaBridge	145:64910690c574	947
AnnaBridge	145:64910690c574	948	__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge	145:64910690c574	949	{
AnnaBridge	145:64910690c574	950	GICInterface->ICCBPR = binary_point & 0x07; //set binary point
AnnaBridge	145:64910690c574	951	}
AnnaBridge	145:64910690c574	952
AnnaBridge	145:64910690c574	953	__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
AnnaBridge	145:64910690c574	954	{
AnnaBridge	145:64910690c574	955	return (uint32_t)GICInterface->ICCBPR;
AnnaBridge	145:64910690c574	956	}
AnnaBridge	145:64910690c574	957
AnnaBridge	145:64910690c574	958	__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	959	{
AnnaBridge	145:64910690c574	960	uint32_t pending, active;
AnnaBridge	145:64910690c574	961
AnnaBridge	145:64910690c574	962	active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge	145:64910690c574	963	pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge	145:64910690c574	964
AnnaBridge	145:64910690c574	965	return ((active<<1) \| pending);
AnnaBridge	145:64910690c574	966	}
AnnaBridge	145:64910690c574	967
AnnaBridge	145:64910690c574	968	__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge	145:64910690c574	969	{
AnnaBridge	145:64910690c574	970	GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) \| ((target_list & 0xff) << 16) \| (IRQn & 0xf);
AnnaBridge	145:64910690c574	971	}
AnnaBridge	145:64910690c574	972
AnnaBridge	145:64910690c574	973	__STATIC_INLINE void GIC_DistInit(void)
AnnaBridge	145:64910690c574	974	{
AnnaBridge	145:64910690c574	975	IRQn_Type i;
AnnaBridge	145:64910690c574	976	uint32_t num_irq = 0;
AnnaBridge	145:64910690c574	977	uint32_t priority_field;
AnnaBridge	145:64910690c574	978
AnnaBridge	145:64910690c574	979	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge	145:64910690c574	980	//configuring all of the interrupts as Secure.
AnnaBridge	145:64910690c574	981
AnnaBridge	145:64910690c574	982	//Disable interrupt forwarding
AnnaBridge	145:64910690c574	983	GIC_DisableDistributor();
AnnaBridge	145:64910690c574	984	//Get the maximum number of interrupts that the GIC supports
AnnaBridge	145:64910690c574	985	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge	145:64910690c574	986
AnnaBridge	145:64910690c574	987	/* Priority level is implementation defined.
AnnaBridge	145:64910690c574	988	To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge	145:64910690c574	989	priority field and read back the value stored.*/
AnnaBridge	145:64910690c574	990	GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge	145:64910690c574	991	priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge	145:64910690c574	992
AnnaBridge	145:64910690c574	993	for (i = (IRQn_Type)32; i < num_irq; i++)
AnnaBridge	145:64910690c574	994	{
AnnaBridge	145:64910690c574	995	//Disable the SPI interrupt
AnnaBridge	145:64910690c574	996	GIC_DisableIRQ(i);
AnnaBridge	145:64910690c574	997	//Set level-sensitive and 1-N model
AnnaBridge	145:64910690c574	998	GIC_SetLevelModel(i, 0, 1);
AnnaBridge	145:64910690c574	999	//Set priority
AnnaBridge	145:64910690c574	1000	GIC_SetPriority(i, priority_field/2);
AnnaBridge	145:64910690c574	1001	//Set target list to CPU0
AnnaBridge	145:64910690c574	1002	GIC_SetTarget(i, 1);
AnnaBridge	145:64910690c574	1003	}
AnnaBridge	145:64910690c574	1004	//Enable distributor
AnnaBridge	145:64910690c574	1005	GIC_EnableDistributor();
AnnaBridge	145:64910690c574	1006	}
AnnaBridge	145:64910690c574	1007
AnnaBridge	145:64910690c574	1008	__STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge	145:64910690c574	1009	{
AnnaBridge	145:64910690c574	1010	IRQn_Type i;
AnnaBridge	145:64910690c574	1011	uint32_t priority_field;
AnnaBridge	145:64910690c574	1012
AnnaBridge	145:64910690c574	1013	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge	145:64910690c574	1014	//configuring all of the interrupts as Secure.
AnnaBridge	145:64910690c574	1015
AnnaBridge	145:64910690c574	1016	//Disable interrupt forwarding
AnnaBridge	145:64910690c574	1017	GIC_DisableInterface();
AnnaBridge	145:64910690c574	1018
AnnaBridge	145:64910690c574	1019	/* Priority level is implementation defined.
AnnaBridge	145:64910690c574	1020	To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge	145:64910690c574	1021	priority field and read back the value stored.*/
AnnaBridge	145:64910690c574	1022	GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge	145:64910690c574	1023	priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge	145:64910690c574	1024
AnnaBridge	145:64910690c574	1025	//SGI and PPI
AnnaBridge	145:64910690c574	1026	for (i = (IRQn_Type)0; i < 32; i++)
AnnaBridge	145:64910690c574	1027	{
AnnaBridge	145:64910690c574	1028	//Set level-sensitive and 1-N model for PPI
AnnaBridge	145:64910690c574	1029	if(i > 15)
AnnaBridge	145:64910690c574	1030	GIC_SetLevelModel(i, 0, 1);
AnnaBridge	145:64910690c574	1031	//Disable SGI and PPI interrupts
AnnaBridge	145:64910690c574	1032	GIC_DisableIRQ(i);
AnnaBridge	145:64910690c574	1033	//Set priority
AnnaBridge	145:64910690c574	1034	GIC_SetPriority(i, priority_field/2);
AnnaBridge	145:64910690c574	1035	}
AnnaBridge	145:64910690c574	1036	//Enable interface
AnnaBridge	145:64910690c574	1037	GIC_EnableInterface();
AnnaBridge	145:64910690c574	1038	//Set binary point to 0
AnnaBridge	145:64910690c574	1039	GIC_SetBinaryPoint(0);
AnnaBridge	145:64910690c574	1040	//Set priority mask
AnnaBridge	145:64910690c574	1041	GIC_InterfacePriorityMask(0xff);
AnnaBridge	145:64910690c574	1042	}
AnnaBridge	145:64910690c574	1043
AnnaBridge	145:64910690c574	1044	__STATIC_INLINE void GIC_Enable(void)
AnnaBridge	145:64910690c574	1045	{
AnnaBridge	145:64910690c574	1046	GIC_DistInit();
AnnaBridge	145:64910690c574	1047	GIC_CPUInterfaceInit(); //per CPU
AnnaBridge	145:64910690c574	1048	}
AnnaBridge	145:64910690c574	1049	#endif
AnnaBridge	145:64910690c574	1050
AnnaBridge	145:64910690c574	1051	/* ########################## Generic Timer functions ############################ */
AnnaBridge	145:64910690c574	1052	#if (__TIM_PRESENT == 1U)
AnnaBridge	145:64910690c574	1053
AnnaBridge	145:64910690c574	1054	/* PL1 Physical Timer */
AnnaBridge	145:64910690c574	1055	#if (__CORTEX_A == 7U)
AnnaBridge	145:64910690c574	1056	__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
AnnaBridge	145:64910690c574	1057	__set_CNTP_TVAL(value);
AnnaBridge	145:64910690c574	1058	__ISB();
AnnaBridge	145:64910690c574	1059	}
AnnaBridge	145:64910690c574	1060
AnnaBridge	145:64910690c574	1061	__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
AnnaBridge	145:64910690c574	1062	return(__get_CNTP_TVAL());
AnnaBridge	145:64910690c574	1063	}
AnnaBridge	145:64910690c574	1064
AnnaBridge	145:64910690c574	1065	__STATIC_INLINE void PL1_SetControl(uint32_t value) {
AnnaBridge	145:64910690c574	1066	__set_CNTP_CTL(value);
AnnaBridge	145:64910690c574	1067	__ISB();
AnnaBridge	145:64910690c574	1068	}
AnnaBridge	145:64910690c574	1069
AnnaBridge	145:64910690c574	1070	/* Private Timer */
AnnaBridge	145:64910690c574	1071	#elif ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
AnnaBridge	145:64910690c574	1072	__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
AnnaBridge	145:64910690c574	1073	PTIM->LOAD = value;
AnnaBridge	145:64910690c574	1074	}
AnnaBridge	145:64910690c574	1075
AnnaBridge	145:64910690c574	1076	__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
AnnaBridge	145:64910690c574	1077	return(PTIM->LOAD);
AnnaBridge	145:64910690c574	1078	}
AnnaBridge	145:64910690c574	1079
AnnaBridge	145:64910690c574	1080	__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
AnnaBridge	145:64910690c574	1081	return(PTIM->COUNTER);
AnnaBridge	145:64910690c574	1082	}
AnnaBridge	145:64910690c574	1083
AnnaBridge	145:64910690c574	1084	__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
AnnaBridge	145:64910690c574	1085	PTIM->CONTROL = value;
AnnaBridge	145:64910690c574	1086	}
AnnaBridge	145:64910690c574	1087
AnnaBridge	145:64910690c574	1088	__STATIC_INLINE uint32_t PTIM_GetControl(void) {
AnnaBridge	145:64910690c574	1089	return(PTIM->CONTROL);
AnnaBridge	145:64910690c574	1090	}
AnnaBridge	145:64910690c574	1091
AnnaBridge	145:64910690c574	1092	__STATIC_INLINE void PTIM_ClearEventFlag(void) {
AnnaBridge	145:64910690c574	1093	PTIM->ISR = 1;
AnnaBridge	145:64910690c574	1094	}
AnnaBridge	145:64910690c574	1095	#endif
AnnaBridge	145:64910690c574	1096	#endif
AnnaBridge	145:64910690c574	1097
AnnaBridge	145:64910690c574	1098	/* ########################## MMU functions ###################################### */
AnnaBridge	145:64910690c574	1099
AnnaBridge	145:64910690c574	1100	#define SECTION_DESCRIPTOR (0x2)
AnnaBridge	145:64910690c574	1101	#define SECTION_MASK (0xFFFFFFFC)
AnnaBridge	145:64910690c574	1102
AnnaBridge	145:64910690c574	1103	#define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	145:64910690c574	1104	#define SECTION_B_SHIFT (2)
AnnaBridge	145:64910690c574	1105	#define SECTION_C_SHIFT (3)
AnnaBridge	145:64910690c574	1106	#define SECTION_TEX0_SHIFT (12)
AnnaBridge	145:64910690c574	1107	#define SECTION_TEX1_SHIFT (13)
AnnaBridge	145:64910690c574	1108	#define SECTION_TEX2_SHIFT (14)
AnnaBridge	145:64910690c574	1109
AnnaBridge	145:64910690c574	1110	#define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge	145:64910690c574	1111	#define SECTION_XN_SHIFT (4)
AnnaBridge	145:64910690c574	1112
AnnaBridge	145:64910690c574	1113	#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	145:64910690c574	1114	#define SECTION_DOMAIN_SHIFT (5)
AnnaBridge	145:64910690c574	1115
AnnaBridge	145:64910690c574	1116	#define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge	145:64910690c574	1117	#define SECTION_P_SHIFT (9)
AnnaBridge	145:64910690c574	1118
AnnaBridge	145:64910690c574	1119	#define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge	145:64910690c574	1120	#define SECTION_AP_SHIFT (10)
AnnaBridge	145:64910690c574	1121	#define SECTION_AP2_SHIFT (15)
AnnaBridge	145:64910690c574	1122
AnnaBridge	145:64910690c574	1123	#define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge	145:64910690c574	1124	#define SECTION_S_SHIFT (16)
AnnaBridge	145:64910690c574	1125
AnnaBridge	145:64910690c574	1126	#define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge	145:64910690c574	1127	#define SECTION_NG_SHIFT (17)
AnnaBridge	145:64910690c574	1128
AnnaBridge	145:64910690c574	1129	#define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge	145:64910690c574	1130	#define SECTION_NS_SHIFT (19)
AnnaBridge	145:64910690c574	1131
AnnaBridge	145:64910690c574	1132	#define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge	145:64910690c574	1133	#define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge	145:64910690c574	1134
AnnaBridge	145:64910690c574	1135	#define PAGE_L2_4K_DESC (0x2)
AnnaBridge	145:64910690c574	1136	#define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge	145:64910690c574	1137
AnnaBridge	145:64910690c574	1138	#define PAGE_L2_64K_DESC (0x1)
AnnaBridge	145:64910690c574	1139	#define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge	145:64910690c574	1140
AnnaBridge	145:64910690c574	1141	#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge	145:64910690c574	1142	#define PAGE_4K_B_SHIFT (2)
AnnaBridge	145:64910690c574	1143	#define PAGE_4K_C_SHIFT (3)
AnnaBridge	145:64910690c574	1144	#define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge	145:64910690c574	1145	#define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge	145:64910690c574	1146	#define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge	145:64910690c574	1147
AnnaBridge	145:64910690c574	1148	#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	145:64910690c574	1149	#define PAGE_64K_B_SHIFT (2)
AnnaBridge	145:64910690c574	1150	#define PAGE_64K_C_SHIFT (3)
AnnaBridge	145:64910690c574	1151	#define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge	145:64910690c574	1152	#define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge	145:64910690c574	1153	#define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge	145:64910690c574	1154
AnnaBridge	145:64910690c574	1155	#define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	145:64910690c574	1156	#define PAGE_B_SHIFT (2)
AnnaBridge	145:64910690c574	1157	#define PAGE_C_SHIFT (3)
AnnaBridge	145:64910690c574	1158	#define PAGE_TEX_SHIFT (12)
AnnaBridge	145:64910690c574	1159
AnnaBridge	145:64910690c574	1160	#define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge	145:64910690c574	1161	#define PAGE_XN_4K_SHIFT (0)
AnnaBridge	145:64910690c574	1162	#define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge	145:64910690c574	1163	#define PAGE_XN_64K_SHIFT (15)
AnnaBridge	145:64910690c574	1164
AnnaBridge	145:64910690c574	1165	#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	145:64910690c574	1166	#define PAGE_DOMAIN_SHIFT (5)
AnnaBridge	145:64910690c574	1167
AnnaBridge	145:64910690c574	1168	#define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge	145:64910690c574	1169	#define PAGE_P_SHIFT (9)
AnnaBridge	145:64910690c574	1170
AnnaBridge	145:64910690c574	1171	#define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge	145:64910690c574	1172	#define PAGE_AP_SHIFT (4)
AnnaBridge	145:64910690c574	1173	#define PAGE_AP2_SHIFT (9)
AnnaBridge	145:64910690c574	1174
AnnaBridge	145:64910690c574	1175	#define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge	145:64910690c574	1176	#define PAGE_S_SHIFT (10)
AnnaBridge	145:64910690c574	1177
AnnaBridge	145:64910690c574	1178	#define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge	145:64910690c574	1179	#define PAGE_NG_SHIFT (11)
AnnaBridge	145:64910690c574	1180
AnnaBridge	145:64910690c574	1181	#define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge	145:64910690c574	1182	#define PAGE_NS_SHIFT (3)
AnnaBridge	145:64910690c574	1183
AnnaBridge	145:64910690c574	1184	#define OFFSET_1M (0x00100000)
AnnaBridge	145:64910690c574	1185	#define OFFSET_64K (0x00010000)
AnnaBridge	145:64910690c574	1186	#define OFFSET_4K (0x00001000)
AnnaBridge	145:64910690c574	1187
AnnaBridge	145:64910690c574	1188	#define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge	145:64910690c574	1189
AnnaBridge	145:64910690c574	1190	/* Attributes enumerations */
AnnaBridge	145:64910690c574	1191
AnnaBridge	145:64910690c574	1192	/* Region size attributes */
AnnaBridge	145:64910690c574	1193	typedef enum
AnnaBridge	145:64910690c574	1194	{
AnnaBridge	145:64910690c574	1195	SECTION,
AnnaBridge	145:64910690c574	1196	PAGE_4k,
AnnaBridge	145:64910690c574	1197	PAGE_64k,
AnnaBridge	145:64910690c574	1198	} mmu_region_size_Type;
AnnaBridge	145:64910690c574	1199
AnnaBridge	145:64910690c574	1200	/* Region type attributes */
AnnaBridge	145:64910690c574	1201	typedef enum
AnnaBridge	145:64910690c574	1202	{
AnnaBridge	145:64910690c574	1203	NORMAL,
AnnaBridge	145:64910690c574	1204	DEVICE,
AnnaBridge	145:64910690c574	1205	SHARED_DEVICE,
AnnaBridge	145:64910690c574	1206	NON_SHARED_DEVICE,
AnnaBridge	145:64910690c574	1207	STRONGLY_ORDERED
AnnaBridge	145:64910690c574	1208	} mmu_memory_Type;
AnnaBridge	145:64910690c574	1209
AnnaBridge	145:64910690c574	1210	/* Region cacheability attributes */
AnnaBridge	145:64910690c574	1211	typedef enum
AnnaBridge	145:64910690c574	1212	{
AnnaBridge	145:64910690c574	1213	NON_CACHEABLE,
AnnaBridge	145:64910690c574	1214	WB_WA,
AnnaBridge	145:64910690c574	1215	WT,
AnnaBridge	145:64910690c574	1216	WB_NO_WA,
AnnaBridge	145:64910690c574	1217	} mmu_cacheability_Type;
AnnaBridge	145:64910690c574	1218
AnnaBridge	145:64910690c574	1219	/* Region parity check attributes */
AnnaBridge	145:64910690c574	1220	typedef enum
AnnaBridge	145:64910690c574	1221	{
AnnaBridge	145:64910690c574	1222	ECC_DISABLED,
AnnaBridge	145:64910690c574	1223	ECC_ENABLED,
AnnaBridge	145:64910690c574	1224	} mmu_ecc_check_Type;
AnnaBridge	145:64910690c574	1225
AnnaBridge	145:64910690c574	1226	/* Region execution attributes */
AnnaBridge	145:64910690c574	1227	typedef enum
AnnaBridge	145:64910690c574	1228	{
AnnaBridge	145:64910690c574	1229	EXECUTE,
AnnaBridge	145:64910690c574	1230	NON_EXECUTE,
AnnaBridge	145:64910690c574	1231	} mmu_execute_Type;
AnnaBridge	145:64910690c574	1232
AnnaBridge	145:64910690c574	1233	/* Region global attributes */
AnnaBridge	145:64910690c574	1234	typedef enum
AnnaBridge	145:64910690c574	1235	{
AnnaBridge	145:64910690c574	1236	GLOBAL,
AnnaBridge	145:64910690c574	1237	NON_GLOBAL,
AnnaBridge	145:64910690c574	1238	} mmu_global_Type;
AnnaBridge	145:64910690c574	1239
AnnaBridge	145:64910690c574	1240	/* Region shareability attributes */
AnnaBridge	145:64910690c574	1241	typedef enum
AnnaBridge	145:64910690c574	1242	{
AnnaBridge	145:64910690c574	1243	NON_SHARED,
AnnaBridge	145:64910690c574	1244	SHARED,
AnnaBridge	145:64910690c574	1245	} mmu_shared_Type;
AnnaBridge	145:64910690c574	1246
AnnaBridge	145:64910690c574	1247	/* Region security attributes */
AnnaBridge	145:64910690c574	1248	typedef enum
AnnaBridge	145:64910690c574	1249	{
AnnaBridge	145:64910690c574	1250	SECURE,
AnnaBridge	145:64910690c574	1251	NON_SECURE,
AnnaBridge	145:64910690c574	1252	} mmu_secure_Type;
AnnaBridge	145:64910690c574	1253
AnnaBridge	145:64910690c574	1254	/* Region access attributes */
AnnaBridge	145:64910690c574	1255	typedef enum
AnnaBridge	145:64910690c574	1256	{
AnnaBridge	145:64910690c574	1257	NO_ACCESS,
AnnaBridge	145:64910690c574	1258	RW,
AnnaBridge	145:64910690c574	1259	READ,
AnnaBridge	145:64910690c574	1260	} mmu_access_Type;
AnnaBridge	145:64910690c574	1261
AnnaBridge	145:64910690c574	1262	/* Memory Region definition */
AnnaBridge	145:64910690c574	1263	typedef struct RegionStruct {
AnnaBridge	145:64910690c574	1264	mmu_region_size_Type rg_t;
AnnaBridge	145:64910690c574	1265	mmu_memory_Type mem_t;
AnnaBridge	145:64910690c574	1266	uint8_t domain;
AnnaBridge	145:64910690c574	1267	mmu_cacheability_Type inner_norm_t;
AnnaBridge	145:64910690c574	1268	mmu_cacheability_Type outer_norm_t;
AnnaBridge	145:64910690c574	1269	mmu_ecc_check_Type e_t;
AnnaBridge	145:64910690c574	1270	mmu_execute_Type xn_t;
AnnaBridge	145:64910690c574	1271	mmu_global_Type g_t;
AnnaBridge	145:64910690c574	1272	mmu_secure_Type sec_t;
AnnaBridge	145:64910690c574	1273	mmu_access_Type priv_t;
AnnaBridge	145:64910690c574	1274	mmu_access_Type user_t;
AnnaBridge	145:64910690c574	1275	mmu_shared_Type sh_t;
AnnaBridge	145:64910690c574	1276
AnnaBridge	145:64910690c574	1277	} mmu_region_attributes_Type;
AnnaBridge	145:64910690c574	1278
AnnaBridge	145:64910690c574	1279	//Following macros define the descriptors and attributes
AnnaBridge	145:64910690c574	1280	//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge	145:64910690c574	1281	#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1282	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1283	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1284	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1285	region.inner_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1286	region.outer_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1287	region.mem_t = NORMAL; \
AnnaBridge	145:64910690c574	1288	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1289	region.xn_t = EXECUTE; \
AnnaBridge	145:64910690c574	1290	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1291	region.user_t = RW; \
AnnaBridge	145:64910690c574	1292	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1293	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1294
AnnaBridge	145:64910690c574	1295	//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge	145:64910690c574	1296	#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1297	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1298	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1299	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1300	region.inner_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1301	region.outer_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1302	region.mem_t = NORMAL; \
AnnaBridge	145:64910690c574	1303	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1304	region.xn_t = EXECUTE; \
AnnaBridge	145:64910690c574	1305	region.priv_t = READ; \
AnnaBridge	145:64910690c574	1306	region.user_t = READ; \
AnnaBridge	145:64910690c574	1307	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1308	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1309
AnnaBridge	145:64910690c574	1310	//Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge	145:64910690c574	1311	#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1312	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1313	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1314	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1315	region.inner_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1316	region.outer_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1317	region.mem_t = NORMAL; \
AnnaBridge	145:64910690c574	1318	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1319	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1320	region.priv_t = READ; \
AnnaBridge	145:64910690c574	1321	region.user_t = READ; \
AnnaBridge	145:64910690c574	1322	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1323	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1324
AnnaBridge	145:64910690c574	1325	//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge	145:64910690c574	1326	#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1327	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1328	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1329	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1330	region.inner_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1331	region.outer_norm_t = WB_WA; \
AnnaBridge	145:64910690c574	1332	region.mem_t = NORMAL; \
AnnaBridge	145:64910690c574	1333	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1334	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1335	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1336	region.user_t = RW; \
AnnaBridge	145:64910690c574	1337	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1338	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1339	//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge	145:64910690c574	1340	#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1341	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1342	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1343	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1344	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1345	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1346	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	145:64910690c574	1347	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1348	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1349	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1350	region.user_t = RW; \
AnnaBridge	145:64910690c574	1351	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1352	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1353
AnnaBridge	145:64910690c574	1354	//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge	145:64910690c574	1355	#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1356	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1357	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1358	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1359	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1360	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1361	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	145:64910690c574	1362	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1363	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1364	region.priv_t = READ; \
AnnaBridge	145:64910690c574	1365	region.user_t = READ; \
AnnaBridge	145:64910690c574	1366	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1367	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1368
AnnaBridge	145:64910690c574	1369	//Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge	145:64910690c574	1370	#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	145:64910690c574	1371	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1372	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1373	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1374	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1375	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1376	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	145:64910690c574	1377	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1378	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1379	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1380	region.user_t = RW; \
AnnaBridge	145:64910690c574	1381	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1382	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	145:64910690c574	1383	//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	145:64910690c574	1384	#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge	145:64910690c574	1385	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1386	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1387	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1388	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1389	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1390	region.mem_t = SHARED_DEVICE; \
AnnaBridge	145:64910690c574	1391	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1392	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1393	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1394	region.user_t = RW; \
AnnaBridge	145:64910690c574	1395	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1396	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	145:64910690c574	1397
AnnaBridge	145:64910690c574	1398	//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	145:64910690c574	1399	#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge	145:64910690c574	1400	region.domain = 0x0; \
AnnaBridge	145:64910690c574	1401	region.e_t = ECC_DISABLED; \
AnnaBridge	145:64910690c574	1402	region.g_t = GLOBAL; \
AnnaBridge	145:64910690c574	1403	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1404	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	145:64910690c574	1405	region.mem_t = SHARED_DEVICE; \
AnnaBridge	145:64910690c574	1406	region.sec_t = SECURE; \
AnnaBridge	145:64910690c574	1407	region.xn_t = NON_EXECUTE; \
AnnaBridge	145:64910690c574	1408	region.priv_t = RW; \
AnnaBridge	145:64910690c574	1409	region.user_t = RW; \
AnnaBridge	145:64910690c574	1410	region.sh_t = NON_SHARED; \
AnnaBridge	145:64910690c574	1411	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	145:64910690c574	1412
AnnaBridge	145:64910690c574	1413	/** \brief Set section execution-never attribute
AnnaBridge	145:64910690c574	1414
AnnaBridge	145:64910690c574	1415	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1416	\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	145:64910690c574	1417
AnnaBridge	145:64910690c574	1418	\return 0
AnnaBridge	145:64910690c574	1419	*/
AnnaBridge	145:64910690c574	1420	__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge	145:64910690c574	1421	{
AnnaBridge	145:64910690c574	1422	*descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge	145:64910690c574	1423	*descriptor_l1 \|= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge	145:64910690c574	1424	return 0;
AnnaBridge	145:64910690c574	1425	}
AnnaBridge	145:64910690c574	1426
AnnaBridge	145:64910690c574	1427	/** \brief Set section domain
AnnaBridge	145:64910690c574	1428
AnnaBridge	145:64910690c574	1429	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1430	\param [in] domain Section domain
AnnaBridge	145:64910690c574	1431
AnnaBridge	145:64910690c574	1432	\return 0
AnnaBridge	145:64910690c574	1433	*/
AnnaBridge	145:64910690c574	1434	__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	145:64910690c574	1435	{
AnnaBridge	145:64910690c574	1436	*descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge	145:64910690c574	1437	*descriptor_l1 \|= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge	145:64910690c574	1438	return 0;
AnnaBridge	145:64910690c574	1439	}
AnnaBridge	145:64910690c574	1440
AnnaBridge	145:64910690c574	1441	/** \brief Set section parity check
AnnaBridge	145:64910690c574	1442
AnnaBridge	145:64910690c574	1443	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1444	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	145:64910690c574	1445
AnnaBridge	145:64910690c574	1446	\return 0
AnnaBridge	145:64910690c574	1447	*/
AnnaBridge	145:64910690c574	1448	__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	145:64910690c574	1449	{
AnnaBridge	145:64910690c574	1450	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	145:64910690c574	1451	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	145:64910690c574	1452	return 0;
AnnaBridge	145:64910690c574	1453	}
AnnaBridge	145:64910690c574	1454
AnnaBridge	145:64910690c574	1455	/** \brief Set section access privileges
AnnaBridge	145:64910690c574	1456
AnnaBridge	145:64910690c574	1457	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1458	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	145:64910690c574	1459	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	145:64910690c574	1460	\param [in] afe Access flag enable
AnnaBridge	145:64910690c574	1461
AnnaBridge	145:64910690c574	1462	\return 0
AnnaBridge	145:64910690c574	1463	*/
AnnaBridge	145:64910690c574	1464	__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	145:64910690c574	1465	{
AnnaBridge	145:64910690c574	1466	uint32_t ap = 0;
AnnaBridge	145:64910690c574	1467
AnnaBridge	145:64910690c574	1468	if (afe == 0) { //full access
AnnaBridge	145:64910690c574	1469	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	145:64910690c574	1470	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	145:64910690c574	1471	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	145:64910690c574	1472	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	145:64910690c574	1473	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	145:64910690c574	1474	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	145:64910690c574	1475	}
AnnaBridge	145:64910690c574	1476
AnnaBridge	145:64910690c574	1477	else { //Simplified access
AnnaBridge	145:64910690c574	1478	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	145:64910690c574	1479	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	145:64910690c574	1480	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	145:64910690c574	1481	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	145:64910690c574	1482	}
AnnaBridge	145:64910690c574	1483
AnnaBridge	145:64910690c574	1484	*descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge	145:64910690c574	1485	*descriptor_l1 \|= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge	145:64910690c574	1486	*descriptor_l1 \|= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge	145:64910690c574	1487
AnnaBridge	145:64910690c574	1488	return 0;
AnnaBridge	145:64910690c574	1489	}
AnnaBridge	145:64910690c574	1490
AnnaBridge	145:64910690c574	1491	/** \brief Set section shareability
AnnaBridge	145:64910690c574	1492
AnnaBridge	145:64910690c574	1493	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1494	\param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge	145:64910690c574	1495
AnnaBridge	145:64910690c574	1496	\return 0
AnnaBridge	145:64910690c574	1497	*/
AnnaBridge	145:64910690c574	1498	__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge	145:64910690c574	1499	{
AnnaBridge	145:64910690c574	1500	*descriptor_l1 &= SECTION_S_MASK;
AnnaBridge	145:64910690c574	1501	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge	145:64910690c574	1502	return 0;
AnnaBridge	145:64910690c574	1503	}
AnnaBridge	145:64910690c574	1504
AnnaBridge	145:64910690c574	1505	/** \brief Set section Global attribute
AnnaBridge	145:64910690c574	1506
AnnaBridge	145:64910690c574	1507	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1508	\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge	145:64910690c574	1509
AnnaBridge	145:64910690c574	1510	\return 0
AnnaBridge	145:64910690c574	1511	*/
AnnaBridge	145:64910690c574	1512	__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge	145:64910690c574	1513	{
AnnaBridge	145:64910690c574	1514	*descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge	145:64910690c574	1515	*descriptor_l1 \|= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge	145:64910690c574	1516	return 0;
AnnaBridge	145:64910690c574	1517	}
AnnaBridge	145:64910690c574	1518
AnnaBridge	145:64910690c574	1519	/** \brief Set section Security attribute
AnnaBridge	145:64910690c574	1520
AnnaBridge	145:64910690c574	1521	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1522	\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge	145:64910690c574	1523
AnnaBridge	145:64910690c574	1524	\return 0
AnnaBridge	145:64910690c574	1525	*/
AnnaBridge	145:64910690c574	1526	__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	145:64910690c574	1527	{
AnnaBridge	145:64910690c574	1528	*descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge	145:64910690c574	1529	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge	145:64910690c574	1530	return 0;
AnnaBridge	145:64910690c574	1531	}
AnnaBridge	145:64910690c574	1532
AnnaBridge	145:64910690c574	1533	/* Page 4k or 64k */
AnnaBridge	145:64910690c574	1534	/** \brief Set 4k/64k page execution-never attribute
AnnaBridge	145:64910690c574	1535
AnnaBridge	145:64910690c574	1536	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	145:64910690c574	1537	\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	145:64910690c574	1538	\param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge	145:64910690c574	1539
AnnaBridge	145:64910690c574	1540	\return 0
AnnaBridge	145:64910690c574	1541	*/
AnnaBridge	145:64910690c574	1542	__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge	145:64910690c574	1543	{
AnnaBridge	145:64910690c574	1544	if (page == PAGE_4k)
AnnaBridge	145:64910690c574	1545	{
AnnaBridge	145:64910690c574	1546	*descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge	145:64910690c574	1547	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge	145:64910690c574	1548	}
AnnaBridge	145:64910690c574	1549	else
AnnaBridge	145:64910690c574	1550	{
AnnaBridge	145:64910690c574	1551	*descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge	145:64910690c574	1552	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge	145:64910690c574	1553	}
AnnaBridge	145:64910690c574	1554	return 0;
AnnaBridge	145:64910690c574	1555	}
AnnaBridge	145:64910690c574	1556
AnnaBridge	145:64910690c574	1557	/** \brief Set 4k/64k page domain
AnnaBridge	145:64910690c574	1558
AnnaBridge	145:64910690c574	1559	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1560	\param [in] domain Page domain
AnnaBridge	145:64910690c574	1561
AnnaBridge	145:64910690c574	1562	\return 0
AnnaBridge	145:64910690c574	1563	*/
AnnaBridge	145:64910690c574	1564	__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	145:64910690c574	1565	{
AnnaBridge	145:64910690c574	1566	*descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge	145:64910690c574	1567	*descriptor_l1 \|= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge	145:64910690c574	1568	return 0;
AnnaBridge	145:64910690c574	1569	}
AnnaBridge	145:64910690c574	1570
AnnaBridge	145:64910690c574	1571	/** \brief Set 4k/64k page parity check
AnnaBridge	145:64910690c574	1572
AnnaBridge	145:64910690c574	1573	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1574	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	145:64910690c574	1575
AnnaBridge	145:64910690c574	1576	\return 0
AnnaBridge	145:64910690c574	1577	*/
AnnaBridge	145:64910690c574	1578	__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	145:64910690c574	1579	{
AnnaBridge	145:64910690c574	1580	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	145:64910690c574	1581	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	145:64910690c574	1582	return 0;
AnnaBridge	145:64910690c574	1583	}
AnnaBridge	145:64910690c574	1584
AnnaBridge	145:64910690c574	1585	/** \brief Set 4k/64k page access privileges
AnnaBridge	145:64910690c574	1586
AnnaBridge	145:64910690c574	1587	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	145:64910690c574	1588	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	145:64910690c574	1589	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	145:64910690c574	1590	\param [in] afe Access flag enable
AnnaBridge	145:64910690c574	1591
AnnaBridge	145:64910690c574	1592	\return 0
AnnaBridge	145:64910690c574	1593	*/
AnnaBridge	145:64910690c574	1594	__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	145:64910690c574	1595	{
AnnaBridge	145:64910690c574	1596	uint32_t ap = 0;
AnnaBridge	145:64910690c574	1597
AnnaBridge	145:64910690c574	1598	if (afe == 0) { //full access
AnnaBridge	145:64910690c574	1599	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	145:64910690c574	1600	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	145:64910690c574	1601	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	145:64910690c574	1602	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	145:64910690c574	1603	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	145:64910690c574	1604	else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge	145:64910690c574	1605	}
AnnaBridge	145:64910690c574	1606
AnnaBridge	145:64910690c574	1607	else { //Simplified access
AnnaBridge	145:64910690c574	1608	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	145:64910690c574	1609	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	145:64910690c574	1610	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	145:64910690c574	1611	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	145:64910690c574	1612	}
AnnaBridge	145:64910690c574	1613
AnnaBridge	145:64910690c574	1614	*descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge	145:64910690c574	1615	*descriptor_l2 \|= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge	145:64910690c574	1616	*descriptor_l2 \|= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge	145:64910690c574	1617
AnnaBridge	145:64910690c574	1618	return 0;
AnnaBridge	145:64910690c574	1619	}
AnnaBridge	145:64910690c574	1620
AnnaBridge	145:64910690c574	1621	/** \brief Set 4k/64k page shareability
AnnaBridge	145:64910690c574	1622
AnnaBridge	145:64910690c574	1623	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	145:64910690c574	1624	\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge	145:64910690c574	1625
AnnaBridge	145:64910690c574	1626	\return 0
AnnaBridge	145:64910690c574	1627	*/
AnnaBridge	145:64910690c574	1628	__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge	145:64910690c574	1629	{
AnnaBridge	145:64910690c574	1630	*descriptor_l2 &= PAGE_S_MASK;
AnnaBridge	145:64910690c574	1631	*descriptor_l2 \|= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge	145:64910690c574	1632	return 0;
AnnaBridge	145:64910690c574	1633	}
AnnaBridge	145:64910690c574	1634
AnnaBridge	145:64910690c574	1635	/** \brief Set 4k/64k page Global attribute
AnnaBridge	145:64910690c574	1636
AnnaBridge	145:64910690c574	1637	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	145:64910690c574	1638	\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge	145:64910690c574	1639
AnnaBridge	145:64910690c574	1640	\return 0
AnnaBridge	145:64910690c574	1641	*/
AnnaBridge	145:64910690c574	1642	__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge	145:64910690c574	1643	{
AnnaBridge	145:64910690c574	1644	*descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge	145:64910690c574	1645	*descriptor_l2 \|= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge	145:64910690c574	1646	return 0;
AnnaBridge	145:64910690c574	1647	}
AnnaBridge	145:64910690c574	1648
AnnaBridge	145:64910690c574	1649	/** \brief Set 4k/64k page Security attribute
AnnaBridge	145:64910690c574	1650
AnnaBridge	145:64910690c574	1651	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1652	\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge	145:64910690c574	1653
AnnaBridge	145:64910690c574	1654	\return 0
AnnaBridge	145:64910690c574	1655	*/
AnnaBridge	145:64910690c574	1656	__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	145:64910690c574	1657	{
AnnaBridge	145:64910690c574	1658	*descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge	145:64910690c574	1659	*descriptor_l1 \|= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge	145:64910690c574	1660	return 0;
AnnaBridge	145:64910690c574	1661	}
AnnaBridge	145:64910690c574	1662
AnnaBridge	145:64910690c574	1663	/** \brief Set Section memory attributes
AnnaBridge	145:64910690c574	1664
AnnaBridge	145:64910690c574	1665	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	145:64910690c574	1666	\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	145:64910690c574	1667	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	145:64910690c574	1668	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	145:64910690c574	1669
AnnaBridge	145:64910690c574	1670	\return 0
AnnaBridge	145:64910690c574	1671	*/
AnnaBridge	145:64910690c574	1672	__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge	145:64910690c574	1673	{
AnnaBridge	145:64910690c574	1674	*descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge	145:64910690c574	1675
AnnaBridge	145:64910690c574	1676	if (STRONGLY_ORDERED == mem)
AnnaBridge	145:64910690c574	1677	{
AnnaBridge	145:64910690c574	1678	return 0;
AnnaBridge	145:64910690c574	1679	}
AnnaBridge	145:64910690c574	1680	else if (SHARED_DEVICE == mem)
AnnaBridge	145:64910690c574	1681	{
AnnaBridge	145:64910690c574	1682	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	145:64910690c574	1683	}
AnnaBridge	145:64910690c574	1684	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	145:64910690c574	1685	{
AnnaBridge	145:64910690c574	1686	*descriptor_l1 \|= (1 << SECTION_TEX1_SHIFT);
AnnaBridge	145:64910690c574	1687	}
AnnaBridge	145:64910690c574	1688	else if (NORMAL == mem)
AnnaBridge	145:64910690c574	1689	{
AnnaBridge	145:64910690c574	1690	*descriptor_l1 \|= 1 << SECTION_TEX2_SHIFT;
AnnaBridge	145:64910690c574	1691	switch(inner)
AnnaBridge	145:64910690c574	1692	{
AnnaBridge	145:64910690c574	1693	case NON_CACHEABLE:
AnnaBridge	145:64910690c574	1694	break;
AnnaBridge	145:64910690c574	1695	case WB_WA:
AnnaBridge	145:64910690c574	1696	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	145:64910690c574	1697	break;
AnnaBridge	145:64910690c574	1698	case WT:
AnnaBridge	145:64910690c574	1699	*descriptor_l1 \|= 1 << SECTION_C_SHIFT;
AnnaBridge	145:64910690c574	1700	break;
AnnaBridge	145:64910690c574	1701	case WB_NO_WA:
AnnaBridge	145:64910690c574	1702	*descriptor_l1 \|= (1 << SECTION_B_SHIFT) \| (1 << SECTION_C_SHIFT);
AnnaBridge	145:64910690c574	1703	break;
AnnaBridge	145:64910690c574	1704	}
AnnaBridge	145:64910690c574	1705	switch(outer)
AnnaBridge	145:64910690c574	1706	{
AnnaBridge	145:64910690c574	1707	case NON_CACHEABLE:
AnnaBridge	145:64910690c574	1708	break;
AnnaBridge	145:64910690c574	1709	case WB_WA:
AnnaBridge	145:64910690c574	1710	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT);
AnnaBridge	145:64910690c574	1711	break;
AnnaBridge	145:64910690c574	1712	case WT:
AnnaBridge	145:64910690c574	1713	*descriptor_l1 \|= 1 << SECTION_TEX1_SHIFT;
AnnaBridge	145:64910690c574	1714	break;
AnnaBridge	145:64910690c574	1715	case WB_NO_WA:
AnnaBridge	145:64910690c574	1716	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT) \| (1 << SECTION_TEX0_SHIFT);
AnnaBridge	145:64910690c574	1717	break;
AnnaBridge	145:64910690c574	1718	}
AnnaBridge	145:64910690c574	1719	}
AnnaBridge	145:64910690c574	1720	return 0;
AnnaBridge	145:64910690c574	1721	}
AnnaBridge	145:64910690c574	1722
AnnaBridge	145:64910690c574	1723	/** \brief Set 4k/64k page memory attributes
AnnaBridge	145:64910690c574	1724
AnnaBridge	145:64910690c574	1725	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	145:64910690c574	1726	\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	145:64910690c574	1727	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	145:64910690c574	1728	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	145:64910690c574	1729	\param [in] page Page size
AnnaBridge	145:64910690c574	1730
AnnaBridge	145:64910690c574	1731	\return 0
AnnaBridge	145:64910690c574	1732	*/
AnnaBridge	145:64910690c574	1733	__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge	145:64910690c574	1734	{
AnnaBridge	145:64910690c574	1735	*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge	145:64910690c574	1736
AnnaBridge	145:64910690c574	1737	if (page == PAGE_64k)
AnnaBridge	145:64910690c574	1738	{
AnnaBridge	145:64910690c574	1739	//same as section
AnnaBridge	145:64910690c574	1740	MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge	145:64910690c574	1741	}
AnnaBridge	145:64910690c574	1742	else
AnnaBridge	145:64910690c574	1743	{
AnnaBridge	145:64910690c574	1744	if (STRONGLY_ORDERED == mem)
AnnaBridge	145:64910690c574	1745	{
AnnaBridge	145:64910690c574	1746	return 0;
AnnaBridge	145:64910690c574	1747	}
AnnaBridge	145:64910690c574	1748	else if (SHARED_DEVICE == mem)
AnnaBridge	145:64910690c574	1749	{
AnnaBridge	145:64910690c574	1750	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	145:64910690c574	1751	}
AnnaBridge	145:64910690c574	1752	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	145:64910690c574	1753	{
AnnaBridge	145:64910690c574	1754	*descriptor_l2 \|= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge	145:64910690c574	1755	}
AnnaBridge	145:64910690c574	1756	else if (NORMAL == mem)
AnnaBridge	145:64910690c574	1757	{
AnnaBridge	145:64910690c574	1758	*descriptor_l2 \|= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge	145:64910690c574	1759	switch(inner)
AnnaBridge	145:64910690c574	1760	{
AnnaBridge	145:64910690c574	1761	case NON_CACHEABLE:
AnnaBridge	145:64910690c574	1762	break;
AnnaBridge	145:64910690c574	1763	case WB_WA:
AnnaBridge	145:64910690c574	1764	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	145:64910690c574	1765	break;
AnnaBridge	145:64910690c574	1766	case WT:
AnnaBridge	145:64910690c574	1767	*descriptor_l2 \|= 1 << PAGE_4K_C_SHIFT;
AnnaBridge	145:64910690c574	1768	break;
AnnaBridge	145:64910690c574	1769	case WB_NO_WA:
AnnaBridge	145:64910690c574	1770	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT) \| (1 << PAGE_4K_C_SHIFT);
AnnaBridge	145:64910690c574	1771	break;
AnnaBridge	145:64910690c574	1772	}
AnnaBridge	145:64910690c574	1773	switch(outer)
AnnaBridge	145:64910690c574	1774	{
AnnaBridge	145:64910690c574	1775	case NON_CACHEABLE:
AnnaBridge	145:64910690c574	1776	break;
AnnaBridge	145:64910690c574	1777	case WB_WA:
AnnaBridge	145:64910690c574	1778	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	145:64910690c574	1779	break;
AnnaBridge	145:64910690c574	1780	case WT:
AnnaBridge	145:64910690c574	1781	*descriptor_l2 \|= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge	145:64910690c574	1782	break;
AnnaBridge	145:64910690c574	1783	case WB_NO_WA:
AnnaBridge	145:64910690c574	1784	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT) \| (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	145:64910690c574	1785	break;
AnnaBridge	145:64910690c574	1786	}
AnnaBridge	145:64910690c574	1787	}
AnnaBridge	145:64910690c574	1788	}
AnnaBridge	145:64910690c574	1789
AnnaBridge	145:64910690c574	1790	return 0;
AnnaBridge	145:64910690c574	1791	}
AnnaBridge	145:64910690c574	1792
AnnaBridge	145:64910690c574	1793	/** \brief Create a L1 section descriptor
AnnaBridge	145:64910690c574	1794
AnnaBridge	145:64910690c574	1795	\param [out] descriptor L1 descriptor
AnnaBridge	145:64910690c574	1796	\param [in] reg Section attributes
AnnaBridge	145:64910690c574	1797
AnnaBridge	145:64910690c574	1798	\return 0
AnnaBridge	145:64910690c574	1799	*/
AnnaBridge	145:64910690c574	1800	__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge	145:64910690c574	1801	{
AnnaBridge	145:64910690c574	1802	*descriptor = 0;
AnnaBridge	145:64910690c574	1803
AnnaBridge	145:64910690c574	1804	MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge	145:64910690c574	1805	MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge	145:64910690c574	1806	MMU_DomainSection(descriptor, reg.domain);
AnnaBridge	145:64910690c574	1807	MMU_PSection(descriptor, reg.e_t);
AnnaBridge	145:64910690c574	1808	MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge	145:64910690c574	1809	MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge	145:64910690c574	1810	MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge	145:64910690c574	1811	MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge	145:64910690c574	1812	*descriptor &= SECTION_MASK;
AnnaBridge	145:64910690c574	1813	*descriptor \|= SECTION_DESCRIPTOR;
AnnaBridge	145:64910690c574	1814
AnnaBridge	145:64910690c574	1815	return 0;
AnnaBridge	145:64910690c574	1816	}
AnnaBridge	145:64910690c574	1817
AnnaBridge	145:64910690c574	1818
AnnaBridge	145:64910690c574	1819	/** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge	145:64910690c574	1820
AnnaBridge	145:64910690c574	1821	\param [out] descriptor L1 descriptor
AnnaBridge	145:64910690c574	1822	\param [out] descriptor2 L2 descriptor
AnnaBridge	145:64910690c574	1823	\param [in] reg 4k/64k page attributes
AnnaBridge	145:64910690c574	1824
AnnaBridge	145:64910690c574	1825	\return 0
AnnaBridge	145:64910690c574	1826	*/
AnnaBridge	145:64910690c574	1827	__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
AnnaBridge	145:64910690c574	1828	{
AnnaBridge	145:64910690c574	1829	*descriptor = 0;
AnnaBridge	145:64910690c574	1830	*descriptor2 = 0;
AnnaBridge	145:64910690c574	1831
AnnaBridge	145:64910690c574	1832	switch (reg.rg_t)
AnnaBridge	145:64910690c574	1833	{
AnnaBridge	145:64910690c574	1834	case PAGE_4k:
AnnaBridge	145:64910690c574	1835	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge	145:64910690c574	1836	MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge	145:64910690c574	1837	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	145:64910690c574	1838	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	145:64910690c574	1839	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	145:64910690c574	1840	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	145:64910690c574	1841	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	145:64910690c574	1842	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	145:64910690c574	1843	*descriptor &= PAGE_L1_MASK;
AnnaBridge	145:64910690c574	1844	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	145:64910690c574	1845	*descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge	145:64910690c574	1846	*descriptor2 \|= PAGE_L2_4K_DESC;
AnnaBridge	145:64910690c574	1847	break;
AnnaBridge	145:64910690c574	1848
AnnaBridge	145:64910690c574	1849	case PAGE_64k:
AnnaBridge	145:64910690c574	1850	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge	145:64910690c574	1851	MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge	145:64910690c574	1852	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	145:64910690c574	1853	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	145:64910690c574	1854	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	145:64910690c574	1855	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	145:64910690c574	1856	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	145:64910690c574	1857	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	145:64910690c574	1858	*descriptor &= PAGE_L1_MASK;
AnnaBridge	145:64910690c574	1859	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	145:64910690c574	1860	*descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge	145:64910690c574	1861	*descriptor2 \|= PAGE_L2_64K_DESC;
AnnaBridge	145:64910690c574	1862	break;
AnnaBridge	145:64910690c574	1863
AnnaBridge	145:64910690c574	1864	case SECTION:
AnnaBridge	145:64910690c574	1865	//error
AnnaBridge	145:64910690c574	1866	break;
AnnaBridge	145:64910690c574	1867	}
AnnaBridge	145:64910690c574	1868
AnnaBridge	145:64910690c574	1869	return 0;
AnnaBridge	145:64910690c574	1870	}
AnnaBridge	145:64910690c574	1871
AnnaBridge	145:64910690c574	1872	/** \brief Create a 1MB Section
AnnaBridge	145:64910690c574	1873
AnnaBridge	145:64910690c574	1874	\param [in] ttb Translation table base address
AnnaBridge	145:64910690c574	1875	\param [in] base_address Section base address
AnnaBridge	145:64910690c574	1876	\param [in] count Number of sections to create
AnnaBridge	145:64910690c574	1877	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	145:64910690c574	1878
AnnaBridge	145:64910690c574	1879	*/
AnnaBridge	145:64910690c574	1880	__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge	145:64910690c574	1881	{
AnnaBridge	145:64910690c574	1882	uint32_t offset;
AnnaBridge	145:64910690c574	1883	uint32_t entry;
AnnaBridge	145:64910690c574	1884	uint32_t i;
AnnaBridge	145:64910690c574	1885
AnnaBridge	145:64910690c574	1886	offset = base_address >> 20;
AnnaBridge	145:64910690c574	1887	entry = (base_address & 0xFFF00000) \| descriptor_l1;
AnnaBridge	145:64910690c574	1888
AnnaBridge	145:64910690c574	1889	//4 bytes aligned
AnnaBridge	145:64910690c574	1890	ttb = ttb + offset;
AnnaBridge	145:64910690c574	1891
AnnaBridge	145:64910690c574	1892	for (i = 0; i < count; i++ )
AnnaBridge	145:64910690c574	1893	{
AnnaBridge	145:64910690c574	1894	//4 bytes aligned
AnnaBridge	145:64910690c574	1895	*ttb++ = entry;
AnnaBridge	145:64910690c574	1896	entry += OFFSET_1M;
AnnaBridge	145:64910690c574	1897	}
AnnaBridge	145:64910690c574	1898	}
AnnaBridge	145:64910690c574	1899
AnnaBridge	145:64910690c574	1900	/** \brief Create a 4k page entry
AnnaBridge	145:64910690c574	1901
AnnaBridge	145:64910690c574	1902	\param [in] ttb L1 table base address
AnnaBridge	145:64910690c574	1903	\param [in] base_address 4k base address
AnnaBridge	145:64910690c574	1904	\param [in] count Number of 4k pages to create
AnnaBridge	145:64910690c574	1905	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	145:64910690c574	1906	\param [in] ttb_l2 L2 table base address
AnnaBridge	145:64910690c574	1907	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	145:64910690c574	1908
AnnaBridge	145:64910690c574	1909	*/
AnnaBridge	145:64910690c574	1910	__STATIC_INLINE void MMU_TTPage4k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	145:64910690c574	1911	{
AnnaBridge	145:64910690c574	1912
AnnaBridge	145:64910690c574	1913	uint32_t offset, offset2;
AnnaBridge	145:64910690c574	1914	uint32_t entry, entry2;
AnnaBridge	145:64910690c574	1915	uint32_t i;
AnnaBridge	145:64910690c574	1916
AnnaBridge	145:64910690c574	1917	offset = base_address >> 20;
AnnaBridge	145:64910690c574	1918	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	145:64910690c574	1919
AnnaBridge	145:64910690c574	1920	//4 bytes aligned
AnnaBridge	145:64910690c574	1921	ttb += offset;
AnnaBridge	145:64910690c574	1922	//create l1_entry
AnnaBridge	145:64910690c574	1923	*ttb = entry;
AnnaBridge	145:64910690c574	1924
AnnaBridge	145:64910690c574	1925	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	145:64910690c574	1926	ttb_l2 += offset2;
AnnaBridge	145:64910690c574	1927	entry2 = (base_address & 0xFFFFF000) \| descriptor_l2;
AnnaBridge	145:64910690c574	1928	for (i = 0; i < count; i++ )
AnnaBridge	145:64910690c574	1929	{
AnnaBridge	145:64910690c574	1930	//4 bytes aligned
AnnaBridge	145:64910690c574	1931	*ttb_l2++ = entry2;
AnnaBridge	145:64910690c574	1932	entry2 += OFFSET_4K;
AnnaBridge	145:64910690c574	1933	}
AnnaBridge	145:64910690c574	1934	}
AnnaBridge	145:64910690c574	1935
AnnaBridge	145:64910690c574	1936	/** \brief Create a 64k page entry
AnnaBridge	145:64910690c574	1937
AnnaBridge	145:64910690c574	1938	\param [in] ttb L1 table base address
AnnaBridge	145:64910690c574	1939	\param [in] base_address 64k base address
AnnaBridge	145:64910690c574	1940	\param [in] count Number of 64k pages to create
AnnaBridge	145:64910690c574	1941	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	145:64910690c574	1942	\param [in] ttb_l2 L2 table base address
AnnaBridge	145:64910690c574	1943	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	145:64910690c574	1944
AnnaBridge	145:64910690c574	1945	*/
AnnaBridge	145:64910690c574	1946	__STATIC_INLINE void MMU_TTPage64k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	145:64910690c574	1947	{
AnnaBridge	145:64910690c574	1948	uint32_t offset, offset2;
AnnaBridge	145:64910690c574	1949	uint32_t entry, entry2;
AnnaBridge	145:64910690c574	1950	uint32_t i,j;
AnnaBridge	145:64910690c574	1951
AnnaBridge	145:64910690c574	1952
AnnaBridge	145:64910690c574	1953	offset = base_address >> 20;
AnnaBridge	145:64910690c574	1954	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	145:64910690c574	1955
AnnaBridge	145:64910690c574	1956	//4 bytes aligned
AnnaBridge	145:64910690c574	1957	ttb += offset;
AnnaBridge	145:64910690c574	1958	//create l1_entry
AnnaBridge	145:64910690c574	1959	*ttb = entry;
AnnaBridge	145:64910690c574	1960
AnnaBridge	145:64910690c574	1961	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	145:64910690c574	1962	ttb_l2 += offset2;
AnnaBridge	145:64910690c574	1963	entry2 = (base_address & 0xFFFF0000) \| descriptor_l2;
AnnaBridge	145:64910690c574	1964	for (i = 0; i < count; i++ )
AnnaBridge	145:64910690c574	1965	{
AnnaBridge	145:64910690c574	1966	//create 16 entries
AnnaBridge	145:64910690c574	1967	for (j = 0; j < 16; j++)
AnnaBridge	145:64910690c574	1968	{
AnnaBridge	145:64910690c574	1969	//4 bytes aligned
AnnaBridge	145:64910690c574	1970	*ttb_l2++ = entry2;
AnnaBridge	145:64910690c574	1971	}
AnnaBridge	145:64910690c574	1972	entry2 += OFFSET_64K;
AnnaBridge	145:64910690c574	1973	}
AnnaBridge	145:64910690c574	1974	}
AnnaBridge	145:64910690c574	1975
AnnaBridge	145:64910690c574	1976	/** \brief Enable MMU
AnnaBridge	145:64910690c574	1977
AnnaBridge	145:64910690c574	1978	Enable MMU
AnnaBridge	145:64910690c574	1979	*/
AnnaBridge	145:64910690c574	1980	__STATIC_INLINE void MMU_Enable(void) {
AnnaBridge	145:64910690c574	1981	// Set M bit 0 to enable the MMU
AnnaBridge	145:64910690c574	1982	// Set AFE bit to enable simplified access permissions model
AnnaBridge	145:64910690c574	1983	// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge	145:64910690c574	1984	__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) \| 1 \| (1 << 29));
AnnaBridge	145:64910690c574	1985	__ISB();
AnnaBridge	145:64910690c574	1986	}
AnnaBridge	145:64910690c574	1987
AnnaBridge	145:64910690c574	1988	/** \brief Disable MMU
AnnaBridge	145:64910690c574	1989
AnnaBridge	145:64910690c574	1990	Disable MMU
AnnaBridge	145:64910690c574	1991	*/
AnnaBridge	145:64910690c574	1992	__STATIC_INLINE void MMU_Disable(void) {
AnnaBridge	145:64910690c574	1993	// Clear M bit 0 to disable the MMU
AnnaBridge	145:64910690c574	1994	__set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge	145:64910690c574	1995	__ISB();
AnnaBridge	145:64910690c574	1996	}
AnnaBridge	145:64910690c574	1997
AnnaBridge	145:64910690c574	1998	/** \brief Invalidate entire unified TLB
AnnaBridge	145:64910690c574	1999
AnnaBridge	145:64910690c574	2000	TLBIALL. Invalidate entire unified TLB
AnnaBridge	145:64910690c574	2001	*/
AnnaBridge	145:64910690c574	2002
AnnaBridge	145:64910690c574	2003	__STATIC_INLINE void MMU_InvalidateTLB(void) {
AnnaBridge	145:64910690c574	2004	__set_TLBIALL(0);
AnnaBridge	145:64910690c574	2005	__DSB(); //ensure completion of the invalidation
AnnaBridge	145:64910690c574	2006	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	145:64910690c574	2007	}
AnnaBridge	145:64910690c574	2008
AnnaBridge	145:64910690c574	2009
AnnaBridge	145:64910690c574	2010	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2011	}
AnnaBridge	145:64910690c574	2012	#endif
AnnaBridge	145:64910690c574	2013
AnnaBridge	145:64910690c574	2014	#endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge	145:64910690c574	2015
AnnaBridge	145:64910690c574	2016	#endif /* __CMSIS_GENERIC */