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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/cmsis_armclang.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**************************************************************************//**
AnnaBridge 145:64910690c574 2 * @file cmsis_armclang.h
AnnaBridge 145:64910690c574 3 * @brief CMSIS compiler specific macros, functions, instructions
AnnaBridge 145:64910690c574 4 * @version V1.00
AnnaBridge 145:64910690c574 5 * @date 05. Apr 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 145:64910690c574 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 145:64910690c574 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
AnnaBridge 145:64910690c574 24
AnnaBridge 145:64910690c574 25 #ifndef __CMSIS_ARMCLANG_H
AnnaBridge 145:64910690c574 26 #define __CMSIS_ARMCLANG_H
AnnaBridge 145:64910690c574 27
AnnaBridge 145:64910690c574 28 #ifndef __ARM_COMPAT_H
AnnaBridge 145:64910690c574 29 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
AnnaBridge 145:64910690c574 30 #endif
AnnaBridge 145:64910690c574 31
AnnaBridge 145:64910690c574 32 /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 33 #ifndef __ASM
AnnaBridge 145:64910690c574 34 #define __ASM __asm
AnnaBridge 145:64910690c574 35 #endif
AnnaBridge 145:64910690c574 36 #ifndef __INLINE
AnnaBridge 145:64910690c574 37 #define __INLINE __inline
AnnaBridge 145:64910690c574 38 #endif
AnnaBridge 145:64910690c574 39 #ifndef __STATIC_INLINE
AnnaBridge 145:64910690c574 40 #define __STATIC_INLINE static __inline
AnnaBridge 145:64910690c574 41 #endif
AnnaBridge 145:64910690c574 42 #ifndef __STATIC_ASM
AnnaBridge 145:64910690c574 43 #define __STATIC_ASM static __asm
AnnaBridge 145:64910690c574 44 #endif
AnnaBridge 145:64910690c574 45 #ifndef __NO_RETURN
AnnaBridge 145:64910690c574 46 #define __NO_RETURN __declspec(noreturn)
AnnaBridge 145:64910690c574 47 #endif
AnnaBridge 145:64910690c574 48 #ifndef __USED
AnnaBridge 145:64910690c574 49 #define __USED __attribute__((used))
AnnaBridge 145:64910690c574 50 #endif
AnnaBridge 145:64910690c574 51 #ifndef __WEAK
AnnaBridge 145:64910690c574 52 #define __WEAK __attribute__((weak))
AnnaBridge 145:64910690c574 53 #endif
AnnaBridge 145:64910690c574 54 #ifndef __UNALIGNED_UINT32
AnnaBridge 145:64910690c574 55 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
AnnaBridge 145:64910690c574 56 #endif
AnnaBridge 145:64910690c574 57 #ifndef __ALIGNED
AnnaBridge 145:64910690c574 58 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 145:64910690c574 59 #endif
AnnaBridge 145:64910690c574 60 #ifndef __PACKED
AnnaBridge 145:64910690c574 61 #define __PACKED __attribute__((packed))
AnnaBridge 145:64910690c574 62 #endif
AnnaBridge 145:64910690c574 63
AnnaBridge 145:64910690c574 64
AnnaBridge 145:64910690c574 65 /* ########################### Core Function Access ########################### */
AnnaBridge 145:64910690c574 66
AnnaBridge 145:64910690c574 67 /**
AnnaBridge 145:64910690c574 68 \brief Get FPSCR
AnnaBridge 145:64910690c574 69 \return Floating Point Status/Control register value
AnnaBridge 145:64910690c574 70 */
AnnaBridge 145:64910690c574 71 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 145:64910690c574 72 {
AnnaBridge 145:64910690c574 73 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 74 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 75 uint32_t result;
AnnaBridge 145:64910690c574 76 __ASM volatile("MRS %0, fpscr" : "=r" (result) );
AnnaBridge 145:64910690c574 77 return(result);
AnnaBridge 145:64910690c574 78 #else
AnnaBridge 145:64910690c574 79 return(0U);
AnnaBridge 145:64910690c574 80 #endif
AnnaBridge 145:64910690c574 81 }
AnnaBridge 145:64910690c574 82
AnnaBridge 145:64910690c574 83 /**
AnnaBridge 145:64910690c574 84 \brief Set FPSCR
AnnaBridge 145:64910690c574 85 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 145:64910690c574 86 */
AnnaBridge 145:64910690c574 87 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 145:64910690c574 88 {
AnnaBridge 145:64910690c574 89 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 90 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 91 __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory");
AnnaBridge 145:64910690c574 92 #else
AnnaBridge 145:64910690c574 93 (void)fpscr;
AnnaBridge 145:64910690c574 94 #endif
AnnaBridge 145:64910690c574 95 }
AnnaBridge 145:64910690c574 96
AnnaBridge 145:64910690c574 97 /* ########################## Core Instruction Access ######################### */
AnnaBridge 145:64910690c574 98 /**
AnnaBridge 145:64910690c574 99 \brief No Operation
AnnaBridge 145:64910690c574 100 */
AnnaBridge 145:64910690c574 101 #define __NOP __builtin_arm_nop
AnnaBridge 145:64910690c574 102
AnnaBridge 145:64910690c574 103 /**
AnnaBridge 145:64910690c574 104 \brief Wait For Interrupt
AnnaBridge 145:64910690c574 105 */
AnnaBridge 145:64910690c574 106 #define __WFI __builtin_arm_wfi
AnnaBridge 145:64910690c574 107
AnnaBridge 145:64910690c574 108 /**
AnnaBridge 145:64910690c574 109 \brief Wait For Event
AnnaBridge 145:64910690c574 110 */
AnnaBridge 145:64910690c574 111 #define __WFE __builtin_arm_wfe
AnnaBridge 145:64910690c574 112
AnnaBridge 145:64910690c574 113 /**
AnnaBridge 145:64910690c574 114 \brief Send Event
AnnaBridge 145:64910690c574 115 */
AnnaBridge 145:64910690c574 116 #define __SEV __builtin_arm_sev
AnnaBridge 145:64910690c574 117
AnnaBridge 145:64910690c574 118 /**
AnnaBridge 145:64910690c574 119 \brief Instruction Synchronization Barrier
AnnaBridge 145:64910690c574 120 */
AnnaBridge 145:64910690c574 121 #define __ISB() do {\
AnnaBridge 145:64910690c574 122 __schedule_barrier();\
AnnaBridge 145:64910690c574 123 __builtin_arm_isb(0xF);\
AnnaBridge 145:64910690c574 124 __schedule_barrier();\
AnnaBridge 145:64910690c574 125 } while (0U)
AnnaBridge 145:64910690c574 126
AnnaBridge 145:64910690c574 127 /**
AnnaBridge 145:64910690c574 128 \brief Data Synchronization Barrier
AnnaBridge 145:64910690c574 129 */
AnnaBridge 145:64910690c574 130 #define __DSB() do {\
AnnaBridge 145:64910690c574 131 __schedule_barrier();\
AnnaBridge 145:64910690c574 132 __builtin_arm_dsb(0xF);\
AnnaBridge 145:64910690c574 133 __schedule_barrier();\
AnnaBridge 145:64910690c574 134 } while (0U)
AnnaBridge 145:64910690c574 135
AnnaBridge 145:64910690c574 136 /**
AnnaBridge 145:64910690c574 137 \brief Data Memory Barrier
AnnaBridge 145:64910690c574 138 */
AnnaBridge 145:64910690c574 139 #define __DMB() do {\
AnnaBridge 145:64910690c574 140 __schedule_barrier();\
AnnaBridge 145:64910690c574 141 __builtin_arm_dmb(0xF);\
AnnaBridge 145:64910690c574 142 __schedule_barrier();\
AnnaBridge 145:64910690c574 143 } while (0U)
AnnaBridge 145:64910690c574 144
AnnaBridge 145:64910690c574 145 /**
AnnaBridge 145:64910690c574 146 \brief Reverse byte order (32 bit)
AnnaBridge 145:64910690c574 147 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 148 \return Reversed value
AnnaBridge 145:64910690c574 149 */
AnnaBridge 145:64910690c574 150 #define __REV __builtin_bswap32
AnnaBridge 145:64910690c574 151
AnnaBridge 145:64910690c574 152 /**
AnnaBridge 145:64910690c574 153 \brief Reverse byte order (16 bit)
AnnaBridge 145:64910690c574 154 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 155 \return Reversed value
AnnaBridge 145:64910690c574 156 */
AnnaBridge 145:64910690c574 157 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 145:64910690c574 158 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 145:64910690c574 159 {
AnnaBridge 145:64910690c574 160 uint32_t result;
AnnaBridge 145:64910690c574 161 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
AnnaBridge 145:64910690c574 162 return result;
AnnaBridge 145:64910690c574 163 }
AnnaBridge 145:64910690c574 164 #endif
AnnaBridge 145:64910690c574 165
AnnaBridge 145:64910690c574 166 /**
AnnaBridge 145:64910690c574 167 \brief Reverse byte order in signed short value
AnnaBridge 145:64910690c574 168 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 169 \return Reversed value
AnnaBridge 145:64910690c574 170 */
AnnaBridge 145:64910690c574 171 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 145:64910690c574 172 __attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
AnnaBridge 145:64910690c574 173 {
AnnaBridge 145:64910690c574 174 int32_t result;
AnnaBridge 145:64910690c574 175 __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
AnnaBridge 145:64910690c574 176 return result;
AnnaBridge 145:64910690c574 177 }
AnnaBridge 145:64910690c574 178 #endif
AnnaBridge 145:64910690c574 179
AnnaBridge 145:64910690c574 180 /**
AnnaBridge 145:64910690c574 181 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 145:64910690c574 182 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 145:64910690c574 183 \param [in] op1 Value to rotate
AnnaBridge 145:64910690c574 184 \param [in] op2 Number of Bits to rotate
AnnaBridge 145:64910690c574 185 \return Rotated value
AnnaBridge 145:64910690c574 186 */
AnnaBridge 145:64910690c574 187 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 188 {
AnnaBridge 145:64910690c574 189 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 145:64910690c574 190 }
AnnaBridge 145:64910690c574 191
AnnaBridge 145:64910690c574 192 /**
AnnaBridge 145:64910690c574 193 \brief Breakpoint
AnnaBridge 145:64910690c574 194 \param [in] value is ignored by the processor.
AnnaBridge 145:64910690c574 195 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 145:64910690c574 196 */
AnnaBridge 145:64910690c574 197 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 145:64910690c574 198
AnnaBridge 145:64910690c574 199 /**
AnnaBridge 145:64910690c574 200 \brief Reverse bit order of value
AnnaBridge 145:64910690c574 201 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 202 \return Reversed value
AnnaBridge 145:64910690c574 203 */
AnnaBridge 145:64910690c574 204 #define __RBIT __builtin_arm_rbit
AnnaBridge 145:64910690c574 205
AnnaBridge 145:64910690c574 206 /**
AnnaBridge 145:64910690c574 207 \brief Count leading zeros
AnnaBridge 145:64910690c574 208 \param [in] value Value to count the leading zeros
AnnaBridge 145:64910690c574 209 \return number of leading zeros in value
AnnaBridge 145:64910690c574 210 */
AnnaBridge 145:64910690c574 211 #define __CLZ __builtin_clz
AnnaBridge 145:64910690c574 212
AnnaBridge 145:64910690c574 213 /** \brief Get CPSR Register
AnnaBridge 145:64910690c574 214 \return CPSR Register value
AnnaBridge 145:64910690c574 215 */
AnnaBridge 145:64910690c574 216 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 145:64910690c574 217 {
AnnaBridge 145:64910690c574 218 uint32_t result;
AnnaBridge 145:64910690c574 219 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
AnnaBridge 145:64910690c574 220 return(result);
AnnaBridge 145:64910690c574 221 }
AnnaBridge 145:64910690c574 222
AnnaBridge 145:64910690c574 223 /** \brief Get Mode
AnnaBridge 145:64910690c574 224 \return Processor Mode
AnnaBridge 145:64910690c574 225 */
AnnaBridge 145:64910690c574 226 __STATIC_INLINE uint32_t __get_mode(void) {
AnnaBridge 145:64910690c574 227 return (__get_CPSR() & 0x1FU);
AnnaBridge 145:64910690c574 228 }
AnnaBridge 145:64910690c574 229
AnnaBridge 145:64910690c574 230 /** \brief Set Mode
AnnaBridge 145:64910690c574 231 \param [in] mode Mode value to set
AnnaBridge 145:64910690c574 232 */
AnnaBridge 145:64910690c574 233 __STATIC_INLINE void __set_mode(uint32_t mode) {
AnnaBridge 145:64910690c574 234 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
AnnaBridge 145:64910690c574 235 }
AnnaBridge 145:64910690c574 236
AnnaBridge 145:64910690c574 237 /** \brief Set Stack Pointer
AnnaBridge 145:64910690c574 238 \param [in] stack Stack Pointer value to set
AnnaBridge 145:64910690c574 239 */
AnnaBridge 145:64910690c574 240 __STATIC_INLINE void __set_SP(uint32_t stack)
AnnaBridge 145:64910690c574 241 {
AnnaBridge 145:64910690c574 242 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
AnnaBridge 145:64910690c574 243 }
AnnaBridge 145:64910690c574 244
AnnaBridge 145:64910690c574 245 /** \brief Set Process Stack Pointer
AnnaBridge 145:64910690c574 246 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 145:64910690c574 247 */
AnnaBridge 145:64910690c574 248 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 145:64910690c574 249 {
AnnaBridge 145:64910690c574 250 __ASM volatile(
AnnaBridge 145:64910690c574 251 ".preserve8 \n"
AnnaBridge 145:64910690c574 252 "BIC r0, r0, #7 \n" // ensure stack is 8-byte aligned
AnnaBridge 145:64910690c574 253 "MRS r1, cpsr \n"
AnnaBridge 145:64910690c574 254 "CPS #0x1F \n" // no effect in USR mode
AnnaBridge 145:64910690c574 255 "MOV sp, r0 \n"
AnnaBridge 145:64910690c574 256 "MSR cpsr_c, r1 \n" // no effect in USR mode
AnnaBridge 145:64910690c574 257 "ISB"
AnnaBridge 145:64910690c574 258 );
AnnaBridge 145:64910690c574 259 }
AnnaBridge 145:64910690c574 260
AnnaBridge 145:64910690c574 261 /** \brief Set User Mode
AnnaBridge 145:64910690c574 262 */
AnnaBridge 145:64910690c574 263 __STATIC_INLINE void __set_CPS_USR(void)
AnnaBridge 145:64910690c574 264 {
AnnaBridge 145:64910690c574 265 __ASM volatile("CPS #0x10");
AnnaBridge 145:64910690c574 266 }
AnnaBridge 145:64910690c574 267
AnnaBridge 145:64910690c574 268 /** \brief Get FPEXC
AnnaBridge 145:64910690c574 269 \return Floating Point Exception Control register value
AnnaBridge 145:64910690c574 270 */
AnnaBridge 145:64910690c574 271 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 145:64910690c574 272 {
AnnaBridge 145:64910690c574 273 #if (__FPU_PRESENT == 1)
AnnaBridge 145:64910690c574 274 uint32_t result;
AnnaBridge 145:64910690c574 275 __ASM volatile("MRS %0, fpexc" : "=r" (result) );
AnnaBridge 145:64910690c574 276 return(result);
AnnaBridge 145:64910690c574 277 #else
AnnaBridge 145:64910690c574 278 return(0);
AnnaBridge 145:64910690c574 279 #endif
AnnaBridge 145:64910690c574 280 }
AnnaBridge 145:64910690c574 281
AnnaBridge 145:64910690c574 282 /** \brief Set FPEXC
AnnaBridge 145:64910690c574 283 \param [in] fpexc Floating Point Exception Control value to set
AnnaBridge 145:64910690c574 284 */
AnnaBridge 145:64910690c574 285 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 145:64910690c574 286 {
AnnaBridge 145:64910690c574 287 #if (__FPU_PRESENT == 1)
AnnaBridge 145:64910690c574 288 __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
AnnaBridge 145:64910690c574 289 #endif
AnnaBridge 145:64910690c574 290 }
AnnaBridge 145:64910690c574 291
AnnaBridge 145:64910690c574 292 /** \brief Get CPACR
AnnaBridge 145:64910690c574 293 \return Coprocessor Access Control register value
AnnaBridge 145:64910690c574 294 */
AnnaBridge 145:64910690c574 295 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 145:64910690c574 296 {
AnnaBridge 145:64910690c574 297 uint32_t result;
AnnaBridge 145:64910690c574 298 __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
AnnaBridge 145:64910690c574 299 return result;
AnnaBridge 145:64910690c574 300 }
AnnaBridge 145:64910690c574 301
AnnaBridge 145:64910690c574 302 /** \brief Set CPACR
AnnaBridge 145:64910690c574 303 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 145:64910690c574 304 */
AnnaBridge 145:64910690c574 305 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 145:64910690c574 306 {
AnnaBridge 145:64910690c574 307 __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
AnnaBridge 145:64910690c574 308 }
AnnaBridge 145:64910690c574 309
AnnaBridge 145:64910690c574 310 /** \brief Get CBAR
AnnaBridge 145:64910690c574 311 \return Configuration Base Address register value
AnnaBridge 145:64910690c574 312 */
AnnaBridge 145:64910690c574 313 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 145:64910690c574 314 uint32_t result;
AnnaBridge 145:64910690c574 315 __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
AnnaBridge 145:64910690c574 316 return result;
AnnaBridge 145:64910690c574 317 }
AnnaBridge 145:64910690c574 318
AnnaBridge 145:64910690c574 319 /** \brief Get TTBR0
AnnaBridge 145:64910690c574 320
AnnaBridge 145:64910690c574 321 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 145:64910690c574 322
AnnaBridge 145:64910690c574 323 \return Translation Table Base Register 0 value
AnnaBridge 145:64910690c574 324 */
AnnaBridge 145:64910690c574 325 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 145:64910690c574 326 uint32_t result;
AnnaBridge 145:64910690c574 327 __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
AnnaBridge 145:64910690c574 328 return result;
AnnaBridge 145:64910690c574 329 }
AnnaBridge 145:64910690c574 330
AnnaBridge 145:64910690c574 331 /** \brief Set TTBR0
AnnaBridge 145:64910690c574 332
AnnaBridge 145:64910690c574 333 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 145:64910690c574 334
AnnaBridge 145:64910690c574 335 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 145:64910690c574 336 */
AnnaBridge 145:64910690c574 337 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 145:64910690c574 338 __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
AnnaBridge 145:64910690c574 339 }
AnnaBridge 145:64910690c574 340
AnnaBridge 145:64910690c574 341 /** \brief Get DACR
AnnaBridge 145:64910690c574 342
AnnaBridge 145:64910690c574 343 This function returns the value of the Domain Access Control Register.
AnnaBridge 145:64910690c574 344
AnnaBridge 145:64910690c574 345 \return Domain Access Control Register value
AnnaBridge 145:64910690c574 346 */
AnnaBridge 145:64910690c574 347 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 145:64910690c574 348 uint32_t result;
AnnaBridge 145:64910690c574 349 __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
AnnaBridge 145:64910690c574 350 return result;
AnnaBridge 145:64910690c574 351 }
AnnaBridge 145:64910690c574 352
AnnaBridge 145:64910690c574 353 /** \brief Set DACR
AnnaBridge 145:64910690c574 354
AnnaBridge 145:64910690c574 355 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 145:64910690c574 356
AnnaBridge 145:64910690c574 357 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 145:64910690c574 358 */
AnnaBridge 145:64910690c574 359 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 145:64910690c574 360 __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
AnnaBridge 145:64910690c574 361 }
AnnaBridge 145:64910690c574 362
AnnaBridge 145:64910690c574 363 /** \brief Set SCTLR
AnnaBridge 145:64910690c574 364
AnnaBridge 145:64910690c574 365 This function assigns the given value to the System Control Register.
AnnaBridge 145:64910690c574 366
AnnaBridge 145:64910690c574 367 \param [in] sctlr System Control Register value to set
AnnaBridge 145:64910690c574 368 */
AnnaBridge 145:64910690c574 369 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 145:64910690c574 370 {
AnnaBridge 145:64910690c574 371 __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
AnnaBridge 145:64910690c574 372 }
AnnaBridge 145:64910690c574 373
AnnaBridge 145:64910690c574 374 /** \brief Get SCTLR
AnnaBridge 145:64910690c574 375 \return System Control Register value
AnnaBridge 145:64910690c574 376 */
AnnaBridge 145:64910690c574 377 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 145:64910690c574 378 uint32_t result;
AnnaBridge 145:64910690c574 379 __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
AnnaBridge 145:64910690c574 380 return result;
AnnaBridge 145:64910690c574 381 }
AnnaBridge 145:64910690c574 382
AnnaBridge 145:64910690c574 383 /** \brief Set ACTRL
AnnaBridge 145:64910690c574 384 \param [in] actrl Auxiliary Control Register value to set
AnnaBridge 145:64910690c574 385 */
AnnaBridge 145:64910690c574 386 __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
AnnaBridge 145:64910690c574 387 {
AnnaBridge 145:64910690c574 388 __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
AnnaBridge 145:64910690c574 389 }
AnnaBridge 145:64910690c574 390
AnnaBridge 145:64910690c574 391 /** \brief Get ACTRL
AnnaBridge 145:64910690c574 392 \return Auxiliary Control Register value
AnnaBridge 145:64910690c574 393 */
AnnaBridge 145:64910690c574 394 __STATIC_INLINE uint32_t __get_ACTRL(void)
AnnaBridge 145:64910690c574 395 {
AnnaBridge 145:64910690c574 396 uint32_t result;
AnnaBridge 145:64910690c574 397 __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
AnnaBridge 145:64910690c574 398 return result;
AnnaBridge 145:64910690c574 399 }
AnnaBridge 145:64910690c574 400
AnnaBridge 145:64910690c574 401 /** \brief Get MPIDR
AnnaBridge 145:64910690c574 402
AnnaBridge 145:64910690c574 403 This function returns the value of the Multiprocessor Affinity Register.
AnnaBridge 145:64910690c574 404
AnnaBridge 145:64910690c574 405 \return Multiprocessor Affinity Register value
AnnaBridge 145:64910690c574 406 */
AnnaBridge 145:64910690c574 407 __STATIC_INLINE uint32_t __get_MPIDR(void)
AnnaBridge 145:64910690c574 408 {
AnnaBridge 145:64910690c574 409 uint32_t result;
AnnaBridge 145:64910690c574 410 __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
AnnaBridge 145:64910690c574 411 return result;
AnnaBridge 145:64910690c574 412 }
AnnaBridge 145:64910690c574 413
AnnaBridge 145:64910690c574 414 /** \brief Get VBAR
AnnaBridge 145:64910690c574 415
AnnaBridge 145:64910690c574 416 This function returns the value of the Vector Base Address Register.
AnnaBridge 145:64910690c574 417
AnnaBridge 145:64910690c574 418 \return Vector Base Address Register
AnnaBridge 145:64910690c574 419 */
AnnaBridge 145:64910690c574 420 __STATIC_INLINE uint32_t __get_VBAR(void)
AnnaBridge 145:64910690c574 421 {
AnnaBridge 145:64910690c574 422 uint32_t result;
AnnaBridge 145:64910690c574 423 __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
AnnaBridge 145:64910690c574 424 return result;
AnnaBridge 145:64910690c574 425 }
AnnaBridge 145:64910690c574 426
AnnaBridge 145:64910690c574 427 /** \brief Set VBAR
AnnaBridge 145:64910690c574 428
AnnaBridge 145:64910690c574 429 This function assigns the given value to the Vector Base Address Register.
AnnaBridge 145:64910690c574 430
AnnaBridge 145:64910690c574 431 \param [in] vbar Vector Base Address Register value to set
AnnaBridge 145:64910690c574 432 */
AnnaBridge 145:64910690c574 433 __STATIC_INLINE void __set_VBAR(uint32_t vbar)
AnnaBridge 145:64910690c574 434 {
AnnaBridge 145:64910690c574 435 __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
AnnaBridge 145:64910690c574 436 }
AnnaBridge 145:64910690c574 437
AnnaBridge 145:64910690c574 438 /** \brief Set CNTP_TVAL
AnnaBridge 145:64910690c574 439
AnnaBridge 145:64910690c574 440 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
AnnaBridge 145:64910690c574 441
AnnaBridge 145:64910690c574 442 \param [in] value CNTP_TVAL Register value to set
AnnaBridge 145:64910690c574 443 */
AnnaBridge 145:64910690c574 444 __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
AnnaBridge 145:64910690c574 445 __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 446 }
AnnaBridge 145:64910690c574 447
AnnaBridge 145:64910690c574 448 /** \brief Get CNTP_TVAL
AnnaBridge 145:64910690c574 449
AnnaBridge 145:64910690c574 450 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
AnnaBridge 145:64910690c574 451
AnnaBridge 145:64910690c574 452 \return CNTP_TVAL Register value
AnnaBridge 145:64910690c574 453 */
AnnaBridge 145:64910690c574 454 __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
AnnaBridge 145:64910690c574 455 uint32_t result;
AnnaBridge 145:64910690c574 456 __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
AnnaBridge 145:64910690c574 457 return result;
AnnaBridge 145:64910690c574 458 }
AnnaBridge 145:64910690c574 459
AnnaBridge 145:64910690c574 460 /** \brief Set CNTP_CTL
AnnaBridge 145:64910690c574 461
AnnaBridge 145:64910690c574 462 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
AnnaBridge 145:64910690c574 463
AnnaBridge 145:64910690c574 464 \param [in] value CNTP_CTL Register value to set
AnnaBridge 145:64910690c574 465 */
AnnaBridge 145:64910690c574 466 __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
AnnaBridge 145:64910690c574 467 __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 468 }
AnnaBridge 145:64910690c574 469
AnnaBridge 145:64910690c574 470 /** \brief Set TLBIALL
AnnaBridge 145:64910690c574 471
AnnaBridge 145:64910690c574 472 TLB Invalidate All
AnnaBridge 145:64910690c574 473 */
AnnaBridge 145:64910690c574 474 __STATIC_INLINE void __set_TLBIALL(uint32_t value) {
AnnaBridge 145:64910690c574 475 __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 476 }
AnnaBridge 145:64910690c574 477
AnnaBridge 145:64910690c574 478 /** \brief Set BPIALL.
AnnaBridge 145:64910690c574 479
AnnaBridge 145:64910690c574 480 Branch Predictor Invalidate All
AnnaBridge 145:64910690c574 481 */
AnnaBridge 145:64910690c574 482 __STATIC_INLINE void __set_BPIALL(uint32_t value) {
AnnaBridge 145:64910690c574 483 __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 484 }
AnnaBridge 145:64910690c574 485
AnnaBridge 145:64910690c574 486 /** \brief Set ICIALLU
AnnaBridge 145:64910690c574 487
AnnaBridge 145:64910690c574 488 Instruction Cache Invalidate All
AnnaBridge 145:64910690c574 489 */
AnnaBridge 145:64910690c574 490 __STATIC_INLINE void __set_ICIALLU(uint32_t value) {
AnnaBridge 145:64910690c574 491 __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 492 }
AnnaBridge 145:64910690c574 493
AnnaBridge 145:64910690c574 494 /** \brief Set DCCMVAC
AnnaBridge 145:64910690c574 495
AnnaBridge 145:64910690c574 496 Data cache clean
AnnaBridge 145:64910690c574 497 */
AnnaBridge 145:64910690c574 498 __STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 499 __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 500 }
AnnaBridge 145:64910690c574 501
AnnaBridge 145:64910690c574 502 /** \brief Set DCIMVAC
AnnaBridge 145:64910690c574 503
AnnaBridge 145:64910690c574 504 Data cache invalidate
AnnaBridge 145:64910690c574 505 */
AnnaBridge 145:64910690c574 506 __STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 507 __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 508 }
AnnaBridge 145:64910690c574 509
AnnaBridge 145:64910690c574 510 /** \brief Set DCCIMVAC
AnnaBridge 145:64910690c574 511
AnnaBridge 145:64910690c574 512 Data cache clean and invalidate
AnnaBridge 145:64910690c574 513 */
AnnaBridge 145:64910690c574 514 __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 515 __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
AnnaBridge 145:64910690c574 516 }
AnnaBridge 145:64910690c574 517
AnnaBridge 145:64910690c574 518 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 145:64910690c574 519
AnnaBridge 145:64910690c574 520 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge 145:64910690c574 521 */
AnnaBridge 145:64910690c574 522 __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 145:64910690c574 523 __ASM volatile(
AnnaBridge 145:64910690c574 524 " PUSH {R4-R11} \n"
AnnaBridge 145:64910690c574 525
AnnaBridge 145:64910690c574 526 " MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR
AnnaBridge 145:64910690c574 527 " ANDS R3, R6, #0x07000000 \n" // Extract coherency level
AnnaBridge 145:64910690c574 528 " MOV R3, R3, LSR #23 \n" // Total cache levels << 1
AnnaBridge 145:64910690c574 529 " BEQ Finished \n" // If 0, no need to clean
AnnaBridge 145:64910690c574 530
AnnaBridge 145:64910690c574 531 " MOV R10, #0 \n" // R10 holds current cache level << 1
AnnaBridge 145:64910690c574 532 "Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position
AnnaBridge 145:64910690c574 533 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
AnnaBridge 145:64910690c574 534 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
AnnaBridge 145:64910690c574 535 " CMP R1, #2 \n"
AnnaBridge 145:64910690c574 536 " BLT Skip \n" // No cache or only instruction cache at this level
AnnaBridge 145:64910690c574 537
AnnaBridge 145:64910690c574 538 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
AnnaBridge 145:64910690c574 539 " ISB \n" // ISB to sync the change to the CacheSizeID reg
AnnaBridge 145:64910690c574 540 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
AnnaBridge 145:64910690c574 541 " AND R2, R1, #7 \n" // Extract the line length field
AnnaBridge 145:64910690c574 542 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 145:64910690c574 543 " LDR R4, =0x3FF \n"
AnnaBridge 145:64910690c574 544 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
AnnaBridge 145:64910690c574 545 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
AnnaBridge 145:64910690c574 546 " LDR R7, =0x7FFF \n"
AnnaBridge 145:64910690c574 547 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
AnnaBridge 145:64910690c574 548
AnnaBridge 145:64910690c574 549 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
AnnaBridge 145:64910690c574 550
AnnaBridge 145:64910690c574 551 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
AnnaBridge 145:64910690c574 552 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
AnnaBridge 145:64910690c574 553 " CMP R0, #0 \n"
AnnaBridge 145:64910690c574 554 " BNE Dccsw \n"
AnnaBridge 145:64910690c574 555 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
AnnaBridge 145:64910690c574 556 " B cont \n"
AnnaBridge 145:64910690c574 557 "Dccsw: CMP R0, #1 \n"
AnnaBridge 145:64910690c574 558 " BNE Dccisw \n"
AnnaBridge 145:64910690c574 559 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
AnnaBridge 145:64910690c574 560 " B cont \n"
AnnaBridge 145:64910690c574 561 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 145:64910690c574 562 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
AnnaBridge 145:64910690c574 563 " BGE Loop3 \n"
AnnaBridge 145:64910690c574 564 " SUBS R7, R7, #1 \n" // Decrement the Set number
AnnaBridge 145:64910690c574 565 " BGE Loop2 \n"
AnnaBridge 145:64910690c574 566 "Skip: ADD R10, R10, #2 \n" // Increment the cache number
AnnaBridge 145:64910690c574 567 " CMP R3, R10 \n"
AnnaBridge 145:64910690c574 568 " BGT Loop1 \n"
AnnaBridge 145:64910690c574 569
AnnaBridge 145:64910690c574 570 "Finished: \n"
AnnaBridge 145:64910690c574 571 " DSB \n"
AnnaBridge 145:64910690c574 572 " POP {R4-R11} "
AnnaBridge 145:64910690c574 573 );
AnnaBridge 145:64910690c574 574 }
AnnaBridge 145:64910690c574 575
AnnaBridge 145:64910690c574 576 /** \brief Enable Floating Point Unit
AnnaBridge 145:64910690c574 577
AnnaBridge 145:64910690c574 578 Critical section, called from undef handler, so systick is disabled
AnnaBridge 145:64910690c574 579 */
AnnaBridge 145:64910690c574 580 __STATIC_INLINE void __FPU_Enable(void) {
AnnaBridge 145:64910690c574 581 __ASM volatile(
AnnaBridge 145:64910690c574 582 //Permit access to VFP/NEON, registers by modifying CPACR
AnnaBridge 145:64910690c574 583 " MRC p15,0,R1,c1,c0,2 \n"
AnnaBridge 145:64910690c574 584 " ORR R1,R1,#0x00F00000 \n"
AnnaBridge 145:64910690c574 585 " MCR p15,0,R1,c1,c0,2 \n"
AnnaBridge 145:64910690c574 586
AnnaBridge 145:64910690c574 587 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
AnnaBridge 145:64910690c574 588 " ISB \n"
AnnaBridge 145:64910690c574 589
AnnaBridge 145:64910690c574 590 //Enable VFP/NEON
AnnaBridge 145:64910690c574 591 " VMRS R1,FPEXC \n"
AnnaBridge 145:64910690c574 592 " ORR R1,R1,#0x40000000 \n"
AnnaBridge 145:64910690c574 593 " VMSR FPEXC,R1 \n"
AnnaBridge 145:64910690c574 594
AnnaBridge 145:64910690c574 595 //Initialise VFP/NEON registers to 0
AnnaBridge 145:64910690c574 596 " MOV R2,#0 \n"
AnnaBridge 145:64910690c574 597 #if 0 // TODO: Initialize FPU registers according to available register count
AnnaBridge 145:64910690c574 598 ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
AnnaBridge 145:64910690c574 599 //Initialise D16 registers to 0
AnnaBridge 145:64910690c574 600 " VMOV D0, R2,R2 \n"
AnnaBridge 145:64910690c574 601 " VMOV D1, R2,R2 \n"
AnnaBridge 145:64910690c574 602 " VMOV D2, R2,R2 \n"
AnnaBridge 145:64910690c574 603 " VMOV D3, R2,R2 \n"
AnnaBridge 145:64910690c574 604 " VMOV D4, R2,R2 \n"
AnnaBridge 145:64910690c574 605 " VMOV D5, R2,R2 \n"
AnnaBridge 145:64910690c574 606 " VMOV D6, R2,R2 \n"
AnnaBridge 145:64910690c574 607 " VMOV D7, R2,R2 \n"
AnnaBridge 145:64910690c574 608 " VMOV D8, R2,R2 \n"
AnnaBridge 145:64910690c574 609 " VMOV D9, R2,R2 \n"
AnnaBridge 145:64910690c574 610 " VMOV D10,R2,R2 \n"
AnnaBridge 145:64910690c574 611 " VMOV D11,R2,R2 \n"
AnnaBridge 145:64910690c574 612 " VMOV D12,R2,R2 \n"
AnnaBridge 145:64910690c574 613 " VMOV D13,R2,R2 \n"
AnnaBridge 145:64910690c574 614 " VMOV D14,R2,R2 \n"
AnnaBridge 145:64910690c574 615 " VMOV D15,R2,R2 \n"
AnnaBridge 145:64910690c574 616 ".endif \n"
AnnaBridge 145:64910690c574 617
AnnaBridge 145:64910690c574 618 ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
AnnaBridge 145:64910690c574 619 //Initialise D32 registers to 0
AnnaBridge 145:64910690c574 620 " VMOV D16,R2,R2 \n"
AnnaBridge 145:64910690c574 621 " VMOV D17,R2,R2 \n"
AnnaBridge 145:64910690c574 622 " VMOV D18,R2,R2 \n"
AnnaBridge 145:64910690c574 623 " VMOV D19,R2,R2 \n"
AnnaBridge 145:64910690c574 624 " VMOV D20,R2,R2 \n"
AnnaBridge 145:64910690c574 625 " VMOV D21,R2,R2 \n"
AnnaBridge 145:64910690c574 626 " VMOV D22,R2,R2 \n"
AnnaBridge 145:64910690c574 627 " VMOV D23,R2,R2 \n"
AnnaBridge 145:64910690c574 628 " VMOV D24,R2,R2 \n"
AnnaBridge 145:64910690c574 629 " VMOV D25,R2,R2 \n"
AnnaBridge 145:64910690c574 630 " VMOV D26,R2,R2 \n"
AnnaBridge 145:64910690c574 631 " VMOV D27,R2,R2 \n"
AnnaBridge 145:64910690c574 632 " VMOV D28,R2,R2 \n"
AnnaBridge 145:64910690c574 633 " VMOV D29,R2,R2 \n"
AnnaBridge 145:64910690c574 634 " VMOV D30,R2,R2 \n"
AnnaBridge 145:64910690c574 635 " VMOV D31,R2,R2 \n"
AnnaBridge 145:64910690c574 636 ".endif \n"
AnnaBridge 145:64910690c574 637 #endif
AnnaBridge 145:64910690c574 638 //Initialise FPSCR to a known state
AnnaBridge 145:64910690c574 639 " VMRS R2,FPSCR \n"
AnnaBridge 145:64910690c574 640 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AnnaBridge 145:64910690c574 641 " AND R2,R2,R3 \n"
AnnaBridge 145:64910690c574 642 " VMSR FPSCR,R2 "
AnnaBridge 145:64910690c574 643 );
AnnaBridge 145:64910690c574 644 }
AnnaBridge 145:64910690c574 645
AnnaBridge 145:64910690c574 646 #endif /* __CMSIS_ARMCC_H */