mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/cmsis_armcc.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**************************************************************************//**
AnnaBridge 145:64910690c574 2 * @file cmsis_armcc.h
AnnaBridge 145:64910690c574 3 * @brief CMSIS compiler specific macros, functions, instructions
AnnaBridge 145:64910690c574 4 * @version V1.00
AnnaBridge 145:64910690c574 5 * @date 22. Feb 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 145:64910690c574 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 145:64910690c574 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
AnnaBridge 145:64910690c574 24
AnnaBridge 145:64910690c574 25 #ifndef __CMSIS_ARMCC_H
AnnaBridge 145:64910690c574 26 #define __CMSIS_ARMCC_H
AnnaBridge 145:64910690c574 27
AnnaBridge 145:64910690c574 28 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
AnnaBridge 145:64910690c574 29 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
AnnaBridge 145:64910690c574 30 #endif
AnnaBridge 145:64910690c574 31
AnnaBridge 145:64910690c574 32 /* CMSIS compiler control architecture macros */
AnnaBridge 145:64910690c574 33 #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
AnnaBridge 145:64910690c574 34 #define __ARM_ARCH_7A__ 1
AnnaBridge 145:64910690c574 35 #endif
AnnaBridge 145:64910690c574 36
AnnaBridge 145:64910690c574 37 /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 38 #ifndef __ASM
AnnaBridge 145:64910690c574 39 #define __ASM __asm
AnnaBridge 145:64910690c574 40 #endif
AnnaBridge 145:64910690c574 41 #ifndef __INLINE
AnnaBridge 145:64910690c574 42 #define __INLINE __inline
AnnaBridge 145:64910690c574 43 #endif
AnnaBridge 145:64910690c574 44 #ifndef __STATIC_INLINE
AnnaBridge 145:64910690c574 45 #define __STATIC_INLINE static __inline
AnnaBridge 145:64910690c574 46 #endif
AnnaBridge 145:64910690c574 47 #ifndef __STATIC_ASM
AnnaBridge 145:64910690c574 48 #define __STATIC_ASM static __asm
AnnaBridge 145:64910690c574 49 #endif
AnnaBridge 145:64910690c574 50 #ifndef __NO_RETURN
AnnaBridge 145:64910690c574 51 #define __NO_RETURN __declspec(noreturn)
AnnaBridge 145:64910690c574 52 #endif
AnnaBridge 145:64910690c574 53 #ifndef __USED
AnnaBridge 145:64910690c574 54 #define __USED __attribute__((used))
AnnaBridge 145:64910690c574 55 #endif
AnnaBridge 145:64910690c574 56 #ifndef __WEAK
AnnaBridge 145:64910690c574 57 #define __WEAK __attribute__((weak))
AnnaBridge 145:64910690c574 58 #endif
AnnaBridge 145:64910690c574 59 #ifndef __UNALIGNED_UINT32
AnnaBridge 145:64910690c574 60 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
AnnaBridge 145:64910690c574 61 #endif
AnnaBridge 145:64910690c574 62 #ifndef __ALIGNED
AnnaBridge 145:64910690c574 63 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 145:64910690c574 64 #endif
AnnaBridge 145:64910690c574 65 #ifndef __PACKED
AnnaBridge 145:64910690c574 66 #define __PACKED __attribute__((packed))
AnnaBridge 145:64910690c574 67 #endif
AnnaBridge 145:64910690c574 68
AnnaBridge 145:64910690c574 69
AnnaBridge 145:64910690c574 70 /* ########################### Core Function Access ########################### */
AnnaBridge 145:64910690c574 71
AnnaBridge 145:64910690c574 72 /**
AnnaBridge 145:64910690c574 73 \brief Get FPSCR
AnnaBridge 145:64910690c574 74 \return Floating Point Status/Control register value
AnnaBridge 145:64910690c574 75 */
AnnaBridge 145:64910690c574 76 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 145:64910690c574 77 {
AnnaBridge 145:64910690c574 78 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 79 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 80 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 145:64910690c574 81 return(__regfpscr);
AnnaBridge 145:64910690c574 82 #else
AnnaBridge 145:64910690c574 83 return(0U);
AnnaBridge 145:64910690c574 84 #endif
AnnaBridge 145:64910690c574 85 }
AnnaBridge 145:64910690c574 86
AnnaBridge 145:64910690c574 87 /**
AnnaBridge 145:64910690c574 88 \brief Set FPSCR
AnnaBridge 145:64910690c574 89 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 145:64910690c574 90 */
AnnaBridge 145:64910690c574 91 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 145:64910690c574 92 {
AnnaBridge 145:64910690c574 93 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 94 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 95 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 145:64910690c574 96 __regfpscr = (fpscr);
AnnaBridge 145:64910690c574 97 #else
AnnaBridge 145:64910690c574 98 (void)fpscr;
AnnaBridge 145:64910690c574 99 #endif
AnnaBridge 145:64910690c574 100 }
AnnaBridge 145:64910690c574 101
AnnaBridge 145:64910690c574 102 /* ########################## Core Instruction Access ######################### */
AnnaBridge 145:64910690c574 103 /**
AnnaBridge 145:64910690c574 104 \brief No Operation
AnnaBridge 145:64910690c574 105 */
AnnaBridge 145:64910690c574 106 #define __NOP __nop
AnnaBridge 145:64910690c574 107
AnnaBridge 145:64910690c574 108 /**
AnnaBridge 145:64910690c574 109 \brief Wait For Interrupt
AnnaBridge 145:64910690c574 110 */
AnnaBridge 145:64910690c574 111 #define __WFI __wfi
AnnaBridge 145:64910690c574 112
AnnaBridge 145:64910690c574 113 /**
AnnaBridge 145:64910690c574 114 \brief Wait For Event
AnnaBridge 145:64910690c574 115 */
AnnaBridge 145:64910690c574 116 #define __WFE __wfe
AnnaBridge 145:64910690c574 117
AnnaBridge 145:64910690c574 118 /**
AnnaBridge 145:64910690c574 119 \brief Send Event
AnnaBridge 145:64910690c574 120 */
AnnaBridge 145:64910690c574 121 #define __SEV __sev
AnnaBridge 145:64910690c574 122
AnnaBridge 145:64910690c574 123 /**
AnnaBridge 145:64910690c574 124 \brief Instruction Synchronization Barrier
AnnaBridge 145:64910690c574 125 */
AnnaBridge 145:64910690c574 126 #define __ISB() do {\
AnnaBridge 145:64910690c574 127 __schedule_barrier();\
AnnaBridge 145:64910690c574 128 __isb(0xF);\
AnnaBridge 145:64910690c574 129 __schedule_barrier();\
AnnaBridge 145:64910690c574 130 } while (0U)
AnnaBridge 145:64910690c574 131
AnnaBridge 145:64910690c574 132 /**
AnnaBridge 145:64910690c574 133 \brief Data Synchronization Barrier
AnnaBridge 145:64910690c574 134 */
AnnaBridge 145:64910690c574 135 #define __DSB() do {\
AnnaBridge 145:64910690c574 136 __schedule_barrier();\
AnnaBridge 145:64910690c574 137 __dsb(0xF);\
AnnaBridge 145:64910690c574 138 __schedule_barrier();\
AnnaBridge 145:64910690c574 139 } while (0U)
AnnaBridge 145:64910690c574 140
AnnaBridge 145:64910690c574 141 /**
AnnaBridge 145:64910690c574 142 \brief Data Memory Barrier
AnnaBridge 145:64910690c574 143 */
AnnaBridge 145:64910690c574 144 #define __DMB() do {\
AnnaBridge 145:64910690c574 145 __schedule_barrier();\
AnnaBridge 145:64910690c574 146 __dmb(0xF);\
AnnaBridge 145:64910690c574 147 __schedule_barrier();\
AnnaBridge 145:64910690c574 148 } while (0U)
AnnaBridge 145:64910690c574 149
AnnaBridge 145:64910690c574 150 /**
AnnaBridge 145:64910690c574 151 \brief Reverse byte order (32 bit)
AnnaBridge 145:64910690c574 152 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 153 \return Reversed value
AnnaBridge 145:64910690c574 154 */
AnnaBridge 145:64910690c574 155 #define __REV __rev
AnnaBridge 145:64910690c574 156
AnnaBridge 145:64910690c574 157 /**
AnnaBridge 145:64910690c574 158 \brief Reverse byte order (16 bit)
AnnaBridge 145:64910690c574 159 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 160 \return Reversed value
AnnaBridge 145:64910690c574 161 */
AnnaBridge 145:64910690c574 162 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 145:64910690c574 163 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
AnnaBridge 145:64910690c574 164 {
AnnaBridge 145:64910690c574 165 rev16 r0, r0
AnnaBridge 145:64910690c574 166 bx lr
AnnaBridge 145:64910690c574 167 }
AnnaBridge 145:64910690c574 168 #endif
AnnaBridge 145:64910690c574 169
AnnaBridge 145:64910690c574 170 /**
AnnaBridge 145:64910690c574 171 \brief Reverse byte order in signed short value
AnnaBridge 145:64910690c574 172 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 173 \return Reversed value
AnnaBridge 145:64910690c574 174 */
AnnaBridge 145:64910690c574 175 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 145:64910690c574 176 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
AnnaBridge 145:64910690c574 177 {
AnnaBridge 145:64910690c574 178 revsh r0, r0
AnnaBridge 145:64910690c574 179 bx lr
AnnaBridge 145:64910690c574 180 }
AnnaBridge 145:64910690c574 181 #endif
AnnaBridge 145:64910690c574 182
AnnaBridge 145:64910690c574 183 /**
AnnaBridge 145:64910690c574 184 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 145:64910690c574 185 \param [in] op1 Value to rotate
AnnaBridge 145:64910690c574 186 \param [in] op2 Number of Bits to rotate
AnnaBridge 145:64910690c574 187 \return Rotated value
AnnaBridge 145:64910690c574 188 */
AnnaBridge 145:64910690c574 189 #define __ROR __ror
AnnaBridge 145:64910690c574 190
AnnaBridge 145:64910690c574 191 /**
AnnaBridge 145:64910690c574 192 \brief Breakpoint
AnnaBridge 145:64910690c574 193 \param [in] value is ignored by the processor.
AnnaBridge 145:64910690c574 194 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 145:64910690c574 195 */
AnnaBridge 145:64910690c574 196 #define __BKPT(value) __breakpoint(value)
AnnaBridge 145:64910690c574 197
AnnaBridge 145:64910690c574 198 /**
AnnaBridge 145:64910690c574 199 \brief Reverse bit order of value
AnnaBridge 145:64910690c574 200 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 201 \return Reversed value
AnnaBridge 145:64910690c574 202 */
AnnaBridge 145:64910690c574 203 #define __RBIT __rbit
AnnaBridge 145:64910690c574 204
AnnaBridge 145:64910690c574 205 /**
AnnaBridge 145:64910690c574 206 \brief Count leading zeros
AnnaBridge 145:64910690c574 207 \param [in] value Value to count the leading zeros
AnnaBridge 145:64910690c574 208 \return number of leading zeros in value
AnnaBridge 145:64910690c574 209 */
AnnaBridge 145:64910690c574 210 #define __CLZ __clz
AnnaBridge 145:64910690c574 211
AnnaBridge 145:64910690c574 212 /** \brief Get CPSR Register
AnnaBridge 145:64910690c574 213 \return CPSR Register value
AnnaBridge 145:64910690c574 214 */
AnnaBridge 145:64910690c574 215 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 145:64910690c574 216 {
AnnaBridge 145:64910690c574 217 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 145:64910690c574 218 return(__regCPSR);
AnnaBridge 145:64910690c574 219 }
AnnaBridge 145:64910690c574 220
AnnaBridge 145:64910690c574 221
AnnaBridge 145:64910690c574 222 /** \brief Set CPSR Register
AnnaBridge 145:64910690c574 223 \param [in] cpsr CPSR value to set
AnnaBridge 145:64910690c574 224 */
AnnaBridge 145:64910690c574 225 __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
AnnaBridge 145:64910690c574 226 {
AnnaBridge 145:64910690c574 227 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 145:64910690c574 228 __regCPSR = cpsr;
AnnaBridge 145:64910690c574 229 }
AnnaBridge 145:64910690c574 230
AnnaBridge 145:64910690c574 231 /** \brief Get Mode
AnnaBridge 145:64910690c574 232 \return Processor Mode
AnnaBridge 145:64910690c574 233 */
AnnaBridge 145:64910690c574 234 __STATIC_INLINE uint32_t __get_mode(void) {
AnnaBridge 145:64910690c574 235 return (__get_CPSR() & 0x1FU);
AnnaBridge 145:64910690c574 236 }
AnnaBridge 145:64910690c574 237
AnnaBridge 145:64910690c574 238 /** \brief Set Mode
AnnaBridge 145:64910690c574 239 \param [in] mode Mode value to set
AnnaBridge 145:64910690c574 240 */
AnnaBridge 145:64910690c574 241 __STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
AnnaBridge 145:64910690c574 242 MOV r1, lr
AnnaBridge 145:64910690c574 243 MSR CPSR_C, r0
AnnaBridge 145:64910690c574 244 BX r1
AnnaBridge 145:64910690c574 245 }
AnnaBridge 145:64910690c574 246
AnnaBridge 145:64910690c574 247 /** \brief Set Stack Pointer
AnnaBridge 145:64910690c574 248 \param [in] stack Stack Pointer value to set
AnnaBridge 145:64910690c574 249 */
AnnaBridge 145:64910690c574 250 __STATIC_INLINE __ASM void __set_SP(uint32_t stack)
AnnaBridge 145:64910690c574 251 {
AnnaBridge 145:64910690c574 252 MOV sp, r0
AnnaBridge 145:64910690c574 253 BX lr
AnnaBridge 145:64910690c574 254 }
AnnaBridge 145:64910690c574 255
AnnaBridge 145:64910690c574 256 /** \brief Set Process Stack Pointer
AnnaBridge 145:64910690c574 257 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 145:64910690c574 258 */
AnnaBridge 145:64910690c574 259 __STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 145:64910690c574 260 {
AnnaBridge 145:64910690c574 261 ARM
AnnaBridge 145:64910690c574 262 PRESERVE8
AnnaBridge 145:64910690c574 263
AnnaBridge 145:64910690c574 264 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
AnnaBridge 145:64910690c574 265 MRS R1, CPSR
AnnaBridge 145:64910690c574 266 CPS #0x1F ;no effect in USR mode
AnnaBridge 145:64910690c574 267 MOV SP, R0
AnnaBridge 145:64910690c574 268 MSR CPSR_c, R1 ;no effect in USR mode
AnnaBridge 145:64910690c574 269 ISB
AnnaBridge 145:64910690c574 270 BX LR
AnnaBridge 145:64910690c574 271 }
AnnaBridge 145:64910690c574 272
AnnaBridge 145:64910690c574 273 /** \brief Set User Mode
AnnaBridge 145:64910690c574 274 */
AnnaBridge 145:64910690c574 275 __STATIC_INLINE __ASM void __set_CPS_USR(void)
AnnaBridge 145:64910690c574 276 {
AnnaBridge 145:64910690c574 277 ARM
AnnaBridge 145:64910690c574 278
AnnaBridge 145:64910690c574 279 CPS #0x10
AnnaBridge 145:64910690c574 280 BX LR
AnnaBridge 145:64910690c574 281 }
AnnaBridge 145:64910690c574 282
AnnaBridge 145:64910690c574 283 /** \brief Get FPEXC
AnnaBridge 145:64910690c574 284 \return Floating Point Exception Control register value
AnnaBridge 145:64910690c574 285 */
AnnaBridge 145:64910690c574 286 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 145:64910690c574 287 {
AnnaBridge 145:64910690c574 288 #if (__FPU_PRESENT == 1)
AnnaBridge 145:64910690c574 289 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 145:64910690c574 290 return(__regfpexc);
AnnaBridge 145:64910690c574 291 #else
AnnaBridge 145:64910690c574 292 return(0);
AnnaBridge 145:64910690c574 293 #endif
AnnaBridge 145:64910690c574 294 }
AnnaBridge 145:64910690c574 295
AnnaBridge 145:64910690c574 296 /** \brief Set FPEXC
AnnaBridge 145:64910690c574 297 \param [in] fpexc Floating Point Exception Control value to set
AnnaBridge 145:64910690c574 298 */
AnnaBridge 145:64910690c574 299 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 145:64910690c574 300 {
AnnaBridge 145:64910690c574 301 #if (__FPU_PRESENT == 1)
AnnaBridge 145:64910690c574 302 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 145:64910690c574 303 __regfpexc = (fpexc);
AnnaBridge 145:64910690c574 304 #endif
AnnaBridge 145:64910690c574 305 }
AnnaBridge 145:64910690c574 306
AnnaBridge 145:64910690c574 307 /** \brief Get CPACR
AnnaBridge 145:64910690c574 308 \return Coprocessor Access Control register value
AnnaBridge 145:64910690c574 309 */
AnnaBridge 145:64910690c574 310 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 145:64910690c574 311 {
AnnaBridge 145:64910690c574 312 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 145:64910690c574 313 return __regCPACR;
AnnaBridge 145:64910690c574 314 }
AnnaBridge 145:64910690c574 315
AnnaBridge 145:64910690c574 316 /** \brief Set CPACR
AnnaBridge 145:64910690c574 317 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 145:64910690c574 318 */
AnnaBridge 145:64910690c574 319 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 145:64910690c574 320 {
AnnaBridge 145:64910690c574 321 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 145:64910690c574 322 __regCPACR = cpacr;
AnnaBridge 145:64910690c574 323 }
AnnaBridge 145:64910690c574 324
AnnaBridge 145:64910690c574 325 /** \brief Get CBAR
AnnaBridge 145:64910690c574 326 \return Configuration Base Address register value
AnnaBridge 145:64910690c574 327 */
AnnaBridge 145:64910690c574 328 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 145:64910690c574 329 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 145:64910690c574 330 return(__regCBAR);
AnnaBridge 145:64910690c574 331 }
AnnaBridge 145:64910690c574 332
AnnaBridge 145:64910690c574 333 /** \brief Get TTBR0
AnnaBridge 145:64910690c574 334
AnnaBridge 145:64910690c574 335 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 145:64910690c574 336
AnnaBridge 145:64910690c574 337 \return Translation Table Base Register 0 value
AnnaBridge 145:64910690c574 338 */
AnnaBridge 145:64910690c574 339 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 145:64910690c574 340 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 145:64910690c574 341 return(__regTTBR0);
AnnaBridge 145:64910690c574 342 }
AnnaBridge 145:64910690c574 343
AnnaBridge 145:64910690c574 344 /** \brief Set TTBR0
AnnaBridge 145:64910690c574 345
AnnaBridge 145:64910690c574 346 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 145:64910690c574 347
AnnaBridge 145:64910690c574 348 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 145:64910690c574 349 */
AnnaBridge 145:64910690c574 350 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 145:64910690c574 351 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 145:64910690c574 352 __regTTBR0 = ttbr0;
AnnaBridge 145:64910690c574 353 }
AnnaBridge 145:64910690c574 354
AnnaBridge 145:64910690c574 355 /** \brief Get DACR
AnnaBridge 145:64910690c574 356
AnnaBridge 145:64910690c574 357 This function returns the value of the Domain Access Control Register.
AnnaBridge 145:64910690c574 358
AnnaBridge 145:64910690c574 359 \return Domain Access Control Register value
AnnaBridge 145:64910690c574 360 */
AnnaBridge 145:64910690c574 361 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 145:64910690c574 362 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 145:64910690c574 363 return(__regDACR);
AnnaBridge 145:64910690c574 364 }
AnnaBridge 145:64910690c574 365
AnnaBridge 145:64910690c574 366 /** \brief Set DACR
AnnaBridge 145:64910690c574 367
AnnaBridge 145:64910690c574 368 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 145:64910690c574 369
AnnaBridge 145:64910690c574 370 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 145:64910690c574 371 */
AnnaBridge 145:64910690c574 372 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 145:64910690c574 373 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 145:64910690c574 374 __regDACR = dacr;
AnnaBridge 145:64910690c574 375 }
AnnaBridge 145:64910690c574 376
AnnaBridge 145:64910690c574 377 /** \brief Set SCTLR
AnnaBridge 145:64910690c574 378
AnnaBridge 145:64910690c574 379 This function assigns the given value to the System Control Register.
AnnaBridge 145:64910690c574 380
AnnaBridge 145:64910690c574 381 \param [in] sctlr System Control Register value to set
AnnaBridge 145:64910690c574 382 */
AnnaBridge 145:64910690c574 383 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 145:64910690c574 384 {
AnnaBridge 145:64910690c574 385 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 145:64910690c574 386 __regSCTLR = sctlr;
AnnaBridge 145:64910690c574 387 }
AnnaBridge 145:64910690c574 388
AnnaBridge 145:64910690c574 389 /** \brief Get SCTLR
AnnaBridge 145:64910690c574 390 \return System Control Register value
AnnaBridge 145:64910690c574 391 */
AnnaBridge 145:64910690c574 392 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 145:64910690c574 393 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 145:64910690c574 394 return(__regSCTLR);
AnnaBridge 145:64910690c574 395 }
AnnaBridge 145:64910690c574 396
AnnaBridge 145:64910690c574 397 /** \brief Set ACTRL
AnnaBridge 145:64910690c574 398 \param [in] actrl Auxiliary Control Register value to set
AnnaBridge 145:64910690c574 399 */
AnnaBridge 145:64910690c574 400 __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
AnnaBridge 145:64910690c574 401 {
AnnaBridge 145:64910690c574 402 register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1");
AnnaBridge 145:64910690c574 403 __regACTRL = actrl;
AnnaBridge 145:64910690c574 404 }
AnnaBridge 145:64910690c574 405
AnnaBridge 145:64910690c574 406 /** \brief Get ACTRL
AnnaBridge 145:64910690c574 407 \return Auxiliary Control Register value
AnnaBridge 145:64910690c574 408 */
AnnaBridge 145:64910690c574 409 __STATIC_INLINE uint32_t __get_ACTRL(void)
AnnaBridge 145:64910690c574 410 {
AnnaBridge 145:64910690c574 411 register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1");
AnnaBridge 145:64910690c574 412 return(__regACTRL);
AnnaBridge 145:64910690c574 413 }
AnnaBridge 145:64910690c574 414
AnnaBridge 145:64910690c574 415 /** \brief Get MPIDR
AnnaBridge 145:64910690c574 416
AnnaBridge 145:64910690c574 417 This function returns the value of the Multiprocessor Affinity Register.
AnnaBridge 145:64910690c574 418
AnnaBridge 145:64910690c574 419 \return Multiprocessor Affinity Register value
AnnaBridge 145:64910690c574 420 */
AnnaBridge 145:64910690c574 421 __STATIC_INLINE uint32_t __get_MPIDR(void)
AnnaBridge 145:64910690c574 422 {
AnnaBridge 145:64910690c574 423 register uint32_t __regMPIDR __ASM("cp15:0:c0:c0:5");
AnnaBridge 145:64910690c574 424 return(__regMPIDR);
AnnaBridge 145:64910690c574 425 }
AnnaBridge 145:64910690c574 426
AnnaBridge 145:64910690c574 427 /** \brief Get VBAR
AnnaBridge 145:64910690c574 428
AnnaBridge 145:64910690c574 429 This function returns the value of the Vector Base Address Register.
AnnaBridge 145:64910690c574 430
AnnaBridge 145:64910690c574 431 \return Vector Base Address Register
AnnaBridge 145:64910690c574 432 */
AnnaBridge 145:64910690c574 433 __STATIC_INLINE uint32_t __get_VBAR(void)
AnnaBridge 145:64910690c574 434 {
AnnaBridge 145:64910690c574 435 register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0");
AnnaBridge 145:64910690c574 436 return(__regVBAR);
AnnaBridge 145:64910690c574 437 }
AnnaBridge 145:64910690c574 438
AnnaBridge 145:64910690c574 439 /** \brief Set VBAR
AnnaBridge 145:64910690c574 440
AnnaBridge 145:64910690c574 441 This function assigns the given value to the Vector Base Address Register.
AnnaBridge 145:64910690c574 442
AnnaBridge 145:64910690c574 443 \param [in] vbar Vector Base Address Register value to set
AnnaBridge 145:64910690c574 444 */
AnnaBridge 145:64910690c574 445 __STATIC_INLINE void __set_VBAR(uint32_t vbar)
AnnaBridge 145:64910690c574 446 {
AnnaBridge 145:64910690c574 447 register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0");
AnnaBridge 145:64910690c574 448 __regVBAR = vbar;
AnnaBridge 145:64910690c574 449 }
AnnaBridge 145:64910690c574 450
AnnaBridge 145:64910690c574 451 /** \brief Set CNTP_TVAL
AnnaBridge 145:64910690c574 452
AnnaBridge 145:64910690c574 453 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
AnnaBridge 145:64910690c574 454
AnnaBridge 145:64910690c574 455 \param [in] value CNTP_TVAL Register value to set
AnnaBridge 145:64910690c574 456 */
AnnaBridge 145:64910690c574 457 __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
AnnaBridge 145:64910690c574 458 register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0");
AnnaBridge 145:64910690c574 459 __regCNTP_TVAL = value;
AnnaBridge 145:64910690c574 460 }
AnnaBridge 145:64910690c574 461
AnnaBridge 145:64910690c574 462 /** \brief Get CNTP_TVAL
AnnaBridge 145:64910690c574 463
AnnaBridge 145:64910690c574 464 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
AnnaBridge 145:64910690c574 465
AnnaBridge 145:64910690c574 466 \return CNTP_TVAL Register value
AnnaBridge 145:64910690c574 467 */
AnnaBridge 145:64910690c574 468 __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
AnnaBridge 145:64910690c574 469 register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0");
AnnaBridge 145:64910690c574 470 return(__regCNTP_TVAL);
AnnaBridge 145:64910690c574 471 }
AnnaBridge 145:64910690c574 472
AnnaBridge 145:64910690c574 473 /** \brief Set CNTP_CTL
AnnaBridge 145:64910690c574 474
AnnaBridge 145:64910690c574 475 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
AnnaBridge 145:64910690c574 476
AnnaBridge 145:64910690c574 477 \param [in] value CNTP_CTL Register value to set
AnnaBridge 145:64910690c574 478 */
AnnaBridge 145:64910690c574 479 __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
AnnaBridge 145:64910690c574 480 register uint32_t __regCNTP_CTL __ASM("cp15:0:c14:c2:1");
AnnaBridge 145:64910690c574 481 __regCNTP_CTL = value;
AnnaBridge 145:64910690c574 482 }
AnnaBridge 145:64910690c574 483
AnnaBridge 145:64910690c574 484 /** \brief Set TLBIALL
AnnaBridge 145:64910690c574 485
AnnaBridge 145:64910690c574 486 TLB Invalidate All
AnnaBridge 145:64910690c574 487 */
AnnaBridge 145:64910690c574 488 __STATIC_INLINE void __set_TLBIALL(uint32_t value) {
AnnaBridge 145:64910690c574 489 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 145:64910690c574 490 __TLBIALL = value;
AnnaBridge 145:64910690c574 491 }
AnnaBridge 145:64910690c574 492
AnnaBridge 145:64910690c574 493 /** \brief Set BPIALL.
AnnaBridge 145:64910690c574 494
AnnaBridge 145:64910690c574 495 Branch Predictor Invalidate All
AnnaBridge 145:64910690c574 496 */
AnnaBridge 145:64910690c574 497 __STATIC_INLINE void __set_BPIALL(uint32_t value) {
AnnaBridge 145:64910690c574 498 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 145:64910690c574 499 __BPIALL = value;
AnnaBridge 145:64910690c574 500 }
AnnaBridge 145:64910690c574 501
AnnaBridge 145:64910690c574 502 /** \brief Set ICIALLU
AnnaBridge 145:64910690c574 503
AnnaBridge 145:64910690c574 504 Instruction Cache Invalidate All
AnnaBridge 145:64910690c574 505 */
AnnaBridge 145:64910690c574 506 __STATIC_INLINE void __set_ICIALLU(uint32_t value) {
AnnaBridge 145:64910690c574 507 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 145:64910690c574 508 __ICIALLU = value;
AnnaBridge 145:64910690c574 509 }
AnnaBridge 145:64910690c574 510
AnnaBridge 145:64910690c574 511 /** \brief Set DCCMVAC
AnnaBridge 145:64910690c574 512
AnnaBridge 145:64910690c574 513 Data cache clean
AnnaBridge 145:64910690c574 514 */
AnnaBridge 145:64910690c574 515 __STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 516 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 145:64910690c574 517 __DCCMVAC = value;
AnnaBridge 145:64910690c574 518 }
AnnaBridge 145:64910690c574 519
AnnaBridge 145:64910690c574 520 /** \brief Set DCIMVAC
AnnaBridge 145:64910690c574 521
AnnaBridge 145:64910690c574 522 Data cache invalidate
AnnaBridge 145:64910690c574 523 */
AnnaBridge 145:64910690c574 524 __STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 525 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 145:64910690c574 526 __DCIMVAC = value;
AnnaBridge 145:64910690c574 527 }
AnnaBridge 145:64910690c574 528
AnnaBridge 145:64910690c574 529 /** \brief Set DCCIMVAC
AnnaBridge 145:64910690c574 530
AnnaBridge 145:64910690c574 531 Data cache clean and invalidate
AnnaBridge 145:64910690c574 532 */
AnnaBridge 145:64910690c574 533 __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
AnnaBridge 145:64910690c574 534 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 145:64910690c574 535 __DCCIMVAC = value;
AnnaBridge 145:64910690c574 536 }
AnnaBridge 145:64910690c574 537
AnnaBridge 145:64910690c574 538 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 145:64910690c574 539
AnnaBridge 145:64910690c574 540 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge 145:64910690c574 541 */
AnnaBridge 145:64910690c574 542 #pragma push
AnnaBridge 145:64910690c574 543 #pragma arm
AnnaBridge 145:64910690c574 544 __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 145:64910690c574 545 ARM
AnnaBridge 145:64910690c574 546
AnnaBridge 145:64910690c574 547 PUSH {R4-R11}
AnnaBridge 145:64910690c574 548
AnnaBridge 145:64910690c574 549 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
AnnaBridge 145:64910690c574 550 ANDS R3, R6, #0x07000000 // Extract coherency level
AnnaBridge 145:64910690c574 551 MOV R3, R3, LSR #23 // Total cache levels << 1
AnnaBridge 145:64910690c574 552 BEQ Finished // If 0, no need to clean
AnnaBridge 145:64910690c574 553
AnnaBridge 145:64910690c574 554 MOV R10, #0 // R10 holds current cache level << 1
AnnaBridge 145:64910690c574 555 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
AnnaBridge 145:64910690c574 556 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AnnaBridge 145:64910690c574 557 AND R1, R1, #7 // Isolate those lower 3 bits
AnnaBridge 145:64910690c574 558 CMP R1, #2
AnnaBridge 145:64910690c574 559 BLT Skip // No cache or only instruction cache at this level
AnnaBridge 145:64910690c574 560
AnnaBridge 145:64910690c574 561 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
AnnaBridge 145:64910690c574 562 ISB // ISB to sync the change to the CacheSizeID reg
AnnaBridge 145:64910690c574 563 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AnnaBridge 145:64910690c574 564 AND R2, R1, #7 // Extract the line length field
AnnaBridge 145:64910690c574 565 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 145:64910690c574 566 LDR R4, =0x3FF
AnnaBridge 145:64910690c574 567 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
AnnaBridge 145:64910690c574 568 CLZ R5, R4 // R5 is the bit position of the way size increment
AnnaBridge 145:64910690c574 569 LDR R7, =0x7FFF
AnnaBridge 145:64910690c574 570 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
AnnaBridge 145:64910690c574 571
AnnaBridge 145:64910690c574 572 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
AnnaBridge 145:64910690c574 573
AnnaBridge 145:64910690c574 574 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
AnnaBridge 145:64910690c574 575 ORR R11, R11, R7, LSL R2 // Factor in the Set number
AnnaBridge 145:64910690c574 576 CMP R0, #0
AnnaBridge 145:64910690c574 577 BNE Dccsw
AnnaBridge 145:64910690c574 578 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
AnnaBridge 145:64910690c574 579 B cont
AnnaBridge 145:64910690c574 580 Dccsw CMP R0, #1
AnnaBridge 145:64910690c574 581 BNE Dccisw
AnnaBridge 145:64910690c574 582 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
AnnaBridge 145:64910690c574 583 B cont
AnnaBridge 145:64910690c574 584 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 145:64910690c574 585 cont SUBS R9, R9, #1 // Decrement the Way number
AnnaBridge 145:64910690c574 586 BGE Loop3
AnnaBridge 145:64910690c574 587 SUBS R7, R7, #1 // Decrement the Set number
AnnaBridge 145:64910690c574 588 BGE Loop2
AnnaBridge 145:64910690c574 589 Skip ADD R10, R10, #2 // Increment the cache number
AnnaBridge 145:64910690c574 590 CMP R3, R10
AnnaBridge 145:64910690c574 591 BGT Loop1
AnnaBridge 145:64910690c574 592
AnnaBridge 145:64910690c574 593 Finished
AnnaBridge 145:64910690c574 594 DSB
AnnaBridge 145:64910690c574 595 POP {R4-R11}
AnnaBridge 145:64910690c574 596 BX lr
AnnaBridge 145:64910690c574 597 }
AnnaBridge 145:64910690c574 598 #pragma pop
AnnaBridge 145:64910690c574 599
AnnaBridge 145:64910690c574 600 /** \brief Enable Floating Point Unit
AnnaBridge 145:64910690c574 601
AnnaBridge 145:64910690c574 602 Critical section, called from undef handler, so systick is disabled
AnnaBridge 145:64910690c574 603 */
AnnaBridge 145:64910690c574 604 #pragma push
AnnaBridge 145:64910690c574 605 #pragma arm
AnnaBridge 145:64910690c574 606 __STATIC_INLINE __ASM void __FPU_Enable(void) {
AnnaBridge 145:64910690c574 607 ARM
AnnaBridge 145:64910690c574 608
AnnaBridge 145:64910690c574 609 //Permit access to VFP/NEON, registers by modifying CPACR
AnnaBridge 145:64910690c574 610 MRC p15,0,R1,c1,c0,2
AnnaBridge 145:64910690c574 611 ORR R1,R1,#0x00F00000
AnnaBridge 145:64910690c574 612 MCR p15,0,R1,c1,c0,2
AnnaBridge 145:64910690c574 613
AnnaBridge 145:64910690c574 614 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
AnnaBridge 145:64910690c574 615 ISB
AnnaBridge 145:64910690c574 616
AnnaBridge 145:64910690c574 617 //Enable VFP/NEON
AnnaBridge 145:64910690c574 618 VMRS R1,FPEXC
AnnaBridge 145:64910690c574 619 ORR R1,R1,#0x40000000
AnnaBridge 145:64910690c574 620 VMSR FPEXC,R1
AnnaBridge 145:64910690c574 621
AnnaBridge 145:64910690c574 622 //Initialise VFP/NEON registers to 0
AnnaBridge 145:64910690c574 623 MOV R2,#0
AnnaBridge 145:64910690c574 624 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
AnnaBridge 145:64910690c574 625 //Initialise D16 registers to 0
AnnaBridge 145:64910690c574 626 VMOV D0, R2,R2
AnnaBridge 145:64910690c574 627 VMOV D1, R2,R2
AnnaBridge 145:64910690c574 628 VMOV D2, R2,R2
AnnaBridge 145:64910690c574 629 VMOV D3, R2,R2
AnnaBridge 145:64910690c574 630 VMOV D4, R2,R2
AnnaBridge 145:64910690c574 631 VMOV D5, R2,R2
AnnaBridge 145:64910690c574 632 VMOV D6, R2,R2
AnnaBridge 145:64910690c574 633 VMOV D7, R2,R2
AnnaBridge 145:64910690c574 634 VMOV D8, R2,R2
AnnaBridge 145:64910690c574 635 VMOV D9, R2,R2
AnnaBridge 145:64910690c574 636 VMOV D10,R2,R2
AnnaBridge 145:64910690c574 637 VMOV D11,R2,R2
AnnaBridge 145:64910690c574 638 VMOV D12,R2,R2
AnnaBridge 145:64910690c574 639 VMOV D13,R2,R2
AnnaBridge 145:64910690c574 640 VMOV D14,R2,R2
AnnaBridge 145:64910690c574 641 VMOV D15,R2,R2
AnnaBridge 145:64910690c574 642 ENDIF
AnnaBridge 145:64910690c574 643 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
AnnaBridge 145:64910690c574 644 //Initialise D32 registers to 0
AnnaBridge 145:64910690c574 645 VMOV D16,R2,R2
AnnaBridge 145:64910690c574 646 VMOV D17,R2,R2
AnnaBridge 145:64910690c574 647 VMOV D18,R2,R2
AnnaBridge 145:64910690c574 648 VMOV D19,R2,R2
AnnaBridge 145:64910690c574 649 VMOV D20,R2,R2
AnnaBridge 145:64910690c574 650 VMOV D21,R2,R2
AnnaBridge 145:64910690c574 651 VMOV D22,R2,R2
AnnaBridge 145:64910690c574 652 VMOV D23,R2,R2
AnnaBridge 145:64910690c574 653 VMOV D24,R2,R2
AnnaBridge 145:64910690c574 654 VMOV D25,R2,R2
AnnaBridge 145:64910690c574 655 VMOV D26,R2,R2
AnnaBridge 145:64910690c574 656 VMOV D27,R2,R2
AnnaBridge 145:64910690c574 657 VMOV D28,R2,R2
AnnaBridge 145:64910690c574 658 VMOV D29,R2,R2
AnnaBridge 145:64910690c574 659 VMOV D30,R2,R2
AnnaBridge 145:64910690c574 660 VMOV D31,R2,R2
AnnaBridge 145:64910690c574 661 ENDIF
AnnaBridge 145:64910690c574 662
AnnaBridge 145:64910690c574 663 //Initialise FPSCR to a known state
AnnaBridge 145:64910690c574 664 VMRS R2,FPSCR
AnnaBridge 145:64910690c574 665 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AnnaBridge 145:64910690c574 666 AND R2,R2,R3
AnnaBridge 145:64910690c574 667 VMSR FPSCR,R2
AnnaBridge 145:64910690c574 668
AnnaBridge 145:64910690c574 669 BX LR
AnnaBridge 145:64910690c574 670 }
AnnaBridge 145:64910690c574 671 #pragma pop
AnnaBridge 145:64910690c574 672
AnnaBridge 145:64910690c574 673 #endif /* __CMSIS_ARMCC_H */