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TARGET_MAX32625NEXPAQ/core_cm4.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:: Kojto
Date:: Wed Jul 19 16:46:19 2017 +0100
Revision:: 147:a97add6d7e64
Parent:: 145:64910690c574

Release 147 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	129:0ab6a29f35bf	1	/************************************************************************//
<>	129:0ab6a29f35bf	2	* @file core_cm4.h
<>	129:0ab6a29f35bf	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
AnnaBridge	145:64910690c574	4	* @version V5.0.2
AnnaBridge	145:64910690c574	5	* @date 13. February 2017
AnnaBridge	145:64910690c574	6	******************************************************************************/
AnnaBridge	145:64910690c574	7	/*
AnnaBridge	145:64910690c574	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	145:64910690c574	9	*
AnnaBridge	145:64910690c574	10	* SPDX-License-Identifier: Apache-2.0
<>	129:0ab6a29f35bf	11	*
AnnaBridge	145:64910690c574	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	145:64910690c574	13	* not use this file except in compliance with the License.
AnnaBridge	145:64910690c574	14	* You may obtain a copy of the License at
AnnaBridge	145:64910690c574	15	*
AnnaBridge	145:64910690c574	16	* www.apache.org/licenses/LICENSE-2.0
<>	129:0ab6a29f35bf	17	*
AnnaBridge	145:64910690c574	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	145:64910690c574	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	145:64910690c574	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	145:64910690c574	21	* See the License for the specific language governing permissions and
AnnaBridge	145:64910690c574	22	* limitations under the License.
AnnaBridge	145:64910690c574	23	*/
<>	129:0ab6a29f35bf	24
AnnaBridge	145:64910690c574	25	#if defined ( __ICCARM__ )
AnnaBridge	145:64910690c574	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	145:64910690c574	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	145:64910690c574	28	#pragma clang system_header /* treat file as system include file */
<>	129:0ab6a29f35bf	29	#endif
<>	129:0ab6a29f35bf	30
<>	129:0ab6a29f35bf	31	#ifndef __CORE_CM4_H_GENERIC
<>	129:0ab6a29f35bf	32	#define __CORE_CM4_H_GENERIC
<>	129:0ab6a29f35bf	33
AnnaBridge	145:64910690c574	34	#include <stdint.h>
AnnaBridge	145:64910690c574	35
<>	129:0ab6a29f35bf	36	#ifdef __cplusplus
<>	129:0ab6a29f35bf	37	extern "C" {
<>	129:0ab6a29f35bf	38	#endif
<>	129:0ab6a29f35bf	39
AnnaBridge	145:64910690c574	40	/**
AnnaBridge	145:64910690c574	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<>	129:0ab6a29f35bf	42	CMSIS violates the following MISRA-C:2004 rules:
<>	129:0ab6a29f35bf	43
<>	129:0ab6a29f35bf	44	\li Required Rule 8.5, object/function definition in header file.<br>
<>	129:0ab6a29f35bf	45	Function definitions in header files are used to allow 'inlining'.
<>	129:0ab6a29f35bf	46
<>	129:0ab6a29f35bf	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<>	129:0ab6a29f35bf	48	Unions are used for effective representation of core registers.
<>	129:0ab6a29f35bf	49
<>	129:0ab6a29f35bf	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
<>	129:0ab6a29f35bf	51	Function-like macros are used to allow more efficient code.
<>	129:0ab6a29f35bf	52	*/
<>	129:0ab6a29f35bf	53
<>	129:0ab6a29f35bf	54
<>	129:0ab6a29f35bf	55	/*******************************************************************************
<>	129:0ab6a29f35bf	56	* CMSIS definitions
<>	129:0ab6a29f35bf	57	******************************************************************************/
AnnaBridge	145:64910690c574	58	/**
AnnaBridge	145:64910690c574	59	\ingroup Cortex_M4
<>	129:0ab6a29f35bf	60	@{
<>	129:0ab6a29f35bf	61	*/
<>	129:0ab6a29f35bf	62
<>	129:0ab6a29f35bf	63	/* CMSIS CM4 definitions */
AnnaBridge	145:64910690c574	64	#define __CM4_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
AnnaBridge	145:64910690c574	65	#define __CM4_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	145:64910690c574	66	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	145:64910690c574	67	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
<>	129:0ab6a29f35bf	68
AnnaBridge	145:64910690c574	69	#define __CORTEX_M (4U) /!< Cortex-M Core /
<>	129:0ab6a29f35bf	70
<>	129:0ab6a29f35bf	71	/** __FPU_USED indicates whether an FPU is used or not.
<>	129:0ab6a29f35bf	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<>	129:0ab6a29f35bf	73	*/
<>	129:0ab6a29f35bf	74	#if defined ( __CC_ARM )
<>	129:0ab6a29f35bf	75	#if defined __TARGET_FPU_VFP
AnnaBridge	145:64910690c574	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	77	#define __FPU_USED 1U
AnnaBridge	145:64910690c574	78	#else
AnnaBridge	145:64910690c574	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	80	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	81	#endif
AnnaBridge	145:64910690c574	82	#else
AnnaBridge	145:64910690c574	83	#define __FPU_USED 0U
AnnaBridge	145:64910690c574	84	#endif
AnnaBridge	145:64910690c574	85
AnnaBridge	145:64910690c574	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	145:64910690c574	87	#if defined __ARM_PCS_VFP
AnnaBridge	145:64910690c574	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	89	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	90	#else
<>	129:0ab6a29f35bf	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	92	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	93	#endif
<>	129:0ab6a29f35bf	94	#else
AnnaBridge	145:64910690c574	95	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	96	#endif
<>	129:0ab6a29f35bf	97
<>	129:0ab6a29f35bf	98	#elif defined ( __GNUC__ )
<>	129:0ab6a29f35bf	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	145:64910690c574	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	101	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	102	#else
AnnaBridge	145:64910690c574	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	104	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	105	#endif
<>	129:0ab6a29f35bf	106	#else
AnnaBridge	145:64910690c574	107	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	108	#endif
<>	129:0ab6a29f35bf	109
<>	129:0ab6a29f35bf	110	#elif defined ( __ICCARM__ )
<>	129:0ab6a29f35bf	111	#if defined __ARMVFP__
AnnaBridge	145:64910690c574	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	113	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	114	#else
AnnaBridge	145:64910690c574	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	116	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	117	#endif
<>	129:0ab6a29f35bf	118	#else
AnnaBridge	145:64910690c574	119	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	120	#endif
<>	129:0ab6a29f35bf	121
AnnaBridge	145:64910690c574	122	#elif defined ( __TI_ARM__ )
<>	129:0ab6a29f35bf	123	#if defined __TI_VFP_SUPPORT__
AnnaBridge	145:64910690c574	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	125	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	126	#else
AnnaBridge	145:64910690c574	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	128	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	129	#endif
<>	129:0ab6a29f35bf	130	#else
AnnaBridge	145:64910690c574	131	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	132	#endif
<>	129:0ab6a29f35bf	133
<>	129:0ab6a29f35bf	134	#elif defined ( __TASKING__ )
<>	129:0ab6a29f35bf	135	#if defined __FPU_VFP__
AnnaBridge	145:64910690c574	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	137	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	138	#else
<>	129:0ab6a29f35bf	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	140	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	141	#endif
<>	129:0ab6a29f35bf	142	#else
AnnaBridge	145:64910690c574	143	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	144	#endif
<>	129:0ab6a29f35bf	145
AnnaBridge	145:64910690c574	146	#elif defined ( __CSMC__ )
AnnaBridge	145:64910690c574	147	#if ( __CSMC__ & 0x400U)
AnnaBridge	145:64910690c574	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	149	#define __FPU_USED 1U
<>	129:0ab6a29f35bf	150	#else
<>	129:0ab6a29f35bf	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	145:64910690c574	152	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	153	#endif
<>	129:0ab6a29f35bf	154	#else
AnnaBridge	145:64910690c574	155	#define __FPU_USED 0U
<>	129:0ab6a29f35bf	156	#endif
AnnaBridge	145:64910690c574	157
<>	129:0ab6a29f35bf	158	#endif
<>	129:0ab6a29f35bf	159
AnnaBridge	145:64910690c574	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	145:64910690c574	161
<>	129:0ab6a29f35bf	162
<>	129:0ab6a29f35bf	163	#ifdef __cplusplus
<>	129:0ab6a29f35bf	164	}
<>	129:0ab6a29f35bf	165	#endif
<>	129:0ab6a29f35bf	166
<>	129:0ab6a29f35bf	167	#endif /* __CORE_CM4_H_GENERIC */
<>	129:0ab6a29f35bf	168
<>	129:0ab6a29f35bf	169	#ifndef __CMSIS_GENERIC
<>	129:0ab6a29f35bf	170
<>	129:0ab6a29f35bf	171	#ifndef __CORE_CM4_H_DEPENDANT
<>	129:0ab6a29f35bf	172	#define __CORE_CM4_H_DEPENDANT
<>	129:0ab6a29f35bf	173
<>	129:0ab6a29f35bf	174	#ifdef __cplusplus
<>	129:0ab6a29f35bf	175	extern "C" {
<>	129:0ab6a29f35bf	176	#endif
<>	129:0ab6a29f35bf	177
<>	129:0ab6a29f35bf	178	/* check device defines and use defaults */
<>	129:0ab6a29f35bf	179	#if defined __CHECK_DEVICE_DEFINES
<>	129:0ab6a29f35bf	180	#ifndef __CM4_REV
AnnaBridge	145:64910690c574	181	#define __CM4_REV 0x0000U
<>	129:0ab6a29f35bf	182	#warning "__CM4_REV not defined in device header file; using default!"
<>	129:0ab6a29f35bf	183	#endif
<>	129:0ab6a29f35bf	184
<>	129:0ab6a29f35bf	185	#ifndef __FPU_PRESENT
AnnaBridge	145:64910690c574	186	#define __FPU_PRESENT 0U
<>	129:0ab6a29f35bf	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
<>	129:0ab6a29f35bf	188	#endif
<>	129:0ab6a29f35bf	189
<>	129:0ab6a29f35bf	190	#ifndef __MPU_PRESENT
AnnaBridge	145:64910690c574	191	#define __MPU_PRESENT 0U
<>	129:0ab6a29f35bf	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
<>	129:0ab6a29f35bf	193	#endif
<>	129:0ab6a29f35bf	194
<>	129:0ab6a29f35bf	195	#ifndef __NVIC_PRIO_BITS
AnnaBridge	145:64910690c574	196	#define __NVIC_PRIO_BITS 3U
<>	129:0ab6a29f35bf	197	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<>	129:0ab6a29f35bf	198	#endif
<>	129:0ab6a29f35bf	199
<>	129:0ab6a29f35bf	200	#ifndef __Vendor_SysTickConfig
AnnaBridge	145:64910690c574	201	#define __Vendor_SysTickConfig 0U
<>	129:0ab6a29f35bf	202	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<>	129:0ab6a29f35bf	203	#endif
<>	129:0ab6a29f35bf	204	#endif
<>	129:0ab6a29f35bf	205
<>	129:0ab6a29f35bf	206	/* IO definitions (access restrictions to peripheral registers) */
<>	129:0ab6a29f35bf	207	/**
<>	129:0ab6a29f35bf	208	\defgroup CMSIS_glob_defs CMSIS Global Defines
<>	129:0ab6a29f35bf	209
<>	129:0ab6a29f35bf	210	<strong>IO Type Qualifiers</strong> are used
<>	129:0ab6a29f35bf	211	\li to specify the access to peripheral variables.
<>	129:0ab6a29f35bf	212	\li for automatic generation of peripheral register debug information.
<>	129:0ab6a29f35bf	213	*/
<>	129:0ab6a29f35bf	214	#ifdef __cplusplus
AnnaBridge	145:64910690c574	215	#define __I volatile /!< Defines 'read only' permissions /
<>	129:0ab6a29f35bf	216	#else
AnnaBridge	145:64910690c574	217	#define __I volatile const /!< Defines 'read only' permissions /
<>	129:0ab6a29f35bf	218	#endif
AnnaBridge	145:64910690c574	219	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	145:64910690c574	220	#define __IO volatile /!< Defines 'read / write' permissions /
<>	129:0ab6a29f35bf	221
AnnaBridge	145:64910690c574	222	/* following defines should be used for structure members */
AnnaBridge	145:64910690c574	223	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	145:64910690c574	224	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	145:64910690c574	225	#define __IOM volatile /! Defines 'read / write' structure member permissions /
<>	129:0ab6a29f35bf	226
<>	129:0ab6a29f35bf	227	/@} end of group Cortex_M4 /
<>	129:0ab6a29f35bf	228
<>	129:0ab6a29f35bf	229
<>	129:0ab6a29f35bf	230
<>	129:0ab6a29f35bf	231	/*******************************************************************************
<>	129:0ab6a29f35bf	232	* Register Abstraction
<>	129:0ab6a29f35bf	233	Core Register contain:
<>	129:0ab6a29f35bf	234	- Core Register
<>	129:0ab6a29f35bf	235	- Core NVIC Register
<>	129:0ab6a29f35bf	236	- Core SCB Register
<>	129:0ab6a29f35bf	237	- Core SysTick Register
<>	129:0ab6a29f35bf	238	- Core Debug Register
<>	129:0ab6a29f35bf	239	- Core MPU Register
<>	129:0ab6a29f35bf	240	- Core FPU Register
<>	129:0ab6a29f35bf	241	******************************************************************************/
AnnaBridge	145:64910690c574	242	/**
AnnaBridge	145:64910690c574	243	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	145:64910690c574	244	\brief Type definitions and defines for Cortex-M processor based devices.
<>	129:0ab6a29f35bf	245	*/
<>	129:0ab6a29f35bf	246
AnnaBridge	145:64910690c574	247	/**
AnnaBridge	145:64910690c574	248	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	249	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	145:64910690c574	250	\brief Core Register type definitions.
<>	129:0ab6a29f35bf	251	@{
<>	129:0ab6a29f35bf	252	*/
<>	129:0ab6a29f35bf	253
AnnaBridge	145:64910690c574	254	/**
AnnaBridge	145:64910690c574	255	\brief Union type to access the Application Program Status Register (APSR).
<>	129:0ab6a29f35bf	256	*/
<>	129:0ab6a29f35bf	257	typedef union
<>	129:0ab6a29f35bf	258	{
<>	129:0ab6a29f35bf	259	struct
<>	129:0ab6a29f35bf	260	{
AnnaBridge	145:64910690c574	261	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	145:64910690c574	262	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	145:64910690c574	263	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	145:64910690c574	264	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	145:64910690c574	265	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	145:64910690c574	266	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	145:64910690c574	267	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	145:64910690c574	268	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	145:64910690c574	269	} b; /!< Structure used for bit access /
AnnaBridge	145:64910690c574	270	uint32_t w; /!< Type used for word access /
<>	129:0ab6a29f35bf	271	} APSR_Type;
<>	129:0ab6a29f35bf	272
<>	129:0ab6a29f35bf	273	/* APSR Register Definitions */
AnnaBridge	145:64910690c574	274	#define APSR_N_Pos 31U /!< APSR: N Position /
<>	129:0ab6a29f35bf	275	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
<>	129:0ab6a29f35bf	276
AnnaBridge	145:64910690c574	277	#define APSR_Z_Pos 30U /!< APSR: Z Position /
<>	129:0ab6a29f35bf	278	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
<>	129:0ab6a29f35bf	279
AnnaBridge	145:64910690c574	280	#define APSR_C_Pos 29U /!< APSR: C Position /
<>	129:0ab6a29f35bf	281	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
<>	129:0ab6a29f35bf	282
AnnaBridge	145:64910690c574	283	#define APSR_V_Pos 28U /!< APSR: V Position /
<>	129:0ab6a29f35bf	284	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
<>	129:0ab6a29f35bf	285
AnnaBridge	145:64910690c574	286	#define APSR_Q_Pos 27U /!< APSR: Q Position /
<>	129:0ab6a29f35bf	287	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
<>	129:0ab6a29f35bf	288
AnnaBridge	145:64910690c574	289	#define APSR_GE_Pos 16U /!< APSR: GE Position /
<>	129:0ab6a29f35bf	290	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
<>	129:0ab6a29f35bf	291
<>	129:0ab6a29f35bf	292
AnnaBridge	145:64910690c574	293	/**
AnnaBridge	145:64910690c574	294	\brief Union type to access the Interrupt Program Status Register (IPSR).
<>	129:0ab6a29f35bf	295	*/
<>	129:0ab6a29f35bf	296	typedef union
<>	129:0ab6a29f35bf	297	{
<>	129:0ab6a29f35bf	298	struct
<>	129:0ab6a29f35bf	299	{
AnnaBridge	145:64910690c574	300	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	145:64910690c574	301	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	145:64910690c574	302	} b; /!< Structure used for bit access /
AnnaBridge	145:64910690c574	303	uint32_t w; /!< Type used for word access /
<>	129:0ab6a29f35bf	304	} IPSR_Type;
<>	129:0ab6a29f35bf	305
<>	129:0ab6a29f35bf	306	/* IPSR Register Definitions */
AnnaBridge	145:64910690c574	307	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
<>	129:0ab6a29f35bf	308	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
<>	129:0ab6a29f35bf	309
<>	129:0ab6a29f35bf	310
AnnaBridge	145:64910690c574	311	/**
AnnaBridge	145:64910690c574	312	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<>	129:0ab6a29f35bf	313	*/
<>	129:0ab6a29f35bf	314	typedef union
<>	129:0ab6a29f35bf	315	{
<>	129:0ab6a29f35bf	316	struct
<>	129:0ab6a29f35bf	317	{
AnnaBridge	145:64910690c574	318	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	145:64910690c574	319	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	145:64910690c574	320	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	145:64910690c574	321	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	145:64910690c574	322	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	145:64910690c574	323	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	145:64910690c574	324	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	145:64910690c574	325	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	145:64910690c574	326	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	145:64910690c574	327	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	145:64910690c574	328	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	145:64910690c574	329	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	145:64910690c574	330	} b; /!< Structure used for bit access /
AnnaBridge	145:64910690c574	331	uint32_t w; /!< Type used for word access /
<>	129:0ab6a29f35bf	332	} xPSR_Type;
<>	129:0ab6a29f35bf	333
<>	129:0ab6a29f35bf	334	/* xPSR Register Definitions */
AnnaBridge	145:64910690c574	335	#define xPSR_N_Pos 31U /!< xPSR: N Position /
<>	129:0ab6a29f35bf	336	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
<>	129:0ab6a29f35bf	337
AnnaBridge	145:64910690c574	338	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
<>	129:0ab6a29f35bf	339	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
<>	129:0ab6a29f35bf	340
AnnaBridge	145:64910690c574	341	#define xPSR_C_Pos 29U /!< xPSR: C Position /
<>	129:0ab6a29f35bf	342	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
<>	129:0ab6a29f35bf	343
AnnaBridge	145:64910690c574	344	#define xPSR_V_Pos 28U /!< xPSR: V Position /
<>	129:0ab6a29f35bf	345	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
<>	129:0ab6a29f35bf	346
AnnaBridge	145:64910690c574	347	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
<>	129:0ab6a29f35bf	348	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
<>	129:0ab6a29f35bf	349
AnnaBridge	145:64910690c574	350	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	145:64910690c574	351	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
<>	129:0ab6a29f35bf	352
AnnaBridge	145:64910690c574	353	#define xPSR_T_Pos 24U /!< xPSR: T Position /
<>	129:0ab6a29f35bf	354	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
<>	129:0ab6a29f35bf	355
AnnaBridge	145:64910690c574	356	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
<>	129:0ab6a29f35bf	357	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
<>	129:0ab6a29f35bf	358
AnnaBridge	145:64910690c574	359	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	145:64910690c574	360	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
<>	129:0ab6a29f35bf	363	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
<>	129:0ab6a29f35bf	364
<>	129:0ab6a29f35bf	365
AnnaBridge	145:64910690c574	366	/**
AnnaBridge	145:64910690c574	367	\brief Union type to access the Control Registers (CONTROL).
<>	129:0ab6a29f35bf	368	*/
<>	129:0ab6a29f35bf	369	typedef union
<>	129:0ab6a29f35bf	370	{
<>	129:0ab6a29f35bf	371	struct
<>	129:0ab6a29f35bf	372	{
<>	129:0ab6a29f35bf	373	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	145:64910690c574	374	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	145:64910690c574	375	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	145:64910690c574	376	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	145:64910690c574	377	} b; /!< Structure used for bit access /
AnnaBridge	145:64910690c574	378	uint32_t w; /!< Type used for word access /
<>	129:0ab6a29f35bf	379	} CONTROL_Type;
<>	129:0ab6a29f35bf	380
<>	129:0ab6a29f35bf	381	/* CONTROL Register Definitions */
AnnaBridge	145:64910690c574	382	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
<>	129:0ab6a29f35bf	383	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
<>	129:0ab6a29f35bf	384
AnnaBridge	145:64910690c574	385	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
<>	129:0ab6a29f35bf	386	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
<>	129:0ab6a29f35bf	387
AnnaBridge	145:64910690c574	388	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
<>	129:0ab6a29f35bf	389	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
<>	129:0ab6a29f35bf	390
<>	129:0ab6a29f35bf	391	/@} end of group CMSIS_CORE /
<>	129:0ab6a29f35bf	392
<>	129:0ab6a29f35bf	393
AnnaBridge	145:64910690c574	394	/**
AnnaBridge	145:64910690c574	395	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	396	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	145:64910690c574	397	\brief Type definitions for the NVIC Registers
<>	129:0ab6a29f35bf	398	@{
<>	129:0ab6a29f35bf	399	*/
<>	129:0ab6a29f35bf	400
AnnaBridge	145:64910690c574	401	/**
AnnaBridge	145:64910690c574	402	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<>	129:0ab6a29f35bf	403	*/
<>	129:0ab6a29f35bf	404	typedef struct
<>	129:0ab6a29f35bf	405	{
AnnaBridge	145:64910690c574	406	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	145:64910690c574	407	uint32_t RESERVED0[24U];
AnnaBridge	145:64910690c574	408	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	145:64910690c574	409	uint32_t RSERVED1[24U];
AnnaBridge	145:64910690c574	410	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	145:64910690c574	411	uint32_t RESERVED2[24U];
AnnaBridge	145:64910690c574	412	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	145:64910690c574	413	uint32_t RESERVED3[24U];
AnnaBridge	145:64910690c574	414	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	145:64910690c574	415	uint32_t RESERVED4[56U];
AnnaBridge	145:64910690c574	416	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	145:64910690c574	417	uint32_t RESERVED5[644U];
AnnaBridge	145:64910690c574	418	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
<>	129:0ab6a29f35bf	419	} NVIC_Type;
<>	129:0ab6a29f35bf	420
<>	129:0ab6a29f35bf	421	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	145:64910690c574	422	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
<>	129:0ab6a29f35bf	423	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
<>	129:0ab6a29f35bf	424
<>	129:0ab6a29f35bf	425	/@} end of group CMSIS_NVIC /
<>	129:0ab6a29f35bf	426
<>	129:0ab6a29f35bf	427
AnnaBridge	145:64910690c574	428	/**
AnnaBridge	145:64910690c574	429	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	430	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	145:64910690c574	431	\brief Type definitions for the System Control Block Registers
<>	129:0ab6a29f35bf	432	@{
<>	129:0ab6a29f35bf	433	*/
<>	129:0ab6a29f35bf	434
AnnaBridge	145:64910690c574	435	/**
AnnaBridge	145:64910690c574	436	\brief Structure type to access the System Control Block (SCB).
<>	129:0ab6a29f35bf	437	*/
<>	129:0ab6a29f35bf	438	typedef struct
<>	129:0ab6a29f35bf	439	{
AnnaBridge	145:64910690c574	440	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	145:64910690c574	441	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	145:64910690c574	442	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	145:64910690c574	443	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	145:64910690c574	444	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	145:64910690c574	445	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	145:64910690c574	446	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	145:64910690c574	447	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	145:64910690c574	448	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	145:64910690c574	449	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	145:64910690c574	450	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	145:64910690c574	451	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	145:64910690c574	452	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	145:64910690c574	453	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	145:64910690c574	454	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	145:64910690c574	455	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	145:64910690c574	456	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	145:64910690c574	457	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	145:64910690c574	458	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	145:64910690c574	459	uint32_t RESERVED0[5U];
AnnaBridge	145:64910690c574	460	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
<>	129:0ab6a29f35bf	461	} SCB_Type;
<>	129:0ab6a29f35bf	462
<>	129:0ab6a29f35bf	463	/* SCB CPUID Register Definitions */
AnnaBridge	145:64910690c574	464	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
<>	129:0ab6a29f35bf	465	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
<>	129:0ab6a29f35bf	466
AnnaBridge	145:64910690c574	467	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
<>	129:0ab6a29f35bf	468	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
<>	129:0ab6a29f35bf	469
AnnaBridge	145:64910690c574	470	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
<>	129:0ab6a29f35bf	471	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
<>	129:0ab6a29f35bf	472
AnnaBridge	145:64910690c574	473	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
<>	129:0ab6a29f35bf	474	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
<>	129:0ab6a29f35bf	475
AnnaBridge	145:64910690c574	476	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
<>	129:0ab6a29f35bf	477	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
<>	129:0ab6a29f35bf	478
<>	129:0ab6a29f35bf	479	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	145:64910690c574	480	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
<>	129:0ab6a29f35bf	481	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
<>	129:0ab6a29f35bf	482
AnnaBridge	145:64910690c574	483	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
<>	129:0ab6a29f35bf	484	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
<>	129:0ab6a29f35bf	485
AnnaBridge	145:64910690c574	486	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
<>	129:0ab6a29f35bf	487	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
<>	129:0ab6a29f35bf	488
AnnaBridge	145:64910690c574	489	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
<>	129:0ab6a29f35bf	490	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
<>	129:0ab6a29f35bf	491
AnnaBridge	145:64910690c574	492	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
<>	129:0ab6a29f35bf	493	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
<>	129:0ab6a29f35bf	494
AnnaBridge	145:64910690c574	495	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
<>	129:0ab6a29f35bf	496	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
<>	129:0ab6a29f35bf	497
AnnaBridge	145:64910690c574	498	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
<>	129:0ab6a29f35bf	499	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
<>	129:0ab6a29f35bf	500
AnnaBridge	145:64910690c574	501	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
<>	129:0ab6a29f35bf	502	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
<>	129:0ab6a29f35bf	503
AnnaBridge	145:64910690c574	504	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
<>	129:0ab6a29f35bf	505	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
<>	129:0ab6a29f35bf	506
AnnaBridge	145:64910690c574	507	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
<>	129:0ab6a29f35bf	508	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
<>	129:0ab6a29f35bf	509
<>	129:0ab6a29f35bf	510	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	145:64910690c574	511	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
<>	129:0ab6a29f35bf	512	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	129:0ab6a29f35bf	513
<>	129:0ab6a29f35bf	514	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	145:64910690c574	515	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
<>	129:0ab6a29f35bf	516	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
<>	129:0ab6a29f35bf	517
AnnaBridge	145:64910690c574	518	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
<>	129:0ab6a29f35bf	519	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
<>	129:0ab6a29f35bf	520
AnnaBridge	145:64910690c574	521	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
<>	129:0ab6a29f35bf	522	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
<>	129:0ab6a29f35bf	523
AnnaBridge	145:64910690c574	524	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
<>	129:0ab6a29f35bf	525	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
<>	129:0ab6a29f35bf	526
AnnaBridge	145:64910690c574	527	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
<>	129:0ab6a29f35bf	528	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
<>	129:0ab6a29f35bf	529
AnnaBridge	145:64910690c574	530	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
<>	129:0ab6a29f35bf	531	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
<>	129:0ab6a29f35bf	532
AnnaBridge	145:64910690c574	533	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
<>	129:0ab6a29f35bf	534	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
<>	129:0ab6a29f35bf	535
<>	129:0ab6a29f35bf	536	/* SCB System Control Register Definitions */
AnnaBridge	145:64910690c574	537	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
<>	129:0ab6a29f35bf	538	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
<>	129:0ab6a29f35bf	539
AnnaBridge	145:64910690c574	540	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
<>	129:0ab6a29f35bf	541	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
<>	129:0ab6a29f35bf	542
AnnaBridge	145:64910690c574	543	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
<>	129:0ab6a29f35bf	544	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
<>	129:0ab6a29f35bf	545
<>	129:0ab6a29f35bf	546	/* SCB Configuration Control Register Definitions */
AnnaBridge	145:64910690c574	547	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
<>	129:0ab6a29f35bf	548	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
<>	129:0ab6a29f35bf	549
AnnaBridge	145:64910690c574	550	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
<>	129:0ab6a29f35bf	551	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
<>	129:0ab6a29f35bf	552
AnnaBridge	145:64910690c574	553	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
<>	129:0ab6a29f35bf	554	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
<>	129:0ab6a29f35bf	555
AnnaBridge	145:64910690c574	556	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
<>	129:0ab6a29f35bf	557	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
<>	129:0ab6a29f35bf	558
AnnaBridge	145:64910690c574	559	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
<>	129:0ab6a29f35bf	560	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
<>	129:0ab6a29f35bf	561
AnnaBridge	145:64910690c574	562	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
<>	129:0ab6a29f35bf	563	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
<>	129:0ab6a29f35bf	564
<>	129:0ab6a29f35bf	565	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	145:64910690c574	566	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
<>	129:0ab6a29f35bf	567	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
<>	129:0ab6a29f35bf	568
AnnaBridge	145:64910690c574	569	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
<>	129:0ab6a29f35bf	570	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
<>	129:0ab6a29f35bf	571
AnnaBridge	145:64910690c574	572	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
<>	129:0ab6a29f35bf	573	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
<>	129:0ab6a29f35bf	574
AnnaBridge	145:64910690c574	575	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
<>	129:0ab6a29f35bf	576	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
<>	129:0ab6a29f35bf	577
AnnaBridge	145:64910690c574	578	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
<>	129:0ab6a29f35bf	579	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
<>	129:0ab6a29f35bf	580
AnnaBridge	145:64910690c574	581	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
<>	129:0ab6a29f35bf	582	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
<>	129:0ab6a29f35bf	583
AnnaBridge	145:64910690c574	584	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
<>	129:0ab6a29f35bf	585	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
<>	129:0ab6a29f35bf	586
AnnaBridge	145:64910690c574	587	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
<>	129:0ab6a29f35bf	588	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
<>	129:0ab6a29f35bf	589
AnnaBridge	145:64910690c574	590	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
<>	129:0ab6a29f35bf	591	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
<>	129:0ab6a29f35bf	592
AnnaBridge	145:64910690c574	593	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
<>	129:0ab6a29f35bf	594	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
<>	129:0ab6a29f35bf	595
AnnaBridge	145:64910690c574	596	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
<>	129:0ab6a29f35bf	597	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
<>	129:0ab6a29f35bf	598
AnnaBridge	145:64910690c574	599	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
<>	129:0ab6a29f35bf	600	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
<>	129:0ab6a29f35bf	601
AnnaBridge	145:64910690c574	602	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
<>	129:0ab6a29f35bf	603	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
<>	129:0ab6a29f35bf	604
AnnaBridge	145:64910690c574	605	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
<>	129:0ab6a29f35bf	606	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
<>	129:0ab6a29f35bf	607
AnnaBridge	145:64910690c574	608	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	145:64910690c574	609	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
<>	129:0ab6a29f35bf	610	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
<>	129:0ab6a29f35bf	611
AnnaBridge	145:64910690c574	612	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
<>	129:0ab6a29f35bf	613	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
<>	129:0ab6a29f35bf	614
AnnaBridge	145:64910690c574	615	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
<>	129:0ab6a29f35bf	616	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
<>	129:0ab6a29f35bf	617
AnnaBridge	145:64910690c574	618	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	145:64910690c574	619	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	145:64910690c574	620	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	145:64910690c574	621
AnnaBridge	145:64910690c574	622	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	145:64910690c574	623	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	145:64910690c574	624
AnnaBridge	145:64910690c574	625	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	145:64910690c574	626	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	145:64910690c574	627
AnnaBridge	145:64910690c574	628	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	145:64910690c574	629	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	145:64910690c574	630
AnnaBridge	145:64910690c574	631	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	145:64910690c574	632	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	145:64910690c574	633
AnnaBridge	145:64910690c574	634	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	145:64910690c574	635	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	145:64910690c574	636
AnnaBridge	145:64910690c574	637	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	145:64910690c574	638	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	145:64910690c574	639	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	145:64910690c574	640
AnnaBridge	145:64910690c574	641	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	145:64910690c574	642	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	145:64910690c574	643
AnnaBridge	145:64910690c574	644	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	145:64910690c574	645	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	145:64910690c574	646
AnnaBridge	145:64910690c574	647	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	145:64910690c574	648	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	145:64910690c574	649
AnnaBridge	145:64910690c574	650	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	145:64910690c574	651	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	145:64910690c574	652
AnnaBridge	145:64910690c574	653	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	145:64910690c574	654	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	145:64910690c574	655
AnnaBridge	145:64910690c574	656	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	145:64910690c574	657	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	145:64910690c574	658
AnnaBridge	145:64910690c574	659	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	145:64910690c574	660	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	145:64910690c574	661	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	145:64910690c574	662
AnnaBridge	145:64910690c574	663	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	145:64910690c574	664	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	145:64910690c574	665
AnnaBridge	145:64910690c574	666	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	145:64910690c574	667	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	145:64910690c574	668
AnnaBridge	145:64910690c574	669	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	145:64910690c574	670	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	145:64910690c574	671
AnnaBridge	145:64910690c574	672	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	145:64910690c574	673	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	145:64910690c574	674
AnnaBridge	145:64910690c574	675	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	145:64910690c574	676	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	145:64910690c574	677
AnnaBridge	145:64910690c574	678	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	145:64910690c574	679	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
<>	129:0ab6a29f35bf	680	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
<>	129:0ab6a29f35bf	681
AnnaBridge	145:64910690c574	682	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
<>	129:0ab6a29f35bf	683	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
<>	129:0ab6a29f35bf	684
AnnaBridge	145:64910690c574	685	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
<>	129:0ab6a29f35bf	686	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
<>	129:0ab6a29f35bf	687
<>	129:0ab6a29f35bf	688	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	145:64910690c574	689	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
<>	129:0ab6a29f35bf	690	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
<>	129:0ab6a29f35bf	691
AnnaBridge	145:64910690c574	692	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
<>	129:0ab6a29f35bf	693	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
<>	129:0ab6a29f35bf	694
AnnaBridge	145:64910690c574	695	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
<>	129:0ab6a29f35bf	696	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
<>	129:0ab6a29f35bf	697
AnnaBridge	145:64910690c574	698	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
<>	129:0ab6a29f35bf	699	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
<>	129:0ab6a29f35bf	700
AnnaBridge	145:64910690c574	701	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
<>	129:0ab6a29f35bf	702	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
<>	129:0ab6a29f35bf	703
<>	129:0ab6a29f35bf	704	/@} end of group CMSIS_SCB /
<>	129:0ab6a29f35bf	705
<>	129:0ab6a29f35bf	706
AnnaBridge	145:64910690c574	707	/**
AnnaBridge	145:64910690c574	708	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	709	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	145:64910690c574	710	\brief Type definitions for the System Control and ID Register not in the SCB
<>	129:0ab6a29f35bf	711	@{
<>	129:0ab6a29f35bf	712	*/
<>	129:0ab6a29f35bf	713
AnnaBridge	145:64910690c574	714	/**
AnnaBridge	145:64910690c574	715	\brief Structure type to access the System Control and ID Register not in the SCB.
<>	129:0ab6a29f35bf	716	*/
<>	129:0ab6a29f35bf	717	typedef struct
<>	129:0ab6a29f35bf	718	{
AnnaBridge	145:64910690c574	719	uint32_t RESERVED0[1U];
AnnaBridge	145:64910690c574	720	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	145:64910690c574	721	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
<>	129:0ab6a29f35bf	722	} SCnSCB_Type;
<>	129:0ab6a29f35bf	723
<>	129:0ab6a29f35bf	724	/* Interrupt Controller Type Register Definitions */
AnnaBridge	145:64910690c574	725	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
<>	129:0ab6a29f35bf	726	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
<>	129:0ab6a29f35bf	727
<>	129:0ab6a29f35bf	728	/* Auxiliary Control Register Definitions */
AnnaBridge	145:64910690c574	729	#define SCnSCB_ACTLR_DISOOFP_Pos 9U /!< ACTLR: DISOOFP Position /
<>	129:0ab6a29f35bf	730	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
<>	129:0ab6a29f35bf	731
AnnaBridge	145:64910690c574	732	#define SCnSCB_ACTLR_DISFPCA_Pos 8U /!< ACTLR: DISFPCA Position /
<>	129:0ab6a29f35bf	733	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
<>	129:0ab6a29f35bf	734
AnnaBridge	145:64910690c574	735	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
<>	129:0ab6a29f35bf	736	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
<>	129:0ab6a29f35bf	737
AnnaBridge	145:64910690c574	738	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
<>	129:0ab6a29f35bf	739	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
<>	129:0ab6a29f35bf	740
AnnaBridge	145:64910690c574	741	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
<>	129:0ab6a29f35bf	742	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
<>	129:0ab6a29f35bf	743
<>	129:0ab6a29f35bf	744	/@} end of group CMSIS_SCnotSCB /
<>	129:0ab6a29f35bf	745
<>	129:0ab6a29f35bf	746
AnnaBridge	145:64910690c574	747	/**
AnnaBridge	145:64910690c574	748	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	749	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	145:64910690c574	750	\brief Type definitions for the System Timer Registers.
<>	129:0ab6a29f35bf	751	@{
<>	129:0ab6a29f35bf	752	*/
<>	129:0ab6a29f35bf	753
AnnaBridge	145:64910690c574	754	/**
AnnaBridge	145:64910690c574	755	\brief Structure type to access the System Timer (SysTick).
<>	129:0ab6a29f35bf	756	*/
<>	129:0ab6a29f35bf	757	typedef struct
<>	129:0ab6a29f35bf	758	{
AnnaBridge	145:64910690c574	759	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	145:64910690c574	760	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	145:64910690c574	761	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	145:64910690c574	762	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
<>	129:0ab6a29f35bf	763	} SysTick_Type;
<>	129:0ab6a29f35bf	764
<>	129:0ab6a29f35bf	765	/* SysTick Control / Status Register Definitions */
AnnaBridge	145:64910690c574	766	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
<>	129:0ab6a29f35bf	767	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
<>	129:0ab6a29f35bf	768
AnnaBridge	145:64910690c574	769	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
<>	129:0ab6a29f35bf	770	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
<>	129:0ab6a29f35bf	771
AnnaBridge	145:64910690c574	772	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
<>	129:0ab6a29f35bf	773	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
<>	129:0ab6a29f35bf	774
AnnaBridge	145:64910690c574	775	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
<>	129:0ab6a29f35bf	776	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
<>	129:0ab6a29f35bf	777
<>	129:0ab6a29f35bf	778	/* SysTick Reload Register Definitions */
AnnaBridge	145:64910690c574	779	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
<>	129:0ab6a29f35bf	780	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
<>	129:0ab6a29f35bf	781
<>	129:0ab6a29f35bf	782	/* SysTick Current Register Definitions */
AnnaBridge	145:64910690c574	783	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
<>	129:0ab6a29f35bf	784	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
<>	129:0ab6a29f35bf	785
<>	129:0ab6a29f35bf	786	/* SysTick Calibration Register Definitions */
AnnaBridge	145:64910690c574	787	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
<>	129:0ab6a29f35bf	788	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
<>	129:0ab6a29f35bf	789
AnnaBridge	145:64910690c574	790	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
<>	129:0ab6a29f35bf	791	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
<>	129:0ab6a29f35bf	792
AnnaBridge	145:64910690c574	793	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
<>	129:0ab6a29f35bf	794	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
<>	129:0ab6a29f35bf	795
<>	129:0ab6a29f35bf	796	/@} end of group CMSIS_SysTick /
<>	129:0ab6a29f35bf	797
<>	129:0ab6a29f35bf	798
AnnaBridge	145:64910690c574	799	/**
AnnaBridge	145:64910690c574	800	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	801	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	145:64910690c574	802	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<>	129:0ab6a29f35bf	803	@{
<>	129:0ab6a29f35bf	804	*/
<>	129:0ab6a29f35bf	805
AnnaBridge	145:64910690c574	806	/**
AnnaBridge	145:64910690c574	807	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<>	129:0ab6a29f35bf	808	*/
<>	129:0ab6a29f35bf	809	typedef struct
<>	129:0ab6a29f35bf	810	{
AnnaBridge	145:64910690c574	811	__OM union
<>	129:0ab6a29f35bf	812	{
AnnaBridge	145:64910690c574	813	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	145:64910690c574	814	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	145:64910690c574	815	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	145:64910690c574	816	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	145:64910690c574	817	uint32_t RESERVED0[864U];
AnnaBridge	145:64910690c574	818	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	145:64910690c574	819	uint32_t RESERVED1[15U];
AnnaBridge	145:64910690c574	820	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	145:64910690c574	821	uint32_t RESERVED2[15U];
AnnaBridge	145:64910690c574	822	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	145:64910690c574	823	uint32_t RESERVED3[29U];
AnnaBridge	145:64910690c574	824	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	145:64910690c574	825	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	145:64910690c574	826	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	145:64910690c574	827	uint32_t RESERVED4[43U];
AnnaBridge	145:64910690c574	828	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	145:64910690c574	829	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	145:64910690c574	830	uint32_t RESERVED5[6U];
AnnaBridge	145:64910690c574	831	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	145:64910690c574	832	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	145:64910690c574	833	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	145:64910690c574	834	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	145:64910690c574	835	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	145:64910690c574	836	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	145:64910690c574	837	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	145:64910690c574	838	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	145:64910690c574	839	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	145:64910690c574	840	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	145:64910690c574	841	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	145:64910690c574	842	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
<>	129:0ab6a29f35bf	843	} ITM_Type;
<>	129:0ab6a29f35bf	844
<>	129:0ab6a29f35bf	845	/* ITM Trace Privilege Register Definitions */
AnnaBridge	145:64910690c574	846	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
<>	129:0ab6a29f35bf	847	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
<>	129:0ab6a29f35bf	848
<>	129:0ab6a29f35bf	849	/* ITM Trace Control Register Definitions */
AnnaBridge	145:64910690c574	850	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
<>	129:0ab6a29f35bf	851	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
<>	129:0ab6a29f35bf	852
AnnaBridge	145:64910690c574	853	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
<>	129:0ab6a29f35bf	854	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
<>	129:0ab6a29f35bf	855
AnnaBridge	145:64910690c574	856	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
<>	129:0ab6a29f35bf	857	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
<>	129:0ab6a29f35bf	858
AnnaBridge	145:64910690c574	859	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
<>	129:0ab6a29f35bf	860	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
<>	129:0ab6a29f35bf	861
AnnaBridge	145:64910690c574	862	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
<>	129:0ab6a29f35bf	863	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
<>	129:0ab6a29f35bf	864
AnnaBridge	145:64910690c574	865	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
<>	129:0ab6a29f35bf	866	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
<>	129:0ab6a29f35bf	867
AnnaBridge	145:64910690c574	868	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
<>	129:0ab6a29f35bf	869	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
<>	129:0ab6a29f35bf	870
AnnaBridge	145:64910690c574	871	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
<>	129:0ab6a29f35bf	872	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
<>	129:0ab6a29f35bf	873
AnnaBridge	145:64910690c574	874	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
<>	129:0ab6a29f35bf	875	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
<>	129:0ab6a29f35bf	876
<>	129:0ab6a29f35bf	877	/* ITM Integration Write Register Definitions */
AnnaBridge	145:64910690c574	878	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
<>	129:0ab6a29f35bf	879	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
<>	129:0ab6a29f35bf	880
<>	129:0ab6a29f35bf	881	/* ITM Integration Read Register Definitions */
AnnaBridge	145:64910690c574	882	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
<>	129:0ab6a29f35bf	883	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
<>	129:0ab6a29f35bf	884
<>	129:0ab6a29f35bf	885	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	145:64910690c574	886	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
<>	129:0ab6a29f35bf	887	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
<>	129:0ab6a29f35bf	888
<>	129:0ab6a29f35bf	889	/* ITM Lock Status Register Definitions */
AnnaBridge	145:64910690c574	890	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
<>	129:0ab6a29f35bf	891	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
<>	129:0ab6a29f35bf	892
AnnaBridge	145:64910690c574	893	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
<>	129:0ab6a29f35bf	894	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
<>	129:0ab6a29f35bf	895
AnnaBridge	145:64910690c574	896	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
<>	129:0ab6a29f35bf	897	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
<>	129:0ab6a29f35bf	898
<>	129:0ab6a29f35bf	899	/@}/ /* end of group CMSIS_ITM */
<>	129:0ab6a29f35bf	900
<>	129:0ab6a29f35bf	901
AnnaBridge	145:64910690c574	902	/**
AnnaBridge	145:64910690c574	903	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	904	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	145:64910690c574	905	\brief Type definitions for the Data Watchpoint and Trace (DWT)
<>	129:0ab6a29f35bf	906	@{
<>	129:0ab6a29f35bf	907	*/
<>	129:0ab6a29f35bf	908
AnnaBridge	145:64910690c574	909	/**
AnnaBridge	145:64910690c574	910	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<>	129:0ab6a29f35bf	911	*/
<>	129:0ab6a29f35bf	912	typedef struct
<>	129:0ab6a29f35bf	913	{
AnnaBridge	145:64910690c574	914	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	145:64910690c574	915	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	145:64910690c574	916	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	145:64910690c574	917	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	145:64910690c574	918	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	145:64910690c574	919	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	145:64910690c574	920	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	145:64910690c574	921	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	145:64910690c574	922	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	145:64910690c574	923	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	145:64910690c574	924	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	145:64910690c574	925	uint32_t RESERVED0[1U];
AnnaBridge	145:64910690c574	926	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	145:64910690c574	927	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	145:64910690c574	928	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	145:64910690c574	929	uint32_t RESERVED1[1U];
AnnaBridge	145:64910690c574	930	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	145:64910690c574	931	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	145:64910690c574	932	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	145:64910690c574	933	uint32_t RESERVED2[1U];
AnnaBridge	145:64910690c574	934	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	145:64910690c574	935	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	145:64910690c574	936	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
<>	129:0ab6a29f35bf	937	} DWT_Type;
<>	129:0ab6a29f35bf	938
<>	129:0ab6a29f35bf	939	/* DWT Control Register Definitions */
AnnaBridge	145:64910690c574	940	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
<>	129:0ab6a29f35bf	941	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
<>	129:0ab6a29f35bf	942
AnnaBridge	145:64910690c574	943	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
<>	129:0ab6a29f35bf	944	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
<>	129:0ab6a29f35bf	945
AnnaBridge	145:64910690c574	946	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
<>	129:0ab6a29f35bf	947	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
<>	129:0ab6a29f35bf	948
AnnaBridge	145:64910690c574	949	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
<>	129:0ab6a29f35bf	950	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
<>	129:0ab6a29f35bf	951
AnnaBridge	145:64910690c574	952	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
<>	129:0ab6a29f35bf	953	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
<>	129:0ab6a29f35bf	954
AnnaBridge	145:64910690c574	955	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
<>	129:0ab6a29f35bf	956	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
<>	129:0ab6a29f35bf	957
AnnaBridge	145:64910690c574	958	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
<>	129:0ab6a29f35bf	959	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
<>	129:0ab6a29f35bf	960
AnnaBridge	145:64910690c574	961	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
<>	129:0ab6a29f35bf	962	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
<>	129:0ab6a29f35bf	963
AnnaBridge	145:64910690c574	964	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
<>	129:0ab6a29f35bf	965	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
<>	129:0ab6a29f35bf	966
AnnaBridge	145:64910690c574	967	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
<>	129:0ab6a29f35bf	968	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
<>	129:0ab6a29f35bf	969
AnnaBridge	145:64910690c574	970	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
<>	129:0ab6a29f35bf	971	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
<>	129:0ab6a29f35bf	972
AnnaBridge	145:64910690c574	973	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
<>	129:0ab6a29f35bf	974	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
<>	129:0ab6a29f35bf	975
AnnaBridge	145:64910690c574	976	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
<>	129:0ab6a29f35bf	977	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
<>	129:0ab6a29f35bf	978
AnnaBridge	145:64910690c574	979	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
<>	129:0ab6a29f35bf	980	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
<>	129:0ab6a29f35bf	981
AnnaBridge	145:64910690c574	982	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
<>	129:0ab6a29f35bf	983	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
<>	129:0ab6a29f35bf	984
AnnaBridge	145:64910690c574	985	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
<>	129:0ab6a29f35bf	986	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
<>	129:0ab6a29f35bf	987
AnnaBridge	145:64910690c574	988	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
<>	129:0ab6a29f35bf	989	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
<>	129:0ab6a29f35bf	990
AnnaBridge	145:64910690c574	991	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
<>	129:0ab6a29f35bf	992	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
<>	129:0ab6a29f35bf	993
<>	129:0ab6a29f35bf	994	/* DWT CPI Count Register Definitions */
AnnaBridge	145:64910690c574	995	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
<>	129:0ab6a29f35bf	996	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
<>	129:0ab6a29f35bf	997
<>	129:0ab6a29f35bf	998	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	145:64910690c574	999	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
<>	129:0ab6a29f35bf	1000	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
<>	129:0ab6a29f35bf	1001
<>	129:0ab6a29f35bf	1002	/* DWT Sleep Count Register Definitions */
AnnaBridge	145:64910690c574	1003	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
<>	129:0ab6a29f35bf	1004	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
<>	129:0ab6a29f35bf	1005
<>	129:0ab6a29f35bf	1006	/* DWT LSU Count Register Definitions */
AnnaBridge	145:64910690c574	1007	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
<>	129:0ab6a29f35bf	1008	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
<>	129:0ab6a29f35bf	1009
<>	129:0ab6a29f35bf	1010	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	145:64910690c574	1011	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
<>	129:0ab6a29f35bf	1012	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
<>	129:0ab6a29f35bf	1013
<>	129:0ab6a29f35bf	1014	/* DWT Comparator Mask Register Definitions */
AnnaBridge	145:64910690c574	1015	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
<>	129:0ab6a29f35bf	1016	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
<>	129:0ab6a29f35bf	1017
<>	129:0ab6a29f35bf	1018	/* DWT Comparator Function Register Definitions */
AnnaBridge	145:64910690c574	1019	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
<>	129:0ab6a29f35bf	1020	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
<>	129:0ab6a29f35bf	1021
AnnaBridge	145:64910690c574	1022	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
<>	129:0ab6a29f35bf	1023	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
<>	129:0ab6a29f35bf	1024
AnnaBridge	145:64910690c574	1025	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
<>	129:0ab6a29f35bf	1026	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
<>	129:0ab6a29f35bf	1027
AnnaBridge	145:64910690c574	1028	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
<>	129:0ab6a29f35bf	1029	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
<>	129:0ab6a29f35bf	1030
AnnaBridge	145:64910690c574	1031	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
<>	129:0ab6a29f35bf	1032	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
<>	129:0ab6a29f35bf	1033
AnnaBridge	145:64910690c574	1034	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
<>	129:0ab6a29f35bf	1035	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
<>	129:0ab6a29f35bf	1036
AnnaBridge	145:64910690c574	1037	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
<>	129:0ab6a29f35bf	1038	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
<>	129:0ab6a29f35bf	1039
AnnaBridge	145:64910690c574	1040	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
<>	129:0ab6a29f35bf	1041	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
<>	129:0ab6a29f35bf	1042
AnnaBridge	145:64910690c574	1043	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
<>	129:0ab6a29f35bf	1044	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
<>	129:0ab6a29f35bf	1045
<>	129:0ab6a29f35bf	1046	/@}/ /* end of group CMSIS_DWT */
<>	129:0ab6a29f35bf	1047
<>	129:0ab6a29f35bf	1048
AnnaBridge	145:64910690c574	1049	/**
AnnaBridge	145:64910690c574	1050	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1051	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	145:64910690c574	1052	\brief Type definitions for the Trace Port Interface (TPI)
<>	129:0ab6a29f35bf	1053	@{
<>	129:0ab6a29f35bf	1054	*/
<>	129:0ab6a29f35bf	1055
AnnaBridge	145:64910690c574	1056	/**
AnnaBridge	145:64910690c574	1057	\brief Structure type to access the Trace Port Interface Register (TPI).
<>	129:0ab6a29f35bf	1058	*/
<>	129:0ab6a29f35bf	1059	typedef struct
<>	129:0ab6a29f35bf	1060	{
AnnaBridge	145:64910690c574	1061	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	145:64910690c574	1062	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	145:64910690c574	1063	uint32_t RESERVED0[2U];
AnnaBridge	145:64910690c574	1064	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	145:64910690c574	1065	uint32_t RESERVED1[55U];
AnnaBridge	145:64910690c574	1066	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	145:64910690c574	1067	uint32_t RESERVED2[131U];
AnnaBridge	145:64910690c574	1068	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	145:64910690c574	1069	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	145:64910690c574	1070	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	145:64910690c574	1071	uint32_t RESERVED3[759U];
AnnaBridge	145:64910690c574	1072	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	145:64910690c574	1073	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	145:64910690c574	1074	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	145:64910690c574	1075	uint32_t RESERVED4[1U];
AnnaBridge	145:64910690c574	1076	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	145:64910690c574	1077	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	145:64910690c574	1078	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	145:64910690c574	1079	uint32_t RESERVED5[39U];
AnnaBridge	145:64910690c574	1080	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	145:64910690c574	1081	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	145:64910690c574	1082	uint32_t RESERVED7[8U];
AnnaBridge	145:64910690c574	1083	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	145:64910690c574	1084	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
<>	129:0ab6a29f35bf	1085	} TPI_Type;
<>	129:0ab6a29f35bf	1086
<>	129:0ab6a29f35bf	1087	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	145:64910690c574	1088	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
<>	129:0ab6a29f35bf	1089	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
<>	129:0ab6a29f35bf	1090
<>	129:0ab6a29f35bf	1091	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	145:64910690c574	1092	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
<>	129:0ab6a29f35bf	1093	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
<>	129:0ab6a29f35bf	1094
<>	129:0ab6a29f35bf	1095	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	145:64910690c574	1096	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
<>	129:0ab6a29f35bf	1097	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
<>	129:0ab6a29f35bf	1098
AnnaBridge	145:64910690c574	1099	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
<>	129:0ab6a29f35bf	1100	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
<>	129:0ab6a29f35bf	1101
AnnaBridge	145:64910690c574	1102	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
<>	129:0ab6a29f35bf	1103	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
<>	129:0ab6a29f35bf	1104
AnnaBridge	145:64910690c574	1105	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
<>	129:0ab6a29f35bf	1106	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
<>	129:0ab6a29f35bf	1107
<>	129:0ab6a29f35bf	1108	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	145:64910690c574	1109	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
<>	129:0ab6a29f35bf	1110	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
<>	129:0ab6a29f35bf	1111
AnnaBridge	145:64910690c574	1112	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
<>	129:0ab6a29f35bf	1113	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
<>	129:0ab6a29f35bf	1114
<>	129:0ab6a29f35bf	1115	/* TPI TRIGGER Register Definitions */
AnnaBridge	145:64910690c574	1116	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
<>	129:0ab6a29f35bf	1117	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
<>	129:0ab6a29f35bf	1118
<>	129:0ab6a29f35bf	1119	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	145:64910690c574	1120	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
<>	129:0ab6a29f35bf	1121	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
<>	129:0ab6a29f35bf	1122
AnnaBridge	145:64910690c574	1123	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
<>	129:0ab6a29f35bf	1124	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
<>	129:0ab6a29f35bf	1125
AnnaBridge	145:64910690c574	1126	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
<>	129:0ab6a29f35bf	1127	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
<>	129:0ab6a29f35bf	1128
AnnaBridge	145:64910690c574	1129	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
<>	129:0ab6a29f35bf	1130	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
<>	129:0ab6a29f35bf	1131
AnnaBridge	145:64910690c574	1132	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
<>	129:0ab6a29f35bf	1133	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
<>	129:0ab6a29f35bf	1134
AnnaBridge	145:64910690c574	1135	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
<>	129:0ab6a29f35bf	1136	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
<>	129:0ab6a29f35bf	1137
AnnaBridge	145:64910690c574	1138	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
<>	129:0ab6a29f35bf	1139	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
<>	129:0ab6a29f35bf	1140
<>	129:0ab6a29f35bf	1141	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	145:64910690c574	1142	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
<>	129:0ab6a29f35bf	1143	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
<>	129:0ab6a29f35bf	1144
<>	129:0ab6a29f35bf	1145	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	145:64910690c574	1146	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
<>	129:0ab6a29f35bf	1147	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
<>	129:0ab6a29f35bf	1148
AnnaBridge	145:64910690c574	1149	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
<>	129:0ab6a29f35bf	1150	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
<>	129:0ab6a29f35bf	1151
AnnaBridge	145:64910690c574	1152	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
<>	129:0ab6a29f35bf	1153	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
<>	129:0ab6a29f35bf	1154
AnnaBridge	145:64910690c574	1155	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
<>	129:0ab6a29f35bf	1156	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
<>	129:0ab6a29f35bf	1157
AnnaBridge	145:64910690c574	1158	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
<>	129:0ab6a29f35bf	1159	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
<>	129:0ab6a29f35bf	1160
AnnaBridge	145:64910690c574	1161	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
<>	129:0ab6a29f35bf	1162	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
<>	129:0ab6a29f35bf	1163
AnnaBridge	145:64910690c574	1164	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
<>	129:0ab6a29f35bf	1165	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
<>	129:0ab6a29f35bf	1166
<>	129:0ab6a29f35bf	1167	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	145:64910690c574	1168	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
<>	129:0ab6a29f35bf	1169	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
<>	129:0ab6a29f35bf	1170
<>	129:0ab6a29f35bf	1171	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	145:64910690c574	1172	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
<>	129:0ab6a29f35bf	1173	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
<>	129:0ab6a29f35bf	1174
<>	129:0ab6a29f35bf	1175	/* TPI DEVID Register Definitions */
AnnaBridge	145:64910690c574	1176	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
<>	129:0ab6a29f35bf	1177	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
<>	129:0ab6a29f35bf	1178
AnnaBridge	145:64910690c574	1179	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
<>	129:0ab6a29f35bf	1180	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
<>	129:0ab6a29f35bf	1181
AnnaBridge	145:64910690c574	1182	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
<>	129:0ab6a29f35bf	1183	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
<>	129:0ab6a29f35bf	1184
AnnaBridge	145:64910690c574	1185	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
<>	129:0ab6a29f35bf	1186	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
<>	129:0ab6a29f35bf	1187
AnnaBridge	145:64910690c574	1188	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
<>	129:0ab6a29f35bf	1189	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
<>	129:0ab6a29f35bf	1190
AnnaBridge	145:64910690c574	1191	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
<>	129:0ab6a29f35bf	1192	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
<>	129:0ab6a29f35bf	1193
<>	129:0ab6a29f35bf	1194	/* TPI DEVTYPE Register Definitions */
AnnaBridge	145:64910690c574	1195	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
<>	129:0ab6a29f35bf	1196	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
<>	129:0ab6a29f35bf	1197
AnnaBridge	145:64910690c574	1198	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
<>	129:0ab6a29f35bf	1199	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
<>	129:0ab6a29f35bf	1200
<>	129:0ab6a29f35bf	1201	/@}/ /* end of group CMSIS_TPI */
<>	129:0ab6a29f35bf	1202
<>	129:0ab6a29f35bf	1203
AnnaBridge	145:64910690c574	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	1205	/**
AnnaBridge	145:64910690c574	1206	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1207	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	145:64910690c574	1208	\brief Type definitions for the Memory Protection Unit (MPU)
<>	129:0ab6a29f35bf	1209	@{
<>	129:0ab6a29f35bf	1210	*/
<>	129:0ab6a29f35bf	1211
AnnaBridge	145:64910690c574	1212	/**
AnnaBridge	145:64910690c574	1213	\brief Structure type to access the Memory Protection Unit (MPU).
<>	129:0ab6a29f35bf	1214	*/
<>	129:0ab6a29f35bf	1215	typedef struct
<>	129:0ab6a29f35bf	1216	{
AnnaBridge	145:64910690c574	1217	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	145:64910690c574	1218	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	145:64910690c574	1219	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	145:64910690c574	1220	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	145:64910690c574	1221	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	145:64910690c574	1222	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	145:64910690c574	1223	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	145:64910690c574	1224	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	145:64910690c574	1225	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	145:64910690c574	1226	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	145:64910690c574	1227	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
<>	129:0ab6a29f35bf	1228	} MPU_Type;
<>	129:0ab6a29f35bf	1229
AnnaBridge	145:64910690c574	1230	/* MPU Type Register Definitions */
AnnaBridge	145:64910690c574	1231	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
<>	129:0ab6a29f35bf	1232	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
<>	129:0ab6a29f35bf	1233
AnnaBridge	145:64910690c574	1234	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
<>	129:0ab6a29f35bf	1235	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
<>	129:0ab6a29f35bf	1236
AnnaBridge	145:64910690c574	1237	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
<>	129:0ab6a29f35bf	1238	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
<>	129:0ab6a29f35bf	1239
AnnaBridge	145:64910690c574	1240	/* MPU Control Register Definitions */
AnnaBridge	145:64910690c574	1241	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
<>	129:0ab6a29f35bf	1242	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
<>	129:0ab6a29f35bf	1243
AnnaBridge	145:64910690c574	1244	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
<>	129:0ab6a29f35bf	1245	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
<>	129:0ab6a29f35bf	1246
AnnaBridge	145:64910690c574	1247	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
<>	129:0ab6a29f35bf	1248	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
<>	129:0ab6a29f35bf	1249
AnnaBridge	145:64910690c574	1250	/* MPU Region Number Register Definitions */
AnnaBridge	145:64910690c574	1251	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
<>	129:0ab6a29f35bf	1252	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
<>	129:0ab6a29f35bf	1253
AnnaBridge	145:64910690c574	1254	/* MPU Region Base Address Register Definitions */
AnnaBridge	145:64910690c574	1255	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
<>	129:0ab6a29f35bf	1256	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
<>	129:0ab6a29f35bf	1257
AnnaBridge	145:64910690c574	1258	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
<>	129:0ab6a29f35bf	1259	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
<>	129:0ab6a29f35bf	1260
AnnaBridge	145:64910690c574	1261	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
<>	129:0ab6a29f35bf	1262	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
<>	129:0ab6a29f35bf	1263
AnnaBridge	145:64910690c574	1264	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	145:64910690c574	1265	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
<>	129:0ab6a29f35bf	1266	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
<>	129:0ab6a29f35bf	1267
AnnaBridge	145:64910690c574	1268	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
<>	129:0ab6a29f35bf	1269	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
<>	129:0ab6a29f35bf	1270
AnnaBridge	145:64910690c574	1271	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
<>	129:0ab6a29f35bf	1272	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
<>	129:0ab6a29f35bf	1273
AnnaBridge	145:64910690c574	1274	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
<>	129:0ab6a29f35bf	1275	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
<>	129:0ab6a29f35bf	1276
AnnaBridge	145:64910690c574	1277	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
<>	129:0ab6a29f35bf	1278	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
<>	129:0ab6a29f35bf	1279
AnnaBridge	145:64910690c574	1280	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
<>	129:0ab6a29f35bf	1281	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
<>	129:0ab6a29f35bf	1282
AnnaBridge	145:64910690c574	1283	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
<>	129:0ab6a29f35bf	1284	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
<>	129:0ab6a29f35bf	1285
AnnaBridge	145:64910690c574	1286	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
<>	129:0ab6a29f35bf	1287	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
<>	129:0ab6a29f35bf	1288
AnnaBridge	145:64910690c574	1289	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
<>	129:0ab6a29f35bf	1290	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
<>	129:0ab6a29f35bf	1291
AnnaBridge	145:64910690c574	1292	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
<>	129:0ab6a29f35bf	1293	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
<>	129:0ab6a29f35bf	1294
<>	129:0ab6a29f35bf	1295	/@} end of group CMSIS_MPU /
AnnaBridge	145:64910690c574	1296	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
<>	129:0ab6a29f35bf	1297
<>	129:0ab6a29f35bf	1298
AnnaBridge	145:64910690c574	1299	/**
AnnaBridge	145:64910690c574	1300	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1301	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	145:64910690c574	1302	\brief Type definitions for the Floating Point Unit (FPU)
<>	129:0ab6a29f35bf	1303	@{
<>	129:0ab6a29f35bf	1304	*/
<>	129:0ab6a29f35bf	1305
AnnaBridge	145:64910690c574	1306	/**
AnnaBridge	145:64910690c574	1307	\brief Structure type to access the Floating Point Unit (FPU).
<>	129:0ab6a29f35bf	1308	*/
<>	129:0ab6a29f35bf	1309	typedef struct
<>	129:0ab6a29f35bf	1310	{
AnnaBridge	145:64910690c574	1311	uint32_t RESERVED0[1U];
AnnaBridge	145:64910690c574	1312	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	145:64910690c574	1313	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	145:64910690c574	1314	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	145:64910690c574	1315	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	145:64910690c574	1316	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
<>	129:0ab6a29f35bf	1317	} FPU_Type;
<>	129:0ab6a29f35bf	1318
AnnaBridge	145:64910690c574	1319	/* Floating-Point Context Control Register Definitions */
AnnaBridge	145:64910690c574	1320	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
<>	129:0ab6a29f35bf	1321	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
<>	129:0ab6a29f35bf	1322
AnnaBridge	145:64910690c574	1323	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
<>	129:0ab6a29f35bf	1324	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
<>	129:0ab6a29f35bf	1325
AnnaBridge	145:64910690c574	1326	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
<>	129:0ab6a29f35bf	1327	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
<>	129:0ab6a29f35bf	1328
AnnaBridge	145:64910690c574	1329	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
<>	129:0ab6a29f35bf	1330	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
<>	129:0ab6a29f35bf	1331
AnnaBridge	145:64910690c574	1332	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
<>	129:0ab6a29f35bf	1333	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
<>	129:0ab6a29f35bf	1334
AnnaBridge	145:64910690c574	1335	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
<>	129:0ab6a29f35bf	1336	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
<>	129:0ab6a29f35bf	1337
AnnaBridge	145:64910690c574	1338	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
<>	129:0ab6a29f35bf	1339	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
<>	129:0ab6a29f35bf	1340
AnnaBridge	145:64910690c574	1341	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
<>	129:0ab6a29f35bf	1342	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
<>	129:0ab6a29f35bf	1343
AnnaBridge	145:64910690c574	1344	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
<>	129:0ab6a29f35bf	1345	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
<>	129:0ab6a29f35bf	1346
AnnaBridge	145:64910690c574	1347	/* Floating-Point Context Address Register Definitions */
AnnaBridge	145:64910690c574	1348	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
<>	129:0ab6a29f35bf	1349	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
<>	129:0ab6a29f35bf	1350
AnnaBridge	145:64910690c574	1351	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	145:64910690c574	1352	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
<>	129:0ab6a29f35bf	1353	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
<>	129:0ab6a29f35bf	1354
AnnaBridge	145:64910690c574	1355	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
<>	129:0ab6a29f35bf	1356	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
<>	129:0ab6a29f35bf	1357
AnnaBridge	145:64910690c574	1358	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
<>	129:0ab6a29f35bf	1359	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
<>	129:0ab6a29f35bf	1360
AnnaBridge	145:64910690c574	1361	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
<>	129:0ab6a29f35bf	1362	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
<>	129:0ab6a29f35bf	1363
AnnaBridge	145:64910690c574	1364	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	145:64910690c574	1365	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
<>	129:0ab6a29f35bf	1366	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
<>	129:0ab6a29f35bf	1367
AnnaBridge	145:64910690c574	1368	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
<>	129:0ab6a29f35bf	1369	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
<>	129:0ab6a29f35bf	1370
AnnaBridge	145:64910690c574	1371	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
<>	129:0ab6a29f35bf	1372	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
<>	129:0ab6a29f35bf	1373
AnnaBridge	145:64910690c574	1374	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
<>	129:0ab6a29f35bf	1375	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
<>	129:0ab6a29f35bf	1376
AnnaBridge	145:64910690c574	1377	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
<>	129:0ab6a29f35bf	1378	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
<>	129:0ab6a29f35bf	1379
AnnaBridge	145:64910690c574	1380	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
<>	129:0ab6a29f35bf	1381	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
<>	129:0ab6a29f35bf	1382
AnnaBridge	145:64910690c574	1383	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
<>	129:0ab6a29f35bf	1384	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
<>	129:0ab6a29f35bf	1385
AnnaBridge	145:64910690c574	1386	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
<>	129:0ab6a29f35bf	1387	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
<>	129:0ab6a29f35bf	1388
AnnaBridge	145:64910690c574	1389	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	145:64910690c574	1390	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
<>	129:0ab6a29f35bf	1391	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
<>	129:0ab6a29f35bf	1392
AnnaBridge	145:64910690c574	1393	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
<>	129:0ab6a29f35bf	1394	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
<>	129:0ab6a29f35bf	1395
AnnaBridge	145:64910690c574	1396	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
<>	129:0ab6a29f35bf	1397	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
<>	129:0ab6a29f35bf	1398
AnnaBridge	145:64910690c574	1399	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
<>	129:0ab6a29f35bf	1400	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
<>	129:0ab6a29f35bf	1401
<>	129:0ab6a29f35bf	1402	/@} end of group CMSIS_FPU /
<>	129:0ab6a29f35bf	1403
<>	129:0ab6a29f35bf	1404
AnnaBridge	145:64910690c574	1405	/**
AnnaBridge	145:64910690c574	1406	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1407	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	145:64910690c574	1408	\brief Type definitions for the Core Debug Registers
<>	129:0ab6a29f35bf	1409	@{
<>	129:0ab6a29f35bf	1410	*/
<>	129:0ab6a29f35bf	1411
AnnaBridge	145:64910690c574	1412	/**
AnnaBridge	145:64910690c574	1413	\brief Structure type to access the Core Debug Register (CoreDebug).
<>	129:0ab6a29f35bf	1414	*/
<>	129:0ab6a29f35bf	1415	typedef struct
<>	129:0ab6a29f35bf	1416	{
AnnaBridge	145:64910690c574	1417	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	145:64910690c574	1418	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	145:64910690c574	1419	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	145:64910690c574	1420	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
<>	129:0ab6a29f35bf	1421	} CoreDebug_Type;
<>	129:0ab6a29f35bf	1422
AnnaBridge	145:64910690c574	1423	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	145:64910690c574	1424	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
<>	129:0ab6a29f35bf	1425	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
<>	129:0ab6a29f35bf	1426
AnnaBridge	145:64910690c574	1427	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
<>	129:0ab6a29f35bf	1428	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
<>	129:0ab6a29f35bf	1429
AnnaBridge	145:64910690c574	1430	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
<>	129:0ab6a29f35bf	1431	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
<>	129:0ab6a29f35bf	1432
AnnaBridge	145:64910690c574	1433	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
<>	129:0ab6a29f35bf	1434	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
<>	129:0ab6a29f35bf	1435
AnnaBridge	145:64910690c574	1436	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
<>	129:0ab6a29f35bf	1437	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
<>	129:0ab6a29f35bf	1438
AnnaBridge	145:64910690c574	1439	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
<>	129:0ab6a29f35bf	1440	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
<>	129:0ab6a29f35bf	1441
AnnaBridge	145:64910690c574	1442	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
<>	129:0ab6a29f35bf	1443	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
<>	129:0ab6a29f35bf	1444
AnnaBridge	145:64910690c574	1445	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
<>	129:0ab6a29f35bf	1446	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
<>	129:0ab6a29f35bf	1447
AnnaBridge	145:64910690c574	1448	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
<>	129:0ab6a29f35bf	1449	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
<>	129:0ab6a29f35bf	1450
AnnaBridge	145:64910690c574	1451	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
<>	129:0ab6a29f35bf	1452	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
<>	129:0ab6a29f35bf	1453
AnnaBridge	145:64910690c574	1454	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
<>	129:0ab6a29f35bf	1455	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
<>	129:0ab6a29f35bf	1456
AnnaBridge	145:64910690c574	1457	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
<>	129:0ab6a29f35bf	1458	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
<>	129:0ab6a29f35bf	1459
AnnaBridge	145:64910690c574	1460	/* Debug Core Register Selector Register Definitions */
AnnaBridge	145:64910690c574	1461	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
<>	129:0ab6a29f35bf	1462	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
<>	129:0ab6a29f35bf	1463
AnnaBridge	145:64910690c574	1464	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
<>	129:0ab6a29f35bf	1465	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
<>	129:0ab6a29f35bf	1466
AnnaBridge	145:64910690c574	1467	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	145:64910690c574	1468	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
<>	129:0ab6a29f35bf	1469	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
<>	129:0ab6a29f35bf	1470
AnnaBridge	145:64910690c574	1471	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
<>	129:0ab6a29f35bf	1472	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
<>	129:0ab6a29f35bf	1473
AnnaBridge	145:64910690c574	1474	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
<>	129:0ab6a29f35bf	1475	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
<>	129:0ab6a29f35bf	1476
AnnaBridge	145:64910690c574	1477	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
<>	129:0ab6a29f35bf	1478	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
<>	129:0ab6a29f35bf	1479
AnnaBridge	145:64910690c574	1480	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
<>	129:0ab6a29f35bf	1481	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
<>	129:0ab6a29f35bf	1482
AnnaBridge	145:64910690c574	1483	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
<>	129:0ab6a29f35bf	1484	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
<>	129:0ab6a29f35bf	1485
AnnaBridge	145:64910690c574	1486	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
<>	129:0ab6a29f35bf	1487	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
<>	129:0ab6a29f35bf	1488
AnnaBridge	145:64910690c574	1489	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
<>	129:0ab6a29f35bf	1490	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
<>	129:0ab6a29f35bf	1491
AnnaBridge	145:64910690c574	1492	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
<>	129:0ab6a29f35bf	1493	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
<>	129:0ab6a29f35bf	1494
AnnaBridge	145:64910690c574	1495	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
<>	129:0ab6a29f35bf	1496	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
<>	129:0ab6a29f35bf	1497
AnnaBridge	145:64910690c574	1498	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
<>	129:0ab6a29f35bf	1499	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
<>	129:0ab6a29f35bf	1500
AnnaBridge	145:64910690c574	1501	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
<>	129:0ab6a29f35bf	1502	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
<>	129:0ab6a29f35bf	1503
AnnaBridge	145:64910690c574	1504	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
<>	129:0ab6a29f35bf	1505	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
<>	129:0ab6a29f35bf	1506
<>	129:0ab6a29f35bf	1507	/@} end of group CMSIS_CoreDebug /
<>	129:0ab6a29f35bf	1508
<>	129:0ab6a29f35bf	1509
AnnaBridge	145:64910690c574	1510	/**
AnnaBridge	145:64910690c574	1511	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1512	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	145:64910690c574	1513	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<>	129:0ab6a29f35bf	1514	@{
<>	129:0ab6a29f35bf	1515	*/
<>	129:0ab6a29f35bf	1516
AnnaBridge	145:64910690c574	1517	/**
AnnaBridge	145:64910690c574	1518	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	145:64910690c574	1519	\param[in] field Name of the register bit field.
AnnaBridge	145:64910690c574	1520	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	145:64910690c574	1521	\return Masked and shifted value.
AnnaBridge	145:64910690c574	1522	*/
AnnaBridge	145:64910690c574	1523	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	145:64910690c574	1524
AnnaBridge	145:64910690c574	1525	/**
AnnaBridge	145:64910690c574	1526	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	145:64910690c574	1527	\param[in] field Name of the register bit field.
AnnaBridge	145:64910690c574	1528	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	145:64910690c574	1529	\return Masked and shifted bit field value.
AnnaBridge	145:64910690c574	1530	*/
AnnaBridge	145:64910690c574	1531	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	145:64910690c574	1532
AnnaBridge	145:64910690c574	1533	/@} end of group CMSIS_core_bitfield /
AnnaBridge	145:64910690c574	1534
AnnaBridge	145:64910690c574	1535
AnnaBridge	145:64910690c574	1536	/**
AnnaBridge	145:64910690c574	1537	\ingroup CMSIS_core_register
AnnaBridge	145:64910690c574	1538	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	145:64910690c574	1539	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	145:64910690c574	1540	@{
AnnaBridge	145:64910690c574	1541	*/
AnnaBridge	145:64910690c574	1542
AnnaBridge	145:64910690c574	1543	/* Memory mapping of Core Hardware */
AnnaBridge	145:64910690c574	1544	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	145:64910690c574	1545	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	145:64910690c574	1546	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	145:64910690c574	1547	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	145:64910690c574	1548	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	145:64910690c574	1549	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	145:64910690c574	1550	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	145:64910690c574	1551	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
<>	129:0ab6a29f35bf	1552
<>	129:0ab6a29f35bf	1553	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	145:64910690c574	1554	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	145:64910690c574	1555	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	145:64910690c574	1556	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	145:64910690c574	1557	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	145:64910690c574	1558	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	145:64910690c574	1559	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	145:64910690c574	1560	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
<>	129:0ab6a29f35bf	1561
AnnaBridge	145:64910690c574	1562	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	145:64910690c574	1563	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	145:64910690c574	1564	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
<>	129:0ab6a29f35bf	1565	#endif
<>	129:0ab6a29f35bf	1566
AnnaBridge	145:64910690c574	1567	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	145:64910690c574	1568	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
<>	129:0ab6a29f35bf	1569
<>	129:0ab6a29f35bf	1570	/@} /
<>	129:0ab6a29f35bf	1571
<>	129:0ab6a29f35bf	1572
<>	129:0ab6a29f35bf	1573
<>	129:0ab6a29f35bf	1574	/*******************************************************************************
<>	129:0ab6a29f35bf	1575	* Hardware Abstraction Layer
<>	129:0ab6a29f35bf	1576	Core Function Interface contains:
<>	129:0ab6a29f35bf	1577	- Core NVIC Functions
<>	129:0ab6a29f35bf	1578	- Core SysTick Functions
<>	129:0ab6a29f35bf	1579	- Core Debug Functions
<>	129:0ab6a29f35bf	1580	- Core Register Access Functions
<>	129:0ab6a29f35bf	1581	******************************************************************************/
AnnaBridge	145:64910690c574	1582	/**
AnnaBridge	145:64910690c574	1583	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<>	129:0ab6a29f35bf	1584	*/
<>	129:0ab6a29f35bf	1585
<>	129:0ab6a29f35bf	1586
<>	129:0ab6a29f35bf	1587
<>	129:0ab6a29f35bf	1588	/* ########################## NVIC functions #################################### */
AnnaBridge	145:64910690c574	1589	/**
AnnaBridge	145:64910690c574	1590	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	1591	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	145:64910690c574	1592	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	145:64910690c574	1593	@{
<>	129:0ab6a29f35bf	1594	*/
<>	129:0ab6a29f35bf	1595
<>	129:0ab6a29f35bf	1596	#ifdef CMSIS_NVIC_VIRTUAL
<>	129:0ab6a29f35bf	1597	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	129:0ab6a29f35bf	1598	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<>	129:0ab6a29f35bf	1599	#endif
<>	129:0ab6a29f35bf	1600	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	129:0ab6a29f35bf	1601	#else
<>	129:0ab6a29f35bf	1602	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<>	129:0ab6a29f35bf	1603	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<>	129:0ab6a29f35bf	1604	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	145:64910690c574	1605	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<>	129:0ab6a29f35bf	1606	#define NVIC_DisableIRQ __NVIC_DisableIRQ
<>	129:0ab6a29f35bf	1607	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<>	129:0ab6a29f35bf	1608	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<>	129:0ab6a29f35bf	1609	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<>	129:0ab6a29f35bf	1610	#define NVIC_GetActive __NVIC_GetActive
<>	129:0ab6a29f35bf	1611	#define NVIC_SetPriority __NVIC_SetPriority
<>	129:0ab6a29f35bf	1612	#define NVIC_GetPriority __NVIC_GetPriority
<>	129:0ab6a29f35bf	1613	#define NVIC_SystemReset __NVIC_SystemReset
<>	129:0ab6a29f35bf	1614	#endif /* CMSIS_NVIC_VIRTUAL */
<>	129:0ab6a29f35bf	1615
<>	129:0ab6a29f35bf	1616	#ifdef CMSIS_VECTAB_VIRTUAL
<>	129:0ab6a29f35bf	1617	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	145:64910690c574	1618	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<>	129:0ab6a29f35bf	1619	#endif
<>	129:0ab6a29f35bf	1620	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<>	129:0ab6a29f35bf	1621	#else
<>	129:0ab6a29f35bf	1622	#define NVIC_SetVector __NVIC_SetVector
<>	129:0ab6a29f35bf	1623	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	145:64910690c574	1624	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	145:64910690c574	1625
AnnaBridge	145:64910690c574	1626	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	145:64910690c574	1627
<>	129:0ab6a29f35bf	1628
<>	129:0ab6a29f35bf	1629
AnnaBridge	145:64910690c574	1630	/**
AnnaBridge	145:64910690c574	1631	\brief Set Priority Grouping
AnnaBridge	145:64910690c574	1632	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	145:64910690c574	1633	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	145:64910690c574	1634	Only values from 0..7 are used.
AnnaBridge	145:64910690c574	1635	In case of a conflict between priority grouping and available
AnnaBridge	145:64910690c574	1636	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	145:64910690c574	1637	\param [in] PriorityGroup Priority grouping field.
<>	129:0ab6a29f35bf	1638	*/
<>	129:0ab6a29f35bf	1639	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<>	129:0ab6a29f35bf	1640	{
<>	129:0ab6a29f35bf	1641	uint32_t reg_value;
<>	129:0ab6a29f35bf	1642	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	129:0ab6a29f35bf	1643
<>	129:0ab6a29f35bf	1644	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	145:64910690c574	1645	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<>	129:0ab6a29f35bf	1646	reg_value = (reg_value \|
<>	129:0ab6a29f35bf	1647	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	145:64910690c574	1648	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
<>	129:0ab6a29f35bf	1649	SCB->AIRCR = reg_value;
<>	129:0ab6a29f35bf	1650	}
<>	129:0ab6a29f35bf	1651
<>	129:0ab6a29f35bf	1652
AnnaBridge	145:64910690c574	1653	/**
AnnaBridge	145:64910690c574	1654	\brief Get Priority Grouping
AnnaBridge	145:64910690c574	1655	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	145:64910690c574	1656	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<>	129:0ab6a29f35bf	1657	*/
<>	129:0ab6a29f35bf	1658	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<>	129:0ab6a29f35bf	1659	{
<>	129:0ab6a29f35bf	1660	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<>	129:0ab6a29f35bf	1661	}
<>	129:0ab6a29f35bf	1662
<>	129:0ab6a29f35bf	1663
AnnaBridge	145:64910690c574	1664	/**
AnnaBridge	145:64910690c574	1665	\brief Enable Interrupt
AnnaBridge	145:64910690c574	1666	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	145:64910690c574	1667	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1668	\note IRQn must not be negative.
<>	129:0ab6a29f35bf	1669	*/
<>	129:0ab6a29f35bf	1670	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1671	{
AnnaBridge	145:64910690c574	1672	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1673	{
AnnaBridge	145:64910690c574	1674	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	145:64910690c574	1675	}
<>	129:0ab6a29f35bf	1676	}
<>	129:0ab6a29f35bf	1677
<>	129:0ab6a29f35bf	1678
AnnaBridge	145:64910690c574	1679	/**
AnnaBridge	145:64910690c574	1680	\brief Get Interrupt Enable status
AnnaBridge	145:64910690c574	1681	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	145:64910690c574	1682	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1683	\return 0 Interrupt is not enabled.
AnnaBridge	145:64910690c574	1684	\return 1 Interrupt is enabled.
AnnaBridge	145:64910690c574	1685	\note IRQn must not be negative.
<>	129:0ab6a29f35bf	1686	*/
AnnaBridge	145:64910690c574	1687	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1688	{
AnnaBridge	145:64910690c574	1689	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1690	{
AnnaBridge	145:64910690c574	1691	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	145:64910690c574	1692	}
AnnaBridge	145:64910690c574	1693	else
AnnaBridge	145:64910690c574	1694	{
AnnaBridge	145:64910690c574	1695	return(0U);
AnnaBridge	145:64910690c574	1696	}
<>	129:0ab6a29f35bf	1697	}
<>	129:0ab6a29f35bf	1698
<>	129:0ab6a29f35bf	1699
AnnaBridge	145:64910690c574	1700	/**
AnnaBridge	145:64910690c574	1701	\brief Disable Interrupt
AnnaBridge	145:64910690c574	1702	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	145:64910690c574	1703	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1704	\note IRQn must not be negative.
<>	129:0ab6a29f35bf	1705	*/
AnnaBridge	145:64910690c574	1706	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1707	{
AnnaBridge	145:64910690c574	1708	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1709	{
AnnaBridge	145:64910690c574	1710	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	145:64910690c574	1711	__DSB();
AnnaBridge	145:64910690c574	1712	__ISB();
AnnaBridge	145:64910690c574	1713	}
<>	129:0ab6a29f35bf	1714	}
<>	129:0ab6a29f35bf	1715
<>	129:0ab6a29f35bf	1716
AnnaBridge	145:64910690c574	1717	/**
AnnaBridge	145:64910690c574	1718	\brief Get Pending Interrupt
AnnaBridge	145:64910690c574	1719	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	145:64910690c574	1720	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1721	\return 0 Interrupt status is not pending.
AnnaBridge	145:64910690c574	1722	\return 1 Interrupt status is pending.
AnnaBridge	145:64910690c574	1723	\note IRQn must not be negative.
<>	129:0ab6a29f35bf	1724	*/
AnnaBridge	145:64910690c574	1725	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1726	{
AnnaBridge	145:64910690c574	1727	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1728	{
AnnaBridge	145:64910690c574	1729	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	145:64910690c574	1730	}
AnnaBridge	145:64910690c574	1731	else
AnnaBridge	145:64910690c574	1732	{
AnnaBridge	145:64910690c574	1733	return(0U);
AnnaBridge	145:64910690c574	1734	}
<>	129:0ab6a29f35bf	1735	}
<>	129:0ab6a29f35bf	1736
<>	129:0ab6a29f35bf	1737
AnnaBridge	145:64910690c574	1738	/**
AnnaBridge	145:64910690c574	1739	\brief Set Pending Interrupt
AnnaBridge	145:64910690c574	1740	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	145:64910690c574	1741	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1742	\note IRQn must not be negative.
<>	129:0ab6a29f35bf	1743	*/
AnnaBridge	145:64910690c574	1744	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1745	{
AnnaBridge	145:64910690c574	1746	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1747	{
AnnaBridge	145:64910690c574	1748	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	129:0ab6a29f35bf	1749	}
<>	129:0ab6a29f35bf	1750	}
<>	129:0ab6a29f35bf	1751
<>	129:0ab6a29f35bf	1752
AnnaBridge	145:64910690c574	1753	/**
AnnaBridge	145:64910690c574	1754	\brief Clear Pending Interrupt
AnnaBridge	145:64910690c574	1755	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	145:64910690c574	1756	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1757	\note IRQn must not be negative.
AnnaBridge	145:64910690c574	1758	*/
AnnaBridge	145:64910690c574	1759	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	1760	{
AnnaBridge	145:64910690c574	1761	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1762	{
AnnaBridge	145:64910690c574	1763	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	145:64910690c574	1764	}
AnnaBridge	145:64910690c574	1765	}
<>	129:0ab6a29f35bf	1766
<>	129:0ab6a29f35bf	1767
AnnaBridge	145:64910690c574	1768	/**
AnnaBridge	145:64910690c574	1769	\brief Get Active Interrupt
AnnaBridge	145:64910690c574	1770	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	145:64910690c574	1771	\param [in] IRQn Device specific interrupt number.
AnnaBridge	145:64910690c574	1772	\return 0 Interrupt status is not active.
AnnaBridge	145:64910690c574	1773	\return 1 Interrupt status is active.
AnnaBridge	145:64910690c574	1774	\note IRQn must not be negative.
AnnaBridge	145:64910690c574	1775	*/
AnnaBridge	145:64910690c574	1776	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	1777	{
AnnaBridge	145:64910690c574	1778	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1779	{
AnnaBridge	145:64910690c574	1780	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	145:64910690c574	1781	}
AnnaBridge	145:64910690c574	1782	else
AnnaBridge	145:64910690c574	1783	{
AnnaBridge	145:64910690c574	1784	return(0U);
AnnaBridge	145:64910690c574	1785	}
AnnaBridge	145:64910690c574	1786	}
AnnaBridge	145:64910690c574	1787
AnnaBridge	145:64910690c574	1788
AnnaBridge	145:64910690c574	1789	/**
AnnaBridge	145:64910690c574	1790	\brief Set Interrupt Priority
AnnaBridge	145:64910690c574	1791	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	145:64910690c574	1792	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	145:64910690c574	1793	or negative to specify a processor exception.
AnnaBridge	145:64910690c574	1794	\param [in] IRQn Interrupt number.
AnnaBridge	145:64910690c574	1795	\param [in] priority Priority to set.
AnnaBridge	145:64910690c574	1796	\note The priority cannot be set for every processor exception.
AnnaBridge	145:64910690c574	1797	*/
AnnaBridge	145:64910690c574	1798	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	145:64910690c574	1799	{
AnnaBridge	145:64910690c574	1800	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1801	{
AnnaBridge	145:64910690c574	1802	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	145:64910690c574	1803	}
AnnaBridge	145:64910690c574	1804	else
AnnaBridge	145:64910690c574	1805	{
AnnaBridge	145:64910690c574	1806	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	145:64910690c574	1807	}
AnnaBridge	145:64910690c574	1808	}
AnnaBridge	145:64910690c574	1809
AnnaBridge	145:64910690c574	1810
AnnaBridge	145:64910690c574	1811	/**
AnnaBridge	145:64910690c574	1812	\brief Get Interrupt Priority
AnnaBridge	145:64910690c574	1813	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	145:64910690c574	1814	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	145:64910690c574	1815	or negative to specify a processor exception.
AnnaBridge	145:64910690c574	1816	\param [in] IRQn Interrupt number.
AnnaBridge	145:64910690c574	1817	\return Interrupt Priority.
AnnaBridge	145:64910690c574	1818	Value is aligned automatically to the implemented priority bits of the microcontroller.
<>	129:0ab6a29f35bf	1819	*/
<>	129:0ab6a29f35bf	1820	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<>	129:0ab6a29f35bf	1821	{
<>	129:0ab6a29f35bf	1822
AnnaBridge	145:64910690c574	1823	if ((int32_t)(IRQn) >= 0)
AnnaBridge	145:64910690c574	1824	{
AnnaBridge	145:64910690c574	1825	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
<>	129:0ab6a29f35bf	1826	}
AnnaBridge	145:64910690c574	1827	else
AnnaBridge	145:64910690c574	1828	{
AnnaBridge	145:64910690c574	1829	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
<>	129:0ab6a29f35bf	1830	}
<>	129:0ab6a29f35bf	1831	}
<>	129:0ab6a29f35bf	1832
<>	129:0ab6a29f35bf	1833
AnnaBridge	145:64910690c574	1834	/**
AnnaBridge	145:64910690c574	1835	\brief Encode Priority
AnnaBridge	145:64910690c574	1836	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	145:64910690c574	1837	preemptive priority value, and subpriority value.
AnnaBridge	145:64910690c574	1838	In case of a conflict between priority grouping and available
AnnaBridge	145:64910690c574	1839	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	145:64910690c574	1840	\param [in] PriorityGroup Used priority group.
AnnaBridge	145:64910690c574	1841	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	145:64910690c574	1842	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	145:64910690c574	1843	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<>	129:0ab6a29f35bf	1844	*/
<>	129:0ab6a29f35bf	1845	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<>	129:0ab6a29f35bf	1846	{
<>	129:0ab6a29f35bf	1847	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	129:0ab6a29f35bf	1848	uint32_t PreemptPriorityBits;
<>	129:0ab6a29f35bf	1849	uint32_t SubPriorityBits;
<>	129:0ab6a29f35bf	1850
<>	129:0ab6a29f35bf	1851	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	129:0ab6a29f35bf	1852	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	129:0ab6a29f35bf	1853
<>	129:0ab6a29f35bf	1854	return (
<>	129:0ab6a29f35bf	1855	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
<>	129:0ab6a29f35bf	1856	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<>	129:0ab6a29f35bf	1857	);
<>	129:0ab6a29f35bf	1858	}
<>	129:0ab6a29f35bf	1859
<>	129:0ab6a29f35bf	1860
AnnaBridge	145:64910690c574	1861	/**
AnnaBridge	145:64910690c574	1862	\brief Decode Priority
AnnaBridge	145:64910690c574	1863	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	145:64910690c574	1864	preemptive priority value and subpriority value.
AnnaBridge	145:64910690c574	1865	In case of a conflict between priority grouping and available
AnnaBridge	145:64910690c574	1866	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	145:64910690c574	1867	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	145:64910690c574	1868	\param [in] PriorityGroup Used priority group.
AnnaBridge	145:64910690c574	1869	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	145:64910690c574	1870	\param [out] pSubPriority Subpriority value (starting from 0).
<>	129:0ab6a29f35bf	1871	*/
AnnaBridge	145:64910690c574	1872	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
<>	129:0ab6a29f35bf	1873	{
<>	129:0ab6a29f35bf	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	129:0ab6a29f35bf	1875	uint32_t PreemptPriorityBits;
<>	129:0ab6a29f35bf	1876	uint32_t SubPriorityBits;
<>	129:0ab6a29f35bf	1877
<>	129:0ab6a29f35bf	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	129:0ab6a29f35bf	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	129:0ab6a29f35bf	1880
<>	129:0ab6a29f35bf	1881	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<>	129:0ab6a29f35bf	1882	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<>	129:0ab6a29f35bf	1883	}
<>	129:0ab6a29f35bf	1884
<>	129:0ab6a29f35bf	1885
AnnaBridge	145:64910690c574	1886	/**
AnnaBridge	145:64910690c574	1887	\brief Set Interrupt Vector
AnnaBridge	145:64910690c574	1888	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	145:64910690c574	1889	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	145:64910690c574	1890	or negative to specify a processor exception.
AnnaBridge	145:64910690c574	1891	VTOR must been relocated to SRAM before.
AnnaBridge	145:64910690c574	1892	\param [in] IRQn Interrupt number
AnnaBridge	145:64910690c574	1893	\param [in] vector Address of interrupt handler function
AnnaBridge	145:64910690c574	1894	*/
AnnaBridge	145:64910690c574	1895	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	145:64910690c574	1896	{
AnnaBridge	145:64910690c574	1897	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	145:64910690c574	1898	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	145:64910690c574	1899	}
AnnaBridge	145:64910690c574	1900
<>	129:0ab6a29f35bf	1901
AnnaBridge	145:64910690c574	1902	/**
AnnaBridge	145:64910690c574	1903	\brief Get Interrupt Vector
AnnaBridge	145:64910690c574	1904	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	145:64910690c574	1905	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	145:64910690c574	1906	or negative to specify a processor exception.
AnnaBridge	145:64910690c574	1907	\param [in] IRQn Interrupt number.
AnnaBridge	145:64910690c574	1908	\return Address of interrupt handler function
AnnaBridge	145:64910690c574	1909	*/
AnnaBridge	145:64910690c574	1910	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	145:64910690c574	1911	{
AnnaBridge	145:64910690c574	1912	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	145:64910690c574	1913	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	145:64910690c574	1914	}
AnnaBridge	145:64910690c574	1915
AnnaBridge	145:64910690c574	1916
AnnaBridge	145:64910690c574	1917	/**
AnnaBridge	145:64910690c574	1918	\brief System Reset
AnnaBridge	145:64910690c574	1919	\details Initiates a system reset request to reset the MCU.
<>	129:0ab6a29f35bf	1920	*/
<>	129:0ab6a29f35bf	1921	__STATIC_INLINE void __NVIC_SystemReset(void)
<>	129:0ab6a29f35bf	1922	{
<>	129:0ab6a29f35bf	1923	__DSB(); /* Ensure all outstanding memory accesses included
<>	129:0ab6a29f35bf	1924	buffered write are completed before reset */
<>	129:0ab6a29f35bf	1925	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	129:0ab6a29f35bf	1926	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
<>	129:0ab6a29f35bf	1927	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<>	129:0ab6a29f35bf	1928	__DSB(); /* Ensure completion of memory access */
AnnaBridge	145:64910690c574	1929
AnnaBridge	145:64910690c574	1930	for(;;) /* wait until reset */
AnnaBridge	145:64910690c574	1931	{
AnnaBridge	145:64910690c574	1932	__NOP();
AnnaBridge	145:64910690c574	1933	}
<>	129:0ab6a29f35bf	1934	}
<>	129:0ab6a29f35bf	1935
<>	129:0ab6a29f35bf	1936	/@} end of CMSIS_Core_NVICFunctions /
<>	129:0ab6a29f35bf	1937
<>	129:0ab6a29f35bf	1938
AnnaBridge	145:64910690c574	1939	/* ########################## FPU functions #################################### */
AnnaBridge	145:64910690c574	1940	/**
AnnaBridge	145:64910690c574	1941	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	1942	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	145:64910690c574	1943	\brief Function that provides FPU type.
<>	129:0ab6a29f35bf	1944	@{
<>	129:0ab6a29f35bf	1945	*/
<>	129:0ab6a29f35bf	1946
AnnaBridge	145:64910690c574	1947	/**
AnnaBridge	145:64910690c574	1948	\brief get FPU type
AnnaBridge	145:64910690c574	1949	\details returns the FPU type
AnnaBridge	145:64910690c574	1950	\returns
AnnaBridge	145:64910690c574	1951	- \b 0: No FPU
AnnaBridge	145:64910690c574	1952	- \b 1: Single precision FPU
AnnaBridge	145:64910690c574	1953	- \b 2: Double + Single precision FPU
AnnaBridge	145:64910690c574	1954	*/
AnnaBridge	145:64910690c574	1955	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	145:64910690c574	1956	{
AnnaBridge	145:64910690c574	1957	uint32_t mvfr0;
<>	129:0ab6a29f35bf	1958
AnnaBridge	145:64910690c574	1959	mvfr0 = FPU->MVFR0;
AnnaBridge	145:64910690c574	1960	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	145:64910690c574	1961	{
AnnaBridge	145:64910690c574	1962	return 1U; /* Single precision FPU */
AnnaBridge	145:64910690c574	1963	}
AnnaBridge	145:64910690c574	1964	else
AnnaBridge	145:64910690c574	1965	{
AnnaBridge	145:64910690c574	1966	return 0U; /* No FPU */
AnnaBridge	145:64910690c574	1967	}
AnnaBridge	145:64910690c574	1968	}
<>	129:0ab6a29f35bf	1969
<>	129:0ab6a29f35bf	1970
AnnaBridge	145:64910690c574	1971	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	145:64910690c574	1972
AnnaBridge	145:64910690c574	1973
<>	129:0ab6a29f35bf	1974
AnnaBridge	145:64910690c574	1975	/* ################################## SysTick function ############################################ */
AnnaBridge	145:64910690c574	1976	/**
AnnaBridge	145:64910690c574	1977	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	1978	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	145:64910690c574	1979	\brief Functions that configure the System.
AnnaBridge	145:64910690c574	1980	@{
AnnaBridge	145:64910690c574	1981	*/
<>	129:0ab6a29f35bf	1982
AnnaBridge	145:64910690c574	1983	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<>	129:0ab6a29f35bf	1984
AnnaBridge	145:64910690c574	1985	/**
AnnaBridge	145:64910690c574	1986	\brief System Tick Configuration
AnnaBridge	145:64910690c574	1987	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	145:64910690c574	1988	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	145:64910690c574	1989	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	145:64910690c574	1990	\return 0 Function succeeded.
AnnaBridge	145:64910690c574	1991	\return 1 Function failed.
AnnaBridge	145:64910690c574	1992	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	145:64910690c574	1993	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	145:64910690c574	1994	must contain a vendor-specific implementation of this function.
<>	129:0ab6a29f35bf	1995	*/
<>	129:0ab6a29f35bf	1996	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<>	129:0ab6a29f35bf	1997	{
AnnaBridge	145:64910690c574	1998	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	145:64910690c574	1999	{
AnnaBridge	145:64910690c574	2000	return (1UL); /* Reload value impossible */
AnnaBridge	145:64910690c574	2001	}
<>	129:0ab6a29f35bf	2002
<>	129:0ab6a29f35bf	2003	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<>	129:0ab6a29f35bf	2004	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<>	129:0ab6a29f35bf	2005	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<>	129:0ab6a29f35bf	2006	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
<>	129:0ab6a29f35bf	2007	SysTick_CTRL_TICKINT_Msk \|
<>	129:0ab6a29f35bf	2008	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<>	129:0ab6a29f35bf	2009	return (0UL); /* Function successful */
<>	129:0ab6a29f35bf	2010	}
<>	129:0ab6a29f35bf	2011
<>	129:0ab6a29f35bf	2012	#endif
<>	129:0ab6a29f35bf	2013
<>	129:0ab6a29f35bf	2014	/@} end of CMSIS_Core_SysTickFunctions /
<>	129:0ab6a29f35bf	2015
<>	129:0ab6a29f35bf	2016
<>	129:0ab6a29f35bf	2017
<>	129:0ab6a29f35bf	2018	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	145:64910690c574	2019	/**
AnnaBridge	145:64910690c574	2020	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	2021	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	145:64910690c574	2022	\brief Functions that access the ITM debug interface.
<>	129:0ab6a29f35bf	2023	@{
<>	129:0ab6a29f35bf	2024	*/
<>	129:0ab6a29f35bf	2025
AnnaBridge	145:64910690c574	2026	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	145:64910690c574	2027	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
<>	129:0ab6a29f35bf	2028
<>	129:0ab6a29f35bf	2029
AnnaBridge	145:64910690c574	2030	/**
AnnaBridge	145:64910690c574	2031	\brief ITM Send Character
AnnaBridge	145:64910690c574	2032	\details Transmits a character via the ITM channel 0, and
AnnaBridge	145:64910690c574	2033	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	145:64910690c574	2034	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	145:64910690c574	2035	\param [in] ch Character to transmit.
AnnaBridge	145:64910690c574	2036	\returns Character to transmit.
<>	129:0ab6a29f35bf	2037	*/
<>	129:0ab6a29f35bf	2038	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<>	129:0ab6a29f35bf	2039	{
<>	129:0ab6a29f35bf	2040	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<>	129:0ab6a29f35bf	2041	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<>	129:0ab6a29f35bf	2042	{
AnnaBridge	145:64910690c574	2043	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	145:64910690c574	2044	{
AnnaBridge	145:64910690c574	2045	__NOP();
AnnaBridge	145:64910690c574	2046	}
AnnaBridge	145:64910690c574	2047	ITM->PORT[0U].u8 = (uint8_t)ch;
<>	129:0ab6a29f35bf	2048	}
<>	129:0ab6a29f35bf	2049	return (ch);
<>	129:0ab6a29f35bf	2050	}
<>	129:0ab6a29f35bf	2051
<>	129:0ab6a29f35bf	2052
AnnaBridge	145:64910690c574	2053	/**
AnnaBridge	145:64910690c574	2054	\brief ITM Receive Character
AnnaBridge	145:64910690c574	2055	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	145:64910690c574	2056	\return Received character.
AnnaBridge	145:64910690c574	2057	\return -1 No character pending.
<>	129:0ab6a29f35bf	2058	*/
AnnaBridge	145:64910690c574	2059	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	145:64910690c574	2060	{
<>	129:0ab6a29f35bf	2061	int32_t ch = -1; /* no character available */
<>	129:0ab6a29f35bf	2062
AnnaBridge	145:64910690c574	2063	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	145:64910690c574	2064	{
<>	129:0ab6a29f35bf	2065	ch = ITM_RxBuffer;
<>	129:0ab6a29f35bf	2066	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<>	129:0ab6a29f35bf	2067	}
<>	129:0ab6a29f35bf	2068
<>	129:0ab6a29f35bf	2069	return (ch);
<>	129:0ab6a29f35bf	2070	}
<>	129:0ab6a29f35bf	2071
<>	129:0ab6a29f35bf	2072
AnnaBridge	145:64910690c574	2073	/**
AnnaBridge	145:64910690c574	2074	\brief ITM Check Character
AnnaBridge	145:64910690c574	2075	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	145:64910690c574	2076	\return 0 No character available.
AnnaBridge	145:64910690c574	2077	\return 1 Character available.
<>	129:0ab6a29f35bf	2078	*/
AnnaBridge	145:64910690c574	2079	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	145:64910690c574	2080	{
<>	129:0ab6a29f35bf	2081
AnnaBridge	145:64910690c574	2082	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	145:64910690c574	2083	{
AnnaBridge	145:64910690c574	2084	return (0); /* no character available */
AnnaBridge	145:64910690c574	2085	}
AnnaBridge	145:64910690c574	2086	else
AnnaBridge	145:64910690c574	2087	{
AnnaBridge	145:64910690c574	2088	return (1); /* character available */
<>	129:0ab6a29f35bf	2089	}
<>	129:0ab6a29f35bf	2090	}
<>	129:0ab6a29f35bf	2091
<>	129:0ab6a29f35bf	2092	/@} end of CMSIS_core_DebugFunctions /
<>	129:0ab6a29f35bf	2093
<>	129:0ab6a29f35bf	2094
<>	129:0ab6a29f35bf	2095
<>	129:0ab6a29f35bf	2096
<>	129:0ab6a29f35bf	2097	#ifdef __cplusplus
<>	129:0ab6a29f35bf	2098	}
<>	129:0ab6a29f35bf	2099	#endif
<>	129:0ab6a29f35bf	2100
<>	129:0ab6a29f35bf	2101	#endif /* __CORE_CM4_H_DEPENDANT */
<>	129:0ab6a29f35bf	2102
<>	129:0ab6a29f35bf	2103	#endif /* __CMSIS_GENERIC */