mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC11U35_401/core_cm3.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 74:a842253909c9 1 /**************************************************************************//**
bogdanm 74:a842253909c9 2 * @file core_cm3.h
bogdanm 74:a842253909c9 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
bogdanm 74:a842253909c9 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
bogdanm 74:a842253909c9 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
bogdanm 74:a842253909c9 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
bogdanm 74:a842253909c9 29 #endif
bogdanm 74:a842253909c9 30
Kojto 110:165afa46840b 31 #ifndef __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 32 #define __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
bogdanm 74:a842253909c9 36 #ifdef __cplusplus
bogdanm 74:a842253909c9 37 extern "C" {
bogdanm 74:a842253909c9 38 #endif
bogdanm 74:a842253909c9 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 74:a842253909c9 42 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 74:a842253909c9 43
bogdanm 74:a842253909c9 44 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 74:a842253909c9 45 Function definitions in header files are used to allow 'inlining'.
bogdanm 74:a842253909c9 46
bogdanm 74:a842253909c9 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 74:a842253909c9 48 Unions are used for effective representation of core registers.
bogdanm 74:a842253909c9 49
bogdanm 74:a842253909c9 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 74:a842253909c9 51 Function-like macros are used to allow more efficient code.
bogdanm 74:a842253909c9 52 */
bogdanm 74:a842253909c9 53
bogdanm 74:a842253909c9 54
bogdanm 74:a842253909c9 55 /*******************************************************************************
bogdanm 74:a842253909c9 56 * CMSIS definitions
bogdanm 74:a842253909c9 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup Cortex_M3
bogdanm 74:a842253909c9 60 @{
bogdanm 74:a842253909c9 61 */
bogdanm 74:a842253909c9 62
bogdanm 74:a842253909c9 63 /* CMSIS CM3 definitions */
AnnaBridge 145:64910690c574 64 #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 110:165afa46840b 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_M (3U) /*!< Cortex-M Core */
bogdanm 74:a842253909c9 70
Kojto 110:165afa46840b 71 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 72 This core does not support an FPU at all
bogdanm 74:a842253909c9 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
bogdanm 74:a842253909c9 75
bogdanm 74:a842253909c9 76 #if defined ( __CC_ARM )
bogdanm 74:a842253909c9 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 84 #endif
bogdanm 74:a842253909c9 85
Kojto 110:165afa46840b 86 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 89 #endif
Kojto 110:165afa46840b 90
bogdanm 74:a842253909c9 91 #elif defined ( __ICCARM__ )
bogdanm 74:a842253909c9 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 94 #endif
bogdanm 74:a842253909c9 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 99 #endif
bogdanm 74:a842253909c9 100
Kojto 110:165afa46840b 101 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 102 #if defined __FPU_VFP__
Kojto 110:165afa46840b 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 104 #endif
bogdanm 74:a842253909c9 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
bogdanm 74:a842253909c9 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 109 #endif
AnnaBridge 145:64910690c574 110
bogdanm 74:a842253909c9 111 #endif
bogdanm 74:a842253909c9 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
bogdanm 74:a842253909c9 115
Kojto 110:165afa46840b 116 #ifdef __cplusplus
Kojto 110:165afa46840b 117 }
Kojto 110:165afa46840b 118 #endif
Kojto 110:165afa46840b 119
bogdanm 74:a842253909c9 120 #endif /* __CORE_CM3_H_GENERIC */
bogdanm 74:a842253909c9 121
bogdanm 74:a842253909c9 122 #ifndef __CMSIS_GENERIC
bogdanm 74:a842253909c9 123
bogdanm 74:a842253909c9 124 #ifndef __CORE_CM3_H_DEPENDANT
bogdanm 74:a842253909c9 125 #define __CORE_CM3_H_DEPENDANT
bogdanm 74:a842253909c9 126
Kojto 110:165afa46840b 127 #ifdef __cplusplus
Kojto 110:165afa46840b 128 extern "C" {
Kojto 110:165afa46840b 129 #endif
Kojto 110:165afa46840b 130
bogdanm 74:a842253909c9 131 /* check device defines and use defaults */
bogdanm 74:a842253909c9 132 #if defined __CHECK_DEVICE_DEFINES
bogdanm 74:a842253909c9 133 #ifndef __CM3_REV
AnnaBridge 145:64910690c574 134 #define __CM3_REV 0x0200U
bogdanm 74:a842253909c9 135 #warning "__CM3_REV not defined in device header file; using default!"
bogdanm 74:a842253909c9 136 #endif
bogdanm 74:a842253909c9 137
bogdanm 74:a842253909c9 138 #ifndef __MPU_PRESENT
AnnaBridge 145:64910690c574 139 #define __MPU_PRESENT 0U
bogdanm 74:a842253909c9 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 74:a842253909c9 141 #endif
bogdanm 74:a842253909c9 142
bogdanm 74:a842253909c9 143 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 144 #define __NVIC_PRIO_BITS 3U
bogdanm 74:a842253909c9 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 74:a842253909c9 146 #endif
bogdanm 74:a842253909c9 147
bogdanm 74:a842253909c9 148 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 149 #define __Vendor_SysTickConfig 0U
bogdanm 74:a842253909c9 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 74:a842253909c9 151 #endif
bogdanm 74:a842253909c9 152 #endif
bogdanm 74:a842253909c9 153
bogdanm 74:a842253909c9 154 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 74:a842253909c9 155 /**
bogdanm 74:a842253909c9 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 74:a842253909c9 157
bogdanm 74:a842253909c9 158 <strong>IO Type Qualifiers</strong> are used
bogdanm 74:a842253909c9 159 \li to specify the access to peripheral variables.
bogdanm 74:a842253909c9 160 \li for automatic generation of peripheral register debug information.
bogdanm 74:a842253909c9 161 */
bogdanm 74:a842253909c9 162 #ifdef __cplusplus
AnnaBridge 145:64910690c574 163 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 164 #else
AnnaBridge 145:64910690c574 165 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 166 #endif
AnnaBridge 145:64910690c574 167 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 168 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 74:a842253909c9 169
AnnaBridge 145:64910690c574 170 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 128:9bcdf88f62b0 174
bogdanm 74:a842253909c9 175 /*@} end of group Cortex_M3 */
bogdanm 74:a842253909c9 176
bogdanm 74:a842253909c9 177
bogdanm 74:a842253909c9 178
bogdanm 74:a842253909c9 179 /*******************************************************************************
bogdanm 74:a842253909c9 180 * Register Abstraction
bogdanm 74:a842253909c9 181 Core Register contain:
bogdanm 74:a842253909c9 182 - Core Register
bogdanm 74:a842253909c9 183 - Core NVIC Register
bogdanm 74:a842253909c9 184 - Core SCB Register
bogdanm 74:a842253909c9 185 - Core SysTick Register
bogdanm 74:a842253909c9 186 - Core Debug Register
bogdanm 74:a842253909c9 187 - Core MPU Register
bogdanm 74:a842253909c9 188 ******************************************************************************/
AnnaBridge 145:64910690c574 189 /**
AnnaBridge 145:64910690c574 190 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 191 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 74:a842253909c9 192 */
bogdanm 74:a842253909c9 193
AnnaBridge 145:64910690c574 194 /**
AnnaBridge 145:64910690c574 195 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 196 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 197 \brief Core Register type definitions.
bogdanm 74:a842253909c9 198 @{
bogdanm 74:a842253909c9 199 */
bogdanm 74:a842253909c9 200
AnnaBridge 145:64910690c574 201 /**
AnnaBridge 145:64910690c574 202 \brief Union type to access the Application Program Status Register (APSR).
bogdanm 74:a842253909c9 203 */
bogdanm 74:a842253909c9 204 typedef union
bogdanm 74:a842253909c9 205 {
bogdanm 74:a842253909c9 206 struct
bogdanm 74:a842253909c9 207 {
AnnaBridge 145:64910690c574 208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 145:64910690c574 209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 145:64910690c574 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 214 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 215 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 216 } APSR_Type;
bogdanm 74:a842253909c9 217
Kojto 110:165afa46840b 218 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
Kojto 110:165afa46840b 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 221
AnnaBridge 145:64910690c574 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Kojto 110:165afa46840b 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 224
AnnaBridge 145:64910690c574 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
Kojto 110:165afa46840b 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 227
AnnaBridge 145:64910690c574 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
Kojto 110:165afa46840b 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 230
AnnaBridge 145:64910690c574 231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
Kojto 110:165afa46840b 232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 110:165afa46840b 233
bogdanm 74:a842253909c9 234
AnnaBridge 145:64910690c574 235 /**
AnnaBridge 145:64910690c574 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 74:a842253909c9 237 */
bogdanm 74:a842253909c9 238 typedef union
bogdanm 74:a842253909c9 239 {
bogdanm 74:a842253909c9 240 struct
bogdanm 74:a842253909c9 241 {
AnnaBridge 145:64910690c574 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 244 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 245 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 246 } IPSR_Type;
bogdanm 74:a842253909c9 247
Kojto 110:165afa46840b 248 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 251
bogdanm 74:a842253909c9 252
AnnaBridge 145:64910690c574 253 /**
AnnaBridge 145:64910690c574 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 74:a842253909c9 255 */
bogdanm 74:a842253909c9 256 typedef union
bogdanm 74:a842253909c9 257 {
bogdanm 74:a842253909c9 258 struct
bogdanm 74:a842253909c9 259 {
AnnaBridge 145:64910690c574 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 145:64910690c574 262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 145:64910690c574 263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
AnnaBridge 145:64910690c574 264 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 145:64910690c574 265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 145:64910690c574 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 145:64910690c574 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 271 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 272 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 273 } xPSR_Type;
bogdanm 74:a842253909c9 274
Kojto 110:165afa46840b 275 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Kojto 110:165afa46840b 277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 278
AnnaBridge 145:64910690c574 279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Kojto 110:165afa46840b 280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 281
AnnaBridge 145:64910690c574 282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Kojto 110:165afa46840b 283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 284
AnnaBridge 145:64910690c574 285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Kojto 110:165afa46840b 286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 287
AnnaBridge 145:64910690c574 288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
Kojto 110:165afa46840b 289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 110:165afa46840b 290
AnnaBridge 145:64910690c574 291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 145:64910690c574 292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
Kojto 110:165afa46840b 293
AnnaBridge 145:64910690c574 294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Kojto 110:165afa46840b 295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 296
AnnaBridge 145:64910690c574 297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 145:64910690c574 298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 145:64910690c574 299
AnnaBridge 145:64910690c574 300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 302
bogdanm 74:a842253909c9 303
AnnaBridge 145:64910690c574 304 /**
AnnaBridge 145:64910690c574 305 \brief Union type to access the Control Registers (CONTROL).
bogdanm 74:a842253909c9 306 */
bogdanm 74:a842253909c9 307 typedef union
bogdanm 74:a842253909c9 308 {
bogdanm 74:a842253909c9 309 struct
bogdanm 74:a842253909c9 310 {
bogdanm 74:a842253909c9 311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 145:64910690c574 312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 145:64910690c574 313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 314 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 315 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 316 } CONTROL_Type;
bogdanm 74:a842253909c9 317
Kojto 110:165afa46840b 318 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 321
AnnaBridge 145:64910690c574 322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 324
bogdanm 74:a842253909c9 325 /*@} end of group CMSIS_CORE */
bogdanm 74:a842253909c9 326
bogdanm 74:a842253909c9 327
AnnaBridge 145:64910690c574 328 /**
AnnaBridge 145:64910690c574 329 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 331 \brief Type definitions for the NVIC Registers
bogdanm 74:a842253909c9 332 @{
bogdanm 74:a842253909c9 333 */
bogdanm 74:a842253909c9 334
AnnaBridge 145:64910690c574 335 /**
AnnaBridge 145:64910690c574 336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 74:a842253909c9 337 */
bogdanm 74:a842253909c9 338 typedef struct
bogdanm 74:a842253909c9 339 {
AnnaBridge 145:64910690c574 340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 341 uint32_t RESERVED0[24U];
AnnaBridge 145:64910690c574 342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 343 uint32_t RSERVED1[24U];
AnnaBridge 145:64910690c574 344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 345 uint32_t RESERVED2[24U];
AnnaBridge 145:64910690c574 346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 347 uint32_t RESERVED3[24U];
AnnaBridge 145:64910690c574 348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 145:64910690c574 349 uint32_t RESERVED4[56U];
AnnaBridge 145:64910690c574 350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 145:64910690c574 351 uint32_t RESERVED5[644U];
AnnaBridge 145:64910690c574 352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 74:a842253909c9 353 } NVIC_Type;
bogdanm 74:a842253909c9 354
bogdanm 74:a842253909c9 355 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 145:64910690c574 356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
Kojto 110:165afa46840b 357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
bogdanm 74:a842253909c9 358
bogdanm 74:a842253909c9 359 /*@} end of group CMSIS_NVIC */
bogdanm 74:a842253909c9 360
bogdanm 74:a842253909c9 361
AnnaBridge 145:64910690c574 362 /**
AnnaBridge 145:64910690c574 363 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 364 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 365 \brief Type definitions for the System Control Block Registers
bogdanm 74:a842253909c9 366 @{
bogdanm 74:a842253909c9 367 */
bogdanm 74:a842253909c9 368
AnnaBridge 145:64910690c574 369 /**
AnnaBridge 145:64910690c574 370 \brief Structure type to access the System Control Block (SCB).
bogdanm 74:a842253909c9 371 */
bogdanm 74:a842253909c9 372 typedef struct
bogdanm 74:a842253909c9 373 {
AnnaBridge 145:64910690c574 374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 145:64910690c574 377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 145:64910690c574 381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 145:64910690c574 382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 145:64910690c574 383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 145:64910690c574 384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 145:64910690c574 385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 145:64910690c574 386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 145:64910690c574 387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 145:64910690c574 388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 145:64910690c574 389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 145:64910690c574 390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 145:64910690c574 391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 145:64910690c574 392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 145:64910690c574 393 uint32_t RESERVED0[5U];
AnnaBridge 145:64910690c574 394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 74:a842253909c9 395 } SCB_Type;
bogdanm 74:a842253909c9 396
bogdanm 74:a842253909c9 397 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 398 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 74:a842253909c9 399 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 74:a842253909c9 400
AnnaBridge 145:64910690c574 401 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
bogdanm 74:a842253909c9 402 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 74:a842253909c9 403
AnnaBridge 145:64910690c574 404 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 74:a842253909c9 405 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 74:a842253909c9 406
AnnaBridge 145:64910690c574 407 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
bogdanm 74:a842253909c9 408 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 74:a842253909c9 409
AnnaBridge 145:64910690c574 410 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 411 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 74:a842253909c9 412
bogdanm 74:a842253909c9 413 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 414 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 74:a842253909c9 415 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 74:a842253909c9 416
AnnaBridge 145:64910690c574 417 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
bogdanm 74:a842253909c9 418 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 74:a842253909c9 419
AnnaBridge 145:64910690c574 420 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 74:a842253909c9 421 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 74:a842253909c9 422
AnnaBridge 145:64910690c574 423 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
bogdanm 74:a842253909c9 424 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 74:a842253909c9 425
AnnaBridge 145:64910690c574 426 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 74:a842253909c9 427 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 74:a842253909c9 428
AnnaBridge 145:64910690c574 429 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 74:a842253909c9 430 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 74:a842253909c9 431
AnnaBridge 145:64910690c574 432 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
bogdanm 74:a842253909c9 433 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 74:a842253909c9 434
AnnaBridge 145:64910690c574 435 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
bogdanm 74:a842253909c9 436 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 74:a842253909c9 437
AnnaBridge 145:64910690c574 438 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
bogdanm 74:a842253909c9 439 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 74:a842253909c9 440
AnnaBridge 145:64910690c574 441 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 442 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 74:a842253909c9 443
bogdanm 74:a842253909c9 444 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 145:64910690c574 445 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
AnnaBridge 145:64910690c574 446 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
bogdanm 74:a842253909c9 447 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
bogdanm 74:a842253909c9 448
AnnaBridge 145:64910690c574 449 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
bogdanm 74:a842253909c9 450 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 74:a842253909c9 451 #else
AnnaBridge 145:64910690c574 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
bogdanm 74:a842253909c9 453 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 74:a842253909c9 454 #endif
bogdanm 74:a842253909c9 455
bogdanm 74:a842253909c9 456 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 457 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
bogdanm 74:a842253909c9 458 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 74:a842253909c9 459
AnnaBridge 145:64910690c574 460 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 74:a842253909c9 461 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 74:a842253909c9 462
AnnaBridge 145:64910690c574 463 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 74:a842253909c9 464 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 74:a842253909c9 465
AnnaBridge 145:64910690c574 466 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 74:a842253909c9 467 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 74:a842253909c9 468
AnnaBridge 145:64910690c574 469 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 74:a842253909c9 470 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 74:a842253909c9 471
AnnaBridge 145:64910690c574 472 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 74:a842253909c9 473 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 74:a842253909c9 474
AnnaBridge 145:64910690c574 475 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
Kojto 110:165afa46840b 476 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 74:a842253909c9 477
bogdanm 74:a842253909c9 478 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 479 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
bogdanm 74:a842253909c9 480 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 74:a842253909c9 481
AnnaBridge 145:64910690c574 482 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 74:a842253909c9 483 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 74:a842253909c9 484
AnnaBridge 145:64910690c574 485 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 74:a842253909c9 486 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 74:a842253909c9 487
bogdanm 74:a842253909c9 488 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 489 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
bogdanm 74:a842253909c9 490 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 74:a842253909c9 491
AnnaBridge 145:64910690c574 492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 74:a842253909c9 493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 74:a842253909c9 494
AnnaBridge 145:64910690c574 495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 74:a842253909c9 496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 74:a842253909c9 497
AnnaBridge 145:64910690c574 498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 74:a842253909c9 499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 74:a842253909c9 500
AnnaBridge 145:64910690c574 501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
bogdanm 74:a842253909c9 502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 74:a842253909c9 503
AnnaBridge 145:64910690c574 504 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 110:165afa46840b 505 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 74:a842253909c9 506
bogdanm 74:a842253909c9 507 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 508 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 74:a842253909c9 509 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 74:a842253909c9 510
AnnaBridge 145:64910690c574 511 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 74:a842253909c9 512 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 74:a842253909c9 513
AnnaBridge 145:64910690c574 514 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 74:a842253909c9 515 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 74:a842253909c9 516
AnnaBridge 145:64910690c574 517 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 74:a842253909c9 518 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 74:a842253909c9 519
AnnaBridge 145:64910690c574 520 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 74:a842253909c9 521 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 74:a842253909c9 522
AnnaBridge 145:64910690c574 523 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 74:a842253909c9 524 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 74:a842253909c9 525
AnnaBridge 145:64910690c574 526 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 74:a842253909c9 527 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 74:a842253909c9 528
AnnaBridge 145:64910690c574 529 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 74:a842253909c9 530 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 74:a842253909c9 531
AnnaBridge 145:64910690c574 532 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 74:a842253909c9 533 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 74:a842253909c9 534
AnnaBridge 145:64910690c574 535 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
bogdanm 74:a842253909c9 536 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 74:a842253909c9 537
AnnaBridge 145:64910690c574 538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 74:a842253909c9 539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 74:a842253909c9 540
AnnaBridge 145:64910690c574 541 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 74:a842253909c9 542 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 74:a842253909c9 543
AnnaBridge 145:64910690c574 544 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 74:a842253909c9 545 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 74:a842253909c9 546
AnnaBridge 145:64910690c574 547 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 110:165afa46840b 548 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 74:a842253909c9 549
AnnaBridge 145:64910690c574 550 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 145:64910690c574 551 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 74:a842253909c9 552 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 74:a842253909c9 553
AnnaBridge 145:64910690c574 554 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 74:a842253909c9 555 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 74:a842253909c9 556
AnnaBridge 145:64910690c574 557 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 110:165afa46840b 558 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 74:a842253909c9 559
AnnaBridge 145:64910690c574 560 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 145:64910690c574 561 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 145:64910690c574 562 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 145:64910690c574 563
AnnaBridge 145:64910690c574 564 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 145:64910690c574 565 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 145:64910690c574 566
AnnaBridge 145:64910690c574 567 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 145:64910690c574 568 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 145:64910690c574 569
AnnaBridge 145:64910690c574 570 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 145:64910690c574 571 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 145:64910690c574 572
AnnaBridge 145:64910690c574 573 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 145:64910690c574 574 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 145:64910690c574 575
AnnaBridge 145:64910690c574 576 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 145:64910690c574 577 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 145:64910690c574 578 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 145:64910690c574 579
AnnaBridge 145:64910690c574 580 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 145:64910690c574 581 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 145:64910690c574 582
AnnaBridge 145:64910690c574 583 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 145:64910690c574 584 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 145:64910690c574 585
AnnaBridge 145:64910690c574 586 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 145:64910690c574 587 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 145:64910690c574 588
AnnaBridge 145:64910690c574 589 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 145:64910690c574 590 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 145:64910690c574 591
AnnaBridge 145:64910690c574 592 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 145:64910690c574 593 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 145:64910690c574 594
AnnaBridge 145:64910690c574 595 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 145:64910690c574 596 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 145:64910690c574 597 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 145:64910690c574 598
AnnaBridge 145:64910690c574 599 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 145:64910690c574 600 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 145:64910690c574 601
AnnaBridge 145:64910690c574 602 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 145:64910690c574 603 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 145:64910690c574 604
AnnaBridge 145:64910690c574 605 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 145:64910690c574 606 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 145:64910690c574 607
AnnaBridge 145:64910690c574 608 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 145:64910690c574 609 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 145:64910690c574 610
AnnaBridge 145:64910690c574 611 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 145:64910690c574 612 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 145:64910690c574 613
AnnaBridge 145:64910690c574 614 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 145:64910690c574 615 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 74:a842253909c9 616 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 74:a842253909c9 617
AnnaBridge 145:64910690c574 618 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
bogdanm 74:a842253909c9 619 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 74:a842253909c9 620
AnnaBridge 145:64910690c574 621 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
bogdanm 74:a842253909c9 622 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 74:a842253909c9 623
bogdanm 74:a842253909c9 624 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 145:64910690c574 625 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
bogdanm 74:a842253909c9 626 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 74:a842253909c9 627
AnnaBridge 145:64910690c574 628 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
bogdanm 74:a842253909c9 629 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 74:a842253909c9 630
AnnaBridge 145:64910690c574 631 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
bogdanm 74:a842253909c9 632 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 74:a842253909c9 633
AnnaBridge 145:64910690c574 634 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
bogdanm 74:a842253909c9 635 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 74:a842253909c9 636
AnnaBridge 145:64910690c574 637 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
Kojto 110:165afa46840b 638 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
bogdanm 74:a842253909c9 639
bogdanm 74:a842253909c9 640 /*@} end of group CMSIS_SCB */
bogdanm 74:a842253909c9 641
bogdanm 74:a842253909c9 642
AnnaBridge 145:64910690c574 643 /**
AnnaBridge 145:64910690c574 644 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 645 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 145:64910690c574 646 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 74:a842253909c9 647 @{
bogdanm 74:a842253909c9 648 */
bogdanm 74:a842253909c9 649
AnnaBridge 145:64910690c574 650 /**
AnnaBridge 145:64910690c574 651 \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 74:a842253909c9 652 */
bogdanm 74:a842253909c9 653 typedef struct
bogdanm 74:a842253909c9 654 {
AnnaBridge 145:64910690c574 655 uint32_t RESERVED0[1U];
AnnaBridge 145:64910690c574 656 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 145:64910690c574 657 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
AnnaBridge 145:64910690c574 658 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 74:a842253909c9 659 #else
AnnaBridge 145:64910690c574 660 uint32_t RESERVED1[1U];
bogdanm 74:a842253909c9 661 #endif
bogdanm 74:a842253909c9 662 } SCnSCB_Type;
bogdanm 74:a842253909c9 663
bogdanm 74:a842253909c9 664 /* Interrupt Controller Type Register Definitions */
AnnaBridge 145:64910690c574 665 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
Kojto 110:165afa46840b 666 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
bogdanm 74:a842253909c9 667
bogdanm 74:a842253909c9 668 /* Auxiliary Control Register Definitions */
bogdanm 74:a842253909c9 669
AnnaBridge 145:64910690c574 670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
bogdanm 74:a842253909c9 671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 74:a842253909c9 672
AnnaBridge 145:64910690c574 673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
bogdanm 74:a842253909c9 674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 74:a842253909c9 675
AnnaBridge 145:64910690c574 676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Kojto 110:165afa46840b 677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 74:a842253909c9 678
bogdanm 74:a842253909c9 679 /*@} end of group CMSIS_SCnotSCB */
bogdanm 74:a842253909c9 680
bogdanm 74:a842253909c9 681
AnnaBridge 145:64910690c574 682 /**
AnnaBridge 145:64910690c574 683 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 684 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 685 \brief Type definitions for the System Timer Registers.
bogdanm 74:a842253909c9 686 @{
bogdanm 74:a842253909c9 687 */
bogdanm 74:a842253909c9 688
AnnaBridge 145:64910690c574 689 /**
AnnaBridge 145:64910690c574 690 \brief Structure type to access the System Timer (SysTick).
bogdanm 74:a842253909c9 691 */
bogdanm 74:a842253909c9 692 typedef struct
bogdanm 74:a842253909c9 693 {
AnnaBridge 145:64910690c574 694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 74:a842253909c9 698 } SysTick_Type;
bogdanm 74:a842253909c9 699
bogdanm 74:a842253909c9 700 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 74:a842253909c9 702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 74:a842253909c9 703
AnnaBridge 145:64910690c574 704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 74:a842253909c9 705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 74:a842253909c9 706
AnnaBridge 145:64910690c574 707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
bogdanm 74:a842253909c9 708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 74:a842253909c9 709
AnnaBridge 145:64910690c574 710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 712
bogdanm 74:a842253909c9 713 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 74:a842253909c9 716
bogdanm 74:a842253909c9 717 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 74:a842253909c9 720
bogdanm 74:a842253909c9 721 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
bogdanm 74:a842253909c9 723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 74:a842253909c9 724
AnnaBridge 145:64910690c574 725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
bogdanm 74:a842253909c9 726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 74:a842253909c9 727
AnnaBridge 145:64910690c574 728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 74:a842253909c9 730
bogdanm 74:a842253909c9 731 /*@} end of group CMSIS_SysTick */
bogdanm 74:a842253909c9 732
bogdanm 74:a842253909c9 733
AnnaBridge 145:64910690c574 734 /**
AnnaBridge 145:64910690c574 735 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 145:64910690c574 737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 74:a842253909c9 738 @{
bogdanm 74:a842253909c9 739 */
bogdanm 74:a842253909c9 740
AnnaBridge 145:64910690c574 741 /**
AnnaBridge 145:64910690c574 742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 74:a842253909c9 743 */
bogdanm 74:a842253909c9 744 typedef struct
bogdanm 74:a842253909c9 745 {
AnnaBridge 145:64910690c574 746 __OM union
bogdanm 74:a842253909c9 747 {
AnnaBridge 145:64910690c574 748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 145:64910690c574 749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 145:64910690c574 750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 145:64910690c574 751 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 145:64910690c574 752 uint32_t RESERVED0[864U];
AnnaBridge 145:64910690c574 753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 145:64910690c574 754 uint32_t RESERVED1[15U];
AnnaBridge 145:64910690c574 755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 145:64910690c574 756 uint32_t RESERVED2[15U];
AnnaBridge 145:64910690c574 757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 145:64910690c574 758 uint32_t RESERVED3[29U];
AnnaBridge 145:64910690c574 759 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 145:64910690c574 760 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 145:64910690c574 761 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 145:64910690c574 762 uint32_t RESERVED4[43U];
AnnaBridge 145:64910690c574 763 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 145:64910690c574 764 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 145:64910690c574 765 uint32_t RESERVED5[6U];
AnnaBridge 145:64910690c574 766 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 145:64910690c574 767 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 145:64910690c574 768 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 145:64910690c574 769 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 145:64910690c574 770 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 145:64910690c574 771 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 145:64910690c574 772 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 145:64910690c574 773 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 145:64910690c574 774 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 145:64910690c574 775 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 145:64910690c574 776 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 145:64910690c574 777 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 74:a842253909c9 778 } ITM_Type;
bogdanm 74:a842253909c9 779
bogdanm 74:a842253909c9 780 /* ITM Trace Privilege Register Definitions */
AnnaBridge 145:64910690c574 781 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
Kojto 110:165afa46840b 782 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 74:a842253909c9 783
bogdanm 74:a842253909c9 784 /* ITM Trace Control Register Definitions */
AnnaBridge 145:64910690c574 785 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
bogdanm 74:a842253909c9 786 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 74:a842253909c9 787
AnnaBridge 145:64910690c574 788 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
bogdanm 74:a842253909c9 789 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 74:a842253909c9 790
AnnaBridge 145:64910690c574 791 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 74:a842253909c9 792 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 74:a842253909c9 793
AnnaBridge 145:64910690c574 794 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
bogdanm 74:a842253909c9 795 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 74:a842253909c9 796
AnnaBridge 145:64910690c574 797 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
bogdanm 74:a842253909c9 798 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 74:a842253909c9 799
AnnaBridge 145:64910690c574 800 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
bogdanm 74:a842253909c9 801 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 74:a842253909c9 802
AnnaBridge 145:64910690c574 803 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
bogdanm 74:a842253909c9 804 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 74:a842253909c9 805
AnnaBridge 145:64910690c574 806 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
bogdanm 74:a842253909c9 807 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 74:a842253909c9 808
AnnaBridge 145:64910690c574 809 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
Kojto 110:165afa46840b 810 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 74:a842253909c9 811
bogdanm 74:a842253909c9 812 /* ITM Integration Write Register Definitions */
AnnaBridge 145:64910690c574 813 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
Kojto 110:165afa46840b 814 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 74:a842253909c9 815
bogdanm 74:a842253909c9 816 /* ITM Integration Read Register Definitions */
AnnaBridge 145:64910690c574 817 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
Kojto 110:165afa46840b 818 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
bogdanm 74:a842253909c9 819
bogdanm 74:a842253909c9 820 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 145:64910690c574 821 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
Kojto 110:165afa46840b 822 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 74:a842253909c9 823
bogdanm 74:a842253909c9 824 /* ITM Lock Status Register Definitions */
AnnaBridge 145:64910690c574 825 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
bogdanm 74:a842253909c9 826 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 74:a842253909c9 827
AnnaBridge 145:64910690c574 828 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
bogdanm 74:a842253909c9 829 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 74:a842253909c9 830
AnnaBridge 145:64910690c574 831 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
Kojto 110:165afa46840b 832 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
bogdanm 74:a842253909c9 833
bogdanm 74:a842253909c9 834 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 74:a842253909c9 835
bogdanm 74:a842253909c9 836
AnnaBridge 145:64910690c574 837 /**
AnnaBridge 145:64910690c574 838 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 839 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 145:64910690c574 840 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 74:a842253909c9 841 @{
bogdanm 74:a842253909c9 842 */
bogdanm 74:a842253909c9 843
AnnaBridge 145:64910690c574 844 /**
AnnaBridge 145:64910690c574 845 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 74:a842253909c9 846 */
bogdanm 74:a842253909c9 847 typedef struct
bogdanm 74:a842253909c9 848 {
AnnaBridge 145:64910690c574 849 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 145:64910690c574 850 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 145:64910690c574 851 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 145:64910690c574 852 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 145:64910690c574 853 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 145:64910690c574 854 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 145:64910690c574 855 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 145:64910690c574 856 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 145:64910690c574 857 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 145:64910690c574 858 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 145:64910690c574 859 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 145:64910690c574 860 uint32_t RESERVED0[1U];
AnnaBridge 145:64910690c574 861 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 145:64910690c574 862 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 145:64910690c574 863 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 145:64910690c574 864 uint32_t RESERVED1[1U];
AnnaBridge 145:64910690c574 865 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 145:64910690c574 866 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 145:64910690c574 867 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 145:64910690c574 868 uint32_t RESERVED2[1U];
AnnaBridge 145:64910690c574 869 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 145:64910690c574 870 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 145:64910690c574 871 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 74:a842253909c9 872 } DWT_Type;
bogdanm 74:a842253909c9 873
bogdanm 74:a842253909c9 874 /* DWT Control Register Definitions */
AnnaBridge 145:64910690c574 875 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
bogdanm 74:a842253909c9 876 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 74:a842253909c9 877
AnnaBridge 145:64910690c574 878 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 74:a842253909c9 879 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 74:a842253909c9 880
AnnaBridge 145:64910690c574 881 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 74:a842253909c9 882 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 74:a842253909c9 883
AnnaBridge 145:64910690c574 884 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 74:a842253909c9 885 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 74:a842253909c9 886
AnnaBridge 145:64910690c574 887 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 74:a842253909c9 888 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 74:a842253909c9 889
AnnaBridge 145:64910690c574 890 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 74:a842253909c9 891 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 74:a842253909c9 892
AnnaBridge 145:64910690c574 893 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 74:a842253909c9 894 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 74:a842253909c9 895
AnnaBridge 145:64910690c574 896 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 74:a842253909c9 897 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 74:a842253909c9 898
AnnaBridge 145:64910690c574 899 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 74:a842253909c9 900 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 74:a842253909c9 901
AnnaBridge 145:64910690c574 902 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 74:a842253909c9 903 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 74:a842253909c9 904
AnnaBridge 145:64910690c574 905 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 74:a842253909c9 906 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 74:a842253909c9 907
AnnaBridge 145:64910690c574 908 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 74:a842253909c9 909 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 74:a842253909c9 910
AnnaBridge 145:64910690c574 911 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 74:a842253909c9 912 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 74:a842253909c9 913
AnnaBridge 145:64910690c574 914 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
bogdanm 74:a842253909c9 915 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 74:a842253909c9 916
AnnaBridge 145:64910690c574 917 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
bogdanm 74:a842253909c9 918 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 74:a842253909c9 919
AnnaBridge 145:64910690c574 920 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
bogdanm 74:a842253909c9 921 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 74:a842253909c9 922
AnnaBridge 145:64910690c574 923 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
bogdanm 74:a842253909c9 924 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 74:a842253909c9 925
AnnaBridge 145:64910690c574 926 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
Kojto 110:165afa46840b 927 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 74:a842253909c9 928
bogdanm 74:a842253909c9 929 /* DWT CPI Count Register Definitions */
AnnaBridge 145:64910690c574 930 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
Kojto 110:165afa46840b 931 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 74:a842253909c9 932
bogdanm 74:a842253909c9 933 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 145:64910690c574 934 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
Kojto 110:165afa46840b 935 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 74:a842253909c9 936
bogdanm 74:a842253909c9 937 /* DWT Sleep Count Register Definitions */
AnnaBridge 145:64910690c574 938 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 110:165afa46840b 939 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 74:a842253909c9 940
bogdanm 74:a842253909c9 941 /* DWT LSU Count Register Definitions */
AnnaBridge 145:64910690c574 942 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
Kojto 110:165afa46840b 943 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 74:a842253909c9 944
bogdanm 74:a842253909c9 945 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 145:64910690c574 946 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 110:165afa46840b 947 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 74:a842253909c9 948
bogdanm 74:a842253909c9 949 /* DWT Comparator Mask Register Definitions */
AnnaBridge 145:64910690c574 950 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
Kojto 110:165afa46840b 951 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
bogdanm 74:a842253909c9 952
bogdanm 74:a842253909c9 953 /* DWT Comparator Function Register Definitions */
AnnaBridge 145:64910690c574 954 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
bogdanm 74:a842253909c9 955 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 74:a842253909c9 956
AnnaBridge 145:64910690c574 957 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 74:a842253909c9 958 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 74:a842253909c9 959
AnnaBridge 145:64910690c574 960 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 74:a842253909c9 961 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 74:a842253909c9 962
AnnaBridge 145:64910690c574 963 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 74:a842253909c9 964 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 74:a842253909c9 965
AnnaBridge 145:64910690c574 966 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 74:a842253909c9 967 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 74:a842253909c9 968
AnnaBridge 145:64910690c574 969 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 74:a842253909c9 970 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 74:a842253909c9 971
AnnaBridge 145:64910690c574 972 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 74:a842253909c9 973 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 74:a842253909c9 974
AnnaBridge 145:64910690c574 975 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 74:a842253909c9 976 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 74:a842253909c9 977
AnnaBridge 145:64910690c574 978 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
Kojto 110:165afa46840b 979 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 74:a842253909c9 980
bogdanm 74:a842253909c9 981 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 74:a842253909c9 982
bogdanm 74:a842253909c9 983
AnnaBridge 145:64910690c574 984 /**
AnnaBridge 145:64910690c574 985 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 986 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 145:64910690c574 987 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 74:a842253909c9 988 @{
bogdanm 74:a842253909c9 989 */
bogdanm 74:a842253909c9 990
AnnaBridge 145:64910690c574 991 /**
AnnaBridge 145:64910690c574 992 \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 74:a842253909c9 993 */
bogdanm 74:a842253909c9 994 typedef struct
bogdanm 74:a842253909c9 995 {
AnnaBridge 145:64910690c574 996 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 145:64910690c574 997 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 145:64910690c574 998 uint32_t RESERVED0[2U];
AnnaBridge 145:64910690c574 999 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 145:64910690c574 1000 uint32_t RESERVED1[55U];
AnnaBridge 145:64910690c574 1001 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 145:64910690c574 1002 uint32_t RESERVED2[131U];
AnnaBridge 145:64910690c574 1003 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 145:64910690c574 1004 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 145:64910690c574 1005 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 145:64910690c574 1006 uint32_t RESERVED3[759U];
AnnaBridge 145:64910690c574 1007 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 145:64910690c574 1008 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 145:64910690c574 1009 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 145:64910690c574 1010 uint32_t RESERVED4[1U];
AnnaBridge 145:64910690c574 1011 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 145:64910690c574 1012 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 145:64910690c574 1013 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 145:64910690c574 1014 uint32_t RESERVED5[39U];
AnnaBridge 145:64910690c574 1015 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 145:64910690c574 1016 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 145:64910690c574 1017 uint32_t RESERVED7[8U];
AnnaBridge 145:64910690c574 1018 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 145:64910690c574 1019 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 74:a842253909c9 1020 } TPI_Type;
bogdanm 74:a842253909c9 1021
bogdanm 74:a842253909c9 1022 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 145:64910690c574 1023 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
Kojto 110:165afa46840b 1024 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 74:a842253909c9 1025
bogdanm 74:a842253909c9 1026 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 145:64910690c574 1027 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Kojto 110:165afa46840b 1028 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
bogdanm 74:a842253909c9 1029
bogdanm 74:a842253909c9 1030 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 145:64910690c574 1031 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
bogdanm 74:a842253909c9 1032 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 74:a842253909c9 1033
AnnaBridge 145:64910690c574 1034 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
bogdanm 74:a842253909c9 1035 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 74:a842253909c9 1036
AnnaBridge 145:64910690c574 1037 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
bogdanm 74:a842253909c9 1038 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 74:a842253909c9 1039
AnnaBridge 145:64910690c574 1040 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Kojto 110:165afa46840b 1041 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
bogdanm 74:a842253909c9 1042
bogdanm 74:a842253909c9 1043 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 145:64910690c574 1044 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
bogdanm 74:a842253909c9 1045 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 74:a842253909c9 1046
AnnaBridge 145:64910690c574 1047 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
bogdanm 74:a842253909c9 1048 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 74:a842253909c9 1049
bogdanm 74:a842253909c9 1050 /* TPI TRIGGER Register Definitions */
AnnaBridge 145:64910690c574 1051 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Kojto 110:165afa46840b 1052 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 74:a842253909c9 1053
bogdanm 74:a842253909c9 1054 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 145:64910690c574 1055 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 74:a842253909c9 1056 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 74:a842253909c9 1057
AnnaBridge 145:64910690c574 1058 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 74:a842253909c9 1059 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 74:a842253909c9 1060
AnnaBridge 145:64910690c574 1061 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 74:a842253909c9 1062 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 74:a842253909c9 1063
AnnaBridge 145:64910690c574 1064 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 74:a842253909c9 1065 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 74:a842253909c9 1066
AnnaBridge 145:64910690c574 1067 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
bogdanm 74:a842253909c9 1068 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 74:a842253909c9 1069
AnnaBridge 145:64910690c574 1070 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
bogdanm 74:a842253909c9 1071 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 74:a842253909c9 1072
AnnaBridge 145:64910690c574 1073 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
Kojto 110:165afa46840b 1074 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 74:a842253909c9 1075
bogdanm 74:a842253909c9 1076 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 145:64910690c574 1077 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 110:165afa46840b 1078 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 74:a842253909c9 1079
bogdanm 74:a842253909c9 1080 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 145:64910690c574 1081 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 74:a842253909c9 1082 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 74:a842253909c9 1083
AnnaBridge 145:64910690c574 1084 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 74:a842253909c9 1085 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 74:a842253909c9 1086
AnnaBridge 145:64910690c574 1087 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 74:a842253909c9 1088 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 74:a842253909c9 1089
AnnaBridge 145:64910690c574 1090 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 74:a842253909c9 1091 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 74:a842253909c9 1092
AnnaBridge 145:64910690c574 1093 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
bogdanm 74:a842253909c9 1094 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 74:a842253909c9 1095
AnnaBridge 145:64910690c574 1096 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
bogdanm 74:a842253909c9 1097 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 74:a842253909c9 1098
AnnaBridge 145:64910690c574 1099 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
Kojto 110:165afa46840b 1100 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 74:a842253909c9 1101
bogdanm 74:a842253909c9 1102 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 145:64910690c574 1103 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 110:165afa46840b 1104 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 74:a842253909c9 1105
bogdanm 74:a842253909c9 1106 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 145:64910690c574 1107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
Kojto 110:165afa46840b 1108 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
bogdanm 74:a842253909c9 1109
bogdanm 74:a842253909c9 1110 /* TPI DEVID Register Definitions */
AnnaBridge 145:64910690c574 1111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
bogdanm 74:a842253909c9 1112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 74:a842253909c9 1113
AnnaBridge 145:64910690c574 1114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
bogdanm 74:a842253909c9 1115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 74:a842253909c9 1116
AnnaBridge 145:64910690c574 1117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
bogdanm 74:a842253909c9 1118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 74:a842253909c9 1119
AnnaBridge 145:64910690c574 1120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
bogdanm 74:a842253909c9 1121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 74:a842253909c9 1122
AnnaBridge 145:64910690c574 1123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
bogdanm 74:a842253909c9 1124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 74:a842253909c9 1125
AnnaBridge 145:64910690c574 1126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
Kojto 110:165afa46840b 1127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 74:a842253909c9 1128
bogdanm 74:a842253909c9 1129 /* TPI DEVTYPE Register Definitions */
AnnaBridge 145:64910690c574 1130 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
bogdanm 74:a842253909c9 1131 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 74:a842253909c9 1132
AnnaBridge 145:64910690c574 1133 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
Kojto 110:165afa46840b 1134 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 110:165afa46840b 1135
bogdanm 74:a842253909c9 1136 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 74:a842253909c9 1137
bogdanm 74:a842253909c9 1138
AnnaBridge 145:64910690c574 1139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 1140 /**
AnnaBridge 145:64910690c574 1141 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1142 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 1143 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 74:a842253909c9 1144 @{
bogdanm 74:a842253909c9 1145 */
bogdanm 74:a842253909c9 1146
AnnaBridge 145:64910690c574 1147 /**
AnnaBridge 145:64910690c574 1148 \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 74:a842253909c9 1149 */
bogdanm 74:a842253909c9 1150 typedef struct
bogdanm 74:a842253909c9 1151 {
AnnaBridge 145:64910690c574 1152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 145:64910690c574 1153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 145:64910690c574 1154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 145:64910690c574 1155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 145:64910690c574 1156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 145:64910690c574 1157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 145:64910690c574 1158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 145:64910690c574 1159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 145:64910690c574 1160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 145:64910690c574 1161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 145:64910690c574 1162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 74:a842253909c9 1163 } MPU_Type;
bogdanm 74:a842253909c9 1164
AnnaBridge 145:64910690c574 1165 /* MPU Type Register Definitions */
AnnaBridge 145:64910690c574 1166 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
bogdanm 74:a842253909c9 1167 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 74:a842253909c9 1168
AnnaBridge 145:64910690c574 1169 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
bogdanm 74:a842253909c9 1170 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 74:a842253909c9 1171
AnnaBridge 145:64910690c574 1172 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 1173 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 74:a842253909c9 1174
AnnaBridge 145:64910690c574 1175 /* MPU Control Register Definitions */
AnnaBridge 145:64910690c574 1176 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 74:a842253909c9 1177 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 74:a842253909c9 1178
AnnaBridge 145:64910690c574 1179 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
bogdanm 74:a842253909c9 1180 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 74:a842253909c9 1181
AnnaBridge 145:64910690c574 1182 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 1183 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 1184
AnnaBridge 145:64910690c574 1185 /* MPU Region Number Register Definitions */
AnnaBridge 145:64910690c574 1186 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 1187 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 74:a842253909c9 1188
AnnaBridge 145:64910690c574 1189 /* MPU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 1190 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
bogdanm 74:a842253909c9 1191 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 74:a842253909c9 1192
AnnaBridge 145:64910690c574 1193 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
bogdanm 74:a842253909c9 1194 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 74:a842253909c9 1195
AnnaBridge 145:64910690c574 1196 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 1197 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 74:a842253909c9 1198
AnnaBridge 145:64910690c574 1199 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 145:64910690c574 1200 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 74:a842253909c9 1201 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 74:a842253909c9 1202
AnnaBridge 145:64910690c574 1203 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
bogdanm 74:a842253909c9 1204 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 74:a842253909c9 1205
AnnaBridge 145:64910690c574 1206 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
bogdanm 74:a842253909c9 1207 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 74:a842253909c9 1208
AnnaBridge 145:64910690c574 1209 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 74:a842253909c9 1210 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 74:a842253909c9 1211
AnnaBridge 145:64910690c574 1212 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
bogdanm 74:a842253909c9 1213 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 74:a842253909c9 1214
AnnaBridge 145:64910690c574 1215 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
bogdanm 74:a842253909c9 1216 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 74:a842253909c9 1217
AnnaBridge 145:64910690c574 1218 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
bogdanm 74:a842253909c9 1219 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 74:a842253909c9 1220
AnnaBridge 145:64910690c574 1221 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 74:a842253909c9 1222 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 74:a842253909c9 1223
AnnaBridge 145:64910690c574 1224 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
bogdanm 74:a842253909c9 1225 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 74:a842253909c9 1226
AnnaBridge 145:64910690c574 1227 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 1228 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 74:a842253909c9 1229
bogdanm 74:a842253909c9 1230 /*@} end of group CMSIS_MPU */
bogdanm 74:a842253909c9 1231 #endif
bogdanm 74:a842253909c9 1232
bogdanm 74:a842253909c9 1233
AnnaBridge 145:64910690c574 1234 /**
AnnaBridge 145:64910690c574 1235 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1236 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 1237 \brief Type definitions for the Core Debug Registers
bogdanm 74:a842253909c9 1238 @{
bogdanm 74:a842253909c9 1239 */
bogdanm 74:a842253909c9 1240
AnnaBridge 145:64910690c574 1241 /**
AnnaBridge 145:64910690c574 1242 \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 74:a842253909c9 1243 */
bogdanm 74:a842253909c9 1244 typedef struct
bogdanm 74:a842253909c9 1245 {
AnnaBridge 145:64910690c574 1246 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 145:64910690c574 1247 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 145:64910690c574 1248 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 145:64910690c574 1249 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 74:a842253909c9 1250 } CoreDebug_Type;
bogdanm 74:a842253909c9 1251
AnnaBridge 145:64910690c574 1252 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 145:64910690c574 1253 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 74:a842253909c9 1254 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 74:a842253909c9 1255
AnnaBridge 145:64910690c574 1256 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 74:a842253909c9 1257 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 74:a842253909c9 1258
AnnaBridge 145:64910690c574 1259 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 74:a842253909c9 1260 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 74:a842253909c9 1261
AnnaBridge 145:64910690c574 1262 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 74:a842253909c9 1263 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 74:a842253909c9 1264
AnnaBridge 145:64910690c574 1265 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 74:a842253909c9 1266 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 74:a842253909c9 1267
AnnaBridge 145:64910690c574 1268 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 74:a842253909c9 1269 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 74:a842253909c9 1270
AnnaBridge 145:64910690c574 1271 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 74:a842253909c9 1272 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 74:a842253909c9 1273
AnnaBridge 145:64910690c574 1274 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 74:a842253909c9 1275 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 74:a842253909c9 1276
AnnaBridge 145:64910690c574 1277 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 74:a842253909c9 1278 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 74:a842253909c9 1279
AnnaBridge 145:64910690c574 1280 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 74:a842253909c9 1281 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 74:a842253909c9 1282
AnnaBridge 145:64910690c574 1283 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 74:a842253909c9 1284 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 74:a842253909c9 1285
AnnaBridge 145:64910690c574 1286 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 110:165afa46840b 1287 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 74:a842253909c9 1288
AnnaBridge 145:64910690c574 1289 /* Debug Core Register Selector Register Definitions */
AnnaBridge 145:64910690c574 1290 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 74:a842253909c9 1291 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 74:a842253909c9 1292
AnnaBridge 145:64910690c574 1293 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 110:165afa46840b 1294 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 74:a842253909c9 1295
AnnaBridge 145:64910690c574 1296 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 145:64910690c574 1297 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 74:a842253909c9 1298 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 74:a842253909c9 1299
AnnaBridge 145:64910690c574 1300 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 74:a842253909c9 1301 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 74:a842253909c9 1302
AnnaBridge 145:64910690c574 1303 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 74:a842253909c9 1304 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 74:a842253909c9 1305
AnnaBridge 145:64910690c574 1306 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 74:a842253909c9 1307 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 74:a842253909c9 1308
AnnaBridge 145:64910690c574 1309 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 74:a842253909c9 1310 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 74:a842253909c9 1311
AnnaBridge 145:64910690c574 1312 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 74:a842253909c9 1313 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 74:a842253909c9 1314
AnnaBridge 145:64910690c574 1315 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 74:a842253909c9 1316 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 74:a842253909c9 1317
AnnaBridge 145:64910690c574 1318 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 74:a842253909c9 1319 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 74:a842253909c9 1320
AnnaBridge 145:64910690c574 1321 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 74:a842253909c9 1322 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 74:a842253909c9 1323
AnnaBridge 145:64910690c574 1324 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 74:a842253909c9 1325 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 74:a842253909c9 1326
AnnaBridge 145:64910690c574 1327 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 74:a842253909c9 1328 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 74:a842253909c9 1329
AnnaBridge 145:64910690c574 1330 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 74:a842253909c9 1331 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 74:a842253909c9 1332
AnnaBridge 145:64910690c574 1333 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 110:165afa46840b 1334 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 74:a842253909c9 1335
bogdanm 74:a842253909c9 1336 /*@} end of group CMSIS_CoreDebug */
bogdanm 74:a842253909c9 1337
bogdanm 74:a842253909c9 1338
AnnaBridge 145:64910690c574 1339 /**
AnnaBridge 145:64910690c574 1340 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1341 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 1342 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
bogdanm 74:a842253909c9 1343 @{
bogdanm 74:a842253909c9 1344 */
bogdanm 74:a842253909c9 1345
AnnaBridge 145:64910690c574 1346 /**
AnnaBridge 145:64910690c574 1347 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 1348 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 1349 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 1350 \return Masked and shifted value.
AnnaBridge 145:64910690c574 1351 */
AnnaBridge 145:64910690c574 1352 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 1353
AnnaBridge 145:64910690c574 1354 /**
AnnaBridge 145:64910690c574 1355 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 1356 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 1357 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 1358 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 1359 */
AnnaBridge 145:64910690c574 1360 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 1361
AnnaBridge 145:64910690c574 1362 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 1363
AnnaBridge 145:64910690c574 1364
AnnaBridge 145:64910690c574 1365 /**
AnnaBridge 145:64910690c574 1366 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1367 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 1368 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 1369 @{
AnnaBridge 145:64910690c574 1370 */
AnnaBridge 145:64910690c574 1371
AnnaBridge 145:64910690c574 1372 /* Memory mapping of Core Hardware */
AnnaBridge 145:64910690c574 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 145:64910690c574 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 145:64910690c574 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 145:64910690c574 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 145:64910690c574 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 145:64910690c574 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 74:a842253909c9 1381
bogdanm 74:a842253909c9 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 145:64910690c574 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 145:64910690c574 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 145:64910690c574 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 145:64910690c574 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 145:64910690c574 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 74:a842253909c9 1390
AnnaBridge 145:64910690c574 1391 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 74:a842253909c9 1394 #endif
bogdanm 74:a842253909c9 1395
bogdanm 74:a842253909c9 1396 /*@} */
bogdanm 74:a842253909c9 1397
bogdanm 74:a842253909c9 1398
bogdanm 74:a842253909c9 1399
bogdanm 74:a842253909c9 1400 /*******************************************************************************
bogdanm 74:a842253909c9 1401 * Hardware Abstraction Layer
bogdanm 74:a842253909c9 1402 Core Function Interface contains:
bogdanm 74:a842253909c9 1403 - Core NVIC Functions
bogdanm 74:a842253909c9 1404 - Core SysTick Functions
bogdanm 74:a842253909c9 1405 - Core Debug Functions
bogdanm 74:a842253909c9 1406 - Core Register Access Functions
bogdanm 74:a842253909c9 1407 ******************************************************************************/
AnnaBridge 145:64910690c574 1408 /**
AnnaBridge 145:64910690c574 1409 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 74:a842253909c9 1410 */
bogdanm 74:a842253909c9 1411
bogdanm 74:a842253909c9 1412
bogdanm 74:a842253909c9 1413
bogdanm 74:a842253909c9 1414 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 1415 /**
AnnaBridge 145:64910690c574 1416 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1417 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 1418 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 1419 @{
bogdanm 74:a842253909c9 1420 */
bogdanm 74:a842253909c9 1421
<> 127:25aea2a3f4e3 1422 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1423 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1424 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1425 #endif
<> 127:25aea2a3f4e3 1426 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1427 #else
<> 127:25aea2a3f4e3 1428 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1429 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1430 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 1431 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<> 127:25aea2a3f4e3 1432 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1433 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1434 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1435 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1436 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1437 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1438 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1439 #define NVIC_SystemReset __NVIC_SystemReset
<> 127:25aea2a3f4e3 1440 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1441
<> 127:25aea2a3f4e3 1442 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1443 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1444 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1445 #endif
<> 127:25aea2a3f4e3 1446 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1447 #else
<> 127:25aea2a3f4e3 1448 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1449 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 1450 #endif /* (CMSIS_VECTAB_VIRTUAL) */
<> 127:25aea2a3f4e3 1451
AnnaBridge 145:64910690c574 1452 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 1453
AnnaBridge 145:64910690c574 1454
bogdanm 74:a842253909c9 1455
AnnaBridge 145:64910690c574 1456 /**
AnnaBridge 145:64910690c574 1457 \brief Set Priority Grouping
AnnaBridge 145:64910690c574 1458 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 145:64910690c574 1459 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 145:64910690c574 1460 Only values from 0..7 are used.
AnnaBridge 145:64910690c574 1461 In case of a conflict between priority grouping and available
AnnaBridge 145:64910690c574 1462 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 145:64910690c574 1463 \param [in] PriorityGroup Priority grouping field.
bogdanm 74:a842253909c9 1464 */
<> 127:25aea2a3f4e3 1465 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 74:a842253909c9 1466 {
bogdanm 74:a842253909c9 1467 uint32_t reg_value;
Kojto 110:165afa46840b 1468 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 74:a842253909c9 1469
bogdanm 74:a842253909c9 1470 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 145:64910690c574 1471 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 110:165afa46840b 1472 reg_value = (reg_value |
Kojto 110:165afa46840b 1473 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 145:64910690c574 1474 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
bogdanm 74:a842253909c9 1475 SCB->AIRCR = reg_value;
bogdanm 74:a842253909c9 1476 }
bogdanm 74:a842253909c9 1477
bogdanm 74:a842253909c9 1478
AnnaBridge 145:64910690c574 1479 /**
AnnaBridge 145:64910690c574 1480 \brief Get Priority Grouping
AnnaBridge 145:64910690c574 1481 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 145:64910690c574 1482 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 74:a842253909c9 1483 */
<> 127:25aea2a3f4e3 1484 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
bogdanm 74:a842253909c9 1485 {
Kojto 110:165afa46840b 1486 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
bogdanm 74:a842253909c9 1487 }
bogdanm 74:a842253909c9 1488
bogdanm 74:a842253909c9 1489
AnnaBridge 145:64910690c574 1490 /**
AnnaBridge 145:64910690c574 1491 \brief Enable Interrupt
AnnaBridge 145:64910690c574 1492 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1493 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1494 \note IRQn must not be negative.
bogdanm 74:a842253909c9 1495 */
<> 127:25aea2a3f4e3 1496 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1497 {
AnnaBridge 145:64910690c574 1498 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1499 {
AnnaBridge 145:64910690c574 1500 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1501 }
bogdanm 74:a842253909c9 1502 }
bogdanm 74:a842253909c9 1503
bogdanm 74:a842253909c9 1504
AnnaBridge 145:64910690c574 1505 /**
AnnaBridge 145:64910690c574 1506 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 1507 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1508 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1509 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 1510 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 1511 \note IRQn must not be negative.
bogdanm 74:a842253909c9 1512 */
AnnaBridge 145:64910690c574 1513 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1514 {
AnnaBridge 145:64910690c574 1515 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1516 {
AnnaBridge 145:64910690c574 1517 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1518 }
AnnaBridge 145:64910690c574 1519 else
AnnaBridge 145:64910690c574 1520 {
AnnaBridge 145:64910690c574 1521 return(0U);
AnnaBridge 145:64910690c574 1522 }
bogdanm 74:a842253909c9 1523 }
bogdanm 74:a842253909c9 1524
bogdanm 74:a842253909c9 1525
AnnaBridge 145:64910690c574 1526 /**
AnnaBridge 145:64910690c574 1527 \brief Disable Interrupt
AnnaBridge 145:64910690c574 1528 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1529 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1530 \note IRQn must not be negative.
bogdanm 74:a842253909c9 1531 */
AnnaBridge 145:64910690c574 1532 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1533 {
AnnaBridge 145:64910690c574 1534 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1535 {
AnnaBridge 145:64910690c574 1536 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1537 __DSB();
AnnaBridge 145:64910690c574 1538 __ISB();
AnnaBridge 145:64910690c574 1539 }
bogdanm 74:a842253909c9 1540 }
bogdanm 74:a842253909c9 1541
bogdanm 74:a842253909c9 1542
AnnaBridge 145:64910690c574 1543 /**
AnnaBridge 145:64910690c574 1544 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 1545 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 1546 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1547 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 1548 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 1549 \note IRQn must not be negative.
bogdanm 74:a842253909c9 1550 */
AnnaBridge 145:64910690c574 1551 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1552 {
AnnaBridge 145:64910690c574 1553 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1554 {
AnnaBridge 145:64910690c574 1555 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1556 }
AnnaBridge 145:64910690c574 1557 else
AnnaBridge 145:64910690c574 1558 {
AnnaBridge 145:64910690c574 1559 return(0U);
AnnaBridge 145:64910690c574 1560 }
bogdanm 74:a842253909c9 1561 }
bogdanm 74:a842253909c9 1562
bogdanm 74:a842253909c9 1563
AnnaBridge 145:64910690c574 1564 /**
AnnaBridge 145:64910690c574 1565 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 1566 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 1567 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1568 \note IRQn must not be negative.
bogdanm 74:a842253909c9 1569 */
AnnaBridge 145:64910690c574 1570 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1571 {
AnnaBridge 145:64910690c574 1572 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1573 {
AnnaBridge 145:64910690c574 1574 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 110:165afa46840b 1575 }
bogdanm 74:a842253909c9 1576 }
bogdanm 74:a842253909c9 1577
bogdanm 74:a842253909c9 1578
AnnaBridge 145:64910690c574 1579 /**
AnnaBridge 145:64910690c574 1580 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 1581 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 1582 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1583 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1584 */
AnnaBridge 145:64910690c574 1585 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1586 {
AnnaBridge 145:64910690c574 1587 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1588 {
AnnaBridge 145:64910690c574 1589 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1590 }
AnnaBridge 145:64910690c574 1591 }
bogdanm 74:a842253909c9 1592
bogdanm 74:a842253909c9 1593
AnnaBridge 145:64910690c574 1594 /**
AnnaBridge 145:64910690c574 1595 \brief Get Active Interrupt
AnnaBridge 145:64910690c574 1596 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1597 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1598 \return 0 Interrupt status is not active.
AnnaBridge 145:64910690c574 1599 \return 1 Interrupt status is active.
AnnaBridge 145:64910690c574 1600 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1601 */
AnnaBridge 145:64910690c574 1602 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1603 {
AnnaBridge 145:64910690c574 1604 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1605 {
AnnaBridge 145:64910690c574 1606 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1607 }
AnnaBridge 145:64910690c574 1608 else
AnnaBridge 145:64910690c574 1609 {
AnnaBridge 145:64910690c574 1610 return(0U);
AnnaBridge 145:64910690c574 1611 }
AnnaBridge 145:64910690c574 1612 }
AnnaBridge 145:64910690c574 1613
AnnaBridge 145:64910690c574 1614
AnnaBridge 145:64910690c574 1615 /**
AnnaBridge 145:64910690c574 1616 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 1617 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 1618 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1619 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1620 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1621 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 1622 \note The priority cannot be set for every processor exception.
AnnaBridge 145:64910690c574 1623 */
AnnaBridge 145:64910690c574 1624 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 145:64910690c574 1625 {
AnnaBridge 145:64910690c574 1626 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1627 {
AnnaBridge 145:64910690c574 1628 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 145:64910690c574 1629 }
AnnaBridge 145:64910690c574 1630 else
AnnaBridge 145:64910690c574 1631 {
AnnaBridge 145:64910690c574 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 145:64910690c574 1633 }
AnnaBridge 145:64910690c574 1634 }
AnnaBridge 145:64910690c574 1635
AnnaBridge 145:64910690c574 1636
AnnaBridge 145:64910690c574 1637 /**
AnnaBridge 145:64910690c574 1638 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 1639 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 1640 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1641 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1642 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1643 \return Interrupt Priority.
AnnaBridge 145:64910690c574 1644 Value is aligned automatically to the implemented priority bits of the microcontroller.
bogdanm 74:a842253909c9 1645 */
<> 127:25aea2a3f4e3 1646 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 74:a842253909c9 1647 {
bogdanm 74:a842253909c9 1648
AnnaBridge 145:64910690c574 1649 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1650 {
AnnaBridge 145:64910690c574 1651 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1652 }
AnnaBridge 145:64910690c574 1653 else
AnnaBridge 145:64910690c574 1654 {
AnnaBridge 145:64910690c574 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1656 }
bogdanm 74:a842253909c9 1657 }
bogdanm 74:a842253909c9 1658
bogdanm 74:a842253909c9 1659
AnnaBridge 145:64910690c574 1660 /**
AnnaBridge 145:64910690c574 1661 \brief Encode Priority
AnnaBridge 145:64910690c574 1662 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 145:64910690c574 1663 preemptive priority value, and subpriority value.
AnnaBridge 145:64910690c574 1664 In case of a conflict between priority grouping and available
AnnaBridge 145:64910690c574 1665 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 145:64910690c574 1666 \param [in] PriorityGroup Used priority group.
AnnaBridge 145:64910690c574 1667 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 145:64910690c574 1668 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 145:64910690c574 1669 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 74:a842253909c9 1670 */
bogdanm 74:a842253909c9 1671 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 74:a842253909c9 1672 {
Kojto 110:165afa46840b 1673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 74:a842253909c9 1674 uint32_t PreemptPriorityBits;
bogdanm 74:a842253909c9 1675 uint32_t SubPriorityBits;
bogdanm 74:a842253909c9 1676
Kojto 110:165afa46840b 1677 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1678 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 74:a842253909c9 1679
bogdanm 74:a842253909c9 1680 return (
Kojto 110:165afa46840b 1681 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 110:165afa46840b 1682 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
bogdanm 74:a842253909c9 1683 );
bogdanm 74:a842253909c9 1684 }
bogdanm 74:a842253909c9 1685
bogdanm 74:a842253909c9 1686
AnnaBridge 145:64910690c574 1687 /**
AnnaBridge 145:64910690c574 1688 \brief Decode Priority
AnnaBridge 145:64910690c574 1689 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 145:64910690c574 1690 preemptive priority value and subpriority value.
AnnaBridge 145:64910690c574 1691 In case of a conflict between priority grouping and available
AnnaBridge 145:64910690c574 1692 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 145:64910690c574 1693 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 145:64910690c574 1694 \param [in] PriorityGroup Used priority group.
AnnaBridge 145:64910690c574 1695 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 145:64910690c574 1696 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 74:a842253909c9 1697 */
AnnaBridge 145:64910690c574 1698 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
bogdanm 74:a842253909c9 1699 {
Kojto 110:165afa46840b 1700 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 74:a842253909c9 1701 uint32_t PreemptPriorityBits;
bogdanm 74:a842253909c9 1702 uint32_t SubPriorityBits;
bogdanm 74:a842253909c9 1703
Kojto 110:165afa46840b 1704 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1705 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 74:a842253909c9 1706
Kojto 110:165afa46840b 1707 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 110:165afa46840b 1708 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
bogdanm 74:a842253909c9 1709 }
bogdanm 74:a842253909c9 1710
bogdanm 74:a842253909c9 1711
AnnaBridge 145:64910690c574 1712 /**
AnnaBridge 145:64910690c574 1713 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 1714 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 1715 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1716 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1717 VTOR must been relocated to SRAM before.
AnnaBridge 145:64910690c574 1718 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 1719 \param [in] vector Address of interrupt handler function
AnnaBridge 145:64910690c574 1720 */
AnnaBridge 145:64910690c574 1721 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 145:64910690c574 1722 {
AnnaBridge 145:64910690c574 1723 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 1724 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 1725 }
AnnaBridge 145:64910690c574 1726
bogdanm 74:a842253909c9 1727
AnnaBridge 145:64910690c574 1728 /**
AnnaBridge 145:64910690c574 1729 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 1730 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 1731 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1732 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1733 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1734 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 1735 */
AnnaBridge 145:64910690c574 1736 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1737 {
AnnaBridge 145:64910690c574 1738 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 1739 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 1740 }
AnnaBridge 145:64910690c574 1741
AnnaBridge 145:64910690c574 1742
AnnaBridge 145:64910690c574 1743 /**
AnnaBridge 145:64910690c574 1744 \brief System Reset
AnnaBridge 145:64910690c574 1745 \details Initiates a system reset request to reset the MCU.
bogdanm 74:a842253909c9 1746 */
<> 128:9bcdf88f62b0 1747 __STATIC_INLINE void __NVIC_SystemReset(void)
bogdanm 74:a842253909c9 1748 {
Kojto 110:165afa46840b 1749 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 110:165afa46840b 1750 buffered write are completed before reset */
Kojto 110:165afa46840b 1751 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1752 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 110:165afa46840b 1753 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 110:165afa46840b 1754 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 1755
AnnaBridge 145:64910690c574 1756 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 1757 {
AnnaBridge 145:64910690c574 1758 __NOP();
AnnaBridge 145:64910690c574 1759 }
bogdanm 74:a842253909c9 1760 }
bogdanm 74:a842253909c9 1761
bogdanm 74:a842253909c9 1762 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 74:a842253909c9 1763
bogdanm 74:a842253909c9 1764
AnnaBridge 145:64910690c574 1765 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 1766 /**
AnnaBridge 145:64910690c574 1767 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1768 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 1769 \brief Function that provides FPU type.
bogdanm 74:a842253909c9 1770 @{
bogdanm 74:a842253909c9 1771 */
bogdanm 74:a842253909c9 1772
AnnaBridge 145:64910690c574 1773 /**
AnnaBridge 145:64910690c574 1774 \brief get FPU type
AnnaBridge 145:64910690c574 1775 \details returns the FPU type
AnnaBridge 145:64910690c574 1776 \returns
AnnaBridge 145:64910690c574 1777 - \b 0: No FPU
AnnaBridge 145:64910690c574 1778 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 1779 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 1780 */
AnnaBridge 145:64910690c574 1781 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 1782 {
AnnaBridge 145:64910690c574 1783 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 1784 }
bogdanm 74:a842253909c9 1785
bogdanm 74:a842253909c9 1786
AnnaBridge 145:64910690c574 1787 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 1788
AnnaBridge 145:64910690c574 1789
bogdanm 74:a842253909c9 1790
AnnaBridge 145:64910690c574 1791 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 1792 /**
AnnaBridge 145:64910690c574 1793 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 1795 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 1796 @{
AnnaBridge 145:64910690c574 1797 */
bogdanm 74:a842253909c9 1798
AnnaBridge 145:64910690c574 1799 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
bogdanm 74:a842253909c9 1800
AnnaBridge 145:64910690c574 1801 /**
AnnaBridge 145:64910690c574 1802 \brief System Tick Configuration
AnnaBridge 145:64910690c574 1803 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 1804 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 1805 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 1806 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 1807 \return 1 Function failed.
AnnaBridge 145:64910690c574 1808 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 1809 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 1810 must contain a vendor-specific implementation of this function.
bogdanm 74:a842253909c9 1811 */
bogdanm 74:a842253909c9 1812 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 74:a842253909c9 1813 {
AnnaBridge 145:64910690c574 1814 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 1815 {
AnnaBridge 145:64910690c574 1816 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 1817 }
bogdanm 74:a842253909c9 1818
Kojto 110:165afa46840b 1819 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 1820 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 1821 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 74:a842253909c9 1822 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 74:a842253909c9 1823 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 1824 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 1825 return (0UL); /* Function successful */
bogdanm 74:a842253909c9 1826 }
bogdanm 74:a842253909c9 1827
bogdanm 74:a842253909c9 1828 #endif
bogdanm 74:a842253909c9 1829
bogdanm 74:a842253909c9 1830 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 74:a842253909c9 1831
bogdanm 74:a842253909c9 1832
bogdanm 74:a842253909c9 1833
bogdanm 74:a842253909c9 1834 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 145:64910690c574 1835 /**
AnnaBridge 145:64910690c574 1836 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1837 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 145:64910690c574 1838 \brief Functions that access the ITM debug interface.
bogdanm 74:a842253909c9 1839 @{
bogdanm 74:a842253909c9 1840 */
bogdanm 74:a842253909c9 1841
AnnaBridge 145:64910690c574 1842 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 145:64910690c574 1843 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 74:a842253909c9 1844
bogdanm 74:a842253909c9 1845
AnnaBridge 145:64910690c574 1846 /**
AnnaBridge 145:64910690c574 1847 \brief ITM Send Character
AnnaBridge 145:64910690c574 1848 \details Transmits a character via the ITM channel 0, and
AnnaBridge 145:64910690c574 1849 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 145:64910690c574 1850 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 145:64910690c574 1851 \param [in] ch Character to transmit.
AnnaBridge 145:64910690c574 1852 \returns Character to transmit.
bogdanm 74:a842253909c9 1853 */
bogdanm 74:a842253909c9 1854 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 74:a842253909c9 1855 {
Kojto 110:165afa46840b 1856 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 110:165afa46840b 1857 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
bogdanm 74:a842253909c9 1858 {
AnnaBridge 145:64910690c574 1859 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 145:64910690c574 1860 {
AnnaBridge 145:64910690c574 1861 __NOP();
AnnaBridge 145:64910690c574 1862 }
AnnaBridge 145:64910690c574 1863 ITM->PORT[0U].u8 = (uint8_t)ch;
bogdanm 74:a842253909c9 1864 }
bogdanm 74:a842253909c9 1865 return (ch);
bogdanm 74:a842253909c9 1866 }
bogdanm 74:a842253909c9 1867
bogdanm 74:a842253909c9 1868
AnnaBridge 145:64910690c574 1869 /**
AnnaBridge 145:64910690c574 1870 \brief ITM Receive Character
AnnaBridge 145:64910690c574 1871 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 145:64910690c574 1872 \return Received character.
AnnaBridge 145:64910690c574 1873 \return -1 No character pending.
bogdanm 74:a842253909c9 1874 */
AnnaBridge 145:64910690c574 1875 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 145:64910690c574 1876 {
bogdanm 74:a842253909c9 1877 int32_t ch = -1; /* no character available */
bogdanm 74:a842253909c9 1878
AnnaBridge 145:64910690c574 1879 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 145:64910690c574 1880 {
bogdanm 74:a842253909c9 1881 ch = ITM_RxBuffer;
bogdanm 74:a842253909c9 1882 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 74:a842253909c9 1883 }
bogdanm 74:a842253909c9 1884
bogdanm 74:a842253909c9 1885 return (ch);
bogdanm 74:a842253909c9 1886 }
bogdanm 74:a842253909c9 1887
bogdanm 74:a842253909c9 1888
AnnaBridge 145:64910690c574 1889 /**
AnnaBridge 145:64910690c574 1890 \brief ITM Check Character
AnnaBridge 145:64910690c574 1891 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 145:64910690c574 1892 \return 0 No character available.
AnnaBridge 145:64910690c574 1893 \return 1 Character available.
bogdanm 74:a842253909c9 1894 */
AnnaBridge 145:64910690c574 1895 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 145:64910690c574 1896 {
bogdanm 74:a842253909c9 1897
AnnaBridge 145:64910690c574 1898 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 145:64910690c574 1899 {
AnnaBridge 145:64910690c574 1900 return (0); /* no character available */
AnnaBridge 145:64910690c574 1901 }
AnnaBridge 145:64910690c574 1902 else
AnnaBridge 145:64910690c574 1903 {
AnnaBridge 145:64910690c574 1904 return (1); /* character available */
bogdanm 74:a842253909c9 1905 }
bogdanm 74:a842253909c9 1906 }
bogdanm 74:a842253909c9 1907
bogdanm 74:a842253909c9 1908 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 74:a842253909c9 1909
bogdanm 74:a842253909c9 1910
Kojto 110:165afa46840b 1911
bogdanm 74:a842253909c9 1912
bogdanm 74:a842253909c9 1913 #ifdef __cplusplus
bogdanm 74:a842253909c9 1914 }
bogdanm 74:a842253909c9 1915 #endif
Kojto 110:165afa46840b 1916
Kojto 110:165afa46840b 1917 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 110:165afa46840b 1918
Kojto 110:165afa46840b 1919 #endif /* __CMSIS_GENERIC */