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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F413ZH/core_cm0plus.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
146:22da6e220af6
Child:
160:5571c4ff569f
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 146:22da6e220af6 1 /**************************************************************************//**
AnnaBridge 146:22da6e220af6 2 * @file core_cm0plus.h
AnnaBridge 146:22da6e220af6 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 146:22da6e220af6 4 * @version V5.0.2
AnnaBridge 146:22da6e220af6 5 * @date 13. February 2017
AnnaBridge 146:22da6e220af6 6 ******************************************************************************/
AnnaBridge 146:22da6e220af6 7 /*
AnnaBridge 146:22da6e220af6 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 146:22da6e220af6 9 *
AnnaBridge 146:22da6e220af6 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 146:22da6e220af6 11 *
AnnaBridge 146:22da6e220af6 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 146:22da6e220af6 13 * not use this file except in compliance with the License.
AnnaBridge 146:22da6e220af6 14 * You may obtain a copy of the License at
AnnaBridge 146:22da6e220af6 15 *
AnnaBridge 146:22da6e220af6 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 146:22da6e220af6 17 *
AnnaBridge 146:22da6e220af6 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 146:22da6e220af6 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 146:22da6e220af6 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 146:22da6e220af6 21 * See the License for the specific language governing permissions and
AnnaBridge 146:22da6e220af6 22 * limitations under the License.
AnnaBridge 146:22da6e220af6 23 */
AnnaBridge 146:22da6e220af6 24
AnnaBridge 146:22da6e220af6 25 #if defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 146:22da6e220af6 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 146:22da6e220af6 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 146:22da6e220af6 29 #endif
AnnaBridge 146:22da6e220af6 30
AnnaBridge 146:22da6e220af6 31 #ifndef __CORE_CM0PLUS_H_GENERIC
AnnaBridge 146:22da6e220af6 32 #define __CORE_CM0PLUS_H_GENERIC
AnnaBridge 146:22da6e220af6 33
AnnaBridge 146:22da6e220af6 34 #include <stdint.h>
AnnaBridge 146:22da6e220af6 35
AnnaBridge 146:22da6e220af6 36 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 37 extern "C" {
AnnaBridge 146:22da6e220af6 38 #endif
AnnaBridge 146:22da6e220af6 39
AnnaBridge 146:22da6e220af6 40 /**
AnnaBridge 146:22da6e220af6 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 146:22da6e220af6 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 146:22da6e220af6 43
AnnaBridge 146:22da6e220af6 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 146:22da6e220af6 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 146:22da6e220af6 46
AnnaBridge 146:22da6e220af6 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 146:22da6e220af6 48 Unions are used for effective representation of core registers.
AnnaBridge 146:22da6e220af6 49
AnnaBridge 146:22da6e220af6 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 146:22da6e220af6 51 Function-like macros are used to allow more efficient code.
AnnaBridge 146:22da6e220af6 52 */
AnnaBridge 146:22da6e220af6 53
AnnaBridge 146:22da6e220af6 54
AnnaBridge 146:22da6e220af6 55 /*******************************************************************************
AnnaBridge 146:22da6e220af6 56 * CMSIS definitions
AnnaBridge 146:22da6e220af6 57 ******************************************************************************/
AnnaBridge 146:22da6e220af6 58 /**
AnnaBridge 146:22da6e220af6 59 \ingroup Cortex-M0+
AnnaBridge 146:22da6e220af6 60 @{
AnnaBridge 146:22da6e220af6 61 */
AnnaBridge 146:22da6e220af6 62
AnnaBridge 146:22da6e220af6 63 /* CMSIS CM0+ definitions */
AnnaBridge 146:22da6e220af6 64 #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 146:22da6e220af6 65 #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 146:22da6e220af6 66 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 146:22da6e220af6 67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 146:22da6e220af6 68
AnnaBridge 146:22da6e220af6 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 146:22da6e220af6 70
AnnaBridge 146:22da6e220af6 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 146:22da6e220af6 72 This core does not support an FPU at all
AnnaBridge 146:22da6e220af6 73 */
AnnaBridge 146:22da6e220af6 74 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 75
AnnaBridge 146:22da6e220af6 76 #if defined ( __CC_ARM )
AnnaBridge 146:22da6e220af6 77 #if defined __TARGET_FPU_VFP
AnnaBridge 146:22da6e220af6 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 79 #endif
AnnaBridge 146:22da6e220af6 80
AnnaBridge 146:22da6e220af6 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 146:22da6e220af6 82 #if defined __ARM_PCS_VFP
AnnaBridge 146:22da6e220af6 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 84 #endif
AnnaBridge 146:22da6e220af6 85
AnnaBridge 146:22da6e220af6 86 #elif defined ( __GNUC__ )
AnnaBridge 146:22da6e220af6 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 146:22da6e220af6 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 89 #endif
AnnaBridge 146:22da6e220af6 90
AnnaBridge 146:22da6e220af6 91 #elif defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 92 #if defined __ARMVFP__
AnnaBridge 146:22da6e220af6 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 94 #endif
AnnaBridge 146:22da6e220af6 95
AnnaBridge 146:22da6e220af6 96 #elif defined ( __TI_ARM__ )
AnnaBridge 146:22da6e220af6 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 146:22da6e220af6 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 99 #endif
AnnaBridge 146:22da6e220af6 100
AnnaBridge 146:22da6e220af6 101 #elif defined ( __TASKING__ )
AnnaBridge 146:22da6e220af6 102 #if defined __FPU_VFP__
AnnaBridge 146:22da6e220af6 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 104 #endif
AnnaBridge 146:22da6e220af6 105
AnnaBridge 146:22da6e220af6 106 #elif defined ( __CSMC__ )
AnnaBridge 146:22da6e220af6 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 146:22da6e220af6 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 109 #endif
AnnaBridge 146:22da6e220af6 110
AnnaBridge 146:22da6e220af6 111 #endif
AnnaBridge 146:22da6e220af6 112
AnnaBridge 146:22da6e220af6 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 146:22da6e220af6 114
AnnaBridge 146:22da6e220af6 115
AnnaBridge 146:22da6e220af6 116 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 117 }
AnnaBridge 146:22da6e220af6 118 #endif
AnnaBridge 146:22da6e220af6 119
AnnaBridge 146:22da6e220af6 120 #endif /* __CORE_CM0PLUS_H_GENERIC */
AnnaBridge 146:22da6e220af6 121
AnnaBridge 146:22da6e220af6 122 #ifndef __CMSIS_GENERIC
AnnaBridge 146:22da6e220af6 123
AnnaBridge 146:22da6e220af6 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 146:22da6e220af6 125 #define __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 146:22da6e220af6 126
AnnaBridge 146:22da6e220af6 127 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 128 extern "C" {
AnnaBridge 146:22da6e220af6 129 #endif
AnnaBridge 146:22da6e220af6 130
AnnaBridge 146:22da6e220af6 131 /* check device defines and use defaults */
AnnaBridge 146:22da6e220af6 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 146:22da6e220af6 133 #ifndef __CM0PLUS_REV
AnnaBridge 146:22da6e220af6 134 #define __CM0PLUS_REV 0x0000U
AnnaBridge 146:22da6e220af6 135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 136 #endif
AnnaBridge 146:22da6e220af6 137
AnnaBridge 146:22da6e220af6 138 #ifndef __MPU_PRESENT
AnnaBridge 146:22da6e220af6 139 #define __MPU_PRESENT 0U
AnnaBridge 146:22da6e220af6 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 141 #endif
AnnaBridge 146:22da6e220af6 142
AnnaBridge 146:22da6e220af6 143 #ifndef __VTOR_PRESENT
AnnaBridge 146:22da6e220af6 144 #define __VTOR_PRESENT 0U
AnnaBridge 146:22da6e220af6 145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 146 #endif
AnnaBridge 146:22da6e220af6 147
AnnaBridge 146:22da6e220af6 148 #ifndef __NVIC_PRIO_BITS
AnnaBridge 146:22da6e220af6 149 #define __NVIC_PRIO_BITS 2U
AnnaBridge 146:22da6e220af6 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 151 #endif
AnnaBridge 146:22da6e220af6 152
AnnaBridge 146:22da6e220af6 153 #ifndef __Vendor_SysTickConfig
AnnaBridge 146:22da6e220af6 154 #define __Vendor_SysTickConfig 0U
AnnaBridge 146:22da6e220af6 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 156 #endif
AnnaBridge 146:22da6e220af6 157 #endif
AnnaBridge 146:22da6e220af6 158
AnnaBridge 146:22da6e220af6 159 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 146:22da6e220af6 160 /**
AnnaBridge 146:22da6e220af6 161 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 146:22da6e220af6 162
AnnaBridge 146:22da6e220af6 163 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 146:22da6e220af6 164 \li to specify the access to peripheral variables.
AnnaBridge 146:22da6e220af6 165 \li for automatic generation of peripheral register debug information.
AnnaBridge 146:22da6e220af6 166 */
AnnaBridge 146:22da6e220af6 167 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 168 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 169 #else
AnnaBridge 146:22da6e220af6 170 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 171 #endif
AnnaBridge 146:22da6e220af6 172 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 146:22da6e220af6 173 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 146:22da6e220af6 174
AnnaBridge 146:22da6e220af6 175 /* following defines should be used for structure members */
AnnaBridge 146:22da6e220af6 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 146:22da6e220af6 177 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 146:22da6e220af6 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 146:22da6e220af6 179
AnnaBridge 146:22da6e220af6 180 /*@} end of group Cortex-M0+ */
AnnaBridge 146:22da6e220af6 181
AnnaBridge 146:22da6e220af6 182
AnnaBridge 146:22da6e220af6 183
AnnaBridge 146:22da6e220af6 184 /*******************************************************************************
AnnaBridge 146:22da6e220af6 185 * Register Abstraction
AnnaBridge 146:22da6e220af6 186 Core Register contain:
AnnaBridge 146:22da6e220af6 187 - Core Register
AnnaBridge 146:22da6e220af6 188 - Core NVIC Register
AnnaBridge 146:22da6e220af6 189 - Core SCB Register
AnnaBridge 146:22da6e220af6 190 - Core SysTick Register
AnnaBridge 146:22da6e220af6 191 - Core MPU Register
AnnaBridge 146:22da6e220af6 192 ******************************************************************************/
AnnaBridge 146:22da6e220af6 193 /**
AnnaBridge 146:22da6e220af6 194 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 146:22da6e220af6 195 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 146:22da6e220af6 196 */
AnnaBridge 146:22da6e220af6 197
AnnaBridge 146:22da6e220af6 198 /**
AnnaBridge 146:22da6e220af6 199 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 200 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 146:22da6e220af6 201 \brief Core Register type definitions.
AnnaBridge 146:22da6e220af6 202 @{
AnnaBridge 146:22da6e220af6 203 */
AnnaBridge 146:22da6e220af6 204
AnnaBridge 146:22da6e220af6 205 /**
AnnaBridge 146:22da6e220af6 206 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 146:22da6e220af6 207 */
AnnaBridge 146:22da6e220af6 208 typedef union
AnnaBridge 146:22da6e220af6 209 {
AnnaBridge 146:22da6e220af6 210 struct
AnnaBridge 146:22da6e220af6 211 {
AnnaBridge 146:22da6e220af6 212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 146:22da6e220af6 213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 146:22da6e220af6 214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 146:22da6e220af6 215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 146:22da6e220af6 216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 146:22da6e220af6 217 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 218 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 219 } APSR_Type;
AnnaBridge 146:22da6e220af6 220
AnnaBridge 146:22da6e220af6 221 /* APSR Register Definitions */
AnnaBridge 146:22da6e220af6 222 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 146:22da6e220af6 223 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 146:22da6e220af6 224
AnnaBridge 146:22da6e220af6 225 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 146:22da6e220af6 226 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 146:22da6e220af6 227
AnnaBridge 146:22da6e220af6 228 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 146:22da6e220af6 229 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 146:22da6e220af6 230
AnnaBridge 146:22da6e220af6 231 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 146:22da6e220af6 232 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 146:22da6e220af6 233
AnnaBridge 146:22da6e220af6 234
AnnaBridge 146:22da6e220af6 235 /**
AnnaBridge 146:22da6e220af6 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 146:22da6e220af6 237 */
AnnaBridge 146:22da6e220af6 238 typedef union
AnnaBridge 146:22da6e220af6 239 {
AnnaBridge 146:22da6e220af6 240 struct
AnnaBridge 146:22da6e220af6 241 {
AnnaBridge 146:22da6e220af6 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 146:22da6e220af6 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 146:22da6e220af6 244 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 245 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 246 } IPSR_Type;
AnnaBridge 146:22da6e220af6 247
AnnaBridge 146:22da6e220af6 248 /* IPSR Register Definitions */
AnnaBridge 146:22da6e220af6 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 146:22da6e220af6 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 146:22da6e220af6 251
AnnaBridge 146:22da6e220af6 252
AnnaBridge 146:22da6e220af6 253 /**
AnnaBridge 146:22da6e220af6 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 146:22da6e220af6 255 */
AnnaBridge 146:22da6e220af6 256 typedef union
AnnaBridge 146:22da6e220af6 257 {
AnnaBridge 146:22da6e220af6 258 struct
AnnaBridge 146:22da6e220af6 259 {
AnnaBridge 146:22da6e220af6 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 146:22da6e220af6 261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 146:22da6e220af6 262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 146:22da6e220af6 263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 146:22da6e220af6 264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 146:22da6e220af6 265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 146:22da6e220af6 266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 146:22da6e220af6 267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 146:22da6e220af6 268 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 269 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 270 } xPSR_Type;
AnnaBridge 146:22da6e220af6 271
AnnaBridge 146:22da6e220af6 272 /* xPSR Register Definitions */
AnnaBridge 146:22da6e220af6 273 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 146:22da6e220af6 274 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 146:22da6e220af6 275
AnnaBridge 146:22da6e220af6 276 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 146:22da6e220af6 277 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 146:22da6e220af6 278
AnnaBridge 146:22da6e220af6 279 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 146:22da6e220af6 280 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 146:22da6e220af6 281
AnnaBridge 146:22da6e220af6 282 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 146:22da6e220af6 283 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 146:22da6e220af6 284
AnnaBridge 146:22da6e220af6 285 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 146:22da6e220af6 286 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 146:22da6e220af6 287
AnnaBridge 146:22da6e220af6 288 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 146:22da6e220af6 289 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 146:22da6e220af6 290
AnnaBridge 146:22da6e220af6 291
AnnaBridge 146:22da6e220af6 292 /**
AnnaBridge 146:22da6e220af6 293 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 146:22da6e220af6 294 */
AnnaBridge 146:22da6e220af6 295 typedef union
AnnaBridge 146:22da6e220af6 296 {
AnnaBridge 146:22da6e220af6 297 struct
AnnaBridge 146:22da6e220af6 298 {
AnnaBridge 146:22da6e220af6 299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 146:22da6e220af6 300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 146:22da6e220af6 301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 146:22da6e220af6 302 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 303 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 304 } CONTROL_Type;
AnnaBridge 146:22da6e220af6 305
AnnaBridge 146:22da6e220af6 306 /* CONTROL Register Definitions */
AnnaBridge 146:22da6e220af6 307 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 146:22da6e220af6 308 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 146:22da6e220af6 309
AnnaBridge 146:22da6e220af6 310 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 146:22da6e220af6 311 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 146:22da6e220af6 312
AnnaBridge 146:22da6e220af6 313 /*@} end of group CMSIS_CORE */
AnnaBridge 146:22da6e220af6 314
AnnaBridge 146:22da6e220af6 315
AnnaBridge 146:22da6e220af6 316 /**
AnnaBridge 146:22da6e220af6 317 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 146:22da6e220af6 319 \brief Type definitions for the NVIC Registers
AnnaBridge 146:22da6e220af6 320 @{
AnnaBridge 146:22da6e220af6 321 */
AnnaBridge 146:22da6e220af6 322
AnnaBridge 146:22da6e220af6 323 /**
AnnaBridge 146:22da6e220af6 324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 146:22da6e220af6 325 */
AnnaBridge 146:22da6e220af6 326 typedef struct
AnnaBridge 146:22da6e220af6 327 {
AnnaBridge 146:22da6e220af6 328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 146:22da6e220af6 329 uint32_t RESERVED0[31U];
AnnaBridge 146:22da6e220af6 330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 146:22da6e220af6 331 uint32_t RSERVED1[31U];
AnnaBridge 146:22da6e220af6 332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 146:22da6e220af6 333 uint32_t RESERVED2[31U];
AnnaBridge 146:22da6e220af6 334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 146:22da6e220af6 335 uint32_t RESERVED3[31U];
AnnaBridge 146:22da6e220af6 336 uint32_t RESERVED4[64U];
AnnaBridge 146:22da6e220af6 337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 146:22da6e220af6 338 } NVIC_Type;
AnnaBridge 146:22da6e220af6 339
AnnaBridge 146:22da6e220af6 340 /*@} end of group CMSIS_NVIC */
AnnaBridge 146:22da6e220af6 341
AnnaBridge 146:22da6e220af6 342
AnnaBridge 146:22da6e220af6 343 /**
AnnaBridge 146:22da6e220af6 344 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 345 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 146:22da6e220af6 346 \brief Type definitions for the System Control Block Registers
AnnaBridge 146:22da6e220af6 347 @{
AnnaBridge 146:22da6e220af6 348 */
AnnaBridge 146:22da6e220af6 349
AnnaBridge 146:22da6e220af6 350 /**
AnnaBridge 146:22da6e220af6 351 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 146:22da6e220af6 352 */
AnnaBridge 146:22da6e220af6 353 typedef struct
AnnaBridge 146:22da6e220af6 354 {
AnnaBridge 146:22da6e220af6 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 146:22da6e220af6 356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 146:22da6e220af6 357 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 146:22da6e220af6 359 #else
AnnaBridge 146:22da6e220af6 360 uint32_t RESERVED0;
AnnaBridge 146:22da6e220af6 361 #endif
AnnaBridge 146:22da6e220af6 362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 146:22da6e220af6 363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 146:22da6e220af6 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 146:22da6e220af6 365 uint32_t RESERVED1;
AnnaBridge 146:22da6e220af6 366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 146:22da6e220af6 367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 146:22da6e220af6 368 } SCB_Type;
AnnaBridge 146:22da6e220af6 369
AnnaBridge 146:22da6e220af6 370 /* SCB CPUID Register Definitions */
AnnaBridge 146:22da6e220af6 371 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 146:22da6e220af6 372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 146:22da6e220af6 373
AnnaBridge 146:22da6e220af6 374 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 146:22da6e220af6 375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 146:22da6e220af6 376
AnnaBridge 146:22da6e220af6 377 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 146:22da6e220af6 378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 146:22da6e220af6 379
AnnaBridge 146:22da6e220af6 380 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 146:22da6e220af6 381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 146:22da6e220af6 382
AnnaBridge 146:22da6e220af6 383 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 146:22da6e220af6 384 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 146:22da6e220af6 385
AnnaBridge 146:22da6e220af6 386 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 146:22da6e220af6 387 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 146:22da6e220af6 388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 146:22da6e220af6 389
AnnaBridge 146:22da6e220af6 390 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 146:22da6e220af6 391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 146:22da6e220af6 392
AnnaBridge 146:22da6e220af6 393 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 146:22da6e220af6 394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 146:22da6e220af6 395
AnnaBridge 146:22da6e220af6 396 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 146:22da6e220af6 397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 146:22da6e220af6 398
AnnaBridge 146:22da6e220af6 399 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 146:22da6e220af6 400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 146:22da6e220af6 401
AnnaBridge 146:22da6e220af6 402 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 146:22da6e220af6 403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 146:22da6e220af6 404
AnnaBridge 146:22da6e220af6 405 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 146:22da6e220af6 406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 146:22da6e220af6 407
AnnaBridge 146:22da6e220af6 408 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 146:22da6e220af6 409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 146:22da6e220af6 410
AnnaBridge 146:22da6e220af6 411 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 146:22da6e220af6 412 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 146:22da6e220af6 413
AnnaBridge 146:22da6e220af6 414 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 415 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 146:22da6e220af6 416 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 146:22da6e220af6 417 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 146:22da6e220af6 418 #endif
AnnaBridge 146:22da6e220af6 419
AnnaBridge 146:22da6e220af6 420 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 146:22da6e220af6 421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 146:22da6e220af6 422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 146:22da6e220af6 423
AnnaBridge 146:22da6e220af6 424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 146:22da6e220af6 425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 146:22da6e220af6 426
AnnaBridge 146:22da6e220af6 427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 146:22da6e220af6 428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 146:22da6e220af6 429
AnnaBridge 146:22da6e220af6 430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 146:22da6e220af6 431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 146:22da6e220af6 432
AnnaBridge 146:22da6e220af6 433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 146:22da6e220af6 434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 146:22da6e220af6 435
AnnaBridge 146:22da6e220af6 436 /* SCB System Control Register Definitions */
AnnaBridge 146:22da6e220af6 437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 146:22da6e220af6 438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 146:22da6e220af6 439
AnnaBridge 146:22da6e220af6 440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 146:22da6e220af6 441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 146:22da6e220af6 442
AnnaBridge 146:22da6e220af6 443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 146:22da6e220af6 444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 146:22da6e220af6 445
AnnaBridge 146:22da6e220af6 446 /* SCB Configuration Control Register Definitions */
AnnaBridge 146:22da6e220af6 447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 146:22da6e220af6 448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 146:22da6e220af6 449
AnnaBridge 146:22da6e220af6 450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 146:22da6e220af6 451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 146:22da6e220af6 452
AnnaBridge 146:22da6e220af6 453 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 146:22da6e220af6 454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 146:22da6e220af6 455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 146:22da6e220af6 456
AnnaBridge 146:22da6e220af6 457 /*@} end of group CMSIS_SCB */
AnnaBridge 146:22da6e220af6 458
AnnaBridge 146:22da6e220af6 459
AnnaBridge 146:22da6e220af6 460 /**
AnnaBridge 146:22da6e220af6 461 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 146:22da6e220af6 463 \brief Type definitions for the System Timer Registers.
AnnaBridge 146:22da6e220af6 464 @{
AnnaBridge 146:22da6e220af6 465 */
AnnaBridge 146:22da6e220af6 466
AnnaBridge 146:22da6e220af6 467 /**
AnnaBridge 146:22da6e220af6 468 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 146:22da6e220af6 469 */
AnnaBridge 146:22da6e220af6 470 typedef struct
AnnaBridge 146:22da6e220af6 471 {
AnnaBridge 146:22da6e220af6 472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 146:22da6e220af6 473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 146:22da6e220af6 474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 146:22da6e220af6 475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 146:22da6e220af6 476 } SysTick_Type;
AnnaBridge 146:22da6e220af6 477
AnnaBridge 146:22da6e220af6 478 /* SysTick Control / Status Register Definitions */
AnnaBridge 146:22da6e220af6 479 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 146:22da6e220af6 480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 146:22da6e220af6 481
AnnaBridge 146:22da6e220af6 482 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 146:22da6e220af6 483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 146:22da6e220af6 484
AnnaBridge 146:22da6e220af6 485 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 146:22da6e220af6 486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 146:22da6e220af6 487
AnnaBridge 146:22da6e220af6 488 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 146:22da6e220af6 489 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 146:22da6e220af6 490
AnnaBridge 146:22da6e220af6 491 /* SysTick Reload Register Definitions */
AnnaBridge 146:22da6e220af6 492 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 146:22da6e220af6 493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 146:22da6e220af6 494
AnnaBridge 146:22da6e220af6 495 /* SysTick Current Register Definitions */
AnnaBridge 146:22da6e220af6 496 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 146:22da6e220af6 497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 146:22da6e220af6 498
AnnaBridge 146:22da6e220af6 499 /* SysTick Calibration Register Definitions */
AnnaBridge 146:22da6e220af6 500 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 146:22da6e220af6 501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 146:22da6e220af6 502
AnnaBridge 146:22da6e220af6 503 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 146:22da6e220af6 504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 146:22da6e220af6 505
AnnaBridge 146:22da6e220af6 506 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 146:22da6e220af6 507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 146:22da6e220af6 508
AnnaBridge 146:22da6e220af6 509 /*@} end of group CMSIS_SysTick */
AnnaBridge 146:22da6e220af6 510
AnnaBridge 146:22da6e220af6 511 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 512 /**
AnnaBridge 146:22da6e220af6 513 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 146:22da6e220af6 515 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 146:22da6e220af6 516 @{
AnnaBridge 146:22da6e220af6 517 */
AnnaBridge 146:22da6e220af6 518
AnnaBridge 146:22da6e220af6 519 /**
AnnaBridge 146:22da6e220af6 520 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 146:22da6e220af6 521 */
AnnaBridge 146:22da6e220af6 522 typedef struct
AnnaBridge 146:22da6e220af6 523 {
AnnaBridge 146:22da6e220af6 524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 146:22da6e220af6 525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 146:22da6e220af6 526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 146:22da6e220af6 527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 146:22da6e220af6 528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 146:22da6e220af6 529 } MPU_Type;
AnnaBridge 146:22da6e220af6 530
AnnaBridge 146:22da6e220af6 531 /* MPU Type Register Definitions */
AnnaBridge 146:22da6e220af6 532 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 146:22da6e220af6 533 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 146:22da6e220af6 534
AnnaBridge 146:22da6e220af6 535 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 146:22da6e220af6 536 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 146:22da6e220af6 537
AnnaBridge 146:22da6e220af6 538 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 146:22da6e220af6 539 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 146:22da6e220af6 540
AnnaBridge 146:22da6e220af6 541 /* MPU Control Register Definitions */
AnnaBridge 146:22da6e220af6 542 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 146:22da6e220af6 543 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 146:22da6e220af6 544
AnnaBridge 146:22da6e220af6 545 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 146:22da6e220af6 546 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 146:22da6e220af6 547
AnnaBridge 146:22da6e220af6 548 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 146:22da6e220af6 549 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 146:22da6e220af6 550
AnnaBridge 146:22da6e220af6 551 /* MPU Region Number Register Definitions */
AnnaBridge 146:22da6e220af6 552 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 146:22da6e220af6 553 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 146:22da6e220af6 554
AnnaBridge 146:22da6e220af6 555 /* MPU Region Base Address Register Definitions */
AnnaBridge 146:22da6e220af6 556 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 146:22da6e220af6 557 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 146:22da6e220af6 558
AnnaBridge 146:22da6e220af6 559 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 146:22da6e220af6 560 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 146:22da6e220af6 561
AnnaBridge 146:22da6e220af6 562 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 146:22da6e220af6 563 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 146:22da6e220af6 564
AnnaBridge 146:22da6e220af6 565 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 146:22da6e220af6 566 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 146:22da6e220af6 567 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 146:22da6e220af6 568
AnnaBridge 146:22da6e220af6 569 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 146:22da6e220af6 570 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 146:22da6e220af6 571
AnnaBridge 146:22da6e220af6 572 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 146:22da6e220af6 573 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 146:22da6e220af6 574
AnnaBridge 146:22da6e220af6 575 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 146:22da6e220af6 576 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 146:22da6e220af6 577
AnnaBridge 146:22da6e220af6 578 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 146:22da6e220af6 579 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 146:22da6e220af6 580
AnnaBridge 146:22da6e220af6 581 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 146:22da6e220af6 582 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 146:22da6e220af6 583
AnnaBridge 146:22da6e220af6 584 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 146:22da6e220af6 585 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 146:22da6e220af6 586
AnnaBridge 146:22da6e220af6 587 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 146:22da6e220af6 588 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 146:22da6e220af6 589
AnnaBridge 146:22da6e220af6 590 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 146:22da6e220af6 591 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 146:22da6e220af6 592
AnnaBridge 146:22da6e220af6 593 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 146:22da6e220af6 594 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 146:22da6e220af6 595
AnnaBridge 146:22da6e220af6 596 /*@} end of group CMSIS_MPU */
AnnaBridge 146:22da6e220af6 597 #endif
AnnaBridge 146:22da6e220af6 598
AnnaBridge 146:22da6e220af6 599
AnnaBridge 146:22da6e220af6 600 /**
AnnaBridge 146:22da6e220af6 601 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 146:22da6e220af6 603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 146:22da6e220af6 604 Therefore they are not covered by the Cortex-M0+ header file.
AnnaBridge 146:22da6e220af6 605 @{
AnnaBridge 146:22da6e220af6 606 */
AnnaBridge 146:22da6e220af6 607 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 146:22da6e220af6 608
AnnaBridge 146:22da6e220af6 609
AnnaBridge 146:22da6e220af6 610 /**
AnnaBridge 146:22da6e220af6 611 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 612 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 146:22da6e220af6 613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 146:22da6e220af6 614 @{
AnnaBridge 146:22da6e220af6 615 */
AnnaBridge 146:22da6e220af6 616
AnnaBridge 146:22da6e220af6 617 /**
AnnaBridge 146:22da6e220af6 618 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 146:22da6e220af6 619 \param[in] field Name of the register bit field.
AnnaBridge 146:22da6e220af6 620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 146:22da6e220af6 621 \return Masked and shifted value.
AnnaBridge 146:22da6e220af6 622 */
AnnaBridge 146:22da6e220af6 623 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 146:22da6e220af6 624
AnnaBridge 146:22da6e220af6 625 /**
AnnaBridge 146:22da6e220af6 626 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 146:22da6e220af6 627 \param[in] field Name of the register bit field.
AnnaBridge 146:22da6e220af6 628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 146:22da6e220af6 629 \return Masked and shifted bit field value.
AnnaBridge 146:22da6e220af6 630 */
AnnaBridge 146:22da6e220af6 631 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 146:22da6e220af6 632
AnnaBridge 146:22da6e220af6 633 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 146:22da6e220af6 634
AnnaBridge 146:22da6e220af6 635
AnnaBridge 146:22da6e220af6 636 /**
AnnaBridge 146:22da6e220af6 637 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 638 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 146:22da6e220af6 639 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 146:22da6e220af6 640 @{
AnnaBridge 146:22da6e220af6 641 */
AnnaBridge 146:22da6e220af6 642
AnnaBridge 146:22da6e220af6 643 /* Memory mapping of Core Hardware */
AnnaBridge 146:22da6e220af6 644 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 146:22da6e220af6 645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 146:22da6e220af6 646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 146:22da6e220af6 647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 146:22da6e220af6 648
AnnaBridge 146:22da6e220af6 649 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 146:22da6e220af6 650 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 146:22da6e220af6 651 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 146:22da6e220af6 652
AnnaBridge 146:22da6e220af6 653 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 146:22da6e220af6 655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 146:22da6e220af6 656 #endif
AnnaBridge 146:22da6e220af6 657
AnnaBridge 146:22da6e220af6 658 /*@} */
AnnaBridge 146:22da6e220af6 659
AnnaBridge 146:22da6e220af6 660
AnnaBridge 146:22da6e220af6 661
AnnaBridge 146:22da6e220af6 662 /*******************************************************************************
AnnaBridge 146:22da6e220af6 663 * Hardware Abstraction Layer
AnnaBridge 146:22da6e220af6 664 Core Function Interface contains:
AnnaBridge 146:22da6e220af6 665 - Core NVIC Functions
AnnaBridge 146:22da6e220af6 666 - Core SysTick Functions
AnnaBridge 146:22da6e220af6 667 - Core Register Access Functions
AnnaBridge 146:22da6e220af6 668 ******************************************************************************/
AnnaBridge 146:22da6e220af6 669 /**
AnnaBridge 146:22da6e220af6 670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 146:22da6e220af6 671 */
AnnaBridge 146:22da6e220af6 672
AnnaBridge 146:22da6e220af6 673
AnnaBridge 146:22da6e220af6 674
AnnaBridge 146:22da6e220af6 675 /* ########################## NVIC functions #################################### */
AnnaBridge 146:22da6e220af6 676 /**
AnnaBridge 146:22da6e220af6 677 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 146:22da6e220af6 679 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 146:22da6e220af6 680 @{
AnnaBridge 146:22da6e220af6 681 */
AnnaBridge 146:22da6e220af6 682
AnnaBridge 146:22da6e220af6 683 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 146:22da6e220af6 684 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 685 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 146:22da6e220af6 686 #endif
AnnaBridge 146:22da6e220af6 687 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 688 #else
AnnaBridge 146:22da6e220af6 689 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 146:22da6e220af6 690 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 146:22da6e220af6 691 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 146:22da6e220af6 692 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 146:22da6e220af6 693 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 146:22da6e220af6 694 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 146:22da6e220af6 695 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 146:22da6e220af6 696 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 146:22da6e220af6 697 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
AnnaBridge 146:22da6e220af6 698 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 146:22da6e220af6 699 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 146:22da6e220af6 700 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 146:22da6e220af6 701 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 146:22da6e220af6 702
AnnaBridge 146:22da6e220af6 703 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 146:22da6e220af6 704 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 705 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 146:22da6e220af6 706 #endif
AnnaBridge 146:22da6e220af6 707 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 708 #else
AnnaBridge 146:22da6e220af6 709 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 146:22da6e220af6 710 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 146:22da6e220af6 711 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 146:22da6e220af6 712
AnnaBridge 146:22da6e220af6 713 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 146:22da6e220af6 714
AnnaBridge 146:22da6e220af6 715
AnnaBridge 146:22da6e220af6 716 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 146:22da6e220af6 717 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 146:22da6e220af6 718 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 146:22da6e220af6 719 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 146:22da6e220af6 720 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 146:22da6e220af6 721
AnnaBridge 146:22da6e220af6 722
AnnaBridge 146:22da6e220af6 723 /**
AnnaBridge 146:22da6e220af6 724 \brief Enable Interrupt
AnnaBridge 146:22da6e220af6 725 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 726 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 727 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 728 */
AnnaBridge 146:22da6e220af6 729 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 730 {
AnnaBridge 146:22da6e220af6 731 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 732 {
AnnaBridge 146:22da6e220af6 733 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 734 }
AnnaBridge 146:22da6e220af6 735 }
AnnaBridge 146:22da6e220af6 736
AnnaBridge 146:22da6e220af6 737
AnnaBridge 146:22da6e220af6 738 /**
AnnaBridge 146:22da6e220af6 739 \brief Get Interrupt Enable status
AnnaBridge 146:22da6e220af6 740 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 741 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 742 \return 0 Interrupt is not enabled.
AnnaBridge 146:22da6e220af6 743 \return 1 Interrupt is enabled.
AnnaBridge 146:22da6e220af6 744 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 745 */
AnnaBridge 146:22da6e220af6 746 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 747 {
AnnaBridge 146:22da6e220af6 748 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 749 {
AnnaBridge 146:22da6e220af6 750 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 146:22da6e220af6 751 }
AnnaBridge 146:22da6e220af6 752 else
AnnaBridge 146:22da6e220af6 753 {
AnnaBridge 146:22da6e220af6 754 return(0U);
AnnaBridge 146:22da6e220af6 755 }
AnnaBridge 146:22da6e220af6 756 }
AnnaBridge 146:22da6e220af6 757
AnnaBridge 146:22da6e220af6 758
AnnaBridge 146:22da6e220af6 759 /**
AnnaBridge 146:22da6e220af6 760 \brief Disable Interrupt
AnnaBridge 146:22da6e220af6 761 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 762 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 763 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 764 */
AnnaBridge 146:22da6e220af6 765 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 766 {
AnnaBridge 146:22da6e220af6 767 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 768 {
AnnaBridge 146:22da6e220af6 769 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 770 __DSB();
AnnaBridge 146:22da6e220af6 771 __ISB();
AnnaBridge 146:22da6e220af6 772 }
AnnaBridge 146:22da6e220af6 773 }
AnnaBridge 146:22da6e220af6 774
AnnaBridge 146:22da6e220af6 775
AnnaBridge 146:22da6e220af6 776 /**
AnnaBridge 146:22da6e220af6 777 \brief Get Pending Interrupt
AnnaBridge 146:22da6e220af6 778 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 146:22da6e220af6 779 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 780 \return 0 Interrupt status is not pending.
AnnaBridge 146:22da6e220af6 781 \return 1 Interrupt status is pending.
AnnaBridge 146:22da6e220af6 782 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 783 */
AnnaBridge 146:22da6e220af6 784 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 785 {
AnnaBridge 146:22da6e220af6 786 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 787 {
AnnaBridge 146:22da6e220af6 788 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 146:22da6e220af6 789 }
AnnaBridge 146:22da6e220af6 790 else
AnnaBridge 146:22da6e220af6 791 {
AnnaBridge 146:22da6e220af6 792 return(0U);
AnnaBridge 146:22da6e220af6 793 }
AnnaBridge 146:22da6e220af6 794 }
AnnaBridge 146:22da6e220af6 795
AnnaBridge 146:22da6e220af6 796
AnnaBridge 146:22da6e220af6 797 /**
AnnaBridge 146:22da6e220af6 798 \brief Set Pending Interrupt
AnnaBridge 146:22da6e220af6 799 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 146:22da6e220af6 800 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 801 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 802 */
AnnaBridge 146:22da6e220af6 803 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 804 {
AnnaBridge 146:22da6e220af6 805 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 806 {
AnnaBridge 146:22da6e220af6 807 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 808 }
AnnaBridge 146:22da6e220af6 809 }
AnnaBridge 146:22da6e220af6 810
AnnaBridge 146:22da6e220af6 811
AnnaBridge 146:22da6e220af6 812 /**
AnnaBridge 146:22da6e220af6 813 \brief Clear Pending Interrupt
AnnaBridge 146:22da6e220af6 814 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 146:22da6e220af6 815 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 816 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 817 */
AnnaBridge 146:22da6e220af6 818 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 819 {
AnnaBridge 146:22da6e220af6 820 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 821 {
AnnaBridge 146:22da6e220af6 822 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 823 }
AnnaBridge 146:22da6e220af6 824 }
AnnaBridge 146:22da6e220af6 825
AnnaBridge 146:22da6e220af6 826
AnnaBridge 146:22da6e220af6 827 /**
AnnaBridge 146:22da6e220af6 828 \brief Set Interrupt Priority
AnnaBridge 146:22da6e220af6 829 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 146:22da6e220af6 830 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 831 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 832 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 833 \param [in] priority Priority to set.
AnnaBridge 146:22da6e220af6 834 \note The priority cannot be set for every processor exception.
AnnaBridge 146:22da6e220af6 835 */
AnnaBridge 146:22da6e220af6 836 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 146:22da6e220af6 837 {
AnnaBridge 146:22da6e220af6 838 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 839 {
AnnaBridge 146:22da6e220af6 840 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 146:22da6e220af6 841 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 146:22da6e220af6 842 }
AnnaBridge 146:22da6e220af6 843 else
AnnaBridge 146:22da6e220af6 844 {
AnnaBridge 146:22da6e220af6 845 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 146:22da6e220af6 846 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 146:22da6e220af6 847 }
AnnaBridge 146:22da6e220af6 848 }
AnnaBridge 146:22da6e220af6 849
AnnaBridge 146:22da6e220af6 850
AnnaBridge 146:22da6e220af6 851 /**
AnnaBridge 146:22da6e220af6 852 \brief Get Interrupt Priority
AnnaBridge 146:22da6e220af6 853 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 146:22da6e220af6 854 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 855 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 856 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 857 \return Interrupt Priority.
AnnaBridge 146:22da6e220af6 858 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 146:22da6e220af6 859 */
AnnaBridge 146:22da6e220af6 860 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 861 {
AnnaBridge 146:22da6e220af6 862
AnnaBridge 146:22da6e220af6 863 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 864 {
AnnaBridge 146:22da6e220af6 865 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 146:22da6e220af6 866 }
AnnaBridge 146:22da6e220af6 867 else
AnnaBridge 146:22da6e220af6 868 {
AnnaBridge 146:22da6e220af6 869 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 146:22da6e220af6 870 }
AnnaBridge 146:22da6e220af6 871 }
AnnaBridge 146:22da6e220af6 872
AnnaBridge 146:22da6e220af6 873
AnnaBridge 146:22da6e220af6 874 /**
AnnaBridge 146:22da6e220af6 875 \brief Set Interrupt Vector
AnnaBridge 146:22da6e220af6 876 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 146:22da6e220af6 877 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 878 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 879 VTOR must been relocated to SRAM before.
AnnaBridge 146:22da6e220af6 880 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 146:22da6e220af6 881 \param [in] IRQn Interrupt number
AnnaBridge 146:22da6e220af6 882 \param [in] vector Address of interrupt handler function
AnnaBridge 146:22da6e220af6 883 */
AnnaBridge 146:22da6e220af6 884 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 146:22da6e220af6 885 {
AnnaBridge 146:22da6e220af6 886 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 887 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 146:22da6e220af6 888 #else
AnnaBridge 146:22da6e220af6 889 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 146:22da6e220af6 890 #endif
AnnaBridge 146:22da6e220af6 891 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 146:22da6e220af6 892 }
AnnaBridge 146:22da6e220af6 893
AnnaBridge 146:22da6e220af6 894
AnnaBridge 146:22da6e220af6 895 /**
AnnaBridge 146:22da6e220af6 896 \brief Get Interrupt Vector
AnnaBridge 146:22da6e220af6 897 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 146:22da6e220af6 898 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 899 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 900 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 901 \return Address of interrupt handler function
AnnaBridge 146:22da6e220af6 902 */
AnnaBridge 146:22da6e220af6 903 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 904 {
AnnaBridge 146:22da6e220af6 905 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 906 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 146:22da6e220af6 907 #else
AnnaBridge 146:22da6e220af6 908 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 146:22da6e220af6 909 #endif
AnnaBridge 146:22da6e220af6 910 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 146:22da6e220af6 911
AnnaBridge 146:22da6e220af6 912 }
AnnaBridge 146:22da6e220af6 913
AnnaBridge 146:22da6e220af6 914
AnnaBridge 146:22da6e220af6 915 /**
AnnaBridge 146:22da6e220af6 916 \brief System Reset
AnnaBridge 146:22da6e220af6 917 \details Initiates a system reset request to reset the MCU.
AnnaBridge 146:22da6e220af6 918 */
AnnaBridge 146:22da6e220af6 919 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 146:22da6e220af6 920 {
AnnaBridge 146:22da6e220af6 921 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 146:22da6e220af6 922 buffered write are completed before reset */
AnnaBridge 146:22da6e220af6 923 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 146:22da6e220af6 924 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 146:22da6e220af6 925 __DSB(); /* Ensure completion of memory access */
AnnaBridge 146:22da6e220af6 926
AnnaBridge 146:22da6e220af6 927 for(;;) /* wait until reset */
AnnaBridge 146:22da6e220af6 928 {
AnnaBridge 146:22da6e220af6 929 __NOP();
AnnaBridge 146:22da6e220af6 930 }
AnnaBridge 146:22da6e220af6 931 }
AnnaBridge 146:22da6e220af6 932
AnnaBridge 146:22da6e220af6 933 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 146:22da6e220af6 934
AnnaBridge 146:22da6e220af6 935
AnnaBridge 146:22da6e220af6 936 /* ########################## FPU functions #################################### */
AnnaBridge 146:22da6e220af6 937 /**
AnnaBridge 146:22da6e220af6 938 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 939 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 146:22da6e220af6 940 \brief Function that provides FPU type.
AnnaBridge 146:22da6e220af6 941 @{
AnnaBridge 146:22da6e220af6 942 */
AnnaBridge 146:22da6e220af6 943
AnnaBridge 146:22da6e220af6 944 /**
AnnaBridge 146:22da6e220af6 945 \brief get FPU type
AnnaBridge 146:22da6e220af6 946 \details returns the FPU type
AnnaBridge 146:22da6e220af6 947 \returns
AnnaBridge 146:22da6e220af6 948 - \b 0: No FPU
AnnaBridge 146:22da6e220af6 949 - \b 1: Single precision FPU
AnnaBridge 146:22da6e220af6 950 - \b 2: Double + Single precision FPU
AnnaBridge 146:22da6e220af6 951 */
AnnaBridge 146:22da6e220af6 952 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 146:22da6e220af6 953 {
AnnaBridge 146:22da6e220af6 954 return 0U; /* No FPU */
AnnaBridge 146:22da6e220af6 955 }
AnnaBridge 146:22da6e220af6 956
AnnaBridge 146:22da6e220af6 957
AnnaBridge 146:22da6e220af6 958 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 146:22da6e220af6 959
AnnaBridge 146:22da6e220af6 960
AnnaBridge 146:22da6e220af6 961
AnnaBridge 146:22da6e220af6 962 /* ################################## SysTick function ############################################ */
AnnaBridge 146:22da6e220af6 963 /**
AnnaBridge 146:22da6e220af6 964 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 965 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 146:22da6e220af6 966 \brief Functions that configure the System.
AnnaBridge 146:22da6e220af6 967 @{
AnnaBridge 146:22da6e220af6 968 */
AnnaBridge 146:22da6e220af6 969
AnnaBridge 146:22da6e220af6 970 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 146:22da6e220af6 971
AnnaBridge 146:22da6e220af6 972 /**
AnnaBridge 146:22da6e220af6 973 \brief System Tick Configuration
AnnaBridge 146:22da6e220af6 974 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 146:22da6e220af6 975 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 146:22da6e220af6 976 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 146:22da6e220af6 977 \return 0 Function succeeded.
AnnaBridge 146:22da6e220af6 978 \return 1 Function failed.
AnnaBridge 146:22da6e220af6 979 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 146:22da6e220af6 980 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 146:22da6e220af6 981 must contain a vendor-specific implementation of this function.
AnnaBridge 146:22da6e220af6 982 */
AnnaBridge 146:22da6e220af6 983 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 146:22da6e220af6 984 {
AnnaBridge 146:22da6e220af6 985 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 146:22da6e220af6 986 {
AnnaBridge 146:22da6e220af6 987 return (1UL); /* Reload value impossible */
AnnaBridge 146:22da6e220af6 988 }
AnnaBridge 146:22da6e220af6 989
AnnaBridge 146:22da6e220af6 990 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 146:22da6e220af6 991 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 146:22da6e220af6 992 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 146:22da6e220af6 993 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 146:22da6e220af6 994 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 146:22da6e220af6 995 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 146:22da6e220af6 996 return (0UL); /* Function successful */
AnnaBridge 146:22da6e220af6 997 }
AnnaBridge 146:22da6e220af6 998
AnnaBridge 146:22da6e220af6 999 #endif
AnnaBridge 146:22da6e220af6 1000
AnnaBridge 146:22da6e220af6 1001 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 146:22da6e220af6 1002
AnnaBridge 146:22da6e220af6 1003
AnnaBridge 146:22da6e220af6 1004
AnnaBridge 146:22da6e220af6 1005
AnnaBridge 146:22da6e220af6 1006 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 1007 }
AnnaBridge 146:22da6e220af6 1008 #endif
AnnaBridge 146:22da6e220af6 1009
AnnaBridge 146:22da6e220af6 1010 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
AnnaBridge 146:22da6e220af6 1011
AnnaBridge 146:22da6e220af6 1012 #endif /* __CMSIS_GENERIC */