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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F334C8/TARGET_STM/mbed_rtx.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
146:22da6e220af6
Child:
148:fd96258d940d
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /* mbed Microcontroller Library
<> 128:9bcdf88f62b0 2 * Copyright (c) 2016 ARM Limited
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 128:9bcdf88f62b0 5 * you may not use this file except in compliance with the License.
<> 128:9bcdf88f62b0 6 * You may obtain a copy of the License at
<> 128:9bcdf88f62b0 7 *
<> 128:9bcdf88f62b0 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Unless required by applicable law or agreed to in writing, software
<> 128:9bcdf88f62b0 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 128:9bcdf88f62b0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 128:9bcdf88f62b0 13 * See the License for the specific language governing permissions and
<> 128:9bcdf88f62b0 14 * limitations under the License.
<> 128:9bcdf88f62b0 15 */
<> 128:9bcdf88f62b0 16
<> 128:9bcdf88f62b0 17 #ifndef MBED_MBED_RTX_H
<> 128:9bcdf88f62b0 18 #define MBED_MBED_RTX_H
<> 128:9bcdf88f62b0 19
<> 128:9bcdf88f62b0 20 #if defined(TARGET_STM32F051R8)
<> 128:9bcdf88f62b0 21
<> 128:9bcdf88f62b0 22 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 23 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 24 #endif
<> 128:9bcdf88f62b0 25
<> 128:9bcdf88f62b0 26 #elif defined(TARGET_STM32L031K6)
<> 128:9bcdf88f62b0 27
<> 128:9bcdf88f62b0 28 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 29 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 30 #endif
<> 128:9bcdf88f62b0 31
<> 128:9bcdf88f62b0 32 #elif defined(TARGET_STM32F070RB)
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 35 #define INITIAL_SP (0x20004000UL)
<> 128:9bcdf88f62b0 36 #endif
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 #elif defined(TARGET_STM32F072RB)
<> 128:9bcdf88f62b0 39
<> 128:9bcdf88f62b0 40 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 41 #define INITIAL_SP (0x20004000UL)
<> 128:9bcdf88f62b0 42 #endif
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 #elif defined(TARGET_STM32F091RC)
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 47 #define INITIAL_SP (0x20008000UL)
<> 128:9bcdf88f62b0 48 #endif
<> 128:9bcdf88f62b0 49
<> 128:9bcdf88f62b0 50 #elif defined(TARGET_STM32F100RB)
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 53 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 54 #endif
<> 128:9bcdf88f62b0 55
<> 128:9bcdf88f62b0 56 #elif defined(TARGET_STM32F103RB)
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 59 #define INITIAL_SP (0x20005000UL)
<> 128:9bcdf88f62b0 60 #endif
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 #elif defined(TARGET_STM32F207ZG)
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 65 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 66 #endif
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 #elif defined(TARGET_STM32F303VC)
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 71 #define INITIAL_SP (0x2000A000UL)
<> 128:9bcdf88f62b0 72 #endif
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 #elif defined(TARGET_STM32F334C8)
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 77 #define INITIAL_SP (0x20003000UL)
<> 128:9bcdf88f62b0 78 #endif
<> 128:9bcdf88f62b0 79
<> 128:9bcdf88f62b0 80 #elif defined(TARGET_STM32F302R8)
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 83 #define INITIAL_SP (0x20004000UL)
<> 128:9bcdf88f62b0 84 #endif
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 #elif defined(TARGET_STM32F303K8)
<> 128:9bcdf88f62b0 87
<> 128:9bcdf88f62b0 88 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 89 #define INITIAL_SP (0x20003000UL)
<> 128:9bcdf88f62b0 90 #endif
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 #elif defined(TARGET_STM32F303RE)
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 95 #define INITIAL_SP (0x20010000UL)
<> 128:9bcdf88f62b0 96 #endif
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 #elif defined(TARGET_STM32F303ZE)
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 101 #define INITIAL_SP (0x20010000UL)
<> 128:9bcdf88f62b0 102 #endif
<> 128:9bcdf88f62b0 103
<> 128:9bcdf88f62b0 104 #elif defined(TARGET_STM32F334R8)
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 107 #define INITIAL_SP (0x20003000UL)
<> 128:9bcdf88f62b0 108 #endif
<> 128:9bcdf88f62b0 109
<> 128:9bcdf88f62b0 110 #elif defined(TARGET_STM32F446VE)
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 113 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 114 #endif
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 #elif defined(TARGET_STM32F401VC)
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 119 #define INITIAL_SP (0x20010000UL)
<> 128:9bcdf88f62b0 120 #endif
<> 128:9bcdf88f62b0 121
<> 128:9bcdf88f62b0 122 #elif (defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F439ZI))
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 125 #define INITIAL_SP (0x20030000UL)
<> 128:9bcdf88f62b0 126 #endif
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 #elif defined(TARGET_UBLOX_EVK_ODIN_W2)
<> 128:9bcdf88f62b0 129
<> 128:9bcdf88f62b0 130 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 131 #define INITIAL_SP (0x20030000UL)
<> 128:9bcdf88f62b0 132 #endif
<> 128:9bcdf88f62b0 133
<> 140:97feb9bacc10 134 #elif defined(TARGET_UBLOX_C030)
<> 140:97feb9bacc10 135
<> 140:97feb9bacc10 136 #ifndef INITIAL_SP
<> 140:97feb9bacc10 137 #define INITIAL_SP (0x20030000UL)
<> 140:97feb9bacc10 138 #endif
<> 140:97feb9bacc10 139
<> 128:9bcdf88f62b0 140 #elif defined(TARGET_STM32F469NI)
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 143 #define INITIAL_SP (0x20050000UL)
<> 128:9bcdf88f62b0 144 #endif
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 #elif defined(TARGET_STM32F405RG)
<> 128:9bcdf88f62b0 147
<> 128:9bcdf88f62b0 148 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 149 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 150 #endif
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 #elif defined(TARGET_STM32F401RE)
<> 128:9bcdf88f62b0 153
<> 128:9bcdf88f62b0 154 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 155 #define INITIAL_SP (0x20018000UL)
<> 128:9bcdf88f62b0 156 #endif
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 #elif defined(TARGET_STM32F410RB)
<> 128:9bcdf88f62b0 159
<> 128:9bcdf88f62b0 160 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 161 #define INITIAL_SP (0x20008000UL)
<> 128:9bcdf88f62b0 162 #endif
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 #elif defined(TARGET_MTS_MDOT_F411RE) || defined (TARGET_MTS_DRAGONFLY_F411RE)
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 167 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 168 #endif
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 #elif defined(TARGET_STM32F411RE)
<> 128:9bcdf88f62b0 171
<> 128:9bcdf88f62b0 172 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 173 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 174 #endif
<> 128:9bcdf88f62b0 175
<> 132:9baf128c2fab 176 #elif defined(TARGET_STM32F412ZG)
<> 132:9baf128c2fab 177
<> 132:9baf128c2fab 178 #ifndef INITIAL_SP
<> 132:9baf128c2fab 179 #define INITIAL_SP (0x20040000UL)
<> 132:9baf128c2fab 180 #endif
<> 132:9baf128c2fab 181
AnnaBridge 146:22da6e220af6 182 #elif defined(TARGET_STM32F413ZH)
AnnaBridge 146:22da6e220af6 183
AnnaBridge 146:22da6e220af6 184 #ifndef INITIAL_SP
AnnaBridge 146:22da6e220af6 185 #define INITIAL_SP (0x20050000UL)
AnnaBridge 146:22da6e220af6 186 #endif
AnnaBridge 146:22da6e220af6 187 #ifndef OS_TASKCNT
AnnaBridge 146:22da6e220af6 188 #define OS_TASKCNT 14
AnnaBridge 146:22da6e220af6 189 #endif
AnnaBridge 146:22da6e220af6 190 #ifndef OS_MAINSTKSIZE
AnnaBridge 146:22da6e220af6 191 #define OS_MAINSTKSIZE 256
AnnaBridge 146:22da6e220af6 192 #endif
AnnaBridge 146:22da6e220af6 193 #ifndef OS_CLOCK
AnnaBridge 146:22da6e220af6 194 #define OS_CLOCK 100000000
AnnaBridge 146:22da6e220af6 195 #endif
AnnaBridge 146:22da6e220af6 196
AnnaBridge 146:22da6e220af6 197
<> 128:9bcdf88f62b0 198 #elif defined(TARGET_STM32F446RE)
<> 128:9bcdf88f62b0 199
<> 128:9bcdf88f62b0 200 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 201 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 202 #endif
<> 128:9bcdf88f62b0 203
<> 128:9bcdf88f62b0 204 #elif defined(TARGET_STM32F446ZE)
<> 128:9bcdf88f62b0 205
<> 128:9bcdf88f62b0 206 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 207 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 208 #endif
<> 128:9bcdf88f62b0 209
<> 128:9bcdf88f62b0 210 #elif defined(TARGET_STM32F407VG)
<> 128:9bcdf88f62b0 211
<> 128:9bcdf88f62b0 212 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 213 #define INITIAL_SP (0x20020000UL)
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 #elif defined(TARGET_STM32F746NG)
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 219 #define INITIAL_SP (0x20050000UL)
<> 128:9bcdf88f62b0 220 #endif
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 #elif (defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F756ZG))
<> 128:9bcdf88f62b0 223
<> 128:9bcdf88f62b0 224 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 225 #define INITIAL_SP (0x20050000UL)
<> 128:9bcdf88f62b0 226 #endif
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 #elif defined(TARGET_STM32F767ZI)
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 231 #define INITIAL_SP (0x20080000UL)
<> 128:9bcdf88f62b0 232 #endif
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 #elif defined(TARGET_STM32F769NI)
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 237 #define INITIAL_SP (0x20080000UL)
<> 128:9bcdf88f62b0 238 #endif
<> 128:9bcdf88f62b0 239
<> 128:9bcdf88f62b0 240 #elif defined(TARGET_STM32L053C8)
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 243 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 244 #endif
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 #elif defined(TARGET_STM32L031K6)
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 249 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 250 #endif
<> 128:9bcdf88f62b0 251
<> 128:9bcdf88f62b0 252 #elif defined(TARGET_STM32L053R8)
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 255 #define INITIAL_SP (0x20002000UL)
<> 128:9bcdf88f62b0 256 #endif
<> 128:9bcdf88f62b0 257
AnnaBridge 143:86740a56073b 258 #elif defined(TARGET_STM32L072CZ)
AnnaBridge 143:86740a56073b 259
AnnaBridge 143:86740a56073b 260 #ifndef INITIAL_SP
AnnaBridge 143:86740a56073b 261 #define INITIAL_SP (0x20005000UL)
AnnaBridge 143:86740a56073b 262 #endif
AnnaBridge 143:86740a56073b 263
<> 128:9bcdf88f62b0 264 #elif defined(TARGET_STM32L073RZ)
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 267 #define INITIAL_SP (0x20005000UL)
<> 128:9bcdf88f62b0 268 #endif
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 #elif defined(TARGET_STM32L152RC)
<> 128:9bcdf88f62b0 271
<> 128:9bcdf88f62b0 272 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 273 #define INITIAL_SP (0x20008000UL)
<> 128:9bcdf88f62b0 274 #endif
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 #elif defined(TARGET_STM32L152RE)
<> 128:9bcdf88f62b0 277
<> 128:9bcdf88f62b0 278 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 279 #define INITIAL_SP (0x20014000UL)
<> 128:9bcdf88f62b0 280 #endif
<> 128:9bcdf88f62b0 281
<> 128:9bcdf88f62b0 282 #elif defined(TARGET_NZ32_SC151)
<> 128:9bcdf88f62b0 283
<> 128:9bcdf88f62b0 284 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 285 #define INITIAL_SP (0x20008000UL)
<> 128:9bcdf88f62b0 286 #endif
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 #elif defined(TARGET_XDOT_L151CC)
<> 128:9bcdf88f62b0 289
<> 128:9bcdf88f62b0 290 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 291 #define INITIAL_SP (0x20008000UL)
<> 128:9bcdf88f62b0 292 #endif
<> 128:9bcdf88f62b0 293
AnnaBridge 145:64910690c574 294 #elif defined(TARGET_STM32L476VG) || defined(TARGET_STM32L475VG)
<> 128:9bcdf88f62b0 295
<> 128:9bcdf88f62b0 296 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 297 #define INITIAL_SP (0x20018000UL)
<> 128:9bcdf88f62b0 298 #endif
<> 128:9bcdf88f62b0 299
<> 128:9bcdf88f62b0 300 #elif defined(TARGET_STM32L432KC)
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 303 #define INITIAL_SP (0x2000C000UL)
<> 128:9bcdf88f62b0 304 #endif
<> 128:9bcdf88f62b0 305
<> 128:9bcdf88f62b0 306 #elif (defined(TARGET_STM32L476RG) || defined(TARGET_STM32L486RG))
<> 128:9bcdf88f62b0 307
<> 128:9bcdf88f62b0 308 #ifndef INITIAL_SP
<> 128:9bcdf88f62b0 309 #define INITIAL_SP (0x20018000UL)
<> 128:9bcdf88f62b0 310 #endif
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312 #endif
<> 128:9bcdf88f62b0 313
<> 128:9bcdf88f62b0 314 #endif // MBED_MBED_RTX_H