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TARGET_THUNDERBOARD_SENSE/core_cmSecureAccess.h@132:9baf128c2fab, 2016-12-20 (annotated)
- Committer:
- <>
- Date:
- Tue Dec 20 15:36:52 2016 +0000
- Revision:
- 132:9baf128c2fab
- Child:
- 136:ef9c61f8c49f
Release 132 of the mbed library
Ports for Upcoming Targets
3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241
3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291
Fixes and Changes
3062: TARGET_STM :USB device FS https://github.com/ARMmbed/mbed-os/pull/3062
3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213
3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288
3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289
3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302
3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320
3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321
3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352
3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322
3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345
3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309
3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157
3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301
3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303
3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304
3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318
3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317
3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312
3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324
3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369
3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377
3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378
3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382
3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399
3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409
3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416
3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348
3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366
3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379
3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393
3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408
3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411
3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424
3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427
3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429
3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 132:9baf128c2fab | 1 | /**************************************************************************//** |
<> | 132:9baf128c2fab | 2 | * @file core_cmSecureAccess.h |
<> | 132:9baf128c2fab | 3 | * @brief CMSIS Cortex-M Core Secure Access Header File |
<> | 132:9baf128c2fab | 4 | * @version XXX |
<> | 132:9baf128c2fab | 5 | * @date 10. June 2016 |
<> | 132:9baf128c2fab | 6 | * |
<> | 132:9baf128c2fab | 7 | * @note |
<> | 132:9baf128c2fab | 8 | * |
<> | 132:9baf128c2fab | 9 | ******************************************************************************/ |
<> | 132:9baf128c2fab | 10 | /* Copyright (c) 2016 ARM LIMITED |
<> | 132:9baf128c2fab | 11 | |
<> | 132:9baf128c2fab | 12 | All rights reserved. |
<> | 132:9baf128c2fab | 13 | Redistribution and use in source and binary forms, with or without |
<> | 132:9baf128c2fab | 14 | modification, are permitted provided that the following conditions are met: |
<> | 132:9baf128c2fab | 15 | - Redistributions of source code must retain the above copyright |
<> | 132:9baf128c2fab | 16 | notice, this list of conditions and the following disclaimer. |
<> | 132:9baf128c2fab | 17 | - Redistributions in binary form must reproduce the above copyright |
<> | 132:9baf128c2fab | 18 | notice, this list of conditions and the following disclaimer in the |
<> | 132:9baf128c2fab | 19 | documentation and/or other materials provided with the distribution. |
<> | 132:9baf128c2fab | 20 | - Neither the name of ARM nor the names of its contributors may be used |
<> | 132:9baf128c2fab | 21 | to endorse or promote products derived from this software without |
<> | 132:9baf128c2fab | 22 | specific prior written permission. |
<> | 132:9baf128c2fab | 23 | * |
<> | 132:9baf128c2fab | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 132:9baf128c2fab | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 132:9baf128c2fab | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
<> | 132:9baf128c2fab | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
<> | 132:9baf128c2fab | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
<> | 132:9baf128c2fab | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
<> | 132:9baf128c2fab | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
<> | 132:9baf128c2fab | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
<> | 132:9baf128c2fab | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
<> | 132:9baf128c2fab | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
<> | 132:9baf128c2fab | 34 | POSSIBILITY OF SUCH DAMAGE. |
<> | 132:9baf128c2fab | 35 | ---------------------------------------------------------------------------*/ |
<> | 132:9baf128c2fab | 36 | |
<> | 132:9baf128c2fab | 37 | |
<> | 132:9baf128c2fab | 38 | #ifndef __CORE_CM_SECURE_ACCESS_H |
<> | 132:9baf128c2fab | 39 | #define __CORE_CM_SECURE_ACCESS_H |
<> | 132:9baf128c2fab | 40 | |
<> | 132:9baf128c2fab | 41 | |
<> | 132:9baf128c2fab | 42 | /* ########################### Core Secure Access ########################### */ |
<> | 132:9baf128c2fab | 43 | |
<> | 132:9baf128c2fab | 44 | #ifdef FEATURE_UVISOR |
<> | 132:9baf128c2fab | 45 | #include "uvisor-lib.h" |
<> | 132:9baf128c2fab | 46 | |
<> | 132:9baf128c2fab | 47 | /* Secure uVisor implementation. */ |
<> | 132:9baf128c2fab | 48 | |
<> | 132:9baf128c2fab | 49 | /** Set the value at the target address. |
<> | 132:9baf128c2fab | 50 | * |
<> | 132:9baf128c2fab | 51 | * Equivalent to: `*address = value`. |
<> | 132:9baf128c2fab | 52 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 53 | * @param value[in] Value to write at the address location. |
<> | 132:9baf128c2fab | 54 | */ |
<> | 132:9baf128c2fab | 55 | #define SECURE_WRITE(address, value) \ |
<> | 132:9baf128c2fab | 56 | uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL) |
<> | 132:9baf128c2fab | 57 | |
<> | 132:9baf128c2fab | 58 | /** Get the value at the target address. |
<> | 132:9baf128c2fab | 59 | * |
<> | 132:9baf128c2fab | 60 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 61 | * @returns The value `*address`. |
<> | 132:9baf128c2fab | 62 | */ |
<> | 132:9baf128c2fab | 63 | #define SECURE_READ(address) \ |
<> | 132:9baf128c2fab | 64 | uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL) |
<> | 132:9baf128c2fab | 65 | |
<> | 132:9baf128c2fab | 66 | /** Get the selected bits at the target address. |
<> | 132:9baf128c2fab | 67 | * |
<> | 132:9baf128c2fab | 68 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 69 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 70 | * @returns The value `*address & mask`. |
<> | 132:9baf128c2fab | 71 | */ |
<> | 132:9baf128c2fab | 72 | #define SECURE_BITS_GET(address, mask) \ |
<> | 132:9baf128c2fab | 73 | UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask) |
<> | 132:9baf128c2fab | 74 | |
<> | 132:9baf128c2fab | 75 | /** Check the selected bits at the target address. |
<> | 132:9baf128c2fab | 76 | * |
<> | 132:9baf128c2fab | 77 | * @param address[in] Address at which to check the bits |
<> | 132:9baf128c2fab | 78 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 79 | * @returns The value `((*address & mask) == mask)`. |
<> | 132:9baf128c2fab | 80 | */ |
<> | 132:9baf128c2fab | 81 | #define SECURE_BITS_CHECK(address, mask) \ |
<> | 132:9baf128c2fab | 82 | UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask) |
<> | 132:9baf128c2fab | 83 | |
<> | 132:9baf128c2fab | 84 | /** Set the selected bits to 1 at the target address. |
<> | 132:9baf128c2fab | 85 | * |
<> | 132:9baf128c2fab | 86 | * Equivalent to: `*address |= mask`. |
<> | 132:9baf128c2fab | 87 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 88 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 89 | */ |
<> | 132:9baf128c2fab | 90 | #define SECURE_BITS_SET(address, mask) \ |
<> | 132:9baf128c2fab | 91 | UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask) |
<> | 132:9baf128c2fab | 92 | |
<> | 132:9baf128c2fab | 93 | /** Clear the selected bits at the target address. |
<> | 132:9baf128c2fab | 94 | * |
<> | 132:9baf128c2fab | 95 | * Equivalent to: `*address &= ~mask`. |
<> | 132:9baf128c2fab | 96 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 97 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 98 | */ |
<> | 132:9baf128c2fab | 99 | #define SECURE_BITS_CLEAR(address, mask) \ |
<> | 132:9baf128c2fab | 100 | UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask) |
<> | 132:9baf128c2fab | 101 | |
<> | 132:9baf128c2fab | 102 | /** Set the selected bits at the target address to the given value. |
<> | 132:9baf128c2fab | 103 | * |
<> | 132:9baf128c2fab | 104 | * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. |
<> | 132:9baf128c2fab | 105 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 106 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 107 | * @param value[in] Value to write at the address location. Note: The value |
<> | 132:9baf128c2fab | 108 | * must be already shifted to the correct bit position |
<> | 132:9baf128c2fab | 109 | */ |
<> | 132:9baf128c2fab | 110 | #define SECURE_BITS_SET_VALUE(address, mask, value) \ |
<> | 132:9baf128c2fab | 111 | UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value) |
<> | 132:9baf128c2fab | 112 | |
<> | 132:9baf128c2fab | 113 | /** Toggle the selected bits at the target address. |
<> | 132:9baf128c2fab | 114 | * |
<> | 132:9baf128c2fab | 115 | * Equivalent to: `*address ^= mask`. |
<> | 132:9baf128c2fab | 116 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 117 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 118 | */ |
<> | 132:9baf128c2fab | 119 | #define SECURE_BITS_TOGGLE(address, mask) \ |
<> | 132:9baf128c2fab | 120 | UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask) |
<> | 132:9baf128c2fab | 121 | |
<> | 132:9baf128c2fab | 122 | #else |
<> | 132:9baf128c2fab | 123 | |
<> | 132:9baf128c2fab | 124 | /* Insecure fallback implementation. */ |
<> | 132:9baf128c2fab | 125 | |
<> | 132:9baf128c2fab | 126 | /** Set the value at the target address. |
<> | 132:9baf128c2fab | 127 | * |
<> | 132:9baf128c2fab | 128 | * Equivalent to: `*address = value`. |
<> | 132:9baf128c2fab | 129 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 130 | * @param value[in] Value to write at the address location. |
<> | 132:9baf128c2fab | 131 | */ |
<> | 132:9baf128c2fab | 132 | #define SECURE_WRITE(address, value) \ |
<> | 132:9baf128c2fab | 133 | *(address) = (value) |
<> | 132:9baf128c2fab | 134 | |
<> | 132:9baf128c2fab | 135 | /** Get the value at the target address. |
<> | 132:9baf128c2fab | 136 | * |
<> | 132:9baf128c2fab | 137 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 138 | * @returns The value `*address`. |
<> | 132:9baf128c2fab | 139 | */ |
<> | 132:9baf128c2fab | 140 | #define SECURE_READ(address) \ |
<> | 132:9baf128c2fab | 141 | (*(address)) |
<> | 132:9baf128c2fab | 142 | |
<> | 132:9baf128c2fab | 143 | /** Get the selected bits at the target address. |
<> | 132:9baf128c2fab | 144 | * |
<> | 132:9baf128c2fab | 145 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 146 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 147 | * @returns The value `*address & mask`. |
<> | 132:9baf128c2fab | 148 | */ |
<> | 132:9baf128c2fab | 149 | #define SECURE_BITS_GET(address, mask) \ |
<> | 132:9baf128c2fab | 150 | (*(address) & (mask)) |
<> | 132:9baf128c2fab | 151 | |
<> | 132:9baf128c2fab | 152 | /** Check the selected bits at the target address. |
<> | 132:9baf128c2fab | 153 | * |
<> | 132:9baf128c2fab | 154 | * @param address[in] Address at which to check the bits |
<> | 132:9baf128c2fab | 155 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 156 | * @returns The value `((*address & mask) == mask)`. |
<> | 132:9baf128c2fab | 157 | */ |
<> | 132:9baf128c2fab | 158 | #define SECURE_BITS_CHECK(address, mask) \ |
<> | 132:9baf128c2fab | 159 | ((*(address) & (mask)) == (mask)) |
<> | 132:9baf128c2fab | 160 | |
<> | 132:9baf128c2fab | 161 | /** Set the selected bits to 1 at the target address. |
<> | 132:9baf128c2fab | 162 | * |
<> | 132:9baf128c2fab | 163 | * Equivalent to: `*address |= mask`. |
<> | 132:9baf128c2fab | 164 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 165 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 166 | */ |
<> | 132:9baf128c2fab | 167 | #define SECURE_BITS_SET(address, mask) \ |
<> | 132:9baf128c2fab | 168 | *(address) |= (mask) |
<> | 132:9baf128c2fab | 169 | |
<> | 132:9baf128c2fab | 170 | /** Clear the selected bits at the target address. |
<> | 132:9baf128c2fab | 171 | * |
<> | 132:9baf128c2fab | 172 | * Equivalent to: `*address &= ~mask`. |
<> | 132:9baf128c2fab | 173 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 174 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 175 | */ |
<> | 132:9baf128c2fab | 176 | #define SECURE_BITS_CLEAR(address, mask) \ |
<> | 132:9baf128c2fab | 177 | *(address) &= ~(mask) |
<> | 132:9baf128c2fab | 178 | |
<> | 132:9baf128c2fab | 179 | /** Set the selected bits at the target address to the given value. |
<> | 132:9baf128c2fab | 180 | * |
<> | 132:9baf128c2fab | 181 | * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. |
<> | 132:9baf128c2fab | 182 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 183 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 184 | * @param value[in] Value to write at the address location. Note: The value |
<> | 132:9baf128c2fab | 185 | * must be already shifted to the correct bit position |
<> | 132:9baf128c2fab | 186 | */ |
<> | 132:9baf128c2fab | 187 | #define SECURE_BITS_SET_VALUE(address, mask, value) \ |
<> | 132:9baf128c2fab | 188 | *(address) = (*(address) & ~(mask)) | ((value) & (mask)) |
<> | 132:9baf128c2fab | 189 | |
<> | 132:9baf128c2fab | 190 | /** Toggle the selected bits at the target address. |
<> | 132:9baf128c2fab | 191 | * |
<> | 132:9baf128c2fab | 192 | * Equivalent to: `*address ^= mask`. |
<> | 132:9baf128c2fab | 193 | * @param address[in] Target address |
<> | 132:9baf128c2fab | 194 | * @param mask[in] Bits to select out of the target address |
<> | 132:9baf128c2fab | 195 | */ |
<> | 132:9baf128c2fab | 196 | #define SECURE_BITS_TOGGLE(address, mask) \ |
<> | 132:9baf128c2fab | 197 | *(address) ^= (mask) |
<> | 132:9baf128c2fab | 198 | |
<> | 132:9baf128c2fab | 199 | #endif |
<> | 132:9baf128c2fab | 200 | |
<> | 132:9baf128c2fab | 201 | #endif /* __CORE_CM_SECURE_ACCESS_H */ |