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mbed 2
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TARGET_KW41Z/TOOLCHAIN_IAR/MKW41Z512xxx4.icf@132:9baf128c2fab, 2016-12-20 (annotated)
- Committer:
- <>
- Date:
- Tue Dec 20 15:36:52 2016 +0000
- Revision:
- 132:9baf128c2fab
- Child:
- 172:65be27845400
Release 132 of the mbed library
Ports for Upcoming Targets
3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241
3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291
Fixes and Changes
3062: TARGET_STM :USB device FS https://github.com/ARMmbed/mbed-os/pull/3062
3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213
3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288
3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289
3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302
3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320
3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321
3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352
3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322
3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345
3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309
3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157
3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301
3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303
3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304
3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318
3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317
3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312
3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324
3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369
3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377
3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378
3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382
3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399
3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409
3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416
3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348
3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366
3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379
3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393
3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408
3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411
3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424
3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427
3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429
3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 132:9baf128c2fab | 1 | /* |
<> | 132:9baf128c2fab | 2 | ** ################################################################### |
<> | 132:9baf128c2fab | 3 | ** Processor: MKW41Z512VHT4 |
<> | 132:9baf128c2fab | 4 | ** Compiler: IAR ANSI C/C++ Compiler for ARM |
<> | 132:9baf128c2fab | 5 | ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 |
<> | 132:9baf128c2fab | 6 | ** Version: rev. 1.0, 2015-09-23 |
<> | 132:9baf128c2fab | 7 | ** Build: b160720 |
<> | 132:9baf128c2fab | 8 | ** |
<> | 132:9baf128c2fab | 9 | ** Abstract: |
<> | 132:9baf128c2fab | 10 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM |
<> | 132:9baf128c2fab | 11 | ** |
<> | 132:9baf128c2fab | 12 | ** Copyright (c) 2016 Freescale Semiconductor, Inc. |
<> | 132:9baf128c2fab | 13 | ** All rights reserved. |
<> | 132:9baf128c2fab | 14 | ** |
<> | 132:9baf128c2fab | 15 | ** Redistribution and use in source and binary forms, with or without modification, |
<> | 132:9baf128c2fab | 16 | ** are permitted provided that the following conditions are met: |
<> | 132:9baf128c2fab | 17 | ** |
<> | 132:9baf128c2fab | 18 | ** o Redistributions of source code must retain the above copyright notice, this list |
<> | 132:9baf128c2fab | 19 | ** of conditions and the following disclaimer. |
<> | 132:9baf128c2fab | 20 | ** |
<> | 132:9baf128c2fab | 21 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 132:9baf128c2fab | 22 | ** list of conditions and the following disclaimer in the documentation and/or |
<> | 132:9baf128c2fab | 23 | ** other materials provided with the distribution. |
<> | 132:9baf128c2fab | 24 | ** |
<> | 132:9baf128c2fab | 25 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 132:9baf128c2fab | 26 | ** contributors may be used to endorse or promote products derived from this |
<> | 132:9baf128c2fab | 27 | ** software without specific prior written permission. |
<> | 132:9baf128c2fab | 28 | ** |
<> | 132:9baf128c2fab | 29 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 132:9baf128c2fab | 30 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 132:9baf128c2fab | 31 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 132:9baf128c2fab | 32 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 132:9baf128c2fab | 33 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 132:9baf128c2fab | 34 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 132:9baf128c2fab | 35 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 132:9baf128c2fab | 36 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 132:9baf128c2fab | 37 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 132:9baf128c2fab | 38 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 132:9baf128c2fab | 39 | ** |
<> | 132:9baf128c2fab | 40 | ** http: www.freescale.com |
<> | 132:9baf128c2fab | 41 | ** mail: support@freescale.com |
<> | 132:9baf128c2fab | 42 | ** |
<> | 132:9baf128c2fab | 43 | ** ################################################################### |
<> | 132:9baf128c2fab | 44 | */ |
<> | 132:9baf128c2fab | 45 | define symbol __ram_vector_table__ = 1; |
<> | 132:9baf128c2fab | 46 | |
<> | 132:9baf128c2fab | 47 | /* Heap 1/4 of ram and stack 1/8 */ |
<> | 132:9baf128c2fab | 48 | define symbol __stack_size__=0x4000; |
<> | 132:9baf128c2fab | 49 | define symbol __heap_size__=0x8000; |
<> | 132:9baf128c2fab | 50 | |
<> | 132:9baf128c2fab | 51 | define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0; |
<> | 132:9baf128c2fab | 52 | define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0; |
<> | 132:9baf128c2fab | 53 | |
<> | 132:9baf128c2fab | 54 | define symbol m_interrupts_start = 0x00000000; |
<> | 132:9baf128c2fab | 55 | define symbol m_interrupts_end = 0x000001FF; |
<> | 132:9baf128c2fab | 56 | |
<> | 132:9baf128c2fab | 57 | define symbol m_flash_config_start = 0x00000400; |
<> | 132:9baf128c2fab | 58 | define symbol m_flash_config_end = 0x0000040F; |
<> | 132:9baf128c2fab | 59 | |
<> | 132:9baf128c2fab | 60 | define symbol m_text_start = 0x00000410; |
<> | 132:9baf128c2fab | 61 | define symbol m_text_end = 0x0007FFFF; |
<> | 132:9baf128c2fab | 62 | |
<> | 132:9baf128c2fab | 63 | define symbol m_interrupts_ram_start = 0x1FFF8000; |
<> | 132:9baf128c2fab | 64 | define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__; |
<> | 132:9baf128c2fab | 65 | |
<> | 132:9baf128c2fab | 66 | define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; |
<> | 132:9baf128c2fab | 67 | define symbol m_data_end = 0x20017FFF; |
<> | 132:9baf128c2fab | 68 | |
<> | 132:9baf128c2fab | 69 | /* Sizes */ |
<> | 132:9baf128c2fab | 70 | if (isdefinedsymbol(__stack_size__)) { |
<> | 132:9baf128c2fab | 71 | define symbol __size_cstack__ = __stack_size__; |
<> | 132:9baf128c2fab | 72 | } else { |
<> | 132:9baf128c2fab | 73 | define symbol __size_cstack__ = 0x0400; |
<> | 132:9baf128c2fab | 74 | } |
<> | 132:9baf128c2fab | 75 | |
<> | 132:9baf128c2fab | 76 | if (isdefinedsymbol(__heap_size__)) { |
<> | 132:9baf128c2fab | 77 | define symbol __size_heap__ = __heap_size__; |
<> | 132:9baf128c2fab | 78 | } else { |
<> | 132:9baf128c2fab | 79 | define symbol __size_heap__ = 0x0400; |
<> | 132:9baf128c2fab | 80 | } |
<> | 132:9baf128c2fab | 81 | |
<> | 132:9baf128c2fab | 82 | define exported symbol __VECTOR_TABLE = m_interrupts_start; |
<> | 132:9baf128c2fab | 83 | define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; |
<> | 132:9baf128c2fab | 84 | define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; |
<> | 132:9baf128c2fab | 85 | |
<> | 132:9baf128c2fab | 86 | define memory mem with size = 4G; |
<> | 132:9baf128c2fab | 87 | define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; |
<> | 132:9baf128c2fab | 88 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] |
<> | 132:9baf128c2fab | 89 | | mem:[from m_text_start to m_text_end]; |
<> | 132:9baf128c2fab | 90 | define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; |
<> | 132:9baf128c2fab | 91 | define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; |
<> | 132:9baf128c2fab | 92 | define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; |
<> | 132:9baf128c2fab | 93 | |
<> | 132:9baf128c2fab | 94 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; |
<> | 132:9baf128c2fab | 95 | define block HEAP with alignment = 8, size = __size_heap__ { }; |
<> | 132:9baf128c2fab | 96 | define block RW { readwrite }; |
<> | 132:9baf128c2fab | 97 | define block ZI { zi }; |
<> | 132:9baf128c2fab | 98 | |
<> | 132:9baf128c2fab | 99 | initialize by copy { readwrite, section .textrw }; |
<> | 132:9baf128c2fab | 100 | do not initialize { section .noinit }; |
<> | 132:9baf128c2fab | 101 | |
<> | 132:9baf128c2fab | 102 | place at address mem: m_interrupts_start { readonly section .intvec }; |
<> | 132:9baf128c2fab | 103 | place in m_flash_config_region { section FlashConfig }; |
<> | 132:9baf128c2fab | 104 | place in TEXT_region { readonly }; |
<> | 132:9baf128c2fab | 105 | place in DATA_region { block RW }; |
<> | 132:9baf128c2fab | 106 | place in DATA_region { block ZI }; |
<> | 132:9baf128c2fab | 107 | place in DATA_region { last block HEAP }; |
<> | 132:9baf128c2fab | 108 | place in CSTACK_region { block CSTACK }; |
<> | 132:9baf128c2fab | 109 | place in m_interrupts_ram_region { section m_interrupts_ram }; |
<> | 132:9baf128c2fab | 110 |