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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_cm3.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:: <>
Date:: Wed Apr 12 16:07:08 2017 +0100
Revision:: 140:97feb9bacc10
Parent:: 133:99b5ccf27215
Child:: 145:64910690c574

Release 140 of the mbed library

Ports for Upcoming Targets

3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992

Fixes and Changes

3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	133:99b5ccf27215	1	/************************************************************************//
<>	133:99b5ccf27215	2	* @file core_cm3.h
<>	133:99b5ccf27215	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
<>	133:99b5ccf27215	4	* @version V4.10
<>	133:99b5ccf27215	5	* @date 18. March 2015
<>	133:99b5ccf27215	6	*
<>	133:99b5ccf27215	7	* @note
<>	133:99b5ccf27215	8	*
<>	133:99b5ccf27215	9	******************************************************************************/
<>	133:99b5ccf27215	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
<>	133:99b5ccf27215	11
<>	133:99b5ccf27215	12	All rights reserved.
<>	133:99b5ccf27215	13	Redistribution and use in source and binary forms, with or without
<>	133:99b5ccf27215	14	modification, are permitted provided that the following conditions are met:
<>	133:99b5ccf27215	15	- Redistributions of source code must retain the above copyright
<>	133:99b5ccf27215	16	notice, this list of conditions and the following disclaimer.
<>	133:99b5ccf27215	17	- Redistributions in binary form must reproduce the above copyright
<>	133:99b5ccf27215	18	notice, this list of conditions and the following disclaimer in the
<>	133:99b5ccf27215	19	documentation and/or other materials provided with the distribution.
<>	133:99b5ccf27215	20	- Neither the name of ARM nor the names of its contributors may be used
<>	133:99b5ccf27215	21	to endorse or promote products derived from this software without
<>	133:99b5ccf27215	22	specific prior written permission.
<>	133:99b5ccf27215	23	*
<>	133:99b5ccf27215	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	133:99b5ccf27215	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	133:99b5ccf27215	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<>	133:99b5ccf27215	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<>	133:99b5ccf27215	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<>	133:99b5ccf27215	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<>	133:99b5ccf27215	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<>	133:99b5ccf27215	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<>	133:99b5ccf27215	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<>	133:99b5ccf27215	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<>	133:99b5ccf27215	34	POSSIBILITY OF SUCH DAMAGE.
<>	133:99b5ccf27215	35	---------------------------------------------------------------------------*/
<>	133:99b5ccf27215	36
<>	133:99b5ccf27215	37
<>	133:99b5ccf27215	38	#if defined ( __ICCARM__ )
<>	133:99b5ccf27215	39	#pragma system_include /* treat file as system include file for MISRA check */
<>	133:99b5ccf27215	40	#endif
<>	133:99b5ccf27215	41
<>	133:99b5ccf27215	42	#ifndef __CORE_CM3_H_GENERIC
<>	133:99b5ccf27215	43	#define __CORE_CM3_H_GENERIC
<>	133:99b5ccf27215	44
<>	133:99b5ccf27215	45	#ifdef __cplusplus
<>	133:99b5ccf27215	46	extern "C" {
<>	133:99b5ccf27215	47	#endif
<>	133:99b5ccf27215	48
<>	133:99b5ccf27215	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<>	133:99b5ccf27215	50	CMSIS violates the following MISRA-C:2004 rules:
<>	133:99b5ccf27215	51
<>	133:99b5ccf27215	52	\li Required Rule 8.5, object/function definition in header file.<br>
<>	133:99b5ccf27215	53	Function definitions in header files are used to allow 'inlining'.
<>	133:99b5ccf27215	54
<>	133:99b5ccf27215	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<>	133:99b5ccf27215	56	Unions are used for effective representation of core registers.
<>	133:99b5ccf27215	57
<>	133:99b5ccf27215	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
<>	133:99b5ccf27215	59	Function-like macros are used to allow more efficient code.
<>	133:99b5ccf27215	60	*/
<>	133:99b5ccf27215	61
<>	133:99b5ccf27215	62
<>	133:99b5ccf27215	63	/*******************************************************************************
<>	133:99b5ccf27215	64	* CMSIS definitions
<>	133:99b5ccf27215	65	******************************************************************************/
<>	133:99b5ccf27215	66	/** \ingroup Cortex_M3
<>	133:99b5ccf27215	67	@{
<>	133:99b5ccf27215	68	*/
<>	133:99b5ccf27215	69
<>	133:99b5ccf27215	70	/* CMSIS CM3 definitions */
<>	133:99b5ccf27215	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
<>	133:99b5ccf27215	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
<>	133:99b5ccf27215	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
<>	133:99b5ccf27215	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
<>	133:99b5ccf27215	75
<>	133:99b5ccf27215	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
<>	133:99b5ccf27215	77
<>	133:99b5ccf27215	78
<>	133:99b5ccf27215	79	#if defined ( __CC_ARM )
<>	133:99b5ccf27215	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
<>	133:99b5ccf27215	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
<>	133:99b5ccf27215	82	#define __STATIC_INLINE static __inline
<>	133:99b5ccf27215	83
<>	133:99b5ccf27215	84	#elif defined ( __GNUC__ )
<>	133:99b5ccf27215	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
<>	133:99b5ccf27215	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
<>	133:99b5ccf27215	87	#define __STATIC_INLINE static inline
<>	133:99b5ccf27215	88
<>	133:99b5ccf27215	89	#elif defined ( __ICCARM__ )
<>	133:99b5ccf27215	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
<>	133:99b5ccf27215	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
<>	133:99b5ccf27215	92	#define __STATIC_INLINE static inline
<>	133:99b5ccf27215	93
<>	133:99b5ccf27215	94	#elif defined ( __TMS470__ )
<>	133:99b5ccf27215	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
<>	133:99b5ccf27215	96	#define __STATIC_INLINE static inline
<>	133:99b5ccf27215	97
<>	133:99b5ccf27215	98	#elif defined ( __TASKING__ )
<>	133:99b5ccf27215	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
<>	133:99b5ccf27215	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
<>	133:99b5ccf27215	101	#define __STATIC_INLINE static inline
<>	133:99b5ccf27215	102
<>	133:99b5ccf27215	103	#elif defined ( __CSMC__ )
<>	133:99b5ccf27215	104	#define __packed
<>	133:99b5ccf27215	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
<>	133:99b5ccf27215	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
<>	133:99b5ccf27215	107	#define __STATIC_INLINE static inline
<>	133:99b5ccf27215	108
<>	133:99b5ccf27215	109	#endif
<>	133:99b5ccf27215	110
<>	133:99b5ccf27215	111	/** __FPU_USED indicates whether an FPU is used or not.
<>	133:99b5ccf27215	112	This core does not support an FPU at all
<>	133:99b5ccf27215	113	*/
<>	133:99b5ccf27215	114	#define __FPU_USED 0
<>	133:99b5ccf27215	115
<>	133:99b5ccf27215	116	#if defined ( __CC_ARM )
<>	133:99b5ccf27215	117	#if defined __TARGET_FPU_VFP
<>	133:99b5ccf27215	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	119	#endif
<>	133:99b5ccf27215	120
<>	133:99b5ccf27215	121	#elif defined ( __GNUC__ )
<>	133:99b5ccf27215	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
<>	133:99b5ccf27215	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	124	#endif
<>	133:99b5ccf27215	125
<>	133:99b5ccf27215	126	#elif defined ( __ICCARM__ )
<>	133:99b5ccf27215	127	#if defined __ARMVFP__
<>	133:99b5ccf27215	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	129	#endif
<>	133:99b5ccf27215	130
<>	133:99b5ccf27215	131	#elif defined ( __TMS470__ )
<>	133:99b5ccf27215	132	#if defined __TI__VFP_SUPPORT____
<>	133:99b5ccf27215	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	134	#endif
<>	133:99b5ccf27215	135
<>	133:99b5ccf27215	136	#elif defined ( __TASKING__ )
<>	133:99b5ccf27215	137	#if defined __FPU_VFP__
<>	133:99b5ccf27215	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	139	#endif
<>	133:99b5ccf27215	140
<>	133:99b5ccf27215	141	#elif defined ( __CSMC__ ) /* Cosmic */
<>	133:99b5ccf27215	142	#if ( __CSMC__ & 0x400) // FPU present for parser
<>	133:99b5ccf27215	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	133:99b5ccf27215	144	#endif
<>	133:99b5ccf27215	145	#endif
<>	133:99b5ccf27215	146
<>	133:99b5ccf27215	147	#include <stdint.h> /* standard types definitions */
<>	133:99b5ccf27215	148	#include <core_cmInstr.h> /* Core Instruction Access */
<>	133:99b5ccf27215	149	#include <core_cmFunc.h> /* Core Function Access */
<>	133:99b5ccf27215	150
<>	133:99b5ccf27215	151	#ifdef __cplusplus
<>	133:99b5ccf27215	152	}
<>	133:99b5ccf27215	153	#endif
<>	133:99b5ccf27215	154
<>	133:99b5ccf27215	155	#endif /* __CORE_CM3_H_GENERIC */
<>	133:99b5ccf27215	156
<>	133:99b5ccf27215	157	#ifndef __CMSIS_GENERIC
<>	133:99b5ccf27215	158
<>	133:99b5ccf27215	159	#ifndef __CORE_CM3_H_DEPENDANT
<>	133:99b5ccf27215	160	#define __CORE_CM3_H_DEPENDANT
<>	133:99b5ccf27215	161
<>	133:99b5ccf27215	162	#ifdef __cplusplus
<>	133:99b5ccf27215	163	extern "C" {
<>	133:99b5ccf27215	164	#endif
<>	133:99b5ccf27215	165
<>	133:99b5ccf27215	166	/* check device defines and use defaults */
<>	133:99b5ccf27215	167	#if defined __CHECK_DEVICE_DEFINES
<>	133:99b5ccf27215	168	#ifndef __CM3_REV
<>	133:99b5ccf27215	169	#define __CM3_REV 0x0200
<>	133:99b5ccf27215	170	#warning "__CM3_REV not defined in device header file; using default!"
<>	133:99b5ccf27215	171	#endif
<>	133:99b5ccf27215	172
<>	133:99b5ccf27215	173	#ifndef __MPU_PRESENT
<>	133:99b5ccf27215	174	#define __MPU_PRESENT 0
<>	133:99b5ccf27215	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
<>	133:99b5ccf27215	176	#endif
<>	133:99b5ccf27215	177
<>	133:99b5ccf27215	178	#ifndef __NVIC_PRIO_BITS
<>	133:99b5ccf27215	179	#define __NVIC_PRIO_BITS 4
<>	133:99b5ccf27215	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<>	133:99b5ccf27215	181	#endif
<>	133:99b5ccf27215	182
<>	133:99b5ccf27215	183	#ifndef __Vendor_SysTickConfig
<>	133:99b5ccf27215	184	#define __Vendor_SysTickConfig 0
<>	133:99b5ccf27215	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<>	133:99b5ccf27215	186	#endif
<>	133:99b5ccf27215	187	#endif
<>	133:99b5ccf27215	188
<>	133:99b5ccf27215	189	/* IO definitions (access restrictions to peripheral registers) */
<>	133:99b5ccf27215	190	/**
<>	133:99b5ccf27215	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
<>	133:99b5ccf27215	192
<>	133:99b5ccf27215	193	<strong>IO Type Qualifiers</strong> are used
<>	133:99b5ccf27215	194	\li to specify the access to peripheral variables.
<>	133:99b5ccf27215	195	\li for automatic generation of peripheral register debug information.
<>	133:99b5ccf27215	196	*/
<>	133:99b5ccf27215	197	#ifdef __cplusplus
<>	133:99b5ccf27215	198	#define __I volatile /!< Defines 'read only' permissions /
<>	133:99b5ccf27215	199	#else
<>	133:99b5ccf27215	200	#define __I volatile const /!< Defines 'read only' permissions /
<>	133:99b5ccf27215	201	#endif
<>	133:99b5ccf27215	202	#define __O volatile /!< Defines 'write only' permissions /
<>	133:99b5ccf27215	203	#define __IO volatile /!< Defines 'read / write' permissions /
<>	133:99b5ccf27215	204
<>	133:99b5ccf27215	205	#ifdef __cplusplus
<>	133:99b5ccf27215	206	#define __IM volatile /!< Defines 'read only' permissions /
<>	133:99b5ccf27215	207	#else
<>	133:99b5ccf27215	208	#define __IM volatile const /!< Defines 'read only' permissions /
<>	133:99b5ccf27215	209	#endif
<>	133:99b5ccf27215	210	#define __OM volatile /!< Defines 'write only' permissions /
<>	133:99b5ccf27215	211	#define __IOM volatile /!< Defines 'read / write' permissions /
<>	133:99b5ccf27215	212
<>	133:99b5ccf27215	213	/@} end of group Cortex_M3 /
<>	133:99b5ccf27215	214
<>	133:99b5ccf27215	215
<>	133:99b5ccf27215	216
<>	133:99b5ccf27215	217	/*******************************************************************************
<>	133:99b5ccf27215	218	* Register Abstraction
<>	133:99b5ccf27215	219	Core Register contain:
<>	133:99b5ccf27215	220	- Core Register
<>	133:99b5ccf27215	221	- Core NVIC Register
<>	133:99b5ccf27215	222	- Core SCB Register
<>	133:99b5ccf27215	223	- Core SysTick Register
<>	133:99b5ccf27215	224	- Core Debug Register
<>	133:99b5ccf27215	225	- Core MPU Register
<>	133:99b5ccf27215	226	******************************************************************************/
<>	133:99b5ccf27215	227	/** \defgroup CMSIS_core_register Defines and Type Definitions
<>	133:99b5ccf27215	228	\brief Type definitions and defines for Cortex-M processor based devices.
<>	133:99b5ccf27215	229	*/
<>	133:99b5ccf27215	230
<>	133:99b5ccf27215	231	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	232	\defgroup CMSIS_CORE Status and Control Registers
<>	133:99b5ccf27215	233	\brief Core Register type definitions.
<>	133:99b5ccf27215	234	@{
<>	133:99b5ccf27215	235	*/
<>	133:99b5ccf27215	236
<>	133:99b5ccf27215	237	/** \brief Union type to access the Application Program Status Register (APSR).
<>	133:99b5ccf27215	238	*/
<>	133:99b5ccf27215	239	typedef union
<>	133:99b5ccf27215	240	{
<>	133:99b5ccf27215	241	struct
<>	133:99b5ccf27215	242	{
<>	133:99b5ccf27215	243	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
<>	133:99b5ccf27215	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	133:99b5ccf27215	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	133:99b5ccf27215	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	133:99b5ccf27215	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	133:99b5ccf27215	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	133:99b5ccf27215	249	} b; /!< Structure used for bit access /
<>	133:99b5ccf27215	250	uint32_t w; /!< Type used for word access /
<>	133:99b5ccf27215	251	} APSR_Type;
<>	133:99b5ccf27215	252
<>	133:99b5ccf27215	253	/* APSR Register Definitions */
<>	133:99b5ccf27215	254	#define APSR_N_Pos 31 /!< APSR: N Position /
<>	133:99b5ccf27215	255	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
<>	133:99b5ccf27215	256
<>	133:99b5ccf27215	257	#define APSR_Z_Pos 30 /!< APSR: Z Position /
<>	133:99b5ccf27215	258	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
<>	133:99b5ccf27215	259
<>	133:99b5ccf27215	260	#define APSR_C_Pos 29 /!< APSR: C Position /
<>	133:99b5ccf27215	261	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
<>	133:99b5ccf27215	262
<>	133:99b5ccf27215	263	#define APSR_V_Pos 28 /!< APSR: V Position /
<>	133:99b5ccf27215	264	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
<>	133:99b5ccf27215	265
<>	133:99b5ccf27215	266	#define APSR_Q_Pos 27 /!< APSR: Q Position /
<>	133:99b5ccf27215	267	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
<>	133:99b5ccf27215	268
<>	133:99b5ccf27215	269
<>	133:99b5ccf27215	270	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
<>	133:99b5ccf27215	271	*/
<>	133:99b5ccf27215	272	typedef union
<>	133:99b5ccf27215	273	{
<>	133:99b5ccf27215	274	struct
<>	133:99b5ccf27215	275	{
<>	133:99b5ccf27215	276	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	133:99b5ccf27215	277	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
<>	133:99b5ccf27215	278	} b; /!< Structure used for bit access /
<>	133:99b5ccf27215	279	uint32_t w; /!< Type used for word access /
<>	133:99b5ccf27215	280	} IPSR_Type;
<>	133:99b5ccf27215	281
<>	133:99b5ccf27215	282	/* IPSR Register Definitions */
<>	133:99b5ccf27215	283	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
<>	133:99b5ccf27215	284	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
<>	133:99b5ccf27215	285
<>	133:99b5ccf27215	286
<>	133:99b5ccf27215	287	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<>	133:99b5ccf27215	288	*/
<>	133:99b5ccf27215	289	typedef union
<>	133:99b5ccf27215	290	{
<>	133:99b5ccf27215	291	struct
<>	133:99b5ccf27215	292	{
<>	133:99b5ccf27215	293	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	133:99b5ccf27215	294	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
<>	133:99b5ccf27215	295	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
<>	133:99b5ccf27215	296	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
<>	133:99b5ccf27215	297	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	133:99b5ccf27215	298	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	133:99b5ccf27215	299	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	133:99b5ccf27215	300	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	133:99b5ccf27215	301	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	133:99b5ccf27215	302	} b; /!< Structure used for bit access /
<>	133:99b5ccf27215	303	uint32_t w; /!< Type used for word access /
<>	133:99b5ccf27215	304	} xPSR_Type;
<>	133:99b5ccf27215	305
<>	133:99b5ccf27215	306	/* xPSR Register Definitions */
<>	133:99b5ccf27215	307	#define xPSR_N_Pos 31 /!< xPSR: N Position /
<>	133:99b5ccf27215	308	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
<>	133:99b5ccf27215	309
<>	133:99b5ccf27215	310	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
<>	133:99b5ccf27215	311	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
<>	133:99b5ccf27215	312
<>	133:99b5ccf27215	313	#define xPSR_C_Pos 29 /!< xPSR: C Position /
<>	133:99b5ccf27215	314	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
<>	133:99b5ccf27215	315
<>	133:99b5ccf27215	316	#define xPSR_V_Pos 28 /!< xPSR: V Position /
<>	133:99b5ccf27215	317	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
<>	133:99b5ccf27215	318
<>	133:99b5ccf27215	319	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
<>	133:99b5ccf27215	320	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
<>	133:99b5ccf27215	321
<>	133:99b5ccf27215	322	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
<>	133:99b5ccf27215	323	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
<>	133:99b5ccf27215	324
<>	133:99b5ccf27215	325	#define xPSR_T_Pos 24 /!< xPSR: T Position /
<>	133:99b5ccf27215	326	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
<>	133:99b5ccf27215	327
<>	133:99b5ccf27215	328	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
<>	133:99b5ccf27215	329	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
<>	133:99b5ccf27215	330
<>	133:99b5ccf27215	331
<>	133:99b5ccf27215	332	/** \brief Union type to access the Control Registers (CONTROL).
<>	133:99b5ccf27215	333	*/
<>	133:99b5ccf27215	334	typedef union
<>	133:99b5ccf27215	335	{
<>	133:99b5ccf27215	336	struct
<>	133:99b5ccf27215	337	{
<>	133:99b5ccf27215	338	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
<>	133:99b5ccf27215	339	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
<>	133:99b5ccf27215	340	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
<>	133:99b5ccf27215	341	} b; /!< Structure used for bit access /
<>	133:99b5ccf27215	342	uint32_t w; /!< Type used for word access /
<>	133:99b5ccf27215	343	} CONTROL_Type;
<>	133:99b5ccf27215	344
<>	133:99b5ccf27215	345	/* CONTROL Register Definitions */
<>	133:99b5ccf27215	346	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
<>	133:99b5ccf27215	347	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
<>	133:99b5ccf27215	348
<>	133:99b5ccf27215	349	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
<>	133:99b5ccf27215	350	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
<>	133:99b5ccf27215	351
<>	133:99b5ccf27215	352	/@} end of group CMSIS_CORE /
<>	133:99b5ccf27215	353
<>	133:99b5ccf27215	354
<>	133:99b5ccf27215	355	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	356	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<>	133:99b5ccf27215	357	\brief Type definitions for the NVIC Registers
<>	133:99b5ccf27215	358	@{
<>	133:99b5ccf27215	359	*/
<>	133:99b5ccf27215	360
<>	133:99b5ccf27215	361	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<>	133:99b5ccf27215	362	*/
<>	133:99b5ccf27215	363	typedef struct
<>	133:99b5ccf27215	364	{
<>	133:99b5ccf27215	365	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
<>	133:99b5ccf27215	366	uint32_t RESERVED0[24];
<>	133:99b5ccf27215	367	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
<>	133:99b5ccf27215	368	uint32_t RSERVED1[24];
<>	133:99b5ccf27215	369	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
<>	133:99b5ccf27215	370	uint32_t RESERVED2[24];
<>	133:99b5ccf27215	371	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
<>	133:99b5ccf27215	372	uint32_t RESERVED3[24];
<>	133:99b5ccf27215	373	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
<>	133:99b5ccf27215	374	uint32_t RESERVED4[56];
<>	133:99b5ccf27215	375	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
<>	133:99b5ccf27215	376	uint32_t RESERVED5[644];
<>	133:99b5ccf27215	377	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
<>	133:99b5ccf27215	378	} NVIC_Type;
<>	133:99b5ccf27215	379
<>	133:99b5ccf27215	380	/* Software Triggered Interrupt Register Definitions */
<>	133:99b5ccf27215	381	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
<>	133:99b5ccf27215	382	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
<>	133:99b5ccf27215	383
<>	133:99b5ccf27215	384	/@} end of group CMSIS_NVIC /
<>	133:99b5ccf27215	385
<>	133:99b5ccf27215	386
<>	133:99b5ccf27215	387	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	388	\defgroup CMSIS_SCB System Control Block (SCB)
<>	133:99b5ccf27215	389	\brief Type definitions for the System Control Block Registers
<>	133:99b5ccf27215	390	@{
<>	133:99b5ccf27215	391	*/
<>	133:99b5ccf27215	392
<>	133:99b5ccf27215	393	/** \brief Structure type to access the System Control Block (SCB).
<>	133:99b5ccf27215	394	*/
<>	133:99b5ccf27215	395	typedef struct
<>	133:99b5ccf27215	396	{
<>	133:99b5ccf27215	397	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
<>	133:99b5ccf27215	398	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
<>	133:99b5ccf27215	399	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
<>	133:99b5ccf27215	400	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
<>	133:99b5ccf27215	401	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
<>	133:99b5ccf27215	402	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
<>	133:99b5ccf27215	403	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
<>	133:99b5ccf27215	404	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
<>	133:99b5ccf27215	405	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
<>	133:99b5ccf27215	406	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
<>	133:99b5ccf27215	407	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
<>	133:99b5ccf27215	408	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
<>	133:99b5ccf27215	409	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
<>	133:99b5ccf27215	410	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
<>	133:99b5ccf27215	411	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
<>	133:99b5ccf27215	412	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
<>	133:99b5ccf27215	413	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
<>	133:99b5ccf27215	414	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
<>	133:99b5ccf27215	415	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
<>	133:99b5ccf27215	416	uint32_t RESERVED0[5];
<>	133:99b5ccf27215	417	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
<>	133:99b5ccf27215	418	} SCB_Type;
<>	133:99b5ccf27215	419
<>	133:99b5ccf27215	420	/* SCB CPUID Register Definitions */
<>	133:99b5ccf27215	421	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
<>	133:99b5ccf27215	422	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
<>	133:99b5ccf27215	423
<>	133:99b5ccf27215	424	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
<>	133:99b5ccf27215	425	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
<>	133:99b5ccf27215	426
<>	133:99b5ccf27215	427	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
<>	133:99b5ccf27215	428	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
<>	133:99b5ccf27215	429
<>	133:99b5ccf27215	430	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
<>	133:99b5ccf27215	431	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
<>	133:99b5ccf27215	432
<>	133:99b5ccf27215	433	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
<>	133:99b5ccf27215	434	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
<>	133:99b5ccf27215	435
<>	133:99b5ccf27215	436	/* SCB Interrupt Control State Register Definitions */
<>	133:99b5ccf27215	437	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
<>	133:99b5ccf27215	438	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
<>	133:99b5ccf27215	439
<>	133:99b5ccf27215	440	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
<>	133:99b5ccf27215	441	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
<>	133:99b5ccf27215	442
<>	133:99b5ccf27215	443	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
<>	133:99b5ccf27215	444	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
<>	133:99b5ccf27215	445
<>	133:99b5ccf27215	446	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
<>	133:99b5ccf27215	447	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
<>	133:99b5ccf27215	448
<>	133:99b5ccf27215	449	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
<>	133:99b5ccf27215	450	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
<>	133:99b5ccf27215	451
<>	133:99b5ccf27215	452	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
<>	133:99b5ccf27215	453	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
<>	133:99b5ccf27215	454
<>	133:99b5ccf27215	455	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
<>	133:99b5ccf27215	456	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
<>	133:99b5ccf27215	457
<>	133:99b5ccf27215	458	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
<>	133:99b5ccf27215	459	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
<>	133:99b5ccf27215	460
<>	133:99b5ccf27215	461	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
<>	133:99b5ccf27215	462	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
<>	133:99b5ccf27215	463
<>	133:99b5ccf27215	464	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
<>	133:99b5ccf27215	465	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
<>	133:99b5ccf27215	466
<>	133:99b5ccf27215	467	/* SCB Vector Table Offset Register Definitions */
<>	133:99b5ccf27215	468	#if (__CM3_REV < 0x0201) /* core r2p1 */
<>	133:99b5ccf27215	469	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
<>	133:99b5ccf27215	470	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
<>	133:99b5ccf27215	471
<>	133:99b5ccf27215	472	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
<>	133:99b5ccf27215	473	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	133:99b5ccf27215	474	#else
<>	133:99b5ccf27215	475	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
<>	133:99b5ccf27215	476	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	133:99b5ccf27215	477	#endif
<>	133:99b5ccf27215	478
<>	133:99b5ccf27215	479	/* SCB Application Interrupt and Reset Control Register Definitions */
<>	133:99b5ccf27215	480	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
<>	133:99b5ccf27215	481	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
<>	133:99b5ccf27215	482
<>	133:99b5ccf27215	483	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
<>	133:99b5ccf27215	484	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
<>	133:99b5ccf27215	485
<>	133:99b5ccf27215	486	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
<>	133:99b5ccf27215	487	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
<>	133:99b5ccf27215	488
<>	133:99b5ccf27215	489	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
<>	133:99b5ccf27215	490	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
<>	133:99b5ccf27215	491
<>	133:99b5ccf27215	492	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
<>	133:99b5ccf27215	493	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
<>	133:99b5ccf27215	494
<>	133:99b5ccf27215	495	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
<>	133:99b5ccf27215	496	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
<>	133:99b5ccf27215	497
<>	133:99b5ccf27215	498	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
<>	133:99b5ccf27215	499	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
<>	133:99b5ccf27215	500
<>	133:99b5ccf27215	501	/* SCB System Control Register Definitions */
<>	133:99b5ccf27215	502	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
<>	133:99b5ccf27215	503	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
<>	133:99b5ccf27215	504
<>	133:99b5ccf27215	505	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
<>	133:99b5ccf27215	506	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
<>	133:99b5ccf27215	507
<>	133:99b5ccf27215	508	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
<>	133:99b5ccf27215	509	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
<>	133:99b5ccf27215	510
<>	133:99b5ccf27215	511	/* SCB Configuration Control Register Definitions */
<>	133:99b5ccf27215	512	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
<>	133:99b5ccf27215	513	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
<>	133:99b5ccf27215	514
<>	133:99b5ccf27215	515	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
<>	133:99b5ccf27215	516	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
<>	133:99b5ccf27215	517
<>	133:99b5ccf27215	518	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
<>	133:99b5ccf27215	519	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
<>	133:99b5ccf27215	520
<>	133:99b5ccf27215	521	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
<>	133:99b5ccf27215	522	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
<>	133:99b5ccf27215	523
<>	133:99b5ccf27215	524	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
<>	133:99b5ccf27215	525	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
<>	133:99b5ccf27215	526
<>	133:99b5ccf27215	527	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
<>	133:99b5ccf27215	528	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
<>	133:99b5ccf27215	529
<>	133:99b5ccf27215	530	/* SCB System Handler Control and State Register Definitions */
<>	133:99b5ccf27215	531	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
<>	133:99b5ccf27215	532	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
<>	133:99b5ccf27215	533
<>	133:99b5ccf27215	534	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
<>	133:99b5ccf27215	535	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
<>	133:99b5ccf27215	536
<>	133:99b5ccf27215	537	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
<>	133:99b5ccf27215	538	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
<>	133:99b5ccf27215	539
<>	133:99b5ccf27215	540	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
<>	133:99b5ccf27215	541	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
<>	133:99b5ccf27215	542
<>	133:99b5ccf27215	543	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
<>	133:99b5ccf27215	544	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
<>	133:99b5ccf27215	545
<>	133:99b5ccf27215	546	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
<>	133:99b5ccf27215	547	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
<>	133:99b5ccf27215	548
<>	133:99b5ccf27215	549	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
<>	133:99b5ccf27215	550	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
<>	133:99b5ccf27215	551
<>	133:99b5ccf27215	552	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
<>	133:99b5ccf27215	553	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
<>	133:99b5ccf27215	554
<>	133:99b5ccf27215	555	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
<>	133:99b5ccf27215	556	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
<>	133:99b5ccf27215	557
<>	133:99b5ccf27215	558	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
<>	133:99b5ccf27215	559	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
<>	133:99b5ccf27215	560
<>	133:99b5ccf27215	561	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
<>	133:99b5ccf27215	562	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
<>	133:99b5ccf27215	563
<>	133:99b5ccf27215	564	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
<>	133:99b5ccf27215	565	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
<>	133:99b5ccf27215	566
<>	133:99b5ccf27215	567	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
<>	133:99b5ccf27215	568	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
<>	133:99b5ccf27215	569
<>	133:99b5ccf27215	570	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
<>	133:99b5ccf27215	571	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
<>	133:99b5ccf27215	572
<>	133:99b5ccf27215	573	/* SCB Configurable Fault Status Registers Definitions */
<>	133:99b5ccf27215	574	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
<>	133:99b5ccf27215	575	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
<>	133:99b5ccf27215	576
<>	133:99b5ccf27215	577	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
<>	133:99b5ccf27215	578	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
<>	133:99b5ccf27215	579
<>	133:99b5ccf27215	580	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
<>	133:99b5ccf27215	581	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
<>	133:99b5ccf27215	582
<>	133:99b5ccf27215	583	/* SCB Hard Fault Status Registers Definitions */
<>	133:99b5ccf27215	584	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
<>	133:99b5ccf27215	585	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
<>	133:99b5ccf27215	586
<>	133:99b5ccf27215	587	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
<>	133:99b5ccf27215	588	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
<>	133:99b5ccf27215	589
<>	133:99b5ccf27215	590	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
<>	133:99b5ccf27215	591	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
<>	133:99b5ccf27215	592
<>	133:99b5ccf27215	593	/* SCB Debug Fault Status Register Definitions */
<>	133:99b5ccf27215	594	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
<>	133:99b5ccf27215	595	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
<>	133:99b5ccf27215	596
<>	133:99b5ccf27215	597	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
<>	133:99b5ccf27215	598	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
<>	133:99b5ccf27215	599
<>	133:99b5ccf27215	600	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
<>	133:99b5ccf27215	601	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
<>	133:99b5ccf27215	602
<>	133:99b5ccf27215	603	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
<>	133:99b5ccf27215	604	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
<>	133:99b5ccf27215	605
<>	133:99b5ccf27215	606	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
<>	133:99b5ccf27215	607	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
<>	133:99b5ccf27215	608
<>	133:99b5ccf27215	609	/@} end of group CMSIS_SCB /
<>	133:99b5ccf27215	610
<>	133:99b5ccf27215	611
<>	133:99b5ccf27215	612	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	613	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<>	133:99b5ccf27215	614	\brief Type definitions for the System Control and ID Register not in the SCB
<>	133:99b5ccf27215	615	@{
<>	133:99b5ccf27215	616	*/
<>	133:99b5ccf27215	617
<>	133:99b5ccf27215	618	/** \brief Structure type to access the System Control and ID Register not in the SCB.
<>	133:99b5ccf27215	619	*/
<>	133:99b5ccf27215	620	typedef struct
<>	133:99b5ccf27215	621	{
<>	133:99b5ccf27215	622	uint32_t RESERVED0[1];
<>	133:99b5ccf27215	623	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
<>	133:99b5ccf27215	624	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
<>	133:99b5ccf27215	625	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
<>	133:99b5ccf27215	626	#else
<>	133:99b5ccf27215	627	uint32_t RESERVED1[1];
<>	133:99b5ccf27215	628	#endif
<>	133:99b5ccf27215	629	} SCnSCB_Type;
<>	133:99b5ccf27215	630
<>	133:99b5ccf27215	631	/* Interrupt Controller Type Register Definitions */
<>	133:99b5ccf27215	632	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
<>	133:99b5ccf27215	633	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
<>	133:99b5ccf27215	634
<>	133:99b5ccf27215	635	/* Auxiliary Control Register Definitions */
<>	133:99b5ccf27215	636
<>	133:99b5ccf27215	637	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
<>	133:99b5ccf27215	638	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
<>	133:99b5ccf27215	639
<>	133:99b5ccf27215	640	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
<>	133:99b5ccf27215	641	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
<>	133:99b5ccf27215	642
<>	133:99b5ccf27215	643	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
<>	133:99b5ccf27215	644	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
<>	133:99b5ccf27215	645
<>	133:99b5ccf27215	646	/@} end of group CMSIS_SCnotSCB /
<>	133:99b5ccf27215	647
<>	133:99b5ccf27215	648
<>	133:99b5ccf27215	649	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	650	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
<>	133:99b5ccf27215	651	\brief Type definitions for the System Timer Registers.
<>	133:99b5ccf27215	652	@{
<>	133:99b5ccf27215	653	*/
<>	133:99b5ccf27215	654
<>	133:99b5ccf27215	655	/** \brief Structure type to access the System Timer (SysTick).
<>	133:99b5ccf27215	656	*/
<>	133:99b5ccf27215	657	typedef struct
<>	133:99b5ccf27215	658	{
<>	133:99b5ccf27215	659	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
<>	133:99b5ccf27215	660	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
<>	133:99b5ccf27215	661	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
<>	133:99b5ccf27215	662	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
<>	133:99b5ccf27215	663	} SysTick_Type;
<>	133:99b5ccf27215	664
<>	133:99b5ccf27215	665	/* SysTick Control / Status Register Definitions */
<>	133:99b5ccf27215	666	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
<>	133:99b5ccf27215	667	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
<>	133:99b5ccf27215	668
<>	133:99b5ccf27215	669	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
<>	133:99b5ccf27215	670	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
<>	133:99b5ccf27215	671
<>	133:99b5ccf27215	672	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
<>	133:99b5ccf27215	673	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
<>	133:99b5ccf27215	674
<>	133:99b5ccf27215	675	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
<>	133:99b5ccf27215	676	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
<>	133:99b5ccf27215	677
<>	133:99b5ccf27215	678	/* SysTick Reload Register Definitions */
<>	133:99b5ccf27215	679	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
<>	133:99b5ccf27215	680	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
<>	133:99b5ccf27215	681
<>	133:99b5ccf27215	682	/* SysTick Current Register Definitions */
<>	133:99b5ccf27215	683	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
<>	133:99b5ccf27215	684	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
<>	133:99b5ccf27215	685
<>	133:99b5ccf27215	686	/* SysTick Calibration Register Definitions */
<>	133:99b5ccf27215	687	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
<>	133:99b5ccf27215	688	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
<>	133:99b5ccf27215	689
<>	133:99b5ccf27215	690	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
<>	133:99b5ccf27215	691	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
<>	133:99b5ccf27215	692
<>	133:99b5ccf27215	693	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
<>	133:99b5ccf27215	694	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
<>	133:99b5ccf27215	695
<>	133:99b5ccf27215	696	/@} end of group CMSIS_SysTick /
<>	133:99b5ccf27215	697
<>	133:99b5ccf27215	698
<>	133:99b5ccf27215	699	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	700	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<>	133:99b5ccf27215	701	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<>	133:99b5ccf27215	702	@{
<>	133:99b5ccf27215	703	*/
<>	133:99b5ccf27215	704
<>	133:99b5ccf27215	705	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<>	133:99b5ccf27215	706	*/
<>	133:99b5ccf27215	707	typedef struct
<>	133:99b5ccf27215	708	{
<>	133:99b5ccf27215	709	__O union
<>	133:99b5ccf27215	710	{
<>	133:99b5ccf27215	711	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
<>	133:99b5ccf27215	712	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
<>	133:99b5ccf27215	713	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
<>	133:99b5ccf27215	714	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
<>	133:99b5ccf27215	715	uint32_t RESERVED0[864];
<>	133:99b5ccf27215	716	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
<>	133:99b5ccf27215	717	uint32_t RESERVED1[15];
<>	133:99b5ccf27215	718	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
<>	133:99b5ccf27215	719	uint32_t RESERVED2[15];
<>	133:99b5ccf27215	720	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
<>	133:99b5ccf27215	721	uint32_t RESERVED3[29];
<>	133:99b5ccf27215	722	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
<>	133:99b5ccf27215	723	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
<>	133:99b5ccf27215	724	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
<>	133:99b5ccf27215	725	uint32_t RESERVED4[43];
<>	133:99b5ccf27215	726	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
<>	133:99b5ccf27215	727	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
<>	133:99b5ccf27215	728	uint32_t RESERVED5[6];
<>	133:99b5ccf27215	729	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
<>	133:99b5ccf27215	730	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
<>	133:99b5ccf27215	731	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
<>	133:99b5ccf27215	732	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
<>	133:99b5ccf27215	733	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
<>	133:99b5ccf27215	734	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
<>	133:99b5ccf27215	735	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
<>	133:99b5ccf27215	736	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
<>	133:99b5ccf27215	737	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
<>	133:99b5ccf27215	738	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
<>	133:99b5ccf27215	739	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
<>	133:99b5ccf27215	740	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
<>	133:99b5ccf27215	741	} ITM_Type;
<>	133:99b5ccf27215	742
<>	133:99b5ccf27215	743	/* ITM Trace Privilege Register Definitions */
<>	133:99b5ccf27215	744	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
<>	133:99b5ccf27215	745	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
<>	133:99b5ccf27215	746
<>	133:99b5ccf27215	747	/* ITM Trace Control Register Definitions */
<>	133:99b5ccf27215	748	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
<>	133:99b5ccf27215	749	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
<>	133:99b5ccf27215	750
<>	133:99b5ccf27215	751	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
<>	133:99b5ccf27215	752	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
<>	133:99b5ccf27215	753
<>	133:99b5ccf27215	754	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
<>	133:99b5ccf27215	755	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
<>	133:99b5ccf27215	756
<>	133:99b5ccf27215	757	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
<>	133:99b5ccf27215	758	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
<>	133:99b5ccf27215	759
<>	133:99b5ccf27215	760	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
<>	133:99b5ccf27215	761	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
<>	133:99b5ccf27215	762
<>	133:99b5ccf27215	763	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
<>	133:99b5ccf27215	764	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
<>	133:99b5ccf27215	765
<>	133:99b5ccf27215	766	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
<>	133:99b5ccf27215	767	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
<>	133:99b5ccf27215	768
<>	133:99b5ccf27215	769	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
<>	133:99b5ccf27215	770	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
<>	133:99b5ccf27215	771
<>	133:99b5ccf27215	772	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
<>	133:99b5ccf27215	773	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
<>	133:99b5ccf27215	774
<>	133:99b5ccf27215	775	/* ITM Integration Write Register Definitions */
<>	133:99b5ccf27215	776	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
<>	133:99b5ccf27215	777	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
<>	133:99b5ccf27215	778
<>	133:99b5ccf27215	779	/* ITM Integration Read Register Definitions */
<>	133:99b5ccf27215	780	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
<>	133:99b5ccf27215	781	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
<>	133:99b5ccf27215	782
<>	133:99b5ccf27215	783	/* ITM Integration Mode Control Register Definitions */
<>	133:99b5ccf27215	784	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
<>	133:99b5ccf27215	785	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
<>	133:99b5ccf27215	786
<>	133:99b5ccf27215	787	/* ITM Lock Status Register Definitions */
<>	133:99b5ccf27215	788	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
<>	133:99b5ccf27215	789	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
<>	133:99b5ccf27215	790
<>	133:99b5ccf27215	791	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
<>	133:99b5ccf27215	792	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
<>	133:99b5ccf27215	793
<>	133:99b5ccf27215	794	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
<>	133:99b5ccf27215	795	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
<>	133:99b5ccf27215	796
<>	133:99b5ccf27215	797	/@}/ /* end of group CMSIS_ITM */
<>	133:99b5ccf27215	798
<>	133:99b5ccf27215	799
<>	133:99b5ccf27215	800	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	801	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<>	133:99b5ccf27215	802	\brief Type definitions for the Data Watchpoint and Trace (DWT)
<>	133:99b5ccf27215	803	@{
<>	133:99b5ccf27215	804	*/
<>	133:99b5ccf27215	805
<>	133:99b5ccf27215	806	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<>	133:99b5ccf27215	807	*/
<>	133:99b5ccf27215	808	typedef struct
<>	133:99b5ccf27215	809	{
<>	133:99b5ccf27215	810	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
<>	133:99b5ccf27215	811	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
<>	133:99b5ccf27215	812	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
<>	133:99b5ccf27215	813	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
<>	133:99b5ccf27215	814	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
<>	133:99b5ccf27215	815	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
<>	133:99b5ccf27215	816	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
<>	133:99b5ccf27215	817	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
<>	133:99b5ccf27215	818	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
<>	133:99b5ccf27215	819	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
<>	133:99b5ccf27215	820	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
<>	133:99b5ccf27215	821	uint32_t RESERVED0[1];
<>	133:99b5ccf27215	822	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
<>	133:99b5ccf27215	823	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
<>	133:99b5ccf27215	824	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
<>	133:99b5ccf27215	825	uint32_t RESERVED1[1];
<>	133:99b5ccf27215	826	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
<>	133:99b5ccf27215	827	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
<>	133:99b5ccf27215	828	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
<>	133:99b5ccf27215	829	uint32_t RESERVED2[1];
<>	133:99b5ccf27215	830	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
<>	133:99b5ccf27215	831	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
<>	133:99b5ccf27215	832	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
<>	133:99b5ccf27215	833	} DWT_Type;
<>	133:99b5ccf27215	834
<>	133:99b5ccf27215	835	/* DWT Control Register Definitions */
<>	133:99b5ccf27215	836	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
<>	133:99b5ccf27215	837	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
<>	133:99b5ccf27215	838
<>	133:99b5ccf27215	839	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
<>	133:99b5ccf27215	840	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
<>	133:99b5ccf27215	841
<>	133:99b5ccf27215	842	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
<>	133:99b5ccf27215	843	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
<>	133:99b5ccf27215	844
<>	133:99b5ccf27215	845	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
<>	133:99b5ccf27215	846	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
<>	133:99b5ccf27215	847
<>	133:99b5ccf27215	848	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
<>	133:99b5ccf27215	849	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
<>	133:99b5ccf27215	850
<>	133:99b5ccf27215	851	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
<>	133:99b5ccf27215	852	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
<>	133:99b5ccf27215	853
<>	133:99b5ccf27215	854	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
<>	133:99b5ccf27215	855	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
<>	133:99b5ccf27215	856
<>	133:99b5ccf27215	857	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
<>	133:99b5ccf27215	858	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
<>	133:99b5ccf27215	859
<>	133:99b5ccf27215	860	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
<>	133:99b5ccf27215	861	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
<>	133:99b5ccf27215	862
<>	133:99b5ccf27215	863	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
<>	133:99b5ccf27215	864	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
<>	133:99b5ccf27215	865
<>	133:99b5ccf27215	866	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
<>	133:99b5ccf27215	867	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
<>	133:99b5ccf27215	868
<>	133:99b5ccf27215	869	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
<>	133:99b5ccf27215	870	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
<>	133:99b5ccf27215	871
<>	133:99b5ccf27215	872	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
<>	133:99b5ccf27215	873	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
<>	133:99b5ccf27215	874
<>	133:99b5ccf27215	875	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
<>	133:99b5ccf27215	876	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
<>	133:99b5ccf27215	877
<>	133:99b5ccf27215	878	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
<>	133:99b5ccf27215	879	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
<>	133:99b5ccf27215	880
<>	133:99b5ccf27215	881	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
<>	133:99b5ccf27215	882	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
<>	133:99b5ccf27215	883
<>	133:99b5ccf27215	884	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
<>	133:99b5ccf27215	885	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
<>	133:99b5ccf27215	886
<>	133:99b5ccf27215	887	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
<>	133:99b5ccf27215	888	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
<>	133:99b5ccf27215	889
<>	133:99b5ccf27215	890	/* DWT CPI Count Register Definitions */
<>	133:99b5ccf27215	891	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
<>	133:99b5ccf27215	892	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
<>	133:99b5ccf27215	893
<>	133:99b5ccf27215	894	/* DWT Exception Overhead Count Register Definitions */
<>	133:99b5ccf27215	895	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
<>	133:99b5ccf27215	896	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
<>	133:99b5ccf27215	897
<>	133:99b5ccf27215	898	/* DWT Sleep Count Register Definitions */
<>	133:99b5ccf27215	899	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
<>	133:99b5ccf27215	900	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
<>	133:99b5ccf27215	901
<>	133:99b5ccf27215	902	/* DWT LSU Count Register Definitions */
<>	133:99b5ccf27215	903	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
<>	133:99b5ccf27215	904	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
<>	133:99b5ccf27215	905
<>	133:99b5ccf27215	906	/* DWT Folded-instruction Count Register Definitions */
<>	133:99b5ccf27215	907	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
<>	133:99b5ccf27215	908	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
<>	133:99b5ccf27215	909
<>	133:99b5ccf27215	910	/* DWT Comparator Mask Register Definitions */
<>	133:99b5ccf27215	911	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
<>	133:99b5ccf27215	912	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
<>	133:99b5ccf27215	913
<>	133:99b5ccf27215	914	/* DWT Comparator Function Register Definitions */
<>	133:99b5ccf27215	915	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
<>	133:99b5ccf27215	916	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
<>	133:99b5ccf27215	917
<>	133:99b5ccf27215	918	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
<>	133:99b5ccf27215	919	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
<>	133:99b5ccf27215	920
<>	133:99b5ccf27215	921	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
<>	133:99b5ccf27215	922	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
<>	133:99b5ccf27215	923
<>	133:99b5ccf27215	924	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
<>	133:99b5ccf27215	925	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
<>	133:99b5ccf27215	926
<>	133:99b5ccf27215	927	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
<>	133:99b5ccf27215	928	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
<>	133:99b5ccf27215	929
<>	133:99b5ccf27215	930	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
<>	133:99b5ccf27215	931	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
<>	133:99b5ccf27215	932
<>	133:99b5ccf27215	933	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
<>	133:99b5ccf27215	934	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
<>	133:99b5ccf27215	935
<>	133:99b5ccf27215	936	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
<>	133:99b5ccf27215	937	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
<>	133:99b5ccf27215	938
<>	133:99b5ccf27215	939	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
<>	133:99b5ccf27215	940	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
<>	133:99b5ccf27215	941
<>	133:99b5ccf27215	942	/@}/ /* end of group CMSIS_DWT */
<>	133:99b5ccf27215	943
<>	133:99b5ccf27215	944
<>	133:99b5ccf27215	945	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	946	\defgroup CMSIS_TPI Trace Port Interface (TPI)
<>	133:99b5ccf27215	947	\brief Type definitions for the Trace Port Interface (TPI)
<>	133:99b5ccf27215	948	@{
<>	133:99b5ccf27215	949	*/
<>	133:99b5ccf27215	950
<>	133:99b5ccf27215	951	/** \brief Structure type to access the Trace Port Interface Register (TPI).
<>	133:99b5ccf27215	952	*/
<>	133:99b5ccf27215	953	typedef struct
<>	133:99b5ccf27215	954	{
<>	133:99b5ccf27215	955	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
<>	133:99b5ccf27215	956	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
<>	133:99b5ccf27215	957	uint32_t RESERVED0[2];
<>	133:99b5ccf27215	958	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
<>	133:99b5ccf27215	959	uint32_t RESERVED1[55];
<>	133:99b5ccf27215	960	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
<>	133:99b5ccf27215	961	uint32_t RESERVED2[131];
<>	133:99b5ccf27215	962	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
<>	133:99b5ccf27215	963	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
<>	133:99b5ccf27215	964	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
<>	133:99b5ccf27215	965	uint32_t RESERVED3[759];
<>	133:99b5ccf27215	966	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
<>	133:99b5ccf27215	967	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
<>	133:99b5ccf27215	968	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
<>	133:99b5ccf27215	969	uint32_t RESERVED4[1];
<>	133:99b5ccf27215	970	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
<>	133:99b5ccf27215	971	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
<>	133:99b5ccf27215	972	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
<>	133:99b5ccf27215	973	uint32_t RESERVED5[39];
<>	133:99b5ccf27215	974	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
<>	133:99b5ccf27215	975	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
<>	133:99b5ccf27215	976	uint32_t RESERVED7[8];
<>	133:99b5ccf27215	977	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
<>	133:99b5ccf27215	978	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
<>	133:99b5ccf27215	979	} TPI_Type;
<>	133:99b5ccf27215	980
<>	133:99b5ccf27215	981	/* TPI Asynchronous Clock Prescaler Register Definitions */
<>	133:99b5ccf27215	982	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
<>	133:99b5ccf27215	983	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
<>	133:99b5ccf27215	984
<>	133:99b5ccf27215	985	/* TPI Selected Pin Protocol Register Definitions */
<>	133:99b5ccf27215	986	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
<>	133:99b5ccf27215	987	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
<>	133:99b5ccf27215	988
<>	133:99b5ccf27215	989	/* TPI Formatter and Flush Status Register Definitions */
<>	133:99b5ccf27215	990	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
<>	133:99b5ccf27215	991	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
<>	133:99b5ccf27215	992
<>	133:99b5ccf27215	993	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
<>	133:99b5ccf27215	994	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
<>	133:99b5ccf27215	995
<>	133:99b5ccf27215	996	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
<>	133:99b5ccf27215	997	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
<>	133:99b5ccf27215	998
<>	133:99b5ccf27215	999	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
<>	133:99b5ccf27215	1000	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
<>	133:99b5ccf27215	1001
<>	133:99b5ccf27215	1002	/* TPI Formatter and Flush Control Register Definitions */
<>	133:99b5ccf27215	1003	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
<>	133:99b5ccf27215	1004	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
<>	133:99b5ccf27215	1005
<>	133:99b5ccf27215	1006	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
<>	133:99b5ccf27215	1007	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
<>	133:99b5ccf27215	1008
<>	133:99b5ccf27215	1009	/* TPI TRIGGER Register Definitions */
<>	133:99b5ccf27215	1010	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
<>	133:99b5ccf27215	1011	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
<>	133:99b5ccf27215	1012
<>	133:99b5ccf27215	1013	/* TPI Integration ETM Data Register Definitions (FIFO0) */
<>	133:99b5ccf27215	1014	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
<>	133:99b5ccf27215	1015	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
<>	133:99b5ccf27215	1016
<>	133:99b5ccf27215	1017	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
<>	133:99b5ccf27215	1018	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
<>	133:99b5ccf27215	1019
<>	133:99b5ccf27215	1020	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
<>	133:99b5ccf27215	1021	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
<>	133:99b5ccf27215	1022
<>	133:99b5ccf27215	1023	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
<>	133:99b5ccf27215	1024	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
<>	133:99b5ccf27215	1025
<>	133:99b5ccf27215	1026	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
<>	133:99b5ccf27215	1027	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
<>	133:99b5ccf27215	1028
<>	133:99b5ccf27215	1029	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
<>	133:99b5ccf27215	1030	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
<>	133:99b5ccf27215	1031
<>	133:99b5ccf27215	1032	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
<>	133:99b5ccf27215	1033	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
<>	133:99b5ccf27215	1034
<>	133:99b5ccf27215	1035	/* TPI ITATBCTR2 Register Definitions */
<>	133:99b5ccf27215	1036	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
<>	133:99b5ccf27215	1037	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
<>	133:99b5ccf27215	1038
<>	133:99b5ccf27215	1039	/* TPI Integration ITM Data Register Definitions (FIFO1) */
<>	133:99b5ccf27215	1040	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
<>	133:99b5ccf27215	1041	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
<>	133:99b5ccf27215	1042
<>	133:99b5ccf27215	1043	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
<>	133:99b5ccf27215	1044	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
<>	133:99b5ccf27215	1045
<>	133:99b5ccf27215	1046	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
<>	133:99b5ccf27215	1047	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
<>	133:99b5ccf27215	1048
<>	133:99b5ccf27215	1049	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
<>	133:99b5ccf27215	1050	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
<>	133:99b5ccf27215	1051
<>	133:99b5ccf27215	1052	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
<>	133:99b5ccf27215	1053	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
<>	133:99b5ccf27215	1054
<>	133:99b5ccf27215	1055	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
<>	133:99b5ccf27215	1056	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
<>	133:99b5ccf27215	1057
<>	133:99b5ccf27215	1058	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
<>	133:99b5ccf27215	1059	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
<>	133:99b5ccf27215	1060
<>	133:99b5ccf27215	1061	/* TPI ITATBCTR0 Register Definitions */
<>	133:99b5ccf27215	1062	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
<>	133:99b5ccf27215	1063	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
<>	133:99b5ccf27215	1064
<>	133:99b5ccf27215	1065	/* TPI Integration Mode Control Register Definitions */
<>	133:99b5ccf27215	1066	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
<>	133:99b5ccf27215	1067	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
<>	133:99b5ccf27215	1068
<>	133:99b5ccf27215	1069	/* TPI DEVID Register Definitions */
<>	133:99b5ccf27215	1070	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
<>	133:99b5ccf27215	1071	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
<>	133:99b5ccf27215	1072
<>	133:99b5ccf27215	1073	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
<>	133:99b5ccf27215	1074	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
<>	133:99b5ccf27215	1075
<>	133:99b5ccf27215	1076	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
<>	133:99b5ccf27215	1077	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
<>	133:99b5ccf27215	1078
<>	133:99b5ccf27215	1079	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
<>	133:99b5ccf27215	1080	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
<>	133:99b5ccf27215	1081
<>	133:99b5ccf27215	1082	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
<>	133:99b5ccf27215	1083	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
<>	133:99b5ccf27215	1084
<>	133:99b5ccf27215	1085	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
<>	133:99b5ccf27215	1086	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
<>	133:99b5ccf27215	1087
<>	133:99b5ccf27215	1088	/* TPI DEVTYPE Register Definitions */
<>	133:99b5ccf27215	1089	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
<>	133:99b5ccf27215	1090	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
<>	133:99b5ccf27215	1091
<>	133:99b5ccf27215	1092	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
<>	133:99b5ccf27215	1093	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
<>	133:99b5ccf27215	1094
<>	133:99b5ccf27215	1095	/@}/ /* end of group CMSIS_TPI */
<>	133:99b5ccf27215	1096
<>	133:99b5ccf27215	1097
<>	133:99b5ccf27215	1098	#if (__MPU_PRESENT == 1)
<>	133:99b5ccf27215	1099	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	1100	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
<>	133:99b5ccf27215	1101	\brief Type definitions for the Memory Protection Unit (MPU)
<>	133:99b5ccf27215	1102	@{
<>	133:99b5ccf27215	1103	*/
<>	133:99b5ccf27215	1104
<>	133:99b5ccf27215	1105	/** \brief Structure type to access the Memory Protection Unit (MPU).
<>	133:99b5ccf27215	1106	*/
<>	133:99b5ccf27215	1107	typedef struct
<>	133:99b5ccf27215	1108	{
<>	133:99b5ccf27215	1109	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
<>	133:99b5ccf27215	1110	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
<>	133:99b5ccf27215	1111	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
<>	133:99b5ccf27215	1112	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
<>	133:99b5ccf27215	1113	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
<>	133:99b5ccf27215	1114	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
<>	133:99b5ccf27215	1115	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
<>	133:99b5ccf27215	1116	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
<>	133:99b5ccf27215	1117	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
<>	133:99b5ccf27215	1118	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
<>	133:99b5ccf27215	1119	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
<>	133:99b5ccf27215	1120	} MPU_Type;
<>	133:99b5ccf27215	1121
<>	133:99b5ccf27215	1122	/* MPU Type Register */
<>	133:99b5ccf27215	1123	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
<>	133:99b5ccf27215	1124	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
<>	133:99b5ccf27215	1125
<>	133:99b5ccf27215	1126	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
<>	133:99b5ccf27215	1127	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
<>	133:99b5ccf27215	1128
<>	133:99b5ccf27215	1129	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
<>	133:99b5ccf27215	1130	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
<>	133:99b5ccf27215	1131
<>	133:99b5ccf27215	1132	/* MPU Control Register */
<>	133:99b5ccf27215	1133	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
<>	133:99b5ccf27215	1134	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
<>	133:99b5ccf27215	1135
<>	133:99b5ccf27215	1136	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
<>	133:99b5ccf27215	1137	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
<>	133:99b5ccf27215	1138
<>	133:99b5ccf27215	1139	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
<>	133:99b5ccf27215	1140	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
<>	133:99b5ccf27215	1141
<>	133:99b5ccf27215	1142	/* MPU Region Number Register */
<>	133:99b5ccf27215	1143	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
<>	133:99b5ccf27215	1144	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
<>	133:99b5ccf27215	1145
<>	133:99b5ccf27215	1146	/* MPU Region Base Address Register */
<>	133:99b5ccf27215	1147	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
<>	133:99b5ccf27215	1148	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
<>	133:99b5ccf27215	1149
<>	133:99b5ccf27215	1150	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
<>	133:99b5ccf27215	1151	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
<>	133:99b5ccf27215	1152
<>	133:99b5ccf27215	1153	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
<>	133:99b5ccf27215	1154	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
<>	133:99b5ccf27215	1155
<>	133:99b5ccf27215	1156	/* MPU Region Attribute and Size Register */
<>	133:99b5ccf27215	1157	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
<>	133:99b5ccf27215	1158	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
<>	133:99b5ccf27215	1159
<>	133:99b5ccf27215	1160	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
<>	133:99b5ccf27215	1161	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
<>	133:99b5ccf27215	1162
<>	133:99b5ccf27215	1163	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
<>	133:99b5ccf27215	1164	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
<>	133:99b5ccf27215	1165
<>	133:99b5ccf27215	1166	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
<>	133:99b5ccf27215	1167	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
<>	133:99b5ccf27215	1168
<>	133:99b5ccf27215	1169	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
<>	133:99b5ccf27215	1170	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
<>	133:99b5ccf27215	1171
<>	133:99b5ccf27215	1172	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
<>	133:99b5ccf27215	1173	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
<>	133:99b5ccf27215	1174
<>	133:99b5ccf27215	1175	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
<>	133:99b5ccf27215	1176	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
<>	133:99b5ccf27215	1177
<>	133:99b5ccf27215	1178	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
<>	133:99b5ccf27215	1179	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
<>	133:99b5ccf27215	1180
<>	133:99b5ccf27215	1181	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
<>	133:99b5ccf27215	1182	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
<>	133:99b5ccf27215	1183
<>	133:99b5ccf27215	1184	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
<>	133:99b5ccf27215	1185	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
<>	133:99b5ccf27215	1186
<>	133:99b5ccf27215	1187	/@} end of group CMSIS_MPU /
<>	133:99b5ccf27215	1188	#endif
<>	133:99b5ccf27215	1189
<>	133:99b5ccf27215	1190
<>	133:99b5ccf27215	1191	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	1192	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<>	133:99b5ccf27215	1193	\brief Type definitions for the Core Debug Registers
<>	133:99b5ccf27215	1194	@{
<>	133:99b5ccf27215	1195	*/
<>	133:99b5ccf27215	1196
<>	133:99b5ccf27215	1197	/** \brief Structure type to access the Core Debug Register (CoreDebug).
<>	133:99b5ccf27215	1198	*/
<>	133:99b5ccf27215	1199	typedef struct
<>	133:99b5ccf27215	1200	{
<>	133:99b5ccf27215	1201	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
<>	133:99b5ccf27215	1202	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
<>	133:99b5ccf27215	1203	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
<>	133:99b5ccf27215	1204	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
<>	133:99b5ccf27215	1205	} CoreDebug_Type;
<>	133:99b5ccf27215	1206
<>	133:99b5ccf27215	1207	/* Debug Halting Control and Status Register */
<>	133:99b5ccf27215	1208	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
<>	133:99b5ccf27215	1209	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
<>	133:99b5ccf27215	1210
<>	133:99b5ccf27215	1211	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
<>	133:99b5ccf27215	1212	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
<>	133:99b5ccf27215	1213
<>	133:99b5ccf27215	1214	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
<>	133:99b5ccf27215	1215	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
<>	133:99b5ccf27215	1216
<>	133:99b5ccf27215	1217	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
<>	133:99b5ccf27215	1218	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
<>	133:99b5ccf27215	1219
<>	133:99b5ccf27215	1220	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
<>	133:99b5ccf27215	1221	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
<>	133:99b5ccf27215	1222
<>	133:99b5ccf27215	1223	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
<>	133:99b5ccf27215	1224	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
<>	133:99b5ccf27215	1225
<>	133:99b5ccf27215	1226	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
<>	133:99b5ccf27215	1227	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
<>	133:99b5ccf27215	1228
<>	133:99b5ccf27215	1229	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
<>	133:99b5ccf27215	1230	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
<>	133:99b5ccf27215	1231
<>	133:99b5ccf27215	1232	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
<>	133:99b5ccf27215	1233	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
<>	133:99b5ccf27215	1234
<>	133:99b5ccf27215	1235	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
<>	133:99b5ccf27215	1236	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
<>	133:99b5ccf27215	1237
<>	133:99b5ccf27215	1238	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
<>	133:99b5ccf27215	1239	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
<>	133:99b5ccf27215	1240
<>	133:99b5ccf27215	1241	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
<>	133:99b5ccf27215	1242	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
<>	133:99b5ccf27215	1243
<>	133:99b5ccf27215	1244	/* Debug Core Register Selector Register */
<>	133:99b5ccf27215	1245	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
<>	133:99b5ccf27215	1246	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
<>	133:99b5ccf27215	1247
<>	133:99b5ccf27215	1248	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
<>	133:99b5ccf27215	1249	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
<>	133:99b5ccf27215	1250
<>	133:99b5ccf27215	1251	/* Debug Exception and Monitor Control Register */
<>	133:99b5ccf27215	1252	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
<>	133:99b5ccf27215	1253	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
<>	133:99b5ccf27215	1254
<>	133:99b5ccf27215	1255	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
<>	133:99b5ccf27215	1256	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
<>	133:99b5ccf27215	1257
<>	133:99b5ccf27215	1258	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
<>	133:99b5ccf27215	1259	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
<>	133:99b5ccf27215	1260
<>	133:99b5ccf27215	1261	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
<>	133:99b5ccf27215	1262	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
<>	133:99b5ccf27215	1263
<>	133:99b5ccf27215	1264	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
<>	133:99b5ccf27215	1265	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
<>	133:99b5ccf27215	1266
<>	133:99b5ccf27215	1267	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
<>	133:99b5ccf27215	1268	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
<>	133:99b5ccf27215	1269
<>	133:99b5ccf27215	1270	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
<>	133:99b5ccf27215	1271	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
<>	133:99b5ccf27215	1272
<>	133:99b5ccf27215	1273	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
<>	133:99b5ccf27215	1274	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
<>	133:99b5ccf27215	1275
<>	133:99b5ccf27215	1276	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
<>	133:99b5ccf27215	1277	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
<>	133:99b5ccf27215	1278
<>	133:99b5ccf27215	1279	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
<>	133:99b5ccf27215	1280	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
<>	133:99b5ccf27215	1281
<>	133:99b5ccf27215	1282	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
<>	133:99b5ccf27215	1283	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
<>	133:99b5ccf27215	1284
<>	133:99b5ccf27215	1285	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
<>	133:99b5ccf27215	1286	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
<>	133:99b5ccf27215	1287
<>	133:99b5ccf27215	1288	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
<>	133:99b5ccf27215	1289	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
<>	133:99b5ccf27215	1290
<>	133:99b5ccf27215	1291	/@} end of group CMSIS_CoreDebug /
<>	133:99b5ccf27215	1292
<>	133:99b5ccf27215	1293
<>	133:99b5ccf27215	1294	/** \ingroup CMSIS_core_register
<>	133:99b5ccf27215	1295	\defgroup CMSIS_core_base Core Definitions
<>	133:99b5ccf27215	1296	\brief Definitions for base addresses, unions, and structures.
<>	133:99b5ccf27215	1297	@{
<>	133:99b5ccf27215	1298	*/
<>	133:99b5ccf27215	1299
<>	133:99b5ccf27215	1300	/* Memory mapping of Cortex-M3 Hardware */
<>	133:99b5ccf27215	1301	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
<>	133:99b5ccf27215	1302	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
<>	133:99b5ccf27215	1303	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
<>	133:99b5ccf27215	1304	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
<>	133:99b5ccf27215	1305	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
<>	133:99b5ccf27215	1306	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
<>	133:99b5ccf27215	1307	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
<>	133:99b5ccf27215	1308	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
<>	133:99b5ccf27215	1309
<>	133:99b5ccf27215	1310	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
<>	133:99b5ccf27215	1311	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
<>	133:99b5ccf27215	1312	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
<>	133:99b5ccf27215	1313	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
<>	133:99b5ccf27215	1314	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
<>	133:99b5ccf27215	1315	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
<>	133:99b5ccf27215	1316	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
<>	133:99b5ccf27215	1317	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
<>	133:99b5ccf27215	1318
<>	133:99b5ccf27215	1319	#if (__MPU_PRESENT == 1)
<>	133:99b5ccf27215	1320	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
<>	133:99b5ccf27215	1321	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
<>	133:99b5ccf27215	1322	#endif
<>	133:99b5ccf27215	1323
<>	133:99b5ccf27215	1324	/@} /
<>	133:99b5ccf27215	1325
<>	133:99b5ccf27215	1326
<>	133:99b5ccf27215	1327
<>	133:99b5ccf27215	1328	/*******************************************************************************
<>	133:99b5ccf27215	1329	* Hardware Abstraction Layer
<>	133:99b5ccf27215	1330	Core Function Interface contains:
<>	133:99b5ccf27215	1331	- Core NVIC Functions
<>	133:99b5ccf27215	1332	- Core SysTick Functions
<>	133:99b5ccf27215	1333	- Core Debug Functions
<>	133:99b5ccf27215	1334	- Core Register Access Functions
<>	133:99b5ccf27215	1335	******************************************************************************/
<>	133:99b5ccf27215	1336	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<>	133:99b5ccf27215	1337	*/
<>	133:99b5ccf27215	1338
<>	133:99b5ccf27215	1339
<>	133:99b5ccf27215	1340
<>	133:99b5ccf27215	1341	/* ########################## NVIC functions #################################### */
<>	133:99b5ccf27215	1342	/** \ingroup CMSIS_Core_FunctionInterface
<>	133:99b5ccf27215	1343	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
<>	133:99b5ccf27215	1344	\brief Functions that manage interrupts and exceptions via the NVIC.
<>	133:99b5ccf27215	1345	@{
<>	133:99b5ccf27215	1346	*/
<>	133:99b5ccf27215	1347
<>	133:99b5ccf27215	1348	#ifdef CMSIS_NVIC_VIRTUAL
<>	133:99b5ccf27215	1349	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	133:99b5ccf27215	1350	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<>	133:99b5ccf27215	1351	#endif
<>	133:99b5ccf27215	1352	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<>	133:99b5ccf27215	1353	#else
<>	133:99b5ccf27215	1354	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<>	133:99b5ccf27215	1355	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<>	133:99b5ccf27215	1356	#define NVIC_EnableIRQ __NVIC_EnableIRQ
<>	133:99b5ccf27215	1357	#define NVIC_DisableIRQ __NVIC_DisableIRQ
<>	133:99b5ccf27215	1358	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<>	133:99b5ccf27215	1359	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<>	133:99b5ccf27215	1360	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<>	133:99b5ccf27215	1361	#define NVIC_GetActive __NVIC_GetActive
<>	133:99b5ccf27215	1362	#define NVIC_SetPriority __NVIC_SetPriority
<>	133:99b5ccf27215	1363	#define NVIC_GetPriority __NVIC_GetPriority
<>	133:99b5ccf27215	1364	#define NVIC_SystemReset __NVIC_SystemReset
<>	133:99b5ccf27215	1365	#endif /* CMSIS_NVIC_VIRTUAL */
<>	133:99b5ccf27215	1366
<>	133:99b5ccf27215	1367	#ifdef CMSIS_VECTAB_VIRTUAL
<>	133:99b5ccf27215	1368	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<>	133:99b5ccf27215	1369	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<>	133:99b5ccf27215	1370	#endif
<>	133:99b5ccf27215	1371	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<>	133:99b5ccf27215	1372	#else
<>	133:99b5ccf27215	1373	#define NVIC_SetVector __NVIC_SetVector
<>	133:99b5ccf27215	1374	#define NVIC_GetVector __NVIC_GetVector
<>	133:99b5ccf27215	1375	#endif /* CMSIS_VECTAB_VIRTUAL */
<>	133:99b5ccf27215	1376
<>	133:99b5ccf27215	1377	/** \brief Set Priority Grouping
<>	133:99b5ccf27215	1378
<>	133:99b5ccf27215	1379	The function sets the priority grouping field using the required unlock sequence.
<>	133:99b5ccf27215	1380	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<>	133:99b5ccf27215	1381	Only values from 0..7 are used.
<>	133:99b5ccf27215	1382	In case of a conflict between priority grouping and available
<>	133:99b5ccf27215	1383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	133:99b5ccf27215	1384
<>	133:99b5ccf27215	1385	\param [in] PriorityGroup Priority grouping field.
<>	133:99b5ccf27215	1386	*/
<>	133:99b5ccf27215	1387	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<>	133:99b5ccf27215	1388	{
<>	133:99b5ccf27215	1389	uint32_t reg_value;
<>	133:99b5ccf27215	1390	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	133:99b5ccf27215	1391
<>	133:99b5ccf27215	1392	reg_value = SCB->AIRCR; /* read old register configuration */
<>	133:99b5ccf27215	1393	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<>	133:99b5ccf27215	1394	reg_value = (reg_value \|
<>	133:99b5ccf27215	1395	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	133:99b5ccf27215	1396	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<>	133:99b5ccf27215	1397	SCB->AIRCR = reg_value;
<>	133:99b5ccf27215	1398	}
<>	133:99b5ccf27215	1399
<>	133:99b5ccf27215	1400
<>	133:99b5ccf27215	1401	/** \brief Get Priority Grouping
<>	133:99b5ccf27215	1402
<>	133:99b5ccf27215	1403	The function reads the priority grouping field from the NVIC Interrupt Controller.
<>	133:99b5ccf27215	1404
<>	133:99b5ccf27215	1405	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<>	133:99b5ccf27215	1406	*/
<>	133:99b5ccf27215	1407	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<>	133:99b5ccf27215	1408	{
<>	133:99b5ccf27215	1409	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<>	133:99b5ccf27215	1410	}
<>	133:99b5ccf27215	1411
<>	133:99b5ccf27215	1412
<>	133:99b5ccf27215	1413	/** \brief Enable External Interrupt
<>	133:99b5ccf27215	1414
<>	133:99b5ccf27215	1415	The function enables a device-specific interrupt in the NVIC interrupt controller.
<>	133:99b5ccf27215	1416
<>	133:99b5ccf27215	1417	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	133:99b5ccf27215	1418	*/
<>	133:99b5ccf27215	1419	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<>	133:99b5ccf27215	1420	{
<>	133:99b5ccf27215	1421	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	133:99b5ccf27215	1422	}
<>	133:99b5ccf27215	1423
<>	133:99b5ccf27215	1424
<>	133:99b5ccf27215	1425	/** \brief Disable External Interrupt
<>	133:99b5ccf27215	1426
<>	133:99b5ccf27215	1427	The function disables a device-specific interrupt in the NVIC interrupt controller.
<>	133:99b5ccf27215	1428
<>	133:99b5ccf27215	1429	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	133:99b5ccf27215	1430	*/
<>	133:99b5ccf27215	1431	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<>	133:99b5ccf27215	1432	{
<>	133:99b5ccf27215	1433	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	133:99b5ccf27215	1434	__DSB();
<>	133:99b5ccf27215	1435	__ISB();
<>	133:99b5ccf27215	1436	}
<>	133:99b5ccf27215	1437
<>	133:99b5ccf27215	1438
<>	133:99b5ccf27215	1439	/** \brief Get Pending Interrupt
<>	133:99b5ccf27215	1440
<>	133:99b5ccf27215	1441	The function reads the pending register in the NVIC and returns the pending bit
<>	133:99b5ccf27215	1442	for the specified interrupt.
<>	133:99b5ccf27215	1443
<>	133:99b5ccf27215	1444	\param [in] IRQn Interrupt number.
<>	133:99b5ccf27215	1445
<>	133:99b5ccf27215	1446	\return 0 Interrupt status is not pending.
<>	133:99b5ccf27215	1447	\return 1 Interrupt status is pending.
<>	133:99b5ccf27215	1448	*/
<>	133:99b5ccf27215	1449	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<>	133:99b5ccf27215	1450	{
<>	133:99b5ccf27215	1451	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	133:99b5ccf27215	1452	}
<>	133:99b5ccf27215	1453
<>	133:99b5ccf27215	1454
<>	133:99b5ccf27215	1455	/** \brief Set Pending Interrupt
<>	133:99b5ccf27215	1456
<>	133:99b5ccf27215	1457	The function sets the pending bit of an external interrupt.
<>	133:99b5ccf27215	1458
<>	133:99b5ccf27215	1459	\param [in] IRQn Interrupt number. Value cannot be negative.
<>	133:99b5ccf27215	1460	*/
<>	133:99b5ccf27215	1461	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<>	133:99b5ccf27215	1462	{
<>	133:99b5ccf27215	1463	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	133:99b5ccf27215	1464	}
<>	133:99b5ccf27215	1465
<>	133:99b5ccf27215	1466
<>	133:99b5ccf27215	1467	/** \brief Clear Pending Interrupt
<>	133:99b5ccf27215	1468
<>	133:99b5ccf27215	1469	The function clears the pending bit of an external interrupt.
<>	133:99b5ccf27215	1470
<>	133:99b5ccf27215	1471	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	133:99b5ccf27215	1472	*/
<>	133:99b5ccf27215	1473	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<>	133:99b5ccf27215	1474	{
<>	133:99b5ccf27215	1475	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	133:99b5ccf27215	1476	}
<>	133:99b5ccf27215	1477
<>	133:99b5ccf27215	1478
<>	133:99b5ccf27215	1479	/** \brief Get Active Interrupt
<>	133:99b5ccf27215	1480
<>	133:99b5ccf27215	1481	The function reads the active register in NVIC and returns the active bit.
<>	133:99b5ccf27215	1482
<>	133:99b5ccf27215	1483	\param [in] IRQn Interrupt number.
<>	133:99b5ccf27215	1484
<>	133:99b5ccf27215	1485	\return 0 Interrupt status is not active.
<>	133:99b5ccf27215	1486	\return 1 Interrupt status is active.
<>	133:99b5ccf27215	1487	*/
<>	133:99b5ccf27215	1488	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
<>	133:99b5ccf27215	1489	{
<>	133:99b5ccf27215	1490	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	133:99b5ccf27215	1491	}
<>	133:99b5ccf27215	1492
<>	133:99b5ccf27215	1493
<>	133:99b5ccf27215	1494	/** \brief Set Interrupt Priority
<>	133:99b5ccf27215	1495
<>	133:99b5ccf27215	1496	The function sets the priority of an interrupt.
<>	133:99b5ccf27215	1497
<>	133:99b5ccf27215	1498	\note The priority cannot be set for every core interrupt.
<>	133:99b5ccf27215	1499
<>	133:99b5ccf27215	1500	\param [in] IRQn Interrupt number.
<>	133:99b5ccf27215	1501	\param [in] priority Priority to set.
<>	133:99b5ccf27215	1502	*/
<>	133:99b5ccf27215	1503	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<>	133:99b5ccf27215	1504	{
<>	133:99b5ccf27215	1505	if((int32_t)IRQn < 0) {
<>	133:99b5ccf27215	1506	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	133:99b5ccf27215	1507	}
<>	133:99b5ccf27215	1508	else {
<>	133:99b5ccf27215	1509	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	133:99b5ccf27215	1510	}
<>	133:99b5ccf27215	1511	}
<>	133:99b5ccf27215	1512
<>	133:99b5ccf27215	1513
<>	133:99b5ccf27215	1514	/** \brief Get Interrupt Priority
<>	133:99b5ccf27215	1515
<>	133:99b5ccf27215	1516	The function reads the priority of an interrupt. The interrupt
<>	133:99b5ccf27215	1517	number can be positive to specify an external (device specific)
<>	133:99b5ccf27215	1518	interrupt, or negative to specify an internal (core) interrupt.
<>	133:99b5ccf27215	1519
<>	133:99b5ccf27215	1520
<>	133:99b5ccf27215	1521	\param [in] IRQn Interrupt number.
<>	133:99b5ccf27215	1522	\return Interrupt Priority. Value is aligned automatically to the implemented
<>	133:99b5ccf27215	1523	priority bits of the microcontroller.
<>	133:99b5ccf27215	1524	*/
<>	133:99b5ccf27215	1525	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<>	133:99b5ccf27215	1526	{
<>	133:99b5ccf27215	1527
<>	133:99b5ccf27215	1528	if((int32_t)IRQn < 0) {
<>	133:99b5ccf27215	1529	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<>	133:99b5ccf27215	1530	}
<>	133:99b5ccf27215	1531	else {
<>	133:99b5ccf27215	1532	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<>	133:99b5ccf27215	1533	}
<>	133:99b5ccf27215	1534	}
<>	133:99b5ccf27215	1535
<>	133:99b5ccf27215	1536
<>	133:99b5ccf27215	1537	/** \brief Encode Priority
<>	133:99b5ccf27215	1538
<>	133:99b5ccf27215	1539	The function encodes the priority for an interrupt with the given priority group,
<>	133:99b5ccf27215	1540	preemptive priority value, and subpriority value.
<>	133:99b5ccf27215	1541	In case of a conflict between priority grouping and available
<>	133:99b5ccf27215	1542	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	133:99b5ccf27215	1543
<>	133:99b5ccf27215	1544	\param [in] PriorityGroup Used priority group.
<>	133:99b5ccf27215	1545	\param [in] PreemptPriority Preemptive priority value (starting from 0).
<>	133:99b5ccf27215	1546	\param [in] SubPriority Subpriority value (starting from 0).
<>	133:99b5ccf27215	1547	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<>	133:99b5ccf27215	1548	*/
<>	133:99b5ccf27215	1549	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<>	133:99b5ccf27215	1550	{
<>	133:99b5ccf27215	1551	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	133:99b5ccf27215	1552	uint32_t PreemptPriorityBits;
<>	133:99b5ccf27215	1553	uint32_t SubPriorityBits;
<>	133:99b5ccf27215	1554
<>	133:99b5ccf27215	1555	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	133:99b5ccf27215	1556	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	133:99b5ccf27215	1557
<>	133:99b5ccf27215	1558	return (
<>	133:99b5ccf27215	1559	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
<>	133:99b5ccf27215	1560	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<>	133:99b5ccf27215	1561	);
<>	133:99b5ccf27215	1562	}
<>	133:99b5ccf27215	1563
<>	133:99b5ccf27215	1564
<>	133:99b5ccf27215	1565	/** \brief Decode Priority
<>	133:99b5ccf27215	1566
<>	133:99b5ccf27215	1567	The function decodes an interrupt priority value with a given priority group to
<>	133:99b5ccf27215	1568	preemptive priority value and subpriority value.
<>	133:99b5ccf27215	1569	In case of a conflict between priority grouping and available
<>	133:99b5ccf27215	1570	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<>	133:99b5ccf27215	1571
<>	133:99b5ccf27215	1572	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<>	133:99b5ccf27215	1573	\param [in] PriorityGroup Used priority group.
<>	133:99b5ccf27215	1574	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
<>	133:99b5ccf27215	1575	\param [out] pSubPriority Subpriority value (starting from 0).
<>	133:99b5ccf27215	1576	*/
<>	133:99b5ccf27215	1577	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<>	133:99b5ccf27215	1578	{
<>	133:99b5ccf27215	1579	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	133:99b5ccf27215	1580	uint32_t PreemptPriorityBits;
<>	133:99b5ccf27215	1581	uint32_t SubPriorityBits;
<>	133:99b5ccf27215	1582
<>	133:99b5ccf27215	1583	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	133:99b5ccf27215	1584	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	133:99b5ccf27215	1585
<>	133:99b5ccf27215	1586	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<>	133:99b5ccf27215	1587	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<>	133:99b5ccf27215	1588	}
<>	133:99b5ccf27215	1589
<>	133:99b5ccf27215	1590
<>	133:99b5ccf27215	1591	/** \brief System Reset
<>	133:99b5ccf27215	1592
<>	133:99b5ccf27215	1593	The function initiates a system reset request to reset the MCU.
<>	133:99b5ccf27215	1594	*/
<>	133:99b5ccf27215	1595	__STATIC_INLINE void __NVIC_SystemReset(void)
<>	133:99b5ccf27215	1596	{
<>	133:99b5ccf27215	1597	__DSB(); /* Ensure all outstanding memory accesses included
<>	133:99b5ccf27215	1598	buffered write are completed before reset */
<>	133:99b5ccf27215	1599	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	133:99b5ccf27215	1600	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
<>	133:99b5ccf27215	1601	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<>	133:99b5ccf27215	1602	__DSB(); /* Ensure completion of memory access */
<>	133:99b5ccf27215	1603	while(1) { __NOP(); } /* wait until reset */
<>	133:99b5ccf27215	1604	}
<>	133:99b5ccf27215	1605
<>	133:99b5ccf27215	1606	/@} end of CMSIS_Core_NVICFunctions /
<>	133:99b5ccf27215	1607
<>	133:99b5ccf27215	1608
<>	133:99b5ccf27215	1609
<>	133:99b5ccf27215	1610	/* ################################## SysTick function ############################################ */
<>	133:99b5ccf27215	1611	/** \ingroup CMSIS_Core_FunctionInterface
<>	133:99b5ccf27215	1612	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<>	133:99b5ccf27215	1613	\brief Functions that configure the System.
<>	133:99b5ccf27215	1614	@{
<>	133:99b5ccf27215	1615	*/
<>	133:99b5ccf27215	1616
<>	133:99b5ccf27215	1617	#if (__Vendor_SysTickConfig == 0)
<>	133:99b5ccf27215	1618
<>	133:99b5ccf27215	1619	/** \brief System Tick Configuration
<>	133:99b5ccf27215	1620
<>	133:99b5ccf27215	1621	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<>	133:99b5ccf27215	1622	Counter is in free running mode to generate periodic interrupts.
<>	133:99b5ccf27215	1623
<>	133:99b5ccf27215	1624	\param [in] ticks Number of ticks between two interrupts.
<>	133:99b5ccf27215	1625
<>	133:99b5ccf27215	1626	\return 0 Function succeeded.
<>	133:99b5ccf27215	1627	\return 1 Function failed.
<>	133:99b5ccf27215	1628
<>	133:99b5ccf27215	1629	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<>	133:99b5ccf27215	1630	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<>	133:99b5ccf27215	1631	must contain a vendor-specific implementation of this function.
<>	133:99b5ccf27215	1632
<>	133:99b5ccf27215	1633	*/
<>	133:99b5ccf27215	1634	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<>	133:99b5ccf27215	1635	{
<>	133:99b5ccf27215	1636	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<>	133:99b5ccf27215	1637
<>	133:99b5ccf27215	1638	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<>	133:99b5ccf27215	1639	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<>	133:99b5ccf27215	1640	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<>	133:99b5ccf27215	1641	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
<>	133:99b5ccf27215	1642	SysTick_CTRL_TICKINT_Msk \|
<>	133:99b5ccf27215	1643	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<>	133:99b5ccf27215	1644	return (0UL); /* Function successful */
<>	133:99b5ccf27215	1645	}
<>	133:99b5ccf27215	1646
<>	133:99b5ccf27215	1647	#endif
<>	133:99b5ccf27215	1648
<>	133:99b5ccf27215	1649	/@} end of CMSIS_Core_SysTickFunctions /
<>	133:99b5ccf27215	1650
<>	133:99b5ccf27215	1651
<>	133:99b5ccf27215	1652
<>	133:99b5ccf27215	1653	/* ##################################### Debug In/Output function ########################################### */
<>	133:99b5ccf27215	1654	/** \ingroup CMSIS_Core_FunctionInterface
<>	133:99b5ccf27215	1655	\defgroup CMSIS_core_DebugFunctions ITM Functions
<>	133:99b5ccf27215	1656	\brief Functions that access the ITM debug interface.
<>	133:99b5ccf27215	1657	@{
<>	133:99b5ccf27215	1658	*/
<>	133:99b5ccf27215	1659
<>	133:99b5ccf27215	1660	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
<>	133:99b5ccf27215	1661	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
<>	133:99b5ccf27215	1662
<>	133:99b5ccf27215	1663
<>	133:99b5ccf27215	1664	/** \brief ITM Send Character
<>	133:99b5ccf27215	1665
<>	133:99b5ccf27215	1666	The function transmits a character via the ITM channel 0, and
<>	133:99b5ccf27215	1667	\li Just returns when no debugger is connected that has booked the output.
<>	133:99b5ccf27215	1668	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<>	133:99b5ccf27215	1669
<>	133:99b5ccf27215	1670	\param [in] ch Character to transmit.
<>	133:99b5ccf27215	1671
<>	133:99b5ccf27215	1672	\returns Character to transmit.
<>	133:99b5ccf27215	1673	*/
<>	133:99b5ccf27215	1674	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<>	133:99b5ccf27215	1675	{
<>	133:99b5ccf27215	1676	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<>	133:99b5ccf27215	1677	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<>	133:99b5ccf27215	1678	{
<>	133:99b5ccf27215	1679	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<>	133:99b5ccf27215	1680	ITM->PORT[0].u8 = (uint8_t)ch;
<>	133:99b5ccf27215	1681	}
<>	133:99b5ccf27215	1682	return (ch);
<>	133:99b5ccf27215	1683	}
<>	133:99b5ccf27215	1684
<>	133:99b5ccf27215	1685
<>	133:99b5ccf27215	1686	/** \brief ITM Receive Character
<>	133:99b5ccf27215	1687
<>	133:99b5ccf27215	1688	The function inputs a character via the external variable \ref ITM_RxBuffer.
<>	133:99b5ccf27215	1689
<>	133:99b5ccf27215	1690	\return Received character.
<>	133:99b5ccf27215	1691	\return -1 No character pending.
<>	133:99b5ccf27215	1692	*/
<>	133:99b5ccf27215	1693	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<>	133:99b5ccf27215	1694	int32_t ch = -1; /* no character available */
<>	133:99b5ccf27215	1695
<>	133:99b5ccf27215	1696	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<>	133:99b5ccf27215	1697	ch = ITM_RxBuffer;
<>	133:99b5ccf27215	1698	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<>	133:99b5ccf27215	1699	}
<>	133:99b5ccf27215	1700
<>	133:99b5ccf27215	1701	return (ch);
<>	133:99b5ccf27215	1702	}
<>	133:99b5ccf27215	1703
<>	133:99b5ccf27215	1704
<>	133:99b5ccf27215	1705	/** \brief ITM Check Character
<>	133:99b5ccf27215	1706
<>	133:99b5ccf27215	1707	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<>	133:99b5ccf27215	1708
<>	133:99b5ccf27215	1709	\return 0 No character available.
<>	133:99b5ccf27215	1710	\return 1 Character available.
<>	133:99b5ccf27215	1711	*/
<>	133:99b5ccf27215	1712	__STATIC_INLINE int32_t ITM_CheckChar (void) {
<>	133:99b5ccf27215	1713
<>	133:99b5ccf27215	1714	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<>	133:99b5ccf27215	1715	return (0); /* no character available */
<>	133:99b5ccf27215	1716	} else {
<>	133:99b5ccf27215	1717	return (1); /* character available */
<>	133:99b5ccf27215	1718	}
<>	133:99b5ccf27215	1719	}
<>	133:99b5ccf27215	1720
<>	133:99b5ccf27215	1721	/@} end of CMSIS_core_DebugFunctions /
<>	133:99b5ccf27215	1722
<>	133:99b5ccf27215	1723
<>	133:99b5ccf27215	1724
<>	133:99b5ccf27215	1725
<>	133:99b5ccf27215	1726	#ifdef __cplusplus
<>	133:99b5ccf27215	1727	}
<>	133:99b5ccf27215	1728	#endif
<>	133:99b5ccf27215	1729
<>	133:99b5ccf27215	1730	#endif /* __CORE_CM3_H_DEPENDANT */
<>	133:99b5ccf27215	1731
<>	133:99b5ccf27215	1732	#endif /* __CMSIS_GENERIC */