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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_UBLOX_EVK_NINA_B1/core_ca_mmu.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
133:99b5ccf27215 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 ;/**************************************************************************//**
<> 133:99b5ccf27215 2 ; * @file core_ca_mmu.h
<> 133:99b5ccf27215 3 ; * @brief MMU Startup File for A9_MP Device Series
<> 133:99b5ccf27215 4 ; * @version V1.01
<> 133:99b5ccf27215 5 ; * @date 10 Sept 2014
<> 133:99b5ccf27215 6 ; *
<> 133:99b5ccf27215 7 ; * @note
<> 133:99b5ccf27215 8 ; *
<> 133:99b5ccf27215 9 ; ******************************************************************************/
<> 133:99b5ccf27215 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
<> 133:99b5ccf27215 11 ;
<> 133:99b5ccf27215 12 ; All rights reserved.
<> 133:99b5ccf27215 13 ; Redistribution and use in source and binary forms, with or without
<> 133:99b5ccf27215 14 ; modification, are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 ; - Redistributions of source code must retain the above copyright
<> 133:99b5ccf27215 16 ; notice, this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 ; - Redistributions in binary form must reproduce the above copyright
<> 133:99b5ccf27215 18 ; notice, this list of conditions and the following disclaimer in the
<> 133:99b5ccf27215 19 ; documentation and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 ; - Neither the name of ARM nor the names of its contributors may be used
<> 133:99b5ccf27215 21 ; to endorse or promote products derived from this software without
<> 133:99b5ccf27215 22 ; specific prior written permission.
<> 133:99b5ccf27215 23 ; *
<> 133:99b5ccf27215 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 133:99b5ccf27215 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 133:99b5ccf27215 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 133:99b5ccf27215 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 133:99b5ccf27215 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 133:99b5ccf27215 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 133:99b5ccf27215 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 133:99b5ccf27215 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 133:99b5ccf27215 34 ; POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 35 ; ---------------------------------------------------------------------------*/
<> 133:99b5ccf27215 36
<> 133:99b5ccf27215 37 #ifdef __cplusplus
<> 133:99b5ccf27215 38 extern "C" {
<> 133:99b5ccf27215 39 #endif
<> 133:99b5ccf27215 40
<> 133:99b5ccf27215 41 #ifndef _MMU_FUNC_H
<> 133:99b5ccf27215 42 #define _MMU_FUNC_H
<> 133:99b5ccf27215 43
<> 133:99b5ccf27215 44 #define SECTION_DESCRIPTOR (0x2)
<> 133:99b5ccf27215 45 #define SECTION_MASK (0xFFFFFFFC)
<> 133:99b5ccf27215 46
<> 133:99b5ccf27215 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
<> 133:99b5ccf27215 48 #define SECTION_B_SHIFT (2)
<> 133:99b5ccf27215 49 #define SECTION_C_SHIFT (3)
<> 133:99b5ccf27215 50 #define SECTION_TEX0_SHIFT (12)
<> 133:99b5ccf27215 51 #define SECTION_TEX1_SHIFT (13)
<> 133:99b5ccf27215 52 #define SECTION_TEX2_SHIFT (14)
<> 133:99b5ccf27215 53
<> 133:99b5ccf27215 54 #define SECTION_XN_MASK (0xFFFFFFEF)
<> 133:99b5ccf27215 55 #define SECTION_XN_SHIFT (4)
<> 133:99b5ccf27215 56
<> 133:99b5ccf27215 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
<> 133:99b5ccf27215 58 #define SECTION_DOMAIN_SHIFT (5)
<> 133:99b5ccf27215 59
<> 133:99b5ccf27215 60 #define SECTION_P_MASK (0xFFFFFDFF)
<> 133:99b5ccf27215 61 #define SECTION_P_SHIFT (9)
<> 133:99b5ccf27215 62
<> 133:99b5ccf27215 63 #define SECTION_AP_MASK (0xFFFF73FF)
<> 133:99b5ccf27215 64 #define SECTION_AP_SHIFT (10)
<> 133:99b5ccf27215 65 #define SECTION_AP2_SHIFT (15)
<> 133:99b5ccf27215 66
<> 133:99b5ccf27215 67 #define SECTION_S_MASK (0xFFFEFFFF)
<> 133:99b5ccf27215 68 #define SECTION_S_SHIFT (16)
<> 133:99b5ccf27215 69
<> 133:99b5ccf27215 70 #define SECTION_NG_MASK (0xFFFDFFFF)
<> 133:99b5ccf27215 71 #define SECTION_NG_SHIFT (17)
<> 133:99b5ccf27215 72
<> 133:99b5ccf27215 73 #define SECTION_NS_MASK (0xFFF7FFFF)
<> 133:99b5ccf27215 74 #define SECTION_NS_SHIFT (19)
<> 133:99b5ccf27215 75
<> 133:99b5ccf27215 76
<> 133:99b5ccf27215 77 #define PAGE_L1_DESCRIPTOR (0x1)
<> 133:99b5ccf27215 78 #define PAGE_L1_MASK (0xFFFFFFFC)
<> 133:99b5ccf27215 79
<> 133:99b5ccf27215 80 #define PAGE_L2_4K_DESC (0x2)
<> 133:99b5ccf27215 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
<> 133:99b5ccf27215 82
<> 133:99b5ccf27215 83 #define PAGE_L2_64K_DESC (0x1)
<> 133:99b5ccf27215 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
<> 133:99b5ccf27215 85
<> 133:99b5ccf27215 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
<> 133:99b5ccf27215 87 #define PAGE_4K_B_SHIFT (2)
<> 133:99b5ccf27215 88 #define PAGE_4K_C_SHIFT (3)
<> 133:99b5ccf27215 89 #define PAGE_4K_TEX0_SHIFT (6)
<> 133:99b5ccf27215 90 #define PAGE_4K_TEX1_SHIFT (7)
<> 133:99b5ccf27215 91 #define PAGE_4K_TEX2_SHIFT (8)
<> 133:99b5ccf27215 92
<> 133:99b5ccf27215 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
<> 133:99b5ccf27215 94 #define PAGE_64K_B_SHIFT (2)
<> 133:99b5ccf27215 95 #define PAGE_64K_C_SHIFT (3)
<> 133:99b5ccf27215 96 #define PAGE_64K_TEX0_SHIFT (12)
<> 133:99b5ccf27215 97 #define PAGE_64K_TEX1_SHIFT (13)
<> 133:99b5ccf27215 98 #define PAGE_64K_TEX2_SHIFT (14)
<> 133:99b5ccf27215 99
<> 133:99b5ccf27215 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
<> 133:99b5ccf27215 101 #define PAGE_B_SHIFT (2)
<> 133:99b5ccf27215 102 #define PAGE_C_SHIFT (3)
<> 133:99b5ccf27215 103 #define PAGE_TEX_SHIFT (12)
<> 133:99b5ccf27215 104
<> 133:99b5ccf27215 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
<> 133:99b5ccf27215 106 #define PAGE_XN_4K_SHIFT (0)
<> 133:99b5ccf27215 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
<> 133:99b5ccf27215 108 #define PAGE_XN_64K_SHIFT (15)
<> 133:99b5ccf27215 109
<> 133:99b5ccf27215 110
<> 133:99b5ccf27215 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
<> 133:99b5ccf27215 112 #define PAGE_DOMAIN_SHIFT (5)
<> 133:99b5ccf27215 113
<> 133:99b5ccf27215 114 #define PAGE_P_MASK (0xFFFFFDFF)
<> 133:99b5ccf27215 115 #define PAGE_P_SHIFT (9)
<> 133:99b5ccf27215 116
<> 133:99b5ccf27215 117 #define PAGE_AP_MASK (0xFFFFFDCF)
<> 133:99b5ccf27215 118 #define PAGE_AP_SHIFT (4)
<> 133:99b5ccf27215 119 #define PAGE_AP2_SHIFT (9)
<> 133:99b5ccf27215 120
<> 133:99b5ccf27215 121 #define PAGE_S_MASK (0xFFFFFBFF)
<> 133:99b5ccf27215 122 #define PAGE_S_SHIFT (10)
<> 133:99b5ccf27215 123
<> 133:99b5ccf27215 124 #define PAGE_NG_MASK (0xFFFFF7FF)
<> 133:99b5ccf27215 125 #define PAGE_NG_SHIFT (11)
<> 133:99b5ccf27215 126
<> 133:99b5ccf27215 127 #define PAGE_NS_MASK (0xFFFFFFF7)
<> 133:99b5ccf27215 128 #define PAGE_NS_SHIFT (3)
<> 133:99b5ccf27215 129
<> 133:99b5ccf27215 130 #define OFFSET_1M (0x00100000)
<> 133:99b5ccf27215 131 #define OFFSET_64K (0x00010000)
<> 133:99b5ccf27215 132 #define OFFSET_4K (0x00001000)
<> 133:99b5ccf27215 133
<> 133:99b5ccf27215 134 #define DESCRIPTOR_FAULT (0x00000000)
<> 133:99b5ccf27215 135
<> 133:99b5ccf27215 136 /* ########################### MMU Function Access ########################### */
<> 133:99b5ccf27215 137 /** \ingroup MMU_FunctionInterface
<> 133:99b5ccf27215 138 \defgroup MMU_Functions MMU Functions Interface
<> 133:99b5ccf27215 139 @{
<> 133:99b5ccf27215 140 */
<> 133:99b5ccf27215 141
<> 133:99b5ccf27215 142 /* Attributes enumerations */
<> 133:99b5ccf27215 143
<> 133:99b5ccf27215 144 /* Region size attributes */
<> 133:99b5ccf27215 145 typedef enum
<> 133:99b5ccf27215 146 {
<> 133:99b5ccf27215 147 SECTION,
<> 133:99b5ccf27215 148 PAGE_4k,
<> 133:99b5ccf27215 149 PAGE_64k,
<> 133:99b5ccf27215 150 } mmu_region_size_Type;
<> 133:99b5ccf27215 151
<> 133:99b5ccf27215 152 /* Region type attributes */
<> 133:99b5ccf27215 153 typedef enum
<> 133:99b5ccf27215 154 {
<> 133:99b5ccf27215 155 NORMAL,
<> 133:99b5ccf27215 156 DEVICE,
<> 133:99b5ccf27215 157 SHARED_DEVICE,
<> 133:99b5ccf27215 158 NON_SHARED_DEVICE,
<> 133:99b5ccf27215 159 STRONGLY_ORDERED
<> 133:99b5ccf27215 160 } mmu_memory_Type;
<> 133:99b5ccf27215 161
<> 133:99b5ccf27215 162 /* Region cacheability attributes */
<> 133:99b5ccf27215 163 typedef enum
<> 133:99b5ccf27215 164 {
<> 133:99b5ccf27215 165 NON_CACHEABLE,
<> 133:99b5ccf27215 166 WB_WA,
<> 133:99b5ccf27215 167 WT,
<> 133:99b5ccf27215 168 WB_NO_WA,
<> 133:99b5ccf27215 169 } mmu_cacheability_Type;
<> 133:99b5ccf27215 170
<> 133:99b5ccf27215 171 /* Region parity check attributes */
<> 133:99b5ccf27215 172 typedef enum
<> 133:99b5ccf27215 173 {
<> 133:99b5ccf27215 174 ECC_DISABLED,
<> 133:99b5ccf27215 175 ECC_ENABLED,
<> 133:99b5ccf27215 176 } mmu_ecc_check_Type;
<> 133:99b5ccf27215 177
<> 133:99b5ccf27215 178 /* Region execution attributes */
<> 133:99b5ccf27215 179 typedef enum
<> 133:99b5ccf27215 180 {
<> 133:99b5ccf27215 181 EXECUTE,
<> 133:99b5ccf27215 182 NON_EXECUTE,
<> 133:99b5ccf27215 183 } mmu_execute_Type;
<> 133:99b5ccf27215 184
<> 133:99b5ccf27215 185 /* Region global attributes */
<> 133:99b5ccf27215 186 typedef enum
<> 133:99b5ccf27215 187 {
<> 133:99b5ccf27215 188 GLOBAL,
<> 133:99b5ccf27215 189 NON_GLOBAL,
<> 133:99b5ccf27215 190 } mmu_global_Type;
<> 133:99b5ccf27215 191
<> 133:99b5ccf27215 192 /* Region shareability attributes */
<> 133:99b5ccf27215 193 typedef enum
<> 133:99b5ccf27215 194 {
<> 133:99b5ccf27215 195 NON_SHARED,
<> 133:99b5ccf27215 196 SHARED,
<> 133:99b5ccf27215 197 } mmu_shared_Type;
<> 133:99b5ccf27215 198
<> 133:99b5ccf27215 199 /* Region security attributes */
<> 133:99b5ccf27215 200 typedef enum
<> 133:99b5ccf27215 201 {
<> 133:99b5ccf27215 202 SECURE,
<> 133:99b5ccf27215 203 NON_SECURE,
<> 133:99b5ccf27215 204 } mmu_secure_Type;
<> 133:99b5ccf27215 205
<> 133:99b5ccf27215 206 /* Region access attributes */
<> 133:99b5ccf27215 207 typedef enum
<> 133:99b5ccf27215 208 {
<> 133:99b5ccf27215 209 NO_ACCESS,
<> 133:99b5ccf27215 210 RW,
<> 133:99b5ccf27215 211 READ,
<> 133:99b5ccf27215 212 } mmu_access_Type;
<> 133:99b5ccf27215 213
<> 133:99b5ccf27215 214 /* Memory Region definition */
<> 133:99b5ccf27215 215 typedef struct RegionStruct {
<> 133:99b5ccf27215 216 mmu_region_size_Type rg_t;
<> 133:99b5ccf27215 217 mmu_memory_Type mem_t;
<> 133:99b5ccf27215 218 uint8_t domain;
<> 133:99b5ccf27215 219 mmu_cacheability_Type inner_norm_t;
<> 133:99b5ccf27215 220 mmu_cacheability_Type outer_norm_t;
<> 133:99b5ccf27215 221 mmu_ecc_check_Type e_t;
<> 133:99b5ccf27215 222 mmu_execute_Type xn_t;
<> 133:99b5ccf27215 223 mmu_global_Type g_t;
<> 133:99b5ccf27215 224 mmu_secure_Type sec_t;
<> 133:99b5ccf27215 225 mmu_access_Type priv_t;
<> 133:99b5ccf27215 226 mmu_access_Type user_t;
<> 133:99b5ccf27215 227 mmu_shared_Type sh_t;
<> 133:99b5ccf27215 228
<> 133:99b5ccf27215 229 } mmu_region_attributes_Type;
<> 133:99b5ccf27215 230
<> 133:99b5ccf27215 231 /** \brief Set section execution-never attribute
<> 133:99b5ccf27215 232
<> 133:99b5ccf27215 233 The function sets section execution-never attribute
<> 133:99b5ccf27215 234
<> 133:99b5ccf27215 235 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
<> 133:99b5ccf27215 237
<> 133:99b5ccf27215 238 \return 0
<> 133:99b5ccf27215 239 */
<> 133:99b5ccf27215 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
<> 133:99b5ccf27215 241 {
<> 133:99b5ccf27215 242 *descriptor_l1 &= SECTION_XN_MASK;
<> 133:99b5ccf27215 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
<> 133:99b5ccf27215 244 return 0;
<> 133:99b5ccf27215 245 }
<> 133:99b5ccf27215 246
<> 133:99b5ccf27215 247 /** \brief Set section domain
<> 133:99b5ccf27215 248
<> 133:99b5ccf27215 249 The function sets section domain
<> 133:99b5ccf27215 250
<> 133:99b5ccf27215 251 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 252 \param [in] domain Section domain
<> 133:99b5ccf27215 253
<> 133:99b5ccf27215 254 \return 0
<> 133:99b5ccf27215 255 */
<> 133:99b5ccf27215 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
<> 133:99b5ccf27215 257 {
<> 133:99b5ccf27215 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
<> 133:99b5ccf27215 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
<> 133:99b5ccf27215 260 return 0;
<> 133:99b5ccf27215 261 }
<> 133:99b5ccf27215 262
<> 133:99b5ccf27215 263 /** \brief Set section parity check
<> 133:99b5ccf27215 264
<> 133:99b5ccf27215 265 The function sets section parity check
<> 133:99b5ccf27215 266
<> 133:99b5ccf27215 267 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 133:99b5ccf27215 269
<> 133:99b5ccf27215 270 \return 0
<> 133:99b5ccf27215 271 */
<> 133:99b5ccf27215 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 133:99b5ccf27215 273 {
<> 133:99b5ccf27215 274 *descriptor_l1 &= SECTION_P_MASK;
<> 133:99b5ccf27215 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 133:99b5ccf27215 276 return 0;
<> 133:99b5ccf27215 277 }
<> 133:99b5ccf27215 278
<> 133:99b5ccf27215 279 /** \brief Set section access privileges
<> 133:99b5ccf27215 280
<> 133:99b5ccf27215 281 The function sets section access privileges
<> 133:99b5ccf27215 282
<> 133:99b5ccf27215 283 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 133:99b5ccf27215 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 133:99b5ccf27215 286 \param [in] afe Access flag enable
<> 133:99b5ccf27215 287
<> 133:99b5ccf27215 288 \return 0
<> 133:99b5ccf27215 289 */
<> 133:99b5ccf27215 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 133:99b5ccf27215 291 {
<> 133:99b5ccf27215 292 uint32_t ap = 0;
<> 133:99b5ccf27215 293
<> 133:99b5ccf27215 294 if (afe == 0) { //full access
<> 133:99b5ccf27215 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 133:99b5ccf27215 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 133:99b5ccf27215 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 133:99b5ccf27215 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 133:99b5ccf27215 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 133:99b5ccf27215 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 133:99b5ccf27215 301 }
<> 133:99b5ccf27215 302
<> 133:99b5ccf27215 303 else { //Simplified access
<> 133:99b5ccf27215 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 133:99b5ccf27215 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 133:99b5ccf27215 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 133:99b5ccf27215 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 133:99b5ccf27215 308 }
<> 133:99b5ccf27215 309
<> 133:99b5ccf27215 310 *descriptor_l1 &= SECTION_AP_MASK;
<> 133:99b5ccf27215 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
<> 133:99b5ccf27215 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
<> 133:99b5ccf27215 313
<> 133:99b5ccf27215 314 return 0;
<> 133:99b5ccf27215 315 }
<> 133:99b5ccf27215 316
<> 133:99b5ccf27215 317 /** \brief Set section shareability
<> 133:99b5ccf27215 318
<> 133:99b5ccf27215 319 The function sets section shareability
<> 133:99b5ccf27215 320
<> 133:99b5ccf27215 321 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
<> 133:99b5ccf27215 323
<> 133:99b5ccf27215 324 \return 0
<> 133:99b5ccf27215 325 */
<> 133:99b5ccf27215 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
<> 133:99b5ccf27215 327 {
<> 133:99b5ccf27215 328 *descriptor_l1 &= SECTION_S_MASK;
<> 133:99b5ccf27215 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
<> 133:99b5ccf27215 330 return 0;
<> 133:99b5ccf27215 331 }
<> 133:99b5ccf27215 332
<> 133:99b5ccf27215 333 /** \brief Set section Global attribute
<> 133:99b5ccf27215 334
<> 133:99b5ccf27215 335 The function sets section Global attribute
<> 133:99b5ccf27215 336
<> 133:99b5ccf27215 337 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
<> 133:99b5ccf27215 339
<> 133:99b5ccf27215 340 \return 0
<> 133:99b5ccf27215 341 */
<> 133:99b5ccf27215 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
<> 133:99b5ccf27215 343 {
<> 133:99b5ccf27215 344 *descriptor_l1 &= SECTION_NG_MASK;
<> 133:99b5ccf27215 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
<> 133:99b5ccf27215 346 return 0;
<> 133:99b5ccf27215 347 }
<> 133:99b5ccf27215 348
<> 133:99b5ccf27215 349 /** \brief Set section Security attribute
<> 133:99b5ccf27215 350
<> 133:99b5ccf27215 351 The function sets section Global attribute
<> 133:99b5ccf27215 352
<> 133:99b5ccf27215 353 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
<> 133:99b5ccf27215 355
<> 133:99b5ccf27215 356 \return 0
<> 133:99b5ccf27215 357 */
<> 133:99b5ccf27215 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 133:99b5ccf27215 359 {
<> 133:99b5ccf27215 360 *descriptor_l1 &= SECTION_NS_MASK;
<> 133:99b5ccf27215 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
<> 133:99b5ccf27215 362 return 0;
<> 133:99b5ccf27215 363 }
<> 133:99b5ccf27215 364
<> 133:99b5ccf27215 365 /* Page 4k or 64k */
<> 133:99b5ccf27215 366 /** \brief Set 4k/64k page execution-never attribute
<> 133:99b5ccf27215 367
<> 133:99b5ccf27215 368 The function sets 4k/64k page execution-never attribute
<> 133:99b5ccf27215 369
<> 133:99b5ccf27215 370 \param [out] descriptor_l2 L2 descriptor.
<> 133:99b5ccf27215 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
<> 133:99b5ccf27215 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
<> 133:99b5ccf27215 373
<> 133:99b5ccf27215 374 \return 0
<> 133:99b5ccf27215 375 */
<> 133:99b5ccf27215 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
<> 133:99b5ccf27215 377 {
<> 133:99b5ccf27215 378 if (page == PAGE_4k)
<> 133:99b5ccf27215 379 {
<> 133:99b5ccf27215 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
<> 133:99b5ccf27215 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
<> 133:99b5ccf27215 382 }
<> 133:99b5ccf27215 383 else
<> 133:99b5ccf27215 384 {
<> 133:99b5ccf27215 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
<> 133:99b5ccf27215 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
<> 133:99b5ccf27215 387 }
<> 133:99b5ccf27215 388 return 0;
<> 133:99b5ccf27215 389 }
<> 133:99b5ccf27215 390
<> 133:99b5ccf27215 391 /** \brief Set 4k/64k page domain
<> 133:99b5ccf27215 392
<> 133:99b5ccf27215 393 The function sets 4k/64k page domain
<> 133:99b5ccf27215 394
<> 133:99b5ccf27215 395 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 396 \param [in] domain Page domain
<> 133:99b5ccf27215 397
<> 133:99b5ccf27215 398 \return 0
<> 133:99b5ccf27215 399 */
<> 133:99b5ccf27215 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
<> 133:99b5ccf27215 401 {
<> 133:99b5ccf27215 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
<> 133:99b5ccf27215 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
<> 133:99b5ccf27215 404 return 0;
<> 133:99b5ccf27215 405 }
<> 133:99b5ccf27215 406
<> 133:99b5ccf27215 407 /** \brief Set 4k/64k page parity check
<> 133:99b5ccf27215 408
<> 133:99b5ccf27215 409 The function sets 4k/64k page parity check
<> 133:99b5ccf27215 410
<> 133:99b5ccf27215 411 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 133:99b5ccf27215 413
<> 133:99b5ccf27215 414 \return 0
<> 133:99b5ccf27215 415 */
<> 133:99b5ccf27215 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 133:99b5ccf27215 417 {
<> 133:99b5ccf27215 418 *descriptor_l1 &= SECTION_P_MASK;
<> 133:99b5ccf27215 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 133:99b5ccf27215 420 return 0;
<> 133:99b5ccf27215 421 }
<> 133:99b5ccf27215 422
<> 133:99b5ccf27215 423 /** \brief Set 4k/64k page access privileges
<> 133:99b5ccf27215 424
<> 133:99b5ccf27215 425 The function sets 4k/64k page access privileges
<> 133:99b5ccf27215 426
<> 133:99b5ccf27215 427 \param [out] descriptor_l2 L2 descriptor.
<> 133:99b5ccf27215 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 133:99b5ccf27215 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 133:99b5ccf27215 430 \param [in] afe Access flag enable
<> 133:99b5ccf27215 431
<> 133:99b5ccf27215 432 \return 0
<> 133:99b5ccf27215 433 */
<> 133:99b5ccf27215 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 133:99b5ccf27215 435 {
<> 133:99b5ccf27215 436 uint32_t ap = 0;
<> 133:99b5ccf27215 437
<> 133:99b5ccf27215 438 if (afe == 0) { //full access
<> 133:99b5ccf27215 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 133:99b5ccf27215 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 133:99b5ccf27215 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 133:99b5ccf27215 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 133:99b5ccf27215 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 133:99b5ccf27215 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
<> 133:99b5ccf27215 445 }
<> 133:99b5ccf27215 446
<> 133:99b5ccf27215 447 else { //Simplified access
<> 133:99b5ccf27215 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 133:99b5ccf27215 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 133:99b5ccf27215 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 133:99b5ccf27215 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 133:99b5ccf27215 452 }
<> 133:99b5ccf27215 453
<> 133:99b5ccf27215 454 *descriptor_l2 &= PAGE_AP_MASK;
<> 133:99b5ccf27215 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
<> 133:99b5ccf27215 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
<> 133:99b5ccf27215 457
<> 133:99b5ccf27215 458 return 0;
<> 133:99b5ccf27215 459 }
<> 133:99b5ccf27215 460
<> 133:99b5ccf27215 461 /** \brief Set 4k/64k page shareability
<> 133:99b5ccf27215 462
<> 133:99b5ccf27215 463 The function sets 4k/64k page shareability
<> 133:99b5ccf27215 464
<> 133:99b5ccf27215 465 \param [out] descriptor_l2 L2 descriptor.
<> 133:99b5ccf27215 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
<> 133:99b5ccf27215 467
<> 133:99b5ccf27215 468 \return 0
<> 133:99b5ccf27215 469 */
<> 133:99b5ccf27215 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
<> 133:99b5ccf27215 471 {
<> 133:99b5ccf27215 472 *descriptor_l2 &= PAGE_S_MASK;
<> 133:99b5ccf27215 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
<> 133:99b5ccf27215 474 return 0;
<> 133:99b5ccf27215 475 }
<> 133:99b5ccf27215 476
<> 133:99b5ccf27215 477 /** \brief Set 4k/64k page Global attribute
<> 133:99b5ccf27215 478
<> 133:99b5ccf27215 479 The function sets 4k/64k page Global attribute
<> 133:99b5ccf27215 480
<> 133:99b5ccf27215 481 \param [out] descriptor_l2 L2 descriptor.
<> 133:99b5ccf27215 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
<> 133:99b5ccf27215 483
<> 133:99b5ccf27215 484 \return 0
<> 133:99b5ccf27215 485 */
<> 133:99b5ccf27215 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
<> 133:99b5ccf27215 487 {
<> 133:99b5ccf27215 488 *descriptor_l2 &= PAGE_NG_MASK;
<> 133:99b5ccf27215 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
<> 133:99b5ccf27215 490 return 0;
<> 133:99b5ccf27215 491 }
<> 133:99b5ccf27215 492
<> 133:99b5ccf27215 493 /** \brief Set 4k/64k page Security attribute
<> 133:99b5ccf27215 494
<> 133:99b5ccf27215 495 The function sets 4k/64k page Global attribute
<> 133:99b5ccf27215 496
<> 133:99b5ccf27215 497 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
<> 133:99b5ccf27215 499
<> 133:99b5ccf27215 500 \return 0
<> 133:99b5ccf27215 501 */
<> 133:99b5ccf27215 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 133:99b5ccf27215 503 {
<> 133:99b5ccf27215 504 *descriptor_l1 &= PAGE_NS_MASK;
<> 133:99b5ccf27215 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
<> 133:99b5ccf27215 506 return 0;
<> 133:99b5ccf27215 507 }
<> 133:99b5ccf27215 508
<> 133:99b5ccf27215 509
<> 133:99b5ccf27215 510 /** \brief Set Section memory attributes
<> 133:99b5ccf27215 511
<> 133:99b5ccf27215 512 The function sets section memory attributes
<> 133:99b5ccf27215 513
<> 133:99b5ccf27215 514 \param [out] descriptor_l1 L1 descriptor.
<> 133:99b5ccf27215 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 133:99b5ccf27215 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 133:99b5ccf27215 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 133:99b5ccf27215 518
<> 133:99b5ccf27215 519 \return 0
<> 133:99b5ccf27215 520 */
<> 133:99b5ccf27215 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
<> 133:99b5ccf27215 522 {
<> 133:99b5ccf27215 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
<> 133:99b5ccf27215 524
<> 133:99b5ccf27215 525 if (STRONGLY_ORDERED == mem)
<> 133:99b5ccf27215 526 {
<> 133:99b5ccf27215 527 return 0;
<> 133:99b5ccf27215 528 }
<> 133:99b5ccf27215 529 else if (SHARED_DEVICE == mem)
<> 133:99b5ccf27215 530 {
<> 133:99b5ccf27215 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 133:99b5ccf27215 532 }
<> 133:99b5ccf27215 533 else if (NON_SHARED_DEVICE == mem)
<> 133:99b5ccf27215 534 {
<> 133:99b5ccf27215 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
<> 133:99b5ccf27215 536 }
<> 133:99b5ccf27215 537 else if (NORMAL == mem)
<> 133:99b5ccf27215 538 {
<> 133:99b5ccf27215 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
<> 133:99b5ccf27215 540 switch(inner)
<> 133:99b5ccf27215 541 {
<> 133:99b5ccf27215 542 case NON_CACHEABLE:
<> 133:99b5ccf27215 543 break;
<> 133:99b5ccf27215 544 case WB_WA:
<> 133:99b5ccf27215 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 133:99b5ccf27215 546 break;
<> 133:99b5ccf27215 547 case WT:
<> 133:99b5ccf27215 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
<> 133:99b5ccf27215 549 break;
<> 133:99b5ccf27215 550 case WB_NO_WA:
<> 133:99b5ccf27215 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
<> 133:99b5ccf27215 552 break;
<> 133:99b5ccf27215 553 }
<> 133:99b5ccf27215 554 switch(outer)
<> 133:99b5ccf27215 555 {
<> 133:99b5ccf27215 556 case NON_CACHEABLE:
<> 133:99b5ccf27215 557 break;
<> 133:99b5ccf27215 558 case WB_WA:
<> 133:99b5ccf27215 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
<> 133:99b5ccf27215 560 break;
<> 133:99b5ccf27215 561 case WT:
<> 133:99b5ccf27215 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
<> 133:99b5ccf27215 563 break;
<> 133:99b5ccf27215 564 case WB_NO_WA:
<> 133:99b5ccf27215 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
<> 133:99b5ccf27215 566 break;
<> 133:99b5ccf27215 567 }
<> 133:99b5ccf27215 568 }
<> 133:99b5ccf27215 569
<> 133:99b5ccf27215 570 return 0;
<> 133:99b5ccf27215 571 }
<> 133:99b5ccf27215 572
<> 133:99b5ccf27215 573 /** \brief Set 4k/64k page memory attributes
<> 133:99b5ccf27215 574
<> 133:99b5ccf27215 575 The function sets 4k/64k page memory attributes
<> 133:99b5ccf27215 576
<> 133:99b5ccf27215 577 \param [out] descriptor_l2 L2 descriptor.
<> 133:99b5ccf27215 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 133:99b5ccf27215 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 133:99b5ccf27215 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 133:99b5ccf27215 581
<> 133:99b5ccf27215 582 \return 0
<> 133:99b5ccf27215 583 */
<> 133:99b5ccf27215 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
<> 133:99b5ccf27215 585 {
<> 133:99b5ccf27215 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
<> 133:99b5ccf27215 587
<> 133:99b5ccf27215 588 if (page == PAGE_64k)
<> 133:99b5ccf27215 589 {
<> 133:99b5ccf27215 590 //same as section
<> 133:99b5ccf27215 591 __memory_section(descriptor_l2, mem, outer, inner);
<> 133:99b5ccf27215 592 }
<> 133:99b5ccf27215 593 else
<> 133:99b5ccf27215 594 {
<> 133:99b5ccf27215 595 if (STRONGLY_ORDERED == mem)
<> 133:99b5ccf27215 596 {
<> 133:99b5ccf27215 597 return 0;
<> 133:99b5ccf27215 598 }
<> 133:99b5ccf27215 599 else if (SHARED_DEVICE == mem)
<> 133:99b5ccf27215 600 {
<> 133:99b5ccf27215 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 133:99b5ccf27215 602 }
<> 133:99b5ccf27215 603 else if (NON_SHARED_DEVICE == mem)
<> 133:99b5ccf27215 604 {
<> 133:99b5ccf27215 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
<> 133:99b5ccf27215 606 }
<> 133:99b5ccf27215 607 else if (NORMAL == mem)
<> 133:99b5ccf27215 608 {
<> 133:99b5ccf27215 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
<> 133:99b5ccf27215 610 switch(inner)
<> 133:99b5ccf27215 611 {
<> 133:99b5ccf27215 612 case NON_CACHEABLE:
<> 133:99b5ccf27215 613 break;
<> 133:99b5ccf27215 614 case WB_WA:
<> 133:99b5ccf27215 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 133:99b5ccf27215 616 break;
<> 133:99b5ccf27215 617 case WT:
<> 133:99b5ccf27215 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
<> 133:99b5ccf27215 619 break;
<> 133:99b5ccf27215 620 case WB_NO_WA:
<> 133:99b5ccf27215 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
<> 133:99b5ccf27215 622 break;
<> 133:99b5ccf27215 623 }
<> 133:99b5ccf27215 624 switch(outer)
<> 133:99b5ccf27215 625 {
<> 133:99b5ccf27215 626 case NON_CACHEABLE:
<> 133:99b5ccf27215 627 break;
<> 133:99b5ccf27215 628 case WB_WA:
<> 133:99b5ccf27215 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
<> 133:99b5ccf27215 630 break;
<> 133:99b5ccf27215 631 case WT:
<> 133:99b5ccf27215 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
<> 133:99b5ccf27215 633 break;
<> 133:99b5ccf27215 634 case WB_NO_WA:
<> 133:99b5ccf27215 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
<> 133:99b5ccf27215 636 break;
<> 133:99b5ccf27215 637 }
<> 133:99b5ccf27215 638 }
<> 133:99b5ccf27215 639 }
<> 133:99b5ccf27215 640
<> 133:99b5ccf27215 641 return 0;
<> 133:99b5ccf27215 642 }
<> 133:99b5ccf27215 643
<> 133:99b5ccf27215 644 /** \brief Create a L1 section descriptor
<> 133:99b5ccf27215 645
<> 133:99b5ccf27215 646 The function creates a section descriptor.
<> 133:99b5ccf27215 647
<> 133:99b5ccf27215 648 Assumptions:
<> 133:99b5ccf27215 649 - 16MB super sections not supported
<> 133:99b5ccf27215 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 133:99b5ccf27215 651 - Functions always return 0
<> 133:99b5ccf27215 652
<> 133:99b5ccf27215 653 \param [out] descriptor L1 descriptor
<> 133:99b5ccf27215 654 \param [out] descriptor2 L2 descriptor
<> 133:99b5ccf27215 655 \param [in] reg Section attributes
<> 133:99b5ccf27215 656
<> 133:99b5ccf27215 657 \return 0
<> 133:99b5ccf27215 658 */
<> 133:99b5ccf27215 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
<> 133:99b5ccf27215 660 {
<> 133:99b5ccf27215 661 *descriptor = 0;
<> 133:99b5ccf27215 662
<> 133:99b5ccf27215 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
<> 133:99b5ccf27215 664 __xn_section(descriptor,reg.xn_t);
<> 133:99b5ccf27215 665 __domain_section(descriptor, reg.domain);
<> 133:99b5ccf27215 666 __p_section(descriptor, reg.e_t);
<> 133:99b5ccf27215 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
<> 133:99b5ccf27215 668 __shared_section(descriptor,reg.sh_t);
<> 133:99b5ccf27215 669 __global_section(descriptor,reg.g_t);
<> 133:99b5ccf27215 670 __secure_section(descriptor,reg.sec_t);
<> 133:99b5ccf27215 671 *descriptor &= SECTION_MASK;
<> 133:99b5ccf27215 672 *descriptor |= SECTION_DESCRIPTOR;
<> 133:99b5ccf27215 673
<> 133:99b5ccf27215 674 return 0;
<> 133:99b5ccf27215 675
<> 133:99b5ccf27215 676 }
<> 133:99b5ccf27215 677
<> 133:99b5ccf27215 678
<> 133:99b5ccf27215 679 /** \brief Create a L1 and L2 4k/64k page descriptor
<> 133:99b5ccf27215 680
<> 133:99b5ccf27215 681 The function creates a 4k/64k page descriptor.
<> 133:99b5ccf27215 682 Assumptions:
<> 133:99b5ccf27215 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 133:99b5ccf27215 684 - Functions always return 0
<> 133:99b5ccf27215 685
<> 133:99b5ccf27215 686 \param [out] descriptor L1 descriptor
<> 133:99b5ccf27215 687 \param [out] descriptor2 L2 descriptor
<> 133:99b5ccf27215 688 \param [in] reg 4k/64k page attributes
<> 133:99b5ccf27215 689
<> 133:99b5ccf27215 690 \return 0
<> 133:99b5ccf27215 691 */
<> 133:99b5ccf27215 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
<> 133:99b5ccf27215 693 {
<> 133:99b5ccf27215 694 *descriptor = 0;
<> 133:99b5ccf27215 695 *descriptor2 = 0;
<> 133:99b5ccf27215 696
<> 133:99b5ccf27215 697 switch (reg.rg_t)
<> 133:99b5ccf27215 698 {
<> 133:99b5ccf27215 699 case PAGE_4k:
<> 133:99b5ccf27215 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
<> 133:99b5ccf27215 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
<> 133:99b5ccf27215 702 __domain_page(descriptor, reg.domain);
<> 133:99b5ccf27215 703 __p_page(descriptor, reg.e_t);
<> 133:99b5ccf27215 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 133:99b5ccf27215 705 __shared_page(descriptor2,reg.sh_t);
<> 133:99b5ccf27215 706 __global_page(descriptor2,reg.g_t);
<> 133:99b5ccf27215 707 __secure_page(descriptor,reg.sec_t);
<> 133:99b5ccf27215 708 *descriptor &= PAGE_L1_MASK;
<> 133:99b5ccf27215 709 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 133:99b5ccf27215 710 *descriptor2 &= PAGE_L2_4K_MASK;
<> 133:99b5ccf27215 711 *descriptor2 |= PAGE_L2_4K_DESC;
<> 133:99b5ccf27215 712 break;
<> 133:99b5ccf27215 713
<> 133:99b5ccf27215 714 case PAGE_64k:
<> 133:99b5ccf27215 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
<> 133:99b5ccf27215 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
<> 133:99b5ccf27215 717 __domain_page(descriptor, reg.domain);
<> 133:99b5ccf27215 718 __p_page(descriptor, reg.e_t);
<> 133:99b5ccf27215 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 133:99b5ccf27215 720 __shared_page(descriptor2,reg.sh_t);
<> 133:99b5ccf27215 721 __global_page(descriptor2,reg.g_t);
<> 133:99b5ccf27215 722 __secure_page(descriptor,reg.sec_t);
<> 133:99b5ccf27215 723 *descriptor &= PAGE_L1_MASK;
<> 133:99b5ccf27215 724 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 133:99b5ccf27215 725 *descriptor2 &= PAGE_L2_64K_MASK;
<> 133:99b5ccf27215 726 *descriptor2 |= PAGE_L2_64K_DESC;
<> 133:99b5ccf27215 727 break;
<> 133:99b5ccf27215 728
<> 133:99b5ccf27215 729 case SECTION:
<> 133:99b5ccf27215 730 //error
<> 133:99b5ccf27215 731 break;
<> 133:99b5ccf27215 732
<> 133:99b5ccf27215 733 }
<> 133:99b5ccf27215 734
<> 133:99b5ccf27215 735 return 0;
<> 133:99b5ccf27215 736
<> 133:99b5ccf27215 737 }
<> 133:99b5ccf27215 738
<> 133:99b5ccf27215 739 /** \brief Create a 1MB Section
<> 133:99b5ccf27215 740
<> 133:99b5ccf27215 741 \param [in] ttb Translation table base address
<> 133:99b5ccf27215 742 \param [in] base_address Section base address
<> 133:99b5ccf27215 743 \param [in] count Number of sections to create
<> 133:99b5ccf27215 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 133:99b5ccf27215 745
<> 133:99b5ccf27215 746 */
<> 133:99b5ccf27215 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
<> 133:99b5ccf27215 748 {
<> 133:99b5ccf27215 749 uint32_t offset;
<> 133:99b5ccf27215 750 uint32_t entry;
<> 133:99b5ccf27215 751 uint32_t i;
<> 133:99b5ccf27215 752
<> 133:99b5ccf27215 753 offset = base_address >> 20;
<> 133:99b5ccf27215 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
<> 133:99b5ccf27215 755
<> 133:99b5ccf27215 756 //4 bytes aligned
<> 133:99b5ccf27215 757 ttb = ttb + offset;
<> 133:99b5ccf27215 758
<> 133:99b5ccf27215 759 for (i = 0; i < count; i++ )
<> 133:99b5ccf27215 760 {
<> 133:99b5ccf27215 761 //4 bytes aligned
<> 133:99b5ccf27215 762 *ttb++ = entry;
<> 133:99b5ccf27215 763 entry += OFFSET_1M;
<> 133:99b5ccf27215 764 }
<> 133:99b5ccf27215 765 }
<> 133:99b5ccf27215 766
<> 133:99b5ccf27215 767 /** \brief Create a 4k page entry
<> 133:99b5ccf27215 768
<> 133:99b5ccf27215 769 \param [in] ttb L1 table base address
<> 133:99b5ccf27215 770 \param [in] base_address 4k base address
<> 133:99b5ccf27215 771 \param [in] count Number of 4k pages to create
<> 133:99b5ccf27215 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 133:99b5ccf27215 773 \param [in] ttb_l2 L2 table base address
<> 133:99b5ccf27215 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 133:99b5ccf27215 775
<> 133:99b5ccf27215 776 */
<> 133:99b5ccf27215 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 133:99b5ccf27215 778 {
<> 133:99b5ccf27215 779
<> 133:99b5ccf27215 780 uint32_t offset, offset2;
<> 133:99b5ccf27215 781 uint32_t entry, entry2;
<> 133:99b5ccf27215 782 uint32_t i;
<> 133:99b5ccf27215 783
<> 133:99b5ccf27215 784
<> 133:99b5ccf27215 785 offset = base_address >> 20;
<> 133:99b5ccf27215 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 133:99b5ccf27215 787
<> 133:99b5ccf27215 788 //4 bytes aligned
<> 133:99b5ccf27215 789 ttb += offset;
<> 133:99b5ccf27215 790 //create l1_entry
<> 133:99b5ccf27215 791 *ttb = entry;
<> 133:99b5ccf27215 792
<> 133:99b5ccf27215 793 offset2 = (base_address & 0xff000) >> 12;
<> 133:99b5ccf27215 794 ttb_l2 += offset2;
<> 133:99b5ccf27215 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
<> 133:99b5ccf27215 796 for (i = 0; i < count; i++ )
<> 133:99b5ccf27215 797 {
<> 133:99b5ccf27215 798 //4 bytes aligned
<> 133:99b5ccf27215 799 *ttb_l2++ = entry2;
<> 133:99b5ccf27215 800 entry2 += OFFSET_4K;
<> 133:99b5ccf27215 801 }
<> 133:99b5ccf27215 802 }
<> 133:99b5ccf27215 803
<> 133:99b5ccf27215 804 /** \brief Create a 64k page entry
<> 133:99b5ccf27215 805
<> 133:99b5ccf27215 806 \param [in] ttb L1 table base address
<> 133:99b5ccf27215 807 \param [in] base_address 64k base address
<> 133:99b5ccf27215 808 \param [in] count Number of 64k pages to create
<> 133:99b5ccf27215 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 133:99b5ccf27215 810 \param [in] ttb_l2 L2 table base address
<> 133:99b5ccf27215 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 133:99b5ccf27215 812
<> 133:99b5ccf27215 813 */
<> 133:99b5ccf27215 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 133:99b5ccf27215 815 {
<> 133:99b5ccf27215 816 uint32_t offset, offset2;
<> 133:99b5ccf27215 817 uint32_t entry, entry2;
<> 133:99b5ccf27215 818 uint32_t i,j;
<> 133:99b5ccf27215 819
<> 133:99b5ccf27215 820
<> 133:99b5ccf27215 821 offset = base_address >> 20;
<> 133:99b5ccf27215 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 133:99b5ccf27215 823
<> 133:99b5ccf27215 824 //4 bytes aligned
<> 133:99b5ccf27215 825 ttb += offset;
<> 133:99b5ccf27215 826 //create l1_entry
<> 133:99b5ccf27215 827 *ttb = entry;
<> 133:99b5ccf27215 828
<> 133:99b5ccf27215 829 offset2 = (base_address & 0xff000) >> 12;
<> 133:99b5ccf27215 830 ttb_l2 += offset2;
<> 133:99b5ccf27215 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
<> 133:99b5ccf27215 832 for (i = 0; i < count; i++ )
<> 133:99b5ccf27215 833 {
<> 133:99b5ccf27215 834 //create 16 entries
<> 133:99b5ccf27215 835 for (j = 0; j < 16; j++)
<> 133:99b5ccf27215 836 //4 bytes aligned
<> 133:99b5ccf27215 837 *ttb_l2++ = entry2;
<> 133:99b5ccf27215 838 entry2 += OFFSET_64K;
<> 133:99b5ccf27215 839 }
<> 133:99b5ccf27215 840 }
<> 133:99b5ccf27215 841
<> 133:99b5ccf27215 842 /*@} end of MMU_Functions */
<> 133:99b5ccf27215 843 #endif
<> 133:99b5ccf27215 844
<> 133:99b5ccf27215 845 #ifdef __cplusplus
<> 133:99b5ccf27215 846 }
<> 133:99b5ccf27215 847 #endif