mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SAMR21G18A/core_sc000.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**************************************************************************//**
Kojto 111:4336505e4b1c 2 * @file core_sc000.h
Kojto 111:4336505e4b1c 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
Kojto 111:4336505e4b1c 4 * @version V4.10
Kojto 111:4336505e4b1c 5 * @date 18. March 2015
Kojto 111:4336505e4b1c 6 *
Kojto 111:4336505e4b1c 7 * @note
Kojto 111:4336505e4b1c 8 *
Kojto 111:4336505e4b1c 9 ******************************************************************************/
Kojto 111:4336505e4b1c 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 111:4336505e4b1c 11
Kojto 111:4336505e4b1c 12 All rights reserved.
Kojto 111:4336505e4b1c 13 Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 14 modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 15 - Redistributions of source code must retain the above copyright
Kojto 111:4336505e4b1c 16 notice, this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 - Redistributions in binary form must reproduce the above copyright
Kojto 111:4336505e4b1c 18 notice, this list of conditions and the following disclaimer in the
Kojto 111:4336505e4b1c 19 documentation and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 111:4336505e4b1c 21 to endorse or promote products derived from this software without
Kojto 111:4336505e4b1c 22 specific prior written permission.
Kojto 111:4336505e4b1c 23 *
Kojto 111:4336505e4b1c 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 111:4336505e4b1c 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 111:4336505e4b1c 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 111:4336505e4b1c 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 111:4336505e4b1c 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 111:4336505e4b1c 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 111:4336505e4b1c 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 111:4336505e4b1c 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 111:4336505e4b1c 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 111:4336505e4b1c 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 35 ---------------------------------------------------------------------------*/
Kojto 111:4336505e4b1c 36
Kojto 111:4336505e4b1c 37
Kojto 111:4336505e4b1c 38 #if defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 111:4336505e4b1c 40 #endif
Kojto 111:4336505e4b1c 41
Kojto 111:4336505e4b1c 42 #ifndef __CORE_SC000_H_GENERIC
Kojto 111:4336505e4b1c 43 #define __CORE_SC000_H_GENERIC
Kojto 111:4336505e4b1c 44
Kojto 111:4336505e4b1c 45 #ifdef __cplusplus
Kojto 111:4336505e4b1c 46 extern "C" {
Kojto 111:4336505e4b1c 47 #endif
Kojto 111:4336505e4b1c 48
Kojto 111:4336505e4b1c 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 111:4336505e4b1c 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 111:4336505e4b1c 51
Kojto 111:4336505e4b1c 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 111:4336505e4b1c 53 Function definitions in header files are used to allow 'inlining'.
Kojto 111:4336505e4b1c 54
Kojto 111:4336505e4b1c 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 111:4336505e4b1c 56 Unions are used for effective representation of core registers.
Kojto 111:4336505e4b1c 57
Kojto 111:4336505e4b1c 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 111:4336505e4b1c 59 Function-like macros are used to allow more efficient code.
Kojto 111:4336505e4b1c 60 */
Kojto 111:4336505e4b1c 61
Kojto 111:4336505e4b1c 62
Kojto 111:4336505e4b1c 63 /*******************************************************************************
Kojto 111:4336505e4b1c 64 * CMSIS definitions
Kojto 111:4336505e4b1c 65 ******************************************************************************/
Kojto 111:4336505e4b1c 66 /** \ingroup SC000
Kojto 111:4336505e4b1c 67 @{
Kojto 111:4336505e4b1c 68 */
Kojto 111:4336505e4b1c 69
Kojto 111:4336505e4b1c 70 /* CMSIS SC000 definitions */
Kojto 111:4336505e4b1c 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 111:4336505e4b1c 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 111:4336505e4b1c 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
Kojto 111:4336505e4b1c 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 111:4336505e4b1c 75
Kojto 111:4336505e4b1c 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
Kojto 111:4336505e4b1c 77
Kojto 111:4336505e4b1c 78
Kojto 111:4336505e4b1c 79 #if defined ( __CC_ARM )
Kojto 111:4336505e4b1c 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 111:4336505e4b1c 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 111:4336505e4b1c 82 #define __STATIC_INLINE static __inline
Kojto 111:4336505e4b1c 83
Kojto 111:4336505e4b1c 84 #elif defined ( __GNUC__ )
Kojto 111:4336505e4b1c 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 111:4336505e4b1c 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 111:4336505e4b1c 87 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 88
Kojto 111:4336505e4b1c 89 #elif defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 111:4336505e4b1c 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 111:4336505e4b1c 92 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 93
Kojto 111:4336505e4b1c 94 #elif defined ( __TMS470__ )
Kojto 111:4336505e4b1c 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 111:4336505e4b1c 96 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 97
Kojto 111:4336505e4b1c 98 #elif defined ( __TASKING__ )
Kojto 111:4336505e4b1c 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 111:4336505e4b1c 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 111:4336505e4b1c 101 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 102
Kojto 111:4336505e4b1c 103 #elif defined ( __CSMC__ )
Kojto 111:4336505e4b1c 104 #define __packed
Kojto 111:4336505e4b1c 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 111:4336505e4b1c 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 111:4336505e4b1c 107 #define __STATIC_INLINE static inline
Kojto 111:4336505e4b1c 108
Kojto 111:4336505e4b1c 109 #endif
Kojto 111:4336505e4b1c 110
Kojto 111:4336505e4b1c 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 111:4336505e4b1c 112 This core does not support an FPU at all
Kojto 111:4336505e4b1c 113 */
Kojto 111:4336505e4b1c 114 #define __FPU_USED 0
Kojto 111:4336505e4b1c 115
Kojto 111:4336505e4b1c 116 #if defined ( __CC_ARM )
Kojto 111:4336505e4b1c 117 #if defined __TARGET_FPU_VFP
Kojto 111:4336505e4b1c 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 119 #endif
Kojto 111:4336505e4b1c 120
Kojto 111:4336505e4b1c 121 #elif defined ( __GNUC__ )
Kojto 111:4336505e4b1c 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 111:4336505e4b1c 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 124 #endif
Kojto 111:4336505e4b1c 125
Kojto 111:4336505e4b1c 126 #elif defined ( __ICCARM__ )
Kojto 111:4336505e4b1c 127 #if defined __ARMVFP__
Kojto 111:4336505e4b1c 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 129 #endif
Kojto 111:4336505e4b1c 130
Kojto 111:4336505e4b1c 131 #elif defined ( __TMS470__ )
Kojto 111:4336505e4b1c 132 #if defined __TI__VFP_SUPPORT____
Kojto 111:4336505e4b1c 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 134 #endif
Kojto 111:4336505e4b1c 135
Kojto 111:4336505e4b1c 136 #elif defined ( __TASKING__ )
Kojto 111:4336505e4b1c 137 #if defined __FPU_VFP__
Kojto 111:4336505e4b1c 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 139 #endif
Kojto 111:4336505e4b1c 140
Kojto 111:4336505e4b1c 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 111:4336505e4b1c 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 111:4336505e4b1c 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 111:4336505e4b1c 144 #endif
Kojto 111:4336505e4b1c 145 #endif
Kojto 111:4336505e4b1c 146
Kojto 111:4336505e4b1c 147 #include <stdint.h> /* standard types definitions */
Kojto 111:4336505e4b1c 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 111:4336505e4b1c 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 111:4336505e4b1c 150
Kojto 111:4336505e4b1c 151 #ifdef __cplusplus
Kojto 111:4336505e4b1c 152 }
Kojto 111:4336505e4b1c 153 #endif
Kojto 111:4336505e4b1c 154
Kojto 111:4336505e4b1c 155 #endif /* __CORE_SC000_H_GENERIC */
Kojto 111:4336505e4b1c 156
Kojto 111:4336505e4b1c 157 #ifndef __CMSIS_GENERIC
Kojto 111:4336505e4b1c 158
Kojto 111:4336505e4b1c 159 #ifndef __CORE_SC000_H_DEPENDANT
Kojto 111:4336505e4b1c 160 #define __CORE_SC000_H_DEPENDANT
Kojto 111:4336505e4b1c 161
Kojto 111:4336505e4b1c 162 #ifdef __cplusplus
Kojto 111:4336505e4b1c 163 extern "C" {
Kojto 111:4336505e4b1c 164 #endif
Kojto 111:4336505e4b1c 165
Kojto 111:4336505e4b1c 166 /* check device defines and use defaults */
Kojto 111:4336505e4b1c 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 111:4336505e4b1c 168 #ifndef __SC000_REV
Kojto 111:4336505e4b1c 169 #define __SC000_REV 0x0000
Kojto 111:4336505e4b1c 170 #warning "__SC000_REV not defined in device header file; using default!"
Kojto 111:4336505e4b1c 171 #endif
Kojto 111:4336505e4b1c 172
Kojto 111:4336505e4b1c 173 #ifndef __MPU_PRESENT
Kojto 111:4336505e4b1c 174 #define __MPU_PRESENT 0
Kojto 111:4336505e4b1c 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 111:4336505e4b1c 176 #endif
Kojto 111:4336505e4b1c 177
Kojto 111:4336505e4b1c 178 #ifndef __NVIC_PRIO_BITS
Kojto 111:4336505e4b1c 179 #define __NVIC_PRIO_BITS 2
Kojto 111:4336505e4b1c 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 111:4336505e4b1c 181 #endif
Kojto 111:4336505e4b1c 182
Kojto 111:4336505e4b1c 183 #ifndef __Vendor_SysTickConfig
Kojto 111:4336505e4b1c 184 #define __Vendor_SysTickConfig 0
Kojto 111:4336505e4b1c 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 111:4336505e4b1c 186 #endif
Kojto 111:4336505e4b1c 187 #endif
Kojto 111:4336505e4b1c 188
Kojto 111:4336505e4b1c 189 /* IO definitions (access restrictions to peripheral registers) */
Kojto 111:4336505e4b1c 190 /**
Kojto 111:4336505e4b1c 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 111:4336505e4b1c 192
Kojto 111:4336505e4b1c 193 <strong>IO Type Qualifiers</strong> are used
Kojto 111:4336505e4b1c 194 \li to specify the access to peripheral variables.
Kojto 111:4336505e4b1c 195 \li for automatic generation of peripheral register debug information.
Kojto 111:4336505e4b1c 196 */
Kojto 111:4336505e4b1c 197 #ifdef __cplusplus
Kojto 111:4336505e4b1c 198 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 111:4336505e4b1c 199 #else
Kojto 111:4336505e4b1c 200 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 111:4336505e4b1c 201 #endif
Kojto 111:4336505e4b1c 202 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 111:4336505e4b1c 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 111:4336505e4b1c 204
Kojto 111:4336505e4b1c 205 /*@} end of group SC000 */
Kojto 111:4336505e4b1c 206
Kojto 111:4336505e4b1c 207
Kojto 111:4336505e4b1c 208
Kojto 111:4336505e4b1c 209 /*******************************************************************************
Kojto 111:4336505e4b1c 210 * Register Abstraction
Kojto 111:4336505e4b1c 211 Core Register contain:
Kojto 111:4336505e4b1c 212 - Core Register
Kojto 111:4336505e4b1c 213 - Core NVIC Register
Kojto 111:4336505e4b1c 214 - Core SCB Register
Kojto 111:4336505e4b1c 215 - Core SysTick Register
Kojto 111:4336505e4b1c 216 - Core MPU Register
Kojto 111:4336505e4b1c 217 ******************************************************************************/
Kojto 111:4336505e4b1c 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 111:4336505e4b1c 219 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 111:4336505e4b1c 220 */
Kojto 111:4336505e4b1c 221
Kojto 111:4336505e4b1c 222 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 223 \defgroup CMSIS_CORE Status and Control Registers
Kojto 111:4336505e4b1c 224 \brief Core Register type definitions.
Kojto 111:4336505e4b1c 225 @{
Kojto 111:4336505e4b1c 226 */
Kojto 111:4336505e4b1c 227
Kojto 111:4336505e4b1c 228 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 111:4336505e4b1c 229 */
Kojto 111:4336505e4b1c 230 typedef union
Kojto 111:4336505e4b1c 231 {
Kojto 111:4336505e4b1c 232 struct
Kojto 111:4336505e4b1c 233 {
Kojto 111:4336505e4b1c 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 111:4336505e4b1c 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 111:4336505e4b1c 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 111:4336505e4b1c 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 111:4336505e4b1c 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 111:4336505e4b1c 239 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 240 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 241 } APSR_Type;
Kojto 111:4336505e4b1c 242
Kojto 111:4336505e4b1c 243 /* APSR Register Definitions */
Kojto 111:4336505e4b1c 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 111:4336505e4b1c 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 111:4336505e4b1c 246
Kojto 111:4336505e4b1c 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 111:4336505e4b1c 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 111:4336505e4b1c 249
Kojto 111:4336505e4b1c 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 111:4336505e4b1c 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 111:4336505e4b1c 252
Kojto 111:4336505e4b1c 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 111:4336505e4b1c 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 111:4336505e4b1c 255
Kojto 111:4336505e4b1c 256
Kojto 111:4336505e4b1c 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 111:4336505e4b1c 258 */
Kojto 111:4336505e4b1c 259 typedef union
Kojto 111:4336505e4b1c 260 {
Kojto 111:4336505e4b1c 261 struct
Kojto 111:4336505e4b1c 262 {
Kojto 111:4336505e4b1c 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 111:4336505e4b1c 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 111:4336505e4b1c 265 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 266 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 267 } IPSR_Type;
Kojto 111:4336505e4b1c 268
Kojto 111:4336505e4b1c 269 /* IPSR Register Definitions */
Kojto 111:4336505e4b1c 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 111:4336505e4b1c 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 111:4336505e4b1c 272
Kojto 111:4336505e4b1c 273
Kojto 111:4336505e4b1c 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 111:4336505e4b1c 275 */
Kojto 111:4336505e4b1c 276 typedef union
Kojto 111:4336505e4b1c 277 {
Kojto 111:4336505e4b1c 278 struct
Kojto 111:4336505e4b1c 279 {
Kojto 111:4336505e4b1c 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 111:4336505e4b1c 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 111:4336505e4b1c 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 111:4336505e4b1c 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 111:4336505e4b1c 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 111:4336505e4b1c 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 111:4336505e4b1c 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 111:4336505e4b1c 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 111:4336505e4b1c 288 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 289 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 290 } xPSR_Type;
Kojto 111:4336505e4b1c 291
Kojto 111:4336505e4b1c 292 /* xPSR Register Definitions */
Kojto 111:4336505e4b1c 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 111:4336505e4b1c 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 111:4336505e4b1c 295
Kojto 111:4336505e4b1c 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 111:4336505e4b1c 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 111:4336505e4b1c 298
Kojto 111:4336505e4b1c 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 111:4336505e4b1c 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 111:4336505e4b1c 301
Kojto 111:4336505e4b1c 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 111:4336505e4b1c 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 111:4336505e4b1c 304
Kojto 111:4336505e4b1c 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 111:4336505e4b1c 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 111:4336505e4b1c 307
Kojto 111:4336505e4b1c 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 111:4336505e4b1c 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 111:4336505e4b1c 310
Kojto 111:4336505e4b1c 311
Kojto 111:4336505e4b1c 312 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 111:4336505e4b1c 313 */
Kojto 111:4336505e4b1c 314 typedef union
Kojto 111:4336505e4b1c 315 {
Kojto 111:4336505e4b1c 316 struct
Kojto 111:4336505e4b1c 317 {
Kojto 111:4336505e4b1c 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 111:4336505e4b1c 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 111:4336505e4b1c 321 } b; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 322 uint32_t w; /*!< Type used for word access */
Kojto 111:4336505e4b1c 323 } CONTROL_Type;
Kojto 111:4336505e4b1c 324
Kojto 111:4336505e4b1c 325 /* CONTROL Register Definitions */
Kojto 111:4336505e4b1c 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 111:4336505e4b1c 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 111:4336505e4b1c 328
Kojto 111:4336505e4b1c 329 /*@} end of group CMSIS_CORE */
Kojto 111:4336505e4b1c 330
Kojto 111:4336505e4b1c 331
Kojto 111:4336505e4b1c 332 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 111:4336505e4b1c 334 \brief Type definitions for the NVIC Registers
Kojto 111:4336505e4b1c 335 @{
Kojto 111:4336505e4b1c 336 */
Kojto 111:4336505e4b1c 337
Kojto 111:4336505e4b1c 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 111:4336505e4b1c 339 */
Kojto 111:4336505e4b1c 340 typedef struct
Kojto 111:4336505e4b1c 341 {
Kojto 111:4336505e4b1c 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 111:4336505e4b1c 343 uint32_t RESERVED0[31];
Kojto 111:4336505e4b1c 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 111:4336505e4b1c 345 uint32_t RSERVED1[31];
Kojto 111:4336505e4b1c 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 111:4336505e4b1c 347 uint32_t RESERVED2[31];
Kojto 111:4336505e4b1c 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 111:4336505e4b1c 349 uint32_t RESERVED3[31];
Kojto 111:4336505e4b1c 350 uint32_t RESERVED4[64];
Kojto 111:4336505e4b1c 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 111:4336505e4b1c 352 } NVIC_Type;
Kojto 111:4336505e4b1c 353
Kojto 111:4336505e4b1c 354 /*@} end of group CMSIS_NVIC */
Kojto 111:4336505e4b1c 355
Kojto 111:4336505e4b1c 356
Kojto 111:4336505e4b1c 357 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 358 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 111:4336505e4b1c 359 \brief Type definitions for the System Control Block Registers
Kojto 111:4336505e4b1c 360 @{
Kojto 111:4336505e4b1c 361 */
Kojto 111:4336505e4b1c 362
Kojto 111:4336505e4b1c 363 /** \brief Structure type to access the System Control Block (SCB).
Kojto 111:4336505e4b1c 364 */
Kojto 111:4336505e4b1c 365 typedef struct
Kojto 111:4336505e4b1c 366 {
Kojto 111:4336505e4b1c 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 111:4336505e4b1c 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 111:4336505e4b1c 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 111:4336505e4b1c 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 111:4336505e4b1c 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 111:4336505e4b1c 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 111:4336505e4b1c 373 uint32_t RESERVED0[1];
Kojto 111:4336505e4b1c 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 111:4336505e4b1c 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 111:4336505e4b1c 376 uint32_t RESERVED1[154];
Kojto 111:4336505e4b1c 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Kojto 111:4336505e4b1c 378 } SCB_Type;
Kojto 111:4336505e4b1c 379
Kojto 111:4336505e4b1c 380 /* SCB CPUID Register Definitions */
Kojto 111:4336505e4b1c 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 111:4336505e4b1c 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 111:4336505e4b1c 383
Kojto 111:4336505e4b1c 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 111:4336505e4b1c 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 111:4336505e4b1c 386
Kojto 111:4336505e4b1c 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 111:4336505e4b1c 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 111:4336505e4b1c 389
Kojto 111:4336505e4b1c 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 111:4336505e4b1c 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 111:4336505e4b1c 392
Kojto 111:4336505e4b1c 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 111:4336505e4b1c 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 111:4336505e4b1c 395
Kojto 111:4336505e4b1c 396 /* SCB Interrupt Control State Register Definitions */
Kojto 111:4336505e4b1c 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 111:4336505e4b1c 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 111:4336505e4b1c 399
Kojto 111:4336505e4b1c 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 111:4336505e4b1c 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 111:4336505e4b1c 402
Kojto 111:4336505e4b1c 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 111:4336505e4b1c 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 111:4336505e4b1c 405
Kojto 111:4336505e4b1c 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 111:4336505e4b1c 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 111:4336505e4b1c 408
Kojto 111:4336505e4b1c 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 111:4336505e4b1c 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 111:4336505e4b1c 411
Kojto 111:4336505e4b1c 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 111:4336505e4b1c 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 111:4336505e4b1c 414
Kojto 111:4336505e4b1c 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 111:4336505e4b1c 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 111:4336505e4b1c 417
Kojto 111:4336505e4b1c 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 111:4336505e4b1c 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 111:4336505e4b1c 420
Kojto 111:4336505e4b1c 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 111:4336505e4b1c 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 111:4336505e4b1c 423
Kojto 111:4336505e4b1c 424 /* SCB Interrupt Control State Register Definitions */
Kojto 111:4336505e4b1c 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 111:4336505e4b1c 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 111:4336505e4b1c 427
Kojto 111:4336505e4b1c 428 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 111:4336505e4b1c 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 111:4336505e4b1c 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 111:4336505e4b1c 431
Kojto 111:4336505e4b1c 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 111:4336505e4b1c 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 111:4336505e4b1c 434
Kojto 111:4336505e4b1c 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 111:4336505e4b1c 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 111:4336505e4b1c 437
Kojto 111:4336505e4b1c 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 111:4336505e4b1c 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 111:4336505e4b1c 440
Kojto 111:4336505e4b1c 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 111:4336505e4b1c 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 111:4336505e4b1c 443
Kojto 111:4336505e4b1c 444 /* SCB System Control Register Definitions */
Kojto 111:4336505e4b1c 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 111:4336505e4b1c 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 111:4336505e4b1c 447
Kojto 111:4336505e4b1c 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 111:4336505e4b1c 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 111:4336505e4b1c 450
Kojto 111:4336505e4b1c 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 111:4336505e4b1c 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 111:4336505e4b1c 453
Kojto 111:4336505e4b1c 454 /* SCB Configuration Control Register Definitions */
Kojto 111:4336505e4b1c 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 111:4336505e4b1c 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 111:4336505e4b1c 457
Kojto 111:4336505e4b1c 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 111:4336505e4b1c 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 111:4336505e4b1c 460
Kojto 111:4336505e4b1c 461 /* SCB System Handler Control and State Register Definitions */
Kojto 111:4336505e4b1c 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 111:4336505e4b1c 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 111:4336505e4b1c 464
Kojto 111:4336505e4b1c 465 /*@} end of group CMSIS_SCB */
Kojto 111:4336505e4b1c 466
Kojto 111:4336505e4b1c 467
Kojto 111:4336505e4b1c 468 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 111:4336505e4b1c 470 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 111:4336505e4b1c 471 @{
Kojto 111:4336505e4b1c 472 */
Kojto 111:4336505e4b1c 473
Kojto 111:4336505e4b1c 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 111:4336505e4b1c 475 */
Kojto 111:4336505e4b1c 476 typedef struct
Kojto 111:4336505e4b1c 477 {
Kojto 111:4336505e4b1c 478 uint32_t RESERVED0[2];
Kojto 111:4336505e4b1c 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 111:4336505e4b1c 480 } SCnSCB_Type;
Kojto 111:4336505e4b1c 481
Kojto 111:4336505e4b1c 482 /* Auxiliary Control Register Definitions */
Kojto 111:4336505e4b1c 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 111:4336505e4b1c 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 111:4336505e4b1c 485
Kojto 111:4336505e4b1c 486 /*@} end of group CMSIS_SCnotSCB */
Kojto 111:4336505e4b1c 487
Kojto 111:4336505e4b1c 488
Kojto 111:4336505e4b1c 489 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 111:4336505e4b1c 491 \brief Type definitions for the System Timer Registers.
Kojto 111:4336505e4b1c 492 @{
Kojto 111:4336505e4b1c 493 */
Kojto 111:4336505e4b1c 494
Kojto 111:4336505e4b1c 495 /** \brief Structure type to access the System Timer (SysTick).
Kojto 111:4336505e4b1c 496 */
Kojto 111:4336505e4b1c 497 typedef struct
Kojto 111:4336505e4b1c 498 {
Kojto 111:4336505e4b1c 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 111:4336505e4b1c 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 111:4336505e4b1c 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 111:4336505e4b1c 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 111:4336505e4b1c 503 } SysTick_Type;
Kojto 111:4336505e4b1c 504
Kojto 111:4336505e4b1c 505 /* SysTick Control / Status Register Definitions */
Kojto 111:4336505e4b1c 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 111:4336505e4b1c 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 111:4336505e4b1c 508
Kojto 111:4336505e4b1c 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 111:4336505e4b1c 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 111:4336505e4b1c 511
Kojto 111:4336505e4b1c 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 111:4336505e4b1c 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 111:4336505e4b1c 514
Kojto 111:4336505e4b1c 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 111:4336505e4b1c 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 111:4336505e4b1c 517
Kojto 111:4336505e4b1c 518 /* SysTick Reload Register Definitions */
Kojto 111:4336505e4b1c 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 111:4336505e4b1c 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 111:4336505e4b1c 521
Kojto 111:4336505e4b1c 522 /* SysTick Current Register Definitions */
Kojto 111:4336505e4b1c 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 111:4336505e4b1c 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 111:4336505e4b1c 525
Kojto 111:4336505e4b1c 526 /* SysTick Calibration Register Definitions */
Kojto 111:4336505e4b1c 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 111:4336505e4b1c 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 111:4336505e4b1c 529
Kojto 111:4336505e4b1c 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 111:4336505e4b1c 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 111:4336505e4b1c 532
Kojto 111:4336505e4b1c 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 111:4336505e4b1c 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 111:4336505e4b1c 535
Kojto 111:4336505e4b1c 536 /*@} end of group CMSIS_SysTick */
Kojto 111:4336505e4b1c 537
Kojto 111:4336505e4b1c 538 #if (__MPU_PRESENT == 1)
Kojto 111:4336505e4b1c 539 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 111:4336505e4b1c 541 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 111:4336505e4b1c 542 @{
Kojto 111:4336505e4b1c 543 */
Kojto 111:4336505e4b1c 544
Kojto 111:4336505e4b1c 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 111:4336505e4b1c 546 */
Kojto 111:4336505e4b1c 547 typedef struct
Kojto 111:4336505e4b1c 548 {
Kojto 111:4336505e4b1c 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 111:4336505e4b1c 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 111:4336505e4b1c 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 111:4336505e4b1c 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 111:4336505e4b1c 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 111:4336505e4b1c 554 } MPU_Type;
Kojto 111:4336505e4b1c 555
Kojto 111:4336505e4b1c 556 /* MPU Type Register */
Kojto 111:4336505e4b1c 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 111:4336505e4b1c 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 111:4336505e4b1c 559
Kojto 111:4336505e4b1c 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 111:4336505e4b1c 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 111:4336505e4b1c 562
Kojto 111:4336505e4b1c 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 111:4336505e4b1c 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 111:4336505e4b1c 565
Kojto 111:4336505e4b1c 566 /* MPU Control Register */
Kojto 111:4336505e4b1c 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 111:4336505e4b1c 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 111:4336505e4b1c 569
Kojto 111:4336505e4b1c 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 111:4336505e4b1c 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 111:4336505e4b1c 572
Kojto 111:4336505e4b1c 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 111:4336505e4b1c 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 111:4336505e4b1c 575
Kojto 111:4336505e4b1c 576 /* MPU Region Number Register */
Kojto 111:4336505e4b1c 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 111:4336505e4b1c 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 111:4336505e4b1c 579
Kojto 111:4336505e4b1c 580 /* MPU Region Base Address Register */
Kojto 111:4336505e4b1c 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 111:4336505e4b1c 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 111:4336505e4b1c 583
Kojto 111:4336505e4b1c 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 111:4336505e4b1c 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 111:4336505e4b1c 586
Kojto 111:4336505e4b1c 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 111:4336505e4b1c 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 111:4336505e4b1c 589
Kojto 111:4336505e4b1c 590 /* MPU Region Attribute and Size Register */
Kojto 111:4336505e4b1c 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 111:4336505e4b1c 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 111:4336505e4b1c 593
Kojto 111:4336505e4b1c 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 111:4336505e4b1c 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 111:4336505e4b1c 596
Kojto 111:4336505e4b1c 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 111:4336505e4b1c 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 111:4336505e4b1c 599
Kojto 111:4336505e4b1c 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 111:4336505e4b1c 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 111:4336505e4b1c 602
Kojto 111:4336505e4b1c 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 111:4336505e4b1c 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 111:4336505e4b1c 605
Kojto 111:4336505e4b1c 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 111:4336505e4b1c 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 111:4336505e4b1c 608
Kojto 111:4336505e4b1c 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 111:4336505e4b1c 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 111:4336505e4b1c 611
Kojto 111:4336505e4b1c 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 111:4336505e4b1c 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 111:4336505e4b1c 614
Kojto 111:4336505e4b1c 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 111:4336505e4b1c 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 111:4336505e4b1c 617
Kojto 111:4336505e4b1c 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 111:4336505e4b1c 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 111:4336505e4b1c 620
Kojto 111:4336505e4b1c 621 /*@} end of group CMSIS_MPU */
Kojto 111:4336505e4b1c 622 #endif
Kojto 111:4336505e4b1c 623
Kojto 111:4336505e4b1c 624
Kojto 111:4336505e4b1c 625 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 111:4336505e4b1c 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 111:4336505e4b1c 628 are only accessible over DAP and not via processor. Therefore
Kojto 111:4336505e4b1c 629 they are not covered by the Cortex-M0 header file.
Kojto 111:4336505e4b1c 630 @{
Kojto 111:4336505e4b1c 631 */
Kojto 111:4336505e4b1c 632 /*@} end of group CMSIS_CoreDebug */
Kojto 111:4336505e4b1c 633
Kojto 111:4336505e4b1c 634
Kojto 111:4336505e4b1c 635 /** \ingroup CMSIS_core_register
Kojto 111:4336505e4b1c 636 \defgroup CMSIS_core_base Core Definitions
Kojto 111:4336505e4b1c 637 \brief Definitions for base addresses, unions, and structures.
Kojto 111:4336505e4b1c 638 @{
Kojto 111:4336505e4b1c 639 */
Kojto 111:4336505e4b1c 640
Kojto 111:4336505e4b1c 641 /* Memory mapping of SC000 Hardware */
Kojto 111:4336505e4b1c 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 111:4336505e4b1c 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 111:4336505e4b1c 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 111:4336505e4b1c 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 111:4336505e4b1c 646
Kojto 111:4336505e4b1c 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 111:4336505e4b1c 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 111:4336505e4b1c 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 111:4336505e4b1c 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 111:4336505e4b1c 651
Kojto 111:4336505e4b1c 652 #if (__MPU_PRESENT == 1)
Kojto 111:4336505e4b1c 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 111:4336505e4b1c 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 111:4336505e4b1c 655 #endif
Kojto 111:4336505e4b1c 656
Kojto 111:4336505e4b1c 657 /*@} */
Kojto 111:4336505e4b1c 658
Kojto 111:4336505e4b1c 659
Kojto 111:4336505e4b1c 660
Kojto 111:4336505e4b1c 661 /*******************************************************************************
Kojto 111:4336505e4b1c 662 * Hardware Abstraction Layer
Kojto 111:4336505e4b1c 663 Core Function Interface contains:
Kojto 111:4336505e4b1c 664 - Core NVIC Functions
Kojto 111:4336505e4b1c 665 - Core SysTick Functions
Kojto 111:4336505e4b1c 666 - Core Register Access Functions
Kojto 111:4336505e4b1c 667 ******************************************************************************/
Kojto 111:4336505e4b1c 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 111:4336505e4b1c 669 */
Kojto 111:4336505e4b1c 670
Kojto 111:4336505e4b1c 671
Kojto 111:4336505e4b1c 672
Kojto 111:4336505e4b1c 673 /* ########################## NVIC functions #################################### */
Kojto 111:4336505e4b1c 674 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 111:4336505e4b1c 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 111:4336505e4b1c 676 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 111:4336505e4b1c 677 @{
Kojto 111:4336505e4b1c 678 */
Kojto 111:4336505e4b1c 679
Kojto 111:4336505e4b1c 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 111:4336505e4b1c 681 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 111:4336505e4b1c 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 111:4336505e4b1c 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 111:4336505e4b1c 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 111:4336505e4b1c 685
Kojto 111:4336505e4b1c 686
Kojto 111:4336505e4b1c 687 /** \brief Enable External Interrupt
Kojto 111:4336505e4b1c 688
Kojto 111:4336505e4b1c 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 111:4336505e4b1c 690
Kojto 111:4336505e4b1c 691 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 692 */
Kojto 111:4336505e4b1c 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 694 {
Kojto 111:4336505e4b1c 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 696 }
Kojto 111:4336505e4b1c 697
Kojto 111:4336505e4b1c 698
Kojto 111:4336505e4b1c 699 /** \brief Disable External Interrupt
Kojto 111:4336505e4b1c 700
Kojto 111:4336505e4b1c 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 111:4336505e4b1c 702
Kojto 111:4336505e4b1c 703 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 704 */
Kojto 111:4336505e4b1c 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 706 {
Kojto 111:4336505e4b1c 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 708 __DSB();
<> 131:faff56e089b2 709 __ISB();
Kojto 111:4336505e4b1c 710 }
Kojto 111:4336505e4b1c 711
Kojto 111:4336505e4b1c 712
Kojto 111:4336505e4b1c 713 /** \brief Get Pending Interrupt
Kojto 111:4336505e4b1c 714
Kojto 111:4336505e4b1c 715 The function reads the pending register in the NVIC and returns the pending bit
Kojto 111:4336505e4b1c 716 for the specified interrupt.
Kojto 111:4336505e4b1c 717
Kojto 111:4336505e4b1c 718 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 719
Kojto 111:4336505e4b1c 720 \return 0 Interrupt status is not pending.
Kojto 111:4336505e4b1c 721 \return 1 Interrupt status is pending.
Kojto 111:4336505e4b1c 722 */
Kojto 111:4336505e4b1c 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 724 {
Kojto 111:4336505e4b1c 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 111:4336505e4b1c 726 }
Kojto 111:4336505e4b1c 727
Kojto 111:4336505e4b1c 728
Kojto 111:4336505e4b1c 729 /** \brief Set Pending Interrupt
Kojto 111:4336505e4b1c 730
Kojto 111:4336505e4b1c 731 The function sets the pending bit of an external interrupt.
Kojto 111:4336505e4b1c 732
Kojto 111:4336505e4b1c 733 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 734 */
Kojto 111:4336505e4b1c 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 736 {
Kojto 111:4336505e4b1c 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 738 }
Kojto 111:4336505e4b1c 739
Kojto 111:4336505e4b1c 740
Kojto 111:4336505e4b1c 741 /** \brief Clear Pending Interrupt
Kojto 111:4336505e4b1c 742
Kojto 111:4336505e4b1c 743 The function clears the pending bit of an external interrupt.
Kojto 111:4336505e4b1c 744
Kojto 111:4336505e4b1c 745 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 111:4336505e4b1c 746 */
Kojto 111:4336505e4b1c 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 748 {
Kojto 111:4336505e4b1c 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 111:4336505e4b1c 750 }
Kojto 111:4336505e4b1c 751
Kojto 111:4336505e4b1c 752
Kojto 111:4336505e4b1c 753 /** \brief Set Interrupt Priority
Kojto 111:4336505e4b1c 754
Kojto 111:4336505e4b1c 755 The function sets the priority of an interrupt.
Kojto 111:4336505e4b1c 756
Kojto 111:4336505e4b1c 757 \note The priority cannot be set for every core interrupt.
Kojto 111:4336505e4b1c 758
Kojto 111:4336505e4b1c 759 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 760 \param [in] priority Priority to set.
Kojto 111:4336505e4b1c 761 */
Kojto 111:4336505e4b1c 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 111:4336505e4b1c 763 {
Kojto 111:4336505e4b1c 764 if((int32_t)(IRQn) < 0) {
Kojto 111:4336505e4b1c 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 111:4336505e4b1c 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 111:4336505e4b1c 767 }
Kojto 111:4336505e4b1c 768 else {
Kojto 111:4336505e4b1c 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 111:4336505e4b1c 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 111:4336505e4b1c 771 }
Kojto 111:4336505e4b1c 772 }
Kojto 111:4336505e4b1c 773
Kojto 111:4336505e4b1c 774
Kojto 111:4336505e4b1c 775 /** \brief Get Interrupt Priority
Kojto 111:4336505e4b1c 776
Kojto 111:4336505e4b1c 777 The function reads the priority of an interrupt. The interrupt
Kojto 111:4336505e4b1c 778 number can be positive to specify an external (device specific)
Kojto 111:4336505e4b1c 779 interrupt, or negative to specify an internal (core) interrupt.
Kojto 111:4336505e4b1c 780
Kojto 111:4336505e4b1c 781
Kojto 111:4336505e4b1c 782 \param [in] IRQn Interrupt number.
Kojto 111:4336505e4b1c 783 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 111:4336505e4b1c 784 priority bits of the microcontroller.
Kojto 111:4336505e4b1c 785 */
Kojto 111:4336505e4b1c 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 111:4336505e4b1c 787 {
Kojto 111:4336505e4b1c 788
Kojto 111:4336505e4b1c 789 if((int32_t)(IRQn) < 0) {
Kojto 111:4336505e4b1c 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 111:4336505e4b1c 791 }
Kojto 111:4336505e4b1c 792 else {
Kojto 111:4336505e4b1c 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 111:4336505e4b1c 794 }
Kojto 111:4336505e4b1c 795 }
Kojto 111:4336505e4b1c 796
Kojto 111:4336505e4b1c 797
Kojto 111:4336505e4b1c 798 /** \brief System Reset
Kojto 111:4336505e4b1c 799
Kojto 111:4336505e4b1c 800 The function initiates a system reset request to reset the MCU.
Kojto 111:4336505e4b1c 801 */
Kojto 111:4336505e4b1c 802 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 111:4336505e4b1c 803 {
Kojto 111:4336505e4b1c 804 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 111:4336505e4b1c 805 buffered write are completed before reset */
Kojto 111:4336505e4b1c 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 111:4336505e4b1c 807 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 111:4336505e4b1c 808 __DSB(); /* Ensure completion of memory access */
Kojto 111:4336505e4b1c 809 while(1) { __NOP(); } /* wait until reset */
Kojto 111:4336505e4b1c 810 }
Kojto 111:4336505e4b1c 811
Kojto 111:4336505e4b1c 812 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 111:4336505e4b1c 813
Kojto 111:4336505e4b1c 814
Kojto 111:4336505e4b1c 815
Kojto 111:4336505e4b1c 816 /* ################################## SysTick function ############################################ */
Kojto 111:4336505e4b1c 817 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 111:4336505e4b1c 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 111:4336505e4b1c 819 \brief Functions that configure the System.
Kojto 111:4336505e4b1c 820 @{
Kojto 111:4336505e4b1c 821 */
Kojto 111:4336505e4b1c 822
Kojto 111:4336505e4b1c 823 #if (__Vendor_SysTickConfig == 0)
Kojto 111:4336505e4b1c 824
Kojto 111:4336505e4b1c 825 /** \brief System Tick Configuration
Kojto 111:4336505e4b1c 826
Kojto 111:4336505e4b1c 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 111:4336505e4b1c 828 Counter is in free running mode to generate periodic interrupts.
Kojto 111:4336505e4b1c 829
Kojto 111:4336505e4b1c 830 \param [in] ticks Number of ticks between two interrupts.
Kojto 111:4336505e4b1c 831
Kojto 111:4336505e4b1c 832 \return 0 Function succeeded.
Kojto 111:4336505e4b1c 833 \return 1 Function failed.
Kojto 111:4336505e4b1c 834
Kojto 111:4336505e4b1c 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 111:4336505e4b1c 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 111:4336505e4b1c 837 must contain a vendor-specific implementation of this function.
Kojto 111:4336505e4b1c 838
Kojto 111:4336505e4b1c 839 */
Kojto 111:4336505e4b1c 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 111:4336505e4b1c 841 {
Kojto 111:4336505e4b1c 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 111:4336505e4b1c 843
Kojto 111:4336505e4b1c 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 111:4336505e4b1c 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 111:4336505e4b1c 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 111:4336505e4b1c 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 111:4336505e4b1c 848 SysTick_CTRL_TICKINT_Msk |
Kojto 111:4336505e4b1c 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 111:4336505e4b1c 850 return (0UL); /* Function successful */
Kojto 111:4336505e4b1c 851 }
Kojto 111:4336505e4b1c 852
Kojto 111:4336505e4b1c 853 #endif
Kojto 111:4336505e4b1c 854
Kojto 111:4336505e4b1c 855 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 111:4336505e4b1c 856
Kojto 111:4336505e4b1c 857
Kojto 111:4336505e4b1c 858
Kojto 111:4336505e4b1c 859
Kojto 111:4336505e4b1c 860 #ifdef __cplusplus
Kojto 111:4336505e4b1c 861 }
Kojto 111:4336505e4b1c 862 #endif
Kojto 111:4336505e4b1c 863
Kojto 111:4336505e4b1c 864 #endif /* __CORE_SC000_H_DEPENDANT */
Kojto 111:4336505e4b1c 865
Kojto 111:4336505e4b1c 866 #endif /* __CMSIS_GENERIC */