mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F439ZI/core_ca_mmu.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
128:9bcdf88f62b0 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 ;/**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 ; * @file core_ca_mmu.h
Kojto 108:34e6b704fe68 3 ; * @brief MMU Startup File for A9_MP Device Series
bogdanm 92:4fc01daae5a5 4 ; * @version V1.01
Kojto 108:34e6b704fe68 5 ; * @date 10 Sept 2014
bogdanm 92:4fc01daae5a5 6 ; *
bogdanm 92:4fc01daae5a5 7 ; * @note
bogdanm 92:4fc01daae5a5 8 ; *
bogdanm 92:4fc01daae5a5 9 ; ******************************************************************************/
Kojto 108:34e6b704fe68 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
bogdanm 92:4fc01daae5a5 11 ;
bogdanm 92:4fc01daae5a5 12 ; All rights reserved.
bogdanm 92:4fc01daae5a5 13 ; Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 ; modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 ; - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 ; notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 ; - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 ; notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 ; documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 ; - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 ; to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 ; specific prior written permission.
bogdanm 92:4fc01daae5a5 23 ; *
bogdanm 92:4fc01daae5a5 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 ; POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ; ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 38 extern "C" {
bogdanm 92:4fc01daae5a5 39 #endif
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41 #ifndef _MMU_FUNC_H
bogdanm 92:4fc01daae5a5 42 #define _MMU_FUNC_H
bogdanm 92:4fc01daae5a5 43
bogdanm 92:4fc01daae5a5 44 #define SECTION_DESCRIPTOR (0x2)
bogdanm 92:4fc01daae5a5 45 #define SECTION_MASK (0xFFFFFFFC)
bogdanm 92:4fc01daae5a5 46
bogdanm 92:4fc01daae5a5 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
bogdanm 92:4fc01daae5a5 48 #define SECTION_B_SHIFT (2)
bogdanm 92:4fc01daae5a5 49 #define SECTION_C_SHIFT (3)
bogdanm 92:4fc01daae5a5 50 #define SECTION_TEX0_SHIFT (12)
bogdanm 92:4fc01daae5a5 51 #define SECTION_TEX1_SHIFT (13)
bogdanm 92:4fc01daae5a5 52 #define SECTION_TEX2_SHIFT (14)
bogdanm 92:4fc01daae5a5 53
bogdanm 92:4fc01daae5a5 54 #define SECTION_XN_MASK (0xFFFFFFEF)
bogdanm 92:4fc01daae5a5 55 #define SECTION_XN_SHIFT (4)
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
bogdanm 92:4fc01daae5a5 58 #define SECTION_DOMAIN_SHIFT (5)
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 #define SECTION_P_MASK (0xFFFFFDFF)
bogdanm 92:4fc01daae5a5 61 #define SECTION_P_SHIFT (9)
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 #define SECTION_AP_MASK (0xFFFF73FF)
bogdanm 92:4fc01daae5a5 64 #define SECTION_AP_SHIFT (10)
bogdanm 92:4fc01daae5a5 65 #define SECTION_AP2_SHIFT (15)
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 #define SECTION_S_MASK (0xFFFEFFFF)
bogdanm 92:4fc01daae5a5 68 #define SECTION_S_SHIFT (16)
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 #define SECTION_NG_MASK (0xFFFDFFFF)
bogdanm 92:4fc01daae5a5 71 #define SECTION_NG_SHIFT (17)
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 #define SECTION_NS_MASK (0xFFF7FFFF)
bogdanm 92:4fc01daae5a5 74 #define SECTION_NS_SHIFT (19)
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 #define PAGE_L1_DESCRIPTOR (0x1)
bogdanm 92:4fc01daae5a5 78 #define PAGE_L1_MASK (0xFFFFFFFC)
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 #define PAGE_L2_4K_DESC (0x2)
bogdanm 92:4fc01daae5a5 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 #define PAGE_L2_64K_DESC (0x1)
bogdanm 92:4fc01daae5a5 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
bogdanm 92:4fc01daae5a5 87 #define PAGE_4K_B_SHIFT (2)
bogdanm 92:4fc01daae5a5 88 #define PAGE_4K_C_SHIFT (3)
bogdanm 92:4fc01daae5a5 89 #define PAGE_4K_TEX0_SHIFT (6)
bogdanm 92:4fc01daae5a5 90 #define PAGE_4K_TEX1_SHIFT (7)
bogdanm 92:4fc01daae5a5 91 #define PAGE_4K_TEX2_SHIFT (8)
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
bogdanm 92:4fc01daae5a5 94 #define PAGE_64K_B_SHIFT (2)
bogdanm 92:4fc01daae5a5 95 #define PAGE_64K_C_SHIFT (3)
bogdanm 92:4fc01daae5a5 96 #define PAGE_64K_TEX0_SHIFT (12)
bogdanm 92:4fc01daae5a5 97 #define PAGE_64K_TEX1_SHIFT (13)
bogdanm 92:4fc01daae5a5 98 #define PAGE_64K_TEX2_SHIFT (14)
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
bogdanm 92:4fc01daae5a5 101 #define PAGE_B_SHIFT (2)
bogdanm 92:4fc01daae5a5 102 #define PAGE_C_SHIFT (3)
bogdanm 92:4fc01daae5a5 103 #define PAGE_TEX_SHIFT (12)
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
bogdanm 92:4fc01daae5a5 106 #define PAGE_XN_4K_SHIFT (0)
bogdanm 92:4fc01daae5a5 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
bogdanm 92:4fc01daae5a5 108 #define PAGE_XN_64K_SHIFT (15)
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110
bogdanm 92:4fc01daae5a5 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
bogdanm 92:4fc01daae5a5 112 #define PAGE_DOMAIN_SHIFT (5)
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 #define PAGE_P_MASK (0xFFFFFDFF)
bogdanm 92:4fc01daae5a5 115 #define PAGE_P_SHIFT (9)
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 #define PAGE_AP_MASK (0xFFFFFDCF)
bogdanm 92:4fc01daae5a5 118 #define PAGE_AP_SHIFT (4)
bogdanm 92:4fc01daae5a5 119 #define PAGE_AP2_SHIFT (9)
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 #define PAGE_S_MASK (0xFFFFFBFF)
bogdanm 92:4fc01daae5a5 122 #define PAGE_S_SHIFT (10)
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 #define PAGE_NG_MASK (0xFFFFF7FF)
bogdanm 92:4fc01daae5a5 125 #define PAGE_NG_SHIFT (11)
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 #define PAGE_NS_MASK (0xFFFFFFF7)
bogdanm 92:4fc01daae5a5 128 #define PAGE_NS_SHIFT (3)
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 #define OFFSET_1M (0x00100000)
bogdanm 92:4fc01daae5a5 131 #define OFFSET_64K (0x00010000)
bogdanm 92:4fc01daae5a5 132 #define OFFSET_4K (0x00001000)
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 #define DESCRIPTOR_FAULT (0x00000000)
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 /* ########################### MMU Function Access ########################### */
bogdanm 92:4fc01daae5a5 137 /** \ingroup MMU_FunctionInterface
bogdanm 92:4fc01daae5a5 138 \defgroup MMU_Functions MMU Functions Interface
bogdanm 92:4fc01daae5a5 139 @{
bogdanm 92:4fc01daae5a5 140 */
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142 /* Attributes enumerations */
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 /* Region size attributes */
bogdanm 92:4fc01daae5a5 145 typedef enum
bogdanm 92:4fc01daae5a5 146 {
bogdanm 92:4fc01daae5a5 147 SECTION,
bogdanm 92:4fc01daae5a5 148 PAGE_4k,
bogdanm 92:4fc01daae5a5 149 PAGE_64k,
bogdanm 92:4fc01daae5a5 150 } mmu_region_size_Type;
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 /* Region type attributes */
bogdanm 92:4fc01daae5a5 153 typedef enum
bogdanm 92:4fc01daae5a5 154 {
bogdanm 92:4fc01daae5a5 155 NORMAL,
bogdanm 92:4fc01daae5a5 156 DEVICE,
bogdanm 92:4fc01daae5a5 157 SHARED_DEVICE,
bogdanm 92:4fc01daae5a5 158 NON_SHARED_DEVICE,
bogdanm 92:4fc01daae5a5 159 STRONGLY_ORDERED
bogdanm 92:4fc01daae5a5 160 } mmu_memory_Type;
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 /* Region cacheability attributes */
bogdanm 92:4fc01daae5a5 163 typedef enum
bogdanm 92:4fc01daae5a5 164 {
bogdanm 92:4fc01daae5a5 165 NON_CACHEABLE,
bogdanm 92:4fc01daae5a5 166 WB_WA,
bogdanm 92:4fc01daae5a5 167 WT,
bogdanm 92:4fc01daae5a5 168 WB_NO_WA,
bogdanm 92:4fc01daae5a5 169 } mmu_cacheability_Type;
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /* Region parity check attributes */
bogdanm 92:4fc01daae5a5 172 typedef enum
bogdanm 92:4fc01daae5a5 173 {
bogdanm 92:4fc01daae5a5 174 ECC_DISABLED,
bogdanm 92:4fc01daae5a5 175 ECC_ENABLED,
bogdanm 92:4fc01daae5a5 176 } mmu_ecc_check_Type;
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 /* Region execution attributes */
bogdanm 92:4fc01daae5a5 179 typedef enum
bogdanm 92:4fc01daae5a5 180 {
bogdanm 92:4fc01daae5a5 181 EXECUTE,
bogdanm 92:4fc01daae5a5 182 NON_EXECUTE,
bogdanm 92:4fc01daae5a5 183 } mmu_execute_Type;
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 /* Region global attributes */
bogdanm 92:4fc01daae5a5 186 typedef enum
bogdanm 92:4fc01daae5a5 187 {
bogdanm 92:4fc01daae5a5 188 GLOBAL,
bogdanm 92:4fc01daae5a5 189 NON_GLOBAL,
bogdanm 92:4fc01daae5a5 190 } mmu_global_Type;
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192 /* Region shareability attributes */
bogdanm 92:4fc01daae5a5 193 typedef enum
bogdanm 92:4fc01daae5a5 194 {
bogdanm 92:4fc01daae5a5 195 NON_SHARED,
bogdanm 92:4fc01daae5a5 196 SHARED,
bogdanm 92:4fc01daae5a5 197 } mmu_shared_Type;
bogdanm 92:4fc01daae5a5 198
bogdanm 92:4fc01daae5a5 199 /* Region security attributes */
bogdanm 92:4fc01daae5a5 200 typedef enum
bogdanm 92:4fc01daae5a5 201 {
bogdanm 92:4fc01daae5a5 202 SECURE,
bogdanm 92:4fc01daae5a5 203 NON_SECURE,
bogdanm 92:4fc01daae5a5 204 } mmu_secure_Type;
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 /* Region access attributes */
bogdanm 92:4fc01daae5a5 207 typedef enum
bogdanm 92:4fc01daae5a5 208 {
bogdanm 92:4fc01daae5a5 209 NO_ACCESS,
bogdanm 92:4fc01daae5a5 210 RW,
bogdanm 92:4fc01daae5a5 211 READ,
bogdanm 92:4fc01daae5a5 212 } mmu_access_Type;
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 /* Memory Region definition */
bogdanm 92:4fc01daae5a5 215 typedef struct RegionStruct {
bogdanm 92:4fc01daae5a5 216 mmu_region_size_Type rg_t;
bogdanm 92:4fc01daae5a5 217 mmu_memory_Type mem_t;
bogdanm 92:4fc01daae5a5 218 uint8_t domain;
bogdanm 92:4fc01daae5a5 219 mmu_cacheability_Type inner_norm_t;
bogdanm 92:4fc01daae5a5 220 mmu_cacheability_Type outer_norm_t;
bogdanm 92:4fc01daae5a5 221 mmu_ecc_check_Type e_t;
bogdanm 92:4fc01daae5a5 222 mmu_execute_Type xn_t;
bogdanm 92:4fc01daae5a5 223 mmu_global_Type g_t;
bogdanm 92:4fc01daae5a5 224 mmu_secure_Type sec_t;
bogdanm 92:4fc01daae5a5 225 mmu_access_Type priv_t;
bogdanm 92:4fc01daae5a5 226 mmu_access_Type user_t;
bogdanm 92:4fc01daae5a5 227 mmu_shared_Type sh_t;
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 } mmu_region_attributes_Type;
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 /** \brief Set section execution-never attribute
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 The function sets section execution-never attribute
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 \return 0
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
bogdanm 92:4fc01daae5a5 241 {
bogdanm 92:4fc01daae5a5 242 *descriptor_l1 &= SECTION_XN_MASK;
bogdanm 92:4fc01daae5a5 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
bogdanm 92:4fc01daae5a5 244 return 0;
bogdanm 92:4fc01daae5a5 245 }
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 /** \brief Set section domain
bogdanm 92:4fc01daae5a5 248
bogdanm 92:4fc01daae5a5 249 The function sets section domain
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 252 \param [in] domain Section domain
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 \return 0
bogdanm 92:4fc01daae5a5 255 */
bogdanm 92:4fc01daae5a5 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
bogdanm 92:4fc01daae5a5 257 {
bogdanm 92:4fc01daae5a5 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
bogdanm 92:4fc01daae5a5 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
bogdanm 92:4fc01daae5a5 260 return 0;
bogdanm 92:4fc01daae5a5 261 }
bogdanm 92:4fc01daae5a5 262
bogdanm 92:4fc01daae5a5 263 /** \brief Set section parity check
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265 The function sets section parity check
bogdanm 92:4fc01daae5a5 266
bogdanm 92:4fc01daae5a5 267 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 \return 0
bogdanm 92:4fc01daae5a5 271 */
bogdanm 92:4fc01daae5a5 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
bogdanm 92:4fc01daae5a5 273 {
bogdanm 92:4fc01daae5a5 274 *descriptor_l1 &= SECTION_P_MASK;
bogdanm 92:4fc01daae5a5 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
bogdanm 92:4fc01daae5a5 276 return 0;
bogdanm 92:4fc01daae5a5 277 }
bogdanm 92:4fc01daae5a5 278
bogdanm 92:4fc01daae5a5 279 /** \brief Set section access privileges
bogdanm 92:4fc01daae5a5 280
bogdanm 92:4fc01daae5a5 281 The function sets section access privileges
bogdanm 92:4fc01daae5a5 282
bogdanm 92:4fc01daae5a5 283 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
bogdanm 92:4fc01daae5a5 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
bogdanm 92:4fc01daae5a5 286 \param [in] afe Access flag enable
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 \return 0
bogdanm 92:4fc01daae5a5 289 */
bogdanm 92:4fc01daae5a5 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
bogdanm 92:4fc01daae5a5 291 {
bogdanm 92:4fc01daae5a5 292 uint32_t ap = 0;
bogdanm 92:4fc01daae5a5 293
bogdanm 92:4fc01daae5a5 294 if (afe == 0) { //full access
bogdanm 92:4fc01daae5a5 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
bogdanm 92:4fc01daae5a5 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
bogdanm 92:4fc01daae5a5 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
bogdanm 92:4fc01daae5a5 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
bogdanm 92:4fc01daae5a5 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
Kojto 108:34e6b704fe68 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
bogdanm 92:4fc01daae5a5 301 }
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 else { //Simplified access
bogdanm 92:4fc01daae5a5 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
bogdanm 92:4fc01daae5a5 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
bogdanm 92:4fc01daae5a5 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
bogdanm 92:4fc01daae5a5 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
bogdanm 92:4fc01daae5a5 308 }
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 *descriptor_l1 &= SECTION_AP_MASK;
bogdanm 92:4fc01daae5a5 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
bogdanm 92:4fc01daae5a5 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
bogdanm 92:4fc01daae5a5 313
bogdanm 92:4fc01daae5a5 314 return 0;
bogdanm 92:4fc01daae5a5 315 }
bogdanm 92:4fc01daae5a5 316
bogdanm 92:4fc01daae5a5 317 /** \brief Set section shareability
bogdanm 92:4fc01daae5a5 318
bogdanm 92:4fc01daae5a5 319 The function sets section shareability
bogdanm 92:4fc01daae5a5 320
bogdanm 92:4fc01daae5a5 321 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 \return 0
bogdanm 92:4fc01daae5a5 325 */
bogdanm 92:4fc01daae5a5 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
bogdanm 92:4fc01daae5a5 327 {
bogdanm 92:4fc01daae5a5 328 *descriptor_l1 &= SECTION_S_MASK;
bogdanm 92:4fc01daae5a5 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
bogdanm 92:4fc01daae5a5 330 return 0;
bogdanm 92:4fc01daae5a5 331 }
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 /** \brief Set section Global attribute
bogdanm 92:4fc01daae5a5 334
bogdanm 92:4fc01daae5a5 335 The function sets section Global attribute
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 \return 0
bogdanm 92:4fc01daae5a5 341 */
bogdanm 92:4fc01daae5a5 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
bogdanm 92:4fc01daae5a5 343 {
bogdanm 92:4fc01daae5a5 344 *descriptor_l1 &= SECTION_NG_MASK;
bogdanm 92:4fc01daae5a5 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
bogdanm 92:4fc01daae5a5 346 return 0;
bogdanm 92:4fc01daae5a5 347 }
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 /** \brief Set section Security attribute
bogdanm 92:4fc01daae5a5 350
bogdanm 92:4fc01daae5a5 351 The function sets section Global attribute
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 \return 0
bogdanm 92:4fc01daae5a5 357 */
bogdanm 92:4fc01daae5a5 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
bogdanm 92:4fc01daae5a5 359 {
bogdanm 92:4fc01daae5a5 360 *descriptor_l1 &= SECTION_NS_MASK;
bogdanm 92:4fc01daae5a5 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
bogdanm 92:4fc01daae5a5 362 return 0;
bogdanm 92:4fc01daae5a5 363 }
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 /* Page 4k or 64k */
bogdanm 92:4fc01daae5a5 366 /** \brief Set 4k/64k page execution-never attribute
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 The function sets 4k/64k page execution-never attribute
bogdanm 92:4fc01daae5a5 369
bogdanm 92:4fc01daae5a5 370 \param [out] descriptor_l2 L2 descriptor.
bogdanm 92:4fc01daae5a5 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
bogdanm 92:4fc01daae5a5 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 \return 0
bogdanm 92:4fc01daae5a5 375 */
bogdanm 92:4fc01daae5a5 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
bogdanm 92:4fc01daae5a5 377 {
bogdanm 92:4fc01daae5a5 378 if (page == PAGE_4k)
bogdanm 92:4fc01daae5a5 379 {
bogdanm 92:4fc01daae5a5 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
bogdanm 92:4fc01daae5a5 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
bogdanm 92:4fc01daae5a5 382 }
bogdanm 92:4fc01daae5a5 383 else
bogdanm 92:4fc01daae5a5 384 {
bogdanm 92:4fc01daae5a5 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
bogdanm 92:4fc01daae5a5 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
bogdanm 92:4fc01daae5a5 387 }
bogdanm 92:4fc01daae5a5 388 return 0;
bogdanm 92:4fc01daae5a5 389 }
bogdanm 92:4fc01daae5a5 390
bogdanm 92:4fc01daae5a5 391 /** \brief Set 4k/64k page domain
bogdanm 92:4fc01daae5a5 392
bogdanm 92:4fc01daae5a5 393 The function sets 4k/64k page domain
bogdanm 92:4fc01daae5a5 394
bogdanm 92:4fc01daae5a5 395 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 396 \param [in] domain Page domain
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 \return 0
bogdanm 92:4fc01daae5a5 399 */
bogdanm 92:4fc01daae5a5 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
bogdanm 92:4fc01daae5a5 401 {
bogdanm 92:4fc01daae5a5 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
bogdanm 92:4fc01daae5a5 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
bogdanm 92:4fc01daae5a5 404 return 0;
bogdanm 92:4fc01daae5a5 405 }
bogdanm 92:4fc01daae5a5 406
bogdanm 92:4fc01daae5a5 407 /** \brief Set 4k/64k page parity check
bogdanm 92:4fc01daae5a5 408
bogdanm 92:4fc01daae5a5 409 The function sets 4k/64k page parity check
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
bogdanm 92:4fc01daae5a5 413
bogdanm 92:4fc01daae5a5 414 \return 0
bogdanm 92:4fc01daae5a5 415 */
bogdanm 92:4fc01daae5a5 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
bogdanm 92:4fc01daae5a5 417 {
bogdanm 92:4fc01daae5a5 418 *descriptor_l1 &= SECTION_P_MASK;
bogdanm 92:4fc01daae5a5 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
bogdanm 92:4fc01daae5a5 420 return 0;
bogdanm 92:4fc01daae5a5 421 }
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 /** \brief Set 4k/64k page access privileges
bogdanm 92:4fc01daae5a5 424
bogdanm 92:4fc01daae5a5 425 The function sets 4k/64k page access privileges
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 \param [out] descriptor_l2 L2 descriptor.
bogdanm 92:4fc01daae5a5 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
bogdanm 92:4fc01daae5a5 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
bogdanm 92:4fc01daae5a5 430 \param [in] afe Access flag enable
bogdanm 92:4fc01daae5a5 431
bogdanm 92:4fc01daae5a5 432 \return 0
bogdanm 92:4fc01daae5a5 433 */
bogdanm 92:4fc01daae5a5 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
bogdanm 92:4fc01daae5a5 435 {
bogdanm 92:4fc01daae5a5 436 uint32_t ap = 0;
bogdanm 92:4fc01daae5a5 437
bogdanm 92:4fc01daae5a5 438 if (afe == 0) { //full access
bogdanm 92:4fc01daae5a5 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
bogdanm 92:4fc01daae5a5 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
bogdanm 92:4fc01daae5a5 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
bogdanm 92:4fc01daae5a5 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
bogdanm 92:4fc01daae5a5 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
bogdanm 92:4fc01daae5a5 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
bogdanm 92:4fc01daae5a5 445 }
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 else { //Simplified access
bogdanm 92:4fc01daae5a5 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
bogdanm 92:4fc01daae5a5 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
bogdanm 92:4fc01daae5a5 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
bogdanm 92:4fc01daae5a5 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
bogdanm 92:4fc01daae5a5 452 }
bogdanm 92:4fc01daae5a5 453
bogdanm 92:4fc01daae5a5 454 *descriptor_l2 &= PAGE_AP_MASK;
bogdanm 92:4fc01daae5a5 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
bogdanm 92:4fc01daae5a5 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458 return 0;
bogdanm 92:4fc01daae5a5 459 }
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 /** \brief Set 4k/64k page shareability
bogdanm 92:4fc01daae5a5 462
bogdanm 92:4fc01daae5a5 463 The function sets 4k/64k page shareability
bogdanm 92:4fc01daae5a5 464
bogdanm 92:4fc01daae5a5 465 \param [out] descriptor_l2 L2 descriptor.
bogdanm 92:4fc01daae5a5 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
bogdanm 92:4fc01daae5a5 467
bogdanm 92:4fc01daae5a5 468 \return 0
bogdanm 92:4fc01daae5a5 469 */
bogdanm 92:4fc01daae5a5 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
bogdanm 92:4fc01daae5a5 471 {
bogdanm 92:4fc01daae5a5 472 *descriptor_l2 &= PAGE_S_MASK;
bogdanm 92:4fc01daae5a5 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
bogdanm 92:4fc01daae5a5 474 return 0;
bogdanm 92:4fc01daae5a5 475 }
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 /** \brief Set 4k/64k page Global attribute
bogdanm 92:4fc01daae5a5 478
bogdanm 92:4fc01daae5a5 479 The function sets 4k/64k page Global attribute
bogdanm 92:4fc01daae5a5 480
bogdanm 92:4fc01daae5a5 481 \param [out] descriptor_l2 L2 descriptor.
bogdanm 92:4fc01daae5a5 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
bogdanm 92:4fc01daae5a5 483
bogdanm 92:4fc01daae5a5 484 \return 0
bogdanm 92:4fc01daae5a5 485 */
bogdanm 92:4fc01daae5a5 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
bogdanm 92:4fc01daae5a5 487 {
bogdanm 92:4fc01daae5a5 488 *descriptor_l2 &= PAGE_NG_MASK;
bogdanm 92:4fc01daae5a5 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
bogdanm 92:4fc01daae5a5 490 return 0;
bogdanm 92:4fc01daae5a5 491 }
bogdanm 92:4fc01daae5a5 492
bogdanm 92:4fc01daae5a5 493 /** \brief Set 4k/64k page Security attribute
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 The function sets 4k/64k page Global attribute
bogdanm 92:4fc01daae5a5 496
bogdanm 92:4fc01daae5a5 497 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
bogdanm 92:4fc01daae5a5 499
bogdanm 92:4fc01daae5a5 500 \return 0
bogdanm 92:4fc01daae5a5 501 */
bogdanm 92:4fc01daae5a5 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
bogdanm 92:4fc01daae5a5 503 {
bogdanm 92:4fc01daae5a5 504 *descriptor_l1 &= PAGE_NS_MASK;
bogdanm 92:4fc01daae5a5 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
bogdanm 92:4fc01daae5a5 506 return 0;
bogdanm 92:4fc01daae5a5 507 }
bogdanm 92:4fc01daae5a5 508
bogdanm 92:4fc01daae5a5 509
bogdanm 92:4fc01daae5a5 510 /** \brief Set Section memory attributes
bogdanm 92:4fc01daae5a5 511
bogdanm 92:4fc01daae5a5 512 The function sets section memory attributes
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 \param [out] descriptor_l1 L1 descriptor.
bogdanm 92:4fc01daae5a5 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
bogdanm 92:4fc01daae5a5 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
bogdanm 92:4fc01daae5a5 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
bogdanm 92:4fc01daae5a5 518
bogdanm 92:4fc01daae5a5 519 \return 0
bogdanm 92:4fc01daae5a5 520 */
bogdanm 92:4fc01daae5a5 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
bogdanm 92:4fc01daae5a5 522 {
bogdanm 92:4fc01daae5a5 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
bogdanm 92:4fc01daae5a5 524
bogdanm 92:4fc01daae5a5 525 if (STRONGLY_ORDERED == mem)
bogdanm 92:4fc01daae5a5 526 {
bogdanm 92:4fc01daae5a5 527 return 0;
bogdanm 92:4fc01daae5a5 528 }
bogdanm 92:4fc01daae5a5 529 else if (SHARED_DEVICE == mem)
bogdanm 92:4fc01daae5a5 530 {
bogdanm 92:4fc01daae5a5 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
bogdanm 92:4fc01daae5a5 532 }
bogdanm 92:4fc01daae5a5 533 else if (NON_SHARED_DEVICE == mem)
bogdanm 92:4fc01daae5a5 534 {
bogdanm 92:4fc01daae5a5 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
bogdanm 92:4fc01daae5a5 536 }
bogdanm 92:4fc01daae5a5 537 else if (NORMAL == mem)
bogdanm 92:4fc01daae5a5 538 {
bogdanm 92:4fc01daae5a5 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
bogdanm 92:4fc01daae5a5 540 switch(inner)
bogdanm 92:4fc01daae5a5 541 {
bogdanm 92:4fc01daae5a5 542 case NON_CACHEABLE:
bogdanm 92:4fc01daae5a5 543 break;
bogdanm 92:4fc01daae5a5 544 case WB_WA:
bogdanm 92:4fc01daae5a5 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
bogdanm 92:4fc01daae5a5 546 break;
bogdanm 92:4fc01daae5a5 547 case WT:
bogdanm 92:4fc01daae5a5 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
bogdanm 92:4fc01daae5a5 549 break;
bogdanm 92:4fc01daae5a5 550 case WB_NO_WA:
bogdanm 92:4fc01daae5a5 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
bogdanm 92:4fc01daae5a5 552 break;
bogdanm 92:4fc01daae5a5 553 }
bogdanm 92:4fc01daae5a5 554 switch(outer)
bogdanm 92:4fc01daae5a5 555 {
bogdanm 92:4fc01daae5a5 556 case NON_CACHEABLE:
bogdanm 92:4fc01daae5a5 557 break;
bogdanm 92:4fc01daae5a5 558 case WB_WA:
bogdanm 92:4fc01daae5a5 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
bogdanm 92:4fc01daae5a5 560 break;
bogdanm 92:4fc01daae5a5 561 case WT:
bogdanm 92:4fc01daae5a5 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
bogdanm 92:4fc01daae5a5 563 break;
bogdanm 92:4fc01daae5a5 564 case WB_NO_WA:
bogdanm 92:4fc01daae5a5 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
bogdanm 92:4fc01daae5a5 566 break;
bogdanm 92:4fc01daae5a5 567 }
bogdanm 92:4fc01daae5a5 568 }
bogdanm 92:4fc01daae5a5 569
bogdanm 92:4fc01daae5a5 570 return 0;
bogdanm 92:4fc01daae5a5 571 }
bogdanm 92:4fc01daae5a5 572
bogdanm 92:4fc01daae5a5 573 /** \brief Set 4k/64k page memory attributes
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 The function sets 4k/64k page memory attributes
bogdanm 92:4fc01daae5a5 576
bogdanm 92:4fc01daae5a5 577 \param [out] descriptor_l2 L2 descriptor.
bogdanm 92:4fc01daae5a5 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
bogdanm 92:4fc01daae5a5 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
bogdanm 92:4fc01daae5a5 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
bogdanm 92:4fc01daae5a5 581
bogdanm 92:4fc01daae5a5 582 \return 0
bogdanm 92:4fc01daae5a5 583 */
bogdanm 92:4fc01daae5a5 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
bogdanm 92:4fc01daae5a5 585 {
bogdanm 92:4fc01daae5a5 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
bogdanm 92:4fc01daae5a5 587
bogdanm 92:4fc01daae5a5 588 if (page == PAGE_64k)
bogdanm 92:4fc01daae5a5 589 {
bogdanm 92:4fc01daae5a5 590 //same as section
bogdanm 92:4fc01daae5a5 591 __memory_section(descriptor_l2, mem, outer, inner);
bogdanm 92:4fc01daae5a5 592 }
bogdanm 92:4fc01daae5a5 593 else
bogdanm 92:4fc01daae5a5 594 {
bogdanm 92:4fc01daae5a5 595 if (STRONGLY_ORDERED == mem)
bogdanm 92:4fc01daae5a5 596 {
bogdanm 92:4fc01daae5a5 597 return 0;
bogdanm 92:4fc01daae5a5 598 }
bogdanm 92:4fc01daae5a5 599 else if (SHARED_DEVICE == mem)
bogdanm 92:4fc01daae5a5 600 {
bogdanm 92:4fc01daae5a5 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
bogdanm 92:4fc01daae5a5 602 }
bogdanm 92:4fc01daae5a5 603 else if (NON_SHARED_DEVICE == mem)
bogdanm 92:4fc01daae5a5 604 {
bogdanm 92:4fc01daae5a5 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
bogdanm 92:4fc01daae5a5 606 }
bogdanm 92:4fc01daae5a5 607 else if (NORMAL == mem)
bogdanm 92:4fc01daae5a5 608 {
bogdanm 92:4fc01daae5a5 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
bogdanm 92:4fc01daae5a5 610 switch(inner)
bogdanm 92:4fc01daae5a5 611 {
bogdanm 92:4fc01daae5a5 612 case NON_CACHEABLE:
bogdanm 92:4fc01daae5a5 613 break;
bogdanm 92:4fc01daae5a5 614 case WB_WA:
bogdanm 92:4fc01daae5a5 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
bogdanm 92:4fc01daae5a5 616 break;
bogdanm 92:4fc01daae5a5 617 case WT:
bogdanm 92:4fc01daae5a5 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
bogdanm 92:4fc01daae5a5 619 break;
bogdanm 92:4fc01daae5a5 620 case WB_NO_WA:
bogdanm 92:4fc01daae5a5 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
bogdanm 92:4fc01daae5a5 622 break;
bogdanm 92:4fc01daae5a5 623 }
bogdanm 92:4fc01daae5a5 624 switch(outer)
bogdanm 92:4fc01daae5a5 625 {
bogdanm 92:4fc01daae5a5 626 case NON_CACHEABLE:
bogdanm 92:4fc01daae5a5 627 break;
bogdanm 92:4fc01daae5a5 628 case WB_WA:
bogdanm 92:4fc01daae5a5 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
bogdanm 92:4fc01daae5a5 630 break;
bogdanm 92:4fc01daae5a5 631 case WT:
bogdanm 92:4fc01daae5a5 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
bogdanm 92:4fc01daae5a5 633 break;
bogdanm 92:4fc01daae5a5 634 case WB_NO_WA:
bogdanm 92:4fc01daae5a5 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
bogdanm 92:4fc01daae5a5 636 break;
bogdanm 92:4fc01daae5a5 637 }
bogdanm 92:4fc01daae5a5 638 }
bogdanm 92:4fc01daae5a5 639 }
bogdanm 92:4fc01daae5a5 640
bogdanm 92:4fc01daae5a5 641 return 0;
bogdanm 92:4fc01daae5a5 642 }
bogdanm 92:4fc01daae5a5 643
bogdanm 92:4fc01daae5a5 644 /** \brief Create a L1 section descriptor
bogdanm 92:4fc01daae5a5 645
bogdanm 92:4fc01daae5a5 646 The function creates a section descriptor.
bogdanm 92:4fc01daae5a5 647
bogdanm 92:4fc01daae5a5 648 Assumptions:
Kojto 108:34e6b704fe68 649 - 16MB super sections not supported
bogdanm 92:4fc01daae5a5 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
bogdanm 92:4fc01daae5a5 651 - Functions always return 0
bogdanm 92:4fc01daae5a5 652
bogdanm 92:4fc01daae5a5 653 \param [out] descriptor L1 descriptor
bogdanm 92:4fc01daae5a5 654 \param [out] descriptor2 L2 descriptor
bogdanm 92:4fc01daae5a5 655 \param [in] reg Section attributes
bogdanm 92:4fc01daae5a5 656
bogdanm 92:4fc01daae5a5 657 \return 0
bogdanm 92:4fc01daae5a5 658 */
bogdanm 92:4fc01daae5a5 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
bogdanm 92:4fc01daae5a5 660 {
bogdanm 92:4fc01daae5a5 661 *descriptor = 0;
bogdanm 92:4fc01daae5a5 662
bogdanm 92:4fc01daae5a5 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
bogdanm 92:4fc01daae5a5 664 __xn_section(descriptor,reg.xn_t);
bogdanm 92:4fc01daae5a5 665 __domain_section(descriptor, reg.domain);
bogdanm 92:4fc01daae5a5 666 __p_section(descriptor, reg.e_t);
bogdanm 92:4fc01daae5a5 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
bogdanm 92:4fc01daae5a5 668 __shared_section(descriptor,reg.sh_t);
bogdanm 92:4fc01daae5a5 669 __global_section(descriptor,reg.g_t);
bogdanm 92:4fc01daae5a5 670 __secure_section(descriptor,reg.sec_t);
bogdanm 92:4fc01daae5a5 671 *descriptor &= SECTION_MASK;
bogdanm 92:4fc01daae5a5 672 *descriptor |= SECTION_DESCRIPTOR;
bogdanm 92:4fc01daae5a5 673
bogdanm 92:4fc01daae5a5 674 return 0;
bogdanm 92:4fc01daae5a5 675
bogdanm 92:4fc01daae5a5 676 }
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678
bogdanm 92:4fc01daae5a5 679 /** \brief Create a L1 and L2 4k/64k page descriptor
bogdanm 92:4fc01daae5a5 680
bogdanm 92:4fc01daae5a5 681 The function creates a 4k/64k page descriptor.
bogdanm 92:4fc01daae5a5 682 Assumptions:
bogdanm 92:4fc01daae5a5 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
bogdanm 92:4fc01daae5a5 684 - Functions always return 0
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 \param [out] descriptor L1 descriptor
bogdanm 92:4fc01daae5a5 687 \param [out] descriptor2 L2 descriptor
bogdanm 92:4fc01daae5a5 688 \param [in] reg 4k/64k page attributes
bogdanm 92:4fc01daae5a5 689
bogdanm 92:4fc01daae5a5 690 \return 0
bogdanm 92:4fc01daae5a5 691 */
bogdanm 92:4fc01daae5a5 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
bogdanm 92:4fc01daae5a5 693 {
bogdanm 92:4fc01daae5a5 694 *descriptor = 0;
bogdanm 92:4fc01daae5a5 695 *descriptor2 = 0;
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 switch (reg.rg_t)
bogdanm 92:4fc01daae5a5 698 {
bogdanm 92:4fc01daae5a5 699 case PAGE_4k:
bogdanm 92:4fc01daae5a5 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
bogdanm 92:4fc01daae5a5 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
bogdanm 92:4fc01daae5a5 702 __domain_page(descriptor, reg.domain);
bogdanm 92:4fc01daae5a5 703 __p_page(descriptor, reg.e_t);
bogdanm 92:4fc01daae5a5 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
bogdanm 92:4fc01daae5a5 705 __shared_page(descriptor2,reg.sh_t);
bogdanm 92:4fc01daae5a5 706 __global_page(descriptor2,reg.g_t);
bogdanm 92:4fc01daae5a5 707 __secure_page(descriptor,reg.sec_t);
bogdanm 92:4fc01daae5a5 708 *descriptor &= PAGE_L1_MASK;
bogdanm 92:4fc01daae5a5 709 *descriptor |= PAGE_L1_DESCRIPTOR;
bogdanm 92:4fc01daae5a5 710 *descriptor2 &= PAGE_L2_4K_MASK;
bogdanm 92:4fc01daae5a5 711 *descriptor2 |= PAGE_L2_4K_DESC;
bogdanm 92:4fc01daae5a5 712 break;
bogdanm 92:4fc01daae5a5 713
bogdanm 92:4fc01daae5a5 714 case PAGE_64k:
bogdanm 92:4fc01daae5a5 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
bogdanm 92:4fc01daae5a5 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
bogdanm 92:4fc01daae5a5 717 __domain_page(descriptor, reg.domain);
bogdanm 92:4fc01daae5a5 718 __p_page(descriptor, reg.e_t);
bogdanm 92:4fc01daae5a5 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
bogdanm 92:4fc01daae5a5 720 __shared_page(descriptor2,reg.sh_t);
bogdanm 92:4fc01daae5a5 721 __global_page(descriptor2,reg.g_t);
bogdanm 92:4fc01daae5a5 722 __secure_page(descriptor,reg.sec_t);
bogdanm 92:4fc01daae5a5 723 *descriptor &= PAGE_L1_MASK;
bogdanm 92:4fc01daae5a5 724 *descriptor |= PAGE_L1_DESCRIPTOR;
bogdanm 92:4fc01daae5a5 725 *descriptor2 &= PAGE_L2_64K_MASK;
bogdanm 92:4fc01daae5a5 726 *descriptor2 |= PAGE_L2_64K_DESC;
bogdanm 92:4fc01daae5a5 727 break;
bogdanm 92:4fc01daae5a5 728
bogdanm 92:4fc01daae5a5 729 case SECTION:
bogdanm 92:4fc01daae5a5 730 //error
bogdanm 92:4fc01daae5a5 731 break;
bogdanm 92:4fc01daae5a5 732
bogdanm 92:4fc01daae5a5 733 }
bogdanm 92:4fc01daae5a5 734
bogdanm 92:4fc01daae5a5 735 return 0;
bogdanm 92:4fc01daae5a5 736
bogdanm 92:4fc01daae5a5 737 }
bogdanm 92:4fc01daae5a5 738
bogdanm 92:4fc01daae5a5 739 /** \brief Create a 1MB Section
bogdanm 92:4fc01daae5a5 740
bogdanm 92:4fc01daae5a5 741 \param [in] ttb Translation table base address
bogdanm 92:4fc01daae5a5 742 \param [in] base_address Section base address
bogdanm 92:4fc01daae5a5 743 \param [in] count Number of sections to create
bogdanm 92:4fc01daae5a5 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746 */
bogdanm 92:4fc01daae5a5 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
bogdanm 92:4fc01daae5a5 748 {
bogdanm 92:4fc01daae5a5 749 uint32_t offset;
bogdanm 92:4fc01daae5a5 750 uint32_t entry;
bogdanm 92:4fc01daae5a5 751 uint32_t i;
bogdanm 92:4fc01daae5a5 752
bogdanm 92:4fc01daae5a5 753 offset = base_address >> 20;
bogdanm 92:4fc01daae5a5 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
bogdanm 92:4fc01daae5a5 755
bogdanm 92:4fc01daae5a5 756 //4 bytes aligned
bogdanm 92:4fc01daae5a5 757 ttb = ttb + offset;
bogdanm 92:4fc01daae5a5 758
bogdanm 92:4fc01daae5a5 759 for (i = 0; i < count; i++ )
bogdanm 92:4fc01daae5a5 760 {
bogdanm 92:4fc01daae5a5 761 //4 bytes aligned
bogdanm 92:4fc01daae5a5 762 *ttb++ = entry;
bogdanm 92:4fc01daae5a5 763 entry += OFFSET_1M;
bogdanm 92:4fc01daae5a5 764 }
bogdanm 92:4fc01daae5a5 765 }
bogdanm 92:4fc01daae5a5 766
bogdanm 92:4fc01daae5a5 767 /** \brief Create a 4k page entry
bogdanm 92:4fc01daae5a5 768
bogdanm 92:4fc01daae5a5 769 \param [in] ttb L1 table base address
bogdanm 92:4fc01daae5a5 770 \param [in] base_address 4k base address
bogdanm 92:4fc01daae5a5 771 \param [in] count Number of 4k pages to create
bogdanm 92:4fc01daae5a5 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
bogdanm 92:4fc01daae5a5 773 \param [in] ttb_l2 L2 table base address
bogdanm 92:4fc01daae5a5 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
bogdanm 92:4fc01daae5a5 775
bogdanm 92:4fc01daae5a5 776 */
bogdanm 92:4fc01daae5a5 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
bogdanm 92:4fc01daae5a5 778 {
bogdanm 92:4fc01daae5a5 779
bogdanm 92:4fc01daae5a5 780 uint32_t offset, offset2;
bogdanm 92:4fc01daae5a5 781 uint32_t entry, entry2;
bogdanm 92:4fc01daae5a5 782 uint32_t i;
bogdanm 92:4fc01daae5a5 783
bogdanm 92:4fc01daae5a5 784
bogdanm 92:4fc01daae5a5 785 offset = base_address >> 20;
bogdanm 92:4fc01daae5a5 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
bogdanm 92:4fc01daae5a5 787
bogdanm 92:4fc01daae5a5 788 //4 bytes aligned
bogdanm 92:4fc01daae5a5 789 ttb += offset;
bogdanm 92:4fc01daae5a5 790 //create l1_entry
bogdanm 92:4fc01daae5a5 791 *ttb = entry;
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 offset2 = (base_address & 0xff000) >> 12;
bogdanm 92:4fc01daae5a5 794 ttb_l2 += offset2;
bogdanm 92:4fc01daae5a5 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
bogdanm 92:4fc01daae5a5 796 for (i = 0; i < count; i++ )
bogdanm 92:4fc01daae5a5 797 {
bogdanm 92:4fc01daae5a5 798 //4 bytes aligned
bogdanm 92:4fc01daae5a5 799 *ttb_l2++ = entry2;
bogdanm 92:4fc01daae5a5 800 entry2 += OFFSET_4K;
bogdanm 92:4fc01daae5a5 801 }
bogdanm 92:4fc01daae5a5 802 }
bogdanm 92:4fc01daae5a5 803
bogdanm 92:4fc01daae5a5 804 /** \brief Create a 64k page entry
bogdanm 92:4fc01daae5a5 805
bogdanm 92:4fc01daae5a5 806 \param [in] ttb L1 table base address
bogdanm 92:4fc01daae5a5 807 \param [in] base_address 64k base address
bogdanm 92:4fc01daae5a5 808 \param [in] count Number of 64k pages to create
bogdanm 92:4fc01daae5a5 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
bogdanm 92:4fc01daae5a5 810 \param [in] ttb_l2 L2 table base address
bogdanm 92:4fc01daae5a5 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
bogdanm 92:4fc01daae5a5 812
bogdanm 92:4fc01daae5a5 813 */
bogdanm 92:4fc01daae5a5 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
bogdanm 92:4fc01daae5a5 815 {
bogdanm 92:4fc01daae5a5 816 uint32_t offset, offset2;
bogdanm 92:4fc01daae5a5 817 uint32_t entry, entry2;
bogdanm 92:4fc01daae5a5 818 uint32_t i,j;
bogdanm 92:4fc01daae5a5 819
bogdanm 92:4fc01daae5a5 820
bogdanm 92:4fc01daae5a5 821 offset = base_address >> 20;
bogdanm 92:4fc01daae5a5 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
bogdanm 92:4fc01daae5a5 823
bogdanm 92:4fc01daae5a5 824 //4 bytes aligned
bogdanm 92:4fc01daae5a5 825 ttb += offset;
bogdanm 92:4fc01daae5a5 826 //create l1_entry
bogdanm 92:4fc01daae5a5 827 *ttb = entry;
bogdanm 92:4fc01daae5a5 828
bogdanm 92:4fc01daae5a5 829 offset2 = (base_address & 0xff000) >> 12;
bogdanm 92:4fc01daae5a5 830 ttb_l2 += offset2;
bogdanm 92:4fc01daae5a5 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
bogdanm 92:4fc01daae5a5 832 for (i = 0; i < count; i++ )
bogdanm 92:4fc01daae5a5 833 {
bogdanm 92:4fc01daae5a5 834 //create 16 entries
bogdanm 92:4fc01daae5a5 835 for (j = 0; j < 16; j++)
bogdanm 92:4fc01daae5a5 836 //4 bytes aligned
bogdanm 92:4fc01daae5a5 837 *ttb_l2++ = entry2;
bogdanm 92:4fc01daae5a5 838 entry2 += OFFSET_64K;
bogdanm 92:4fc01daae5a5 839 }
bogdanm 92:4fc01daae5a5 840 }
bogdanm 92:4fc01daae5a5 841
bogdanm 92:4fc01daae5a5 842 /*@} end of MMU_Functions */
bogdanm 92:4fc01daae5a5 843 #endif
bogdanm 92:4fc01daae5a5 844
bogdanm 92:4fc01daae5a5 845 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 846 }
bogdanm 92:4fc01daae5a5 847 #endif