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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_sc300.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_sc300.h
<> 140:97feb9bacc10 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
<> 140:97feb9bacc10 4 * @version V4.10
<> 140:97feb9bacc10 5 * @date 18. March 2015
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #if defined ( __ICCARM__ )
<> 140:97feb9bacc10 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 140:97feb9bacc10 40 #endif
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 #ifndef __CORE_SC300_H_GENERIC
<> 140:97feb9bacc10 43 #define __CORE_SC300_H_GENERIC
<> 140:97feb9bacc10 44
<> 140:97feb9bacc10 45 #ifdef __cplusplus
<> 140:97feb9bacc10 46 extern "C" {
<> 140:97feb9bacc10 47 #endif
<> 140:97feb9bacc10 48
<> 140:97feb9bacc10 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 140:97feb9bacc10 50 CMSIS violates the following MISRA-C:2004 rules:
<> 140:97feb9bacc10 51
<> 140:97feb9bacc10 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 140:97feb9bacc10 53 Function definitions in header files are used to allow 'inlining'.
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 140:97feb9bacc10 56 Unions are used for effective representation of core registers.
<> 140:97feb9bacc10 57
<> 140:97feb9bacc10 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 140:97feb9bacc10 59 Function-like macros are used to allow more efficient code.
<> 140:97feb9bacc10 60 */
<> 140:97feb9bacc10 61
<> 140:97feb9bacc10 62
<> 140:97feb9bacc10 63 /*******************************************************************************
<> 140:97feb9bacc10 64 * CMSIS definitions
<> 140:97feb9bacc10 65 ******************************************************************************/
<> 140:97feb9bacc10 66 /** \ingroup SC3000
<> 140:97feb9bacc10 67 @{
<> 140:97feb9bacc10 68 */
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70 /* CMSIS SC300 definitions */
<> 140:97feb9bacc10 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 140:97feb9bacc10 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 140:97feb9bacc10 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
<> 140:97feb9bacc10 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 140:97feb9bacc10 75
<> 140:97feb9bacc10 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
<> 140:97feb9bacc10 77
<> 140:97feb9bacc10 78
<> 140:97feb9bacc10 79 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 140:97feb9bacc10 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 140:97feb9bacc10 82 #define __STATIC_INLINE static __inline
<> 140:97feb9bacc10 83
<> 140:97feb9bacc10 84 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 140:97feb9bacc10 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 140:97feb9bacc10 87 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 88
<> 140:97feb9bacc10 89 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 140:97feb9bacc10 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 140:97feb9bacc10 92 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 93
<> 140:97feb9bacc10 94 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 140:97feb9bacc10 96 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 97
<> 140:97feb9bacc10 98 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 140:97feb9bacc10 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 140:97feb9bacc10 101 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 102
<> 140:97feb9bacc10 103 #elif defined ( __CSMC__ )
<> 140:97feb9bacc10 104 #define __packed
<> 140:97feb9bacc10 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 140:97feb9bacc10 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 140:97feb9bacc10 107 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 108
<> 140:97feb9bacc10 109 #endif
<> 140:97feb9bacc10 110
<> 140:97feb9bacc10 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 140:97feb9bacc10 112 This core does not support an FPU at all
<> 140:97feb9bacc10 113 */
<> 140:97feb9bacc10 114 #define __FPU_USED 0
<> 140:97feb9bacc10 115
<> 140:97feb9bacc10 116 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 117 #if defined __TARGET_FPU_VFP
<> 140:97feb9bacc10 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 119 #endif
<> 140:97feb9bacc10 120
<> 140:97feb9bacc10 121 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 140:97feb9bacc10 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 124 #endif
<> 140:97feb9bacc10 125
<> 140:97feb9bacc10 126 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 127 #if defined __ARMVFP__
<> 140:97feb9bacc10 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 129 #endif
<> 140:97feb9bacc10 130
<> 140:97feb9bacc10 131 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 132 #if defined __TI__VFP_SUPPORT____
<> 140:97feb9bacc10 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 134 #endif
<> 140:97feb9bacc10 135
<> 140:97feb9bacc10 136 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 137 #if defined __FPU_VFP__
<> 140:97feb9bacc10 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 139 #endif
<> 140:97feb9bacc10 140
<> 140:97feb9bacc10 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 140:97feb9bacc10 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 140:97feb9bacc10 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 144 #endif
<> 140:97feb9bacc10 145 #endif
<> 140:97feb9bacc10 146
<> 140:97feb9bacc10 147 #include <stdint.h> /* standard types definitions */
<> 140:97feb9bacc10 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 140:97feb9bacc10 149 #include <core_cmFunc.h> /* Core Function Access */
<> 140:97feb9bacc10 150
<> 140:97feb9bacc10 151 #ifdef __cplusplus
<> 140:97feb9bacc10 152 }
<> 140:97feb9bacc10 153 #endif
<> 140:97feb9bacc10 154
<> 140:97feb9bacc10 155 #endif /* __CORE_SC300_H_GENERIC */
<> 140:97feb9bacc10 156
<> 140:97feb9bacc10 157 #ifndef __CMSIS_GENERIC
<> 140:97feb9bacc10 158
<> 140:97feb9bacc10 159 #ifndef __CORE_SC300_H_DEPENDANT
<> 140:97feb9bacc10 160 #define __CORE_SC300_H_DEPENDANT
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 #ifdef __cplusplus
<> 140:97feb9bacc10 163 extern "C" {
<> 140:97feb9bacc10 164 #endif
<> 140:97feb9bacc10 165
<> 140:97feb9bacc10 166 /* check device defines and use defaults */
<> 140:97feb9bacc10 167 #if defined __CHECK_DEVICE_DEFINES
<> 140:97feb9bacc10 168 #ifndef __SC300_REV
<> 140:97feb9bacc10 169 #define __SC300_REV 0x0000
<> 140:97feb9bacc10 170 #warning "__SC300_REV not defined in device header file; using default!"
<> 140:97feb9bacc10 171 #endif
<> 140:97feb9bacc10 172
<> 140:97feb9bacc10 173 #ifndef __MPU_PRESENT
<> 140:97feb9bacc10 174 #define __MPU_PRESENT 0
<> 140:97feb9bacc10 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 176 #endif
<> 140:97feb9bacc10 177
<> 140:97feb9bacc10 178 #ifndef __NVIC_PRIO_BITS
<> 140:97feb9bacc10 179 #define __NVIC_PRIO_BITS 4
<> 140:97feb9bacc10 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 140:97feb9bacc10 181 #endif
<> 140:97feb9bacc10 182
<> 140:97feb9bacc10 183 #ifndef __Vendor_SysTickConfig
<> 140:97feb9bacc10 184 #define __Vendor_SysTickConfig 0
<> 140:97feb9bacc10 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 140:97feb9bacc10 186 #endif
<> 140:97feb9bacc10 187 #endif
<> 140:97feb9bacc10 188
<> 140:97feb9bacc10 189 /* IO definitions (access restrictions to peripheral registers) */
<> 140:97feb9bacc10 190 /**
<> 140:97feb9bacc10 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 140:97feb9bacc10 192
<> 140:97feb9bacc10 193 <strong>IO Type Qualifiers</strong> are used
<> 140:97feb9bacc10 194 \li to specify the access to peripheral variables.
<> 140:97feb9bacc10 195 \li for automatic generation of peripheral register debug information.
<> 140:97feb9bacc10 196 */
<> 140:97feb9bacc10 197 #ifdef __cplusplus
<> 140:97feb9bacc10 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 199 #else
<> 140:97feb9bacc10 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 201 #endif
<> 140:97feb9bacc10 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 140:97feb9bacc10 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 204
<> 140:97feb9bacc10 205 /*@} end of group SC300 */
<> 140:97feb9bacc10 206
<> 140:97feb9bacc10 207
<> 140:97feb9bacc10 208
<> 140:97feb9bacc10 209 /*******************************************************************************
<> 140:97feb9bacc10 210 * Register Abstraction
<> 140:97feb9bacc10 211 Core Register contain:
<> 140:97feb9bacc10 212 - Core Register
<> 140:97feb9bacc10 213 - Core NVIC Register
<> 140:97feb9bacc10 214 - Core SCB Register
<> 140:97feb9bacc10 215 - Core SysTick Register
<> 140:97feb9bacc10 216 - Core Debug Register
<> 140:97feb9bacc10 217 - Core MPU Register
<> 140:97feb9bacc10 218 ******************************************************************************/
<> 140:97feb9bacc10 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 140:97feb9bacc10 220 \brief Type definitions and defines for Cortex-M processor based devices.
<> 140:97feb9bacc10 221 */
<> 140:97feb9bacc10 222
<> 140:97feb9bacc10 223 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 224 \defgroup CMSIS_CORE Status and Control Registers
<> 140:97feb9bacc10 225 \brief Core Register type definitions.
<> 140:97feb9bacc10 226 @{
<> 140:97feb9bacc10 227 */
<> 140:97feb9bacc10 228
<> 140:97feb9bacc10 229 /** \brief Union type to access the Application Program Status Register (APSR).
<> 140:97feb9bacc10 230 */
<> 140:97feb9bacc10 231 typedef union
<> 140:97feb9bacc10 232 {
<> 140:97feb9bacc10 233 struct
<> 140:97feb9bacc10 234 {
<> 140:97feb9bacc10 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
<> 140:97feb9bacc10 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 140:97feb9bacc10 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 241 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 242 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 243 } APSR_Type;
<> 140:97feb9bacc10 244
<> 140:97feb9bacc10 245 /* APSR Register Definitions */
<> 140:97feb9bacc10 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 140:97feb9bacc10 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 140:97feb9bacc10 248
<> 140:97feb9bacc10 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 140:97feb9bacc10 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 140:97feb9bacc10 251
<> 140:97feb9bacc10 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 140:97feb9bacc10 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 140:97feb9bacc10 254
<> 140:97feb9bacc10 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 140:97feb9bacc10 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 140:97feb9bacc10 257
<> 140:97feb9bacc10 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
<> 140:97feb9bacc10 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 140:97feb9bacc10 260
<> 140:97feb9bacc10 261
<> 140:97feb9bacc10 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 140:97feb9bacc10 263 */
<> 140:97feb9bacc10 264 typedef union
<> 140:97feb9bacc10 265 {
<> 140:97feb9bacc10 266 struct
<> 140:97feb9bacc10 267 {
<> 140:97feb9bacc10 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 140:97feb9bacc10 270 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 271 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 272 } IPSR_Type;
<> 140:97feb9bacc10 273
<> 140:97feb9bacc10 274 /* IPSR Register Definitions */
<> 140:97feb9bacc10 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 140:97feb9bacc10 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 140:97feb9bacc10 277
<> 140:97feb9bacc10 278
<> 140:97feb9bacc10 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 140:97feb9bacc10 280 */
<> 140:97feb9bacc10 281 typedef union
<> 140:97feb9bacc10 282 {
<> 140:97feb9bacc10 283 struct
<> 140:97feb9bacc10 284 {
<> 140:97feb9bacc10 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 140:97feb9bacc10 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 140:97feb9bacc10 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
<> 140:97feb9bacc10 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 140:97feb9bacc10 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 294 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 295 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 296 } xPSR_Type;
<> 140:97feb9bacc10 297
<> 140:97feb9bacc10 298 /* xPSR Register Definitions */
<> 140:97feb9bacc10 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 140:97feb9bacc10 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 140:97feb9bacc10 301
<> 140:97feb9bacc10 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 140:97feb9bacc10 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 140:97feb9bacc10 304
<> 140:97feb9bacc10 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 140:97feb9bacc10 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 140:97feb9bacc10 307
<> 140:97feb9bacc10 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 140:97feb9bacc10 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 140:97feb9bacc10 310
<> 140:97feb9bacc10 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
<> 140:97feb9bacc10 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 140:97feb9bacc10 313
<> 140:97feb9bacc10 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
<> 140:97feb9bacc10 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
<> 140:97feb9bacc10 316
<> 140:97feb9bacc10 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 140:97feb9bacc10 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 140:97feb9bacc10 319
<> 140:97feb9bacc10 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 140:97feb9bacc10 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 140:97feb9bacc10 322
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324 /** \brief Union type to access the Control Registers (CONTROL).
<> 140:97feb9bacc10 325 */
<> 140:97feb9bacc10 326 typedef union
<> 140:97feb9bacc10 327 {
<> 140:97feb9bacc10 328 struct
<> 140:97feb9bacc10 329 {
<> 140:97feb9bacc10 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 140:97feb9bacc10 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 140:97feb9bacc10 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 140:97feb9bacc10 333 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 334 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 335 } CONTROL_Type;
<> 140:97feb9bacc10 336
<> 140:97feb9bacc10 337 /* CONTROL Register Definitions */
<> 140:97feb9bacc10 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 140:97feb9bacc10 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 140:97feb9bacc10 340
<> 140:97feb9bacc10 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 140:97feb9bacc10 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 140:97feb9bacc10 343
<> 140:97feb9bacc10 344 /*@} end of group CMSIS_CORE */
<> 140:97feb9bacc10 345
<> 140:97feb9bacc10 346
<> 140:97feb9bacc10 347 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 140:97feb9bacc10 349 \brief Type definitions for the NVIC Registers
<> 140:97feb9bacc10 350 @{
<> 140:97feb9bacc10 351 */
<> 140:97feb9bacc10 352
<> 140:97feb9bacc10 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 140:97feb9bacc10 354 */
<> 140:97feb9bacc10 355 typedef struct
<> 140:97feb9bacc10 356 {
<> 140:97feb9bacc10 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 140:97feb9bacc10 358 uint32_t RESERVED0[24];
<> 140:97feb9bacc10 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 140:97feb9bacc10 360 uint32_t RSERVED1[24];
<> 140:97feb9bacc10 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 140:97feb9bacc10 362 uint32_t RESERVED2[24];
<> 140:97feb9bacc10 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 140:97feb9bacc10 364 uint32_t RESERVED3[24];
<> 140:97feb9bacc10 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
<> 140:97feb9bacc10 366 uint32_t RESERVED4[56];
<> 140:97feb9bacc10 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
<> 140:97feb9bacc10 368 uint32_t RESERVED5[644];
<> 140:97feb9bacc10 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 140:97feb9bacc10 370 } NVIC_Type;
<> 140:97feb9bacc10 371
<> 140:97feb9bacc10 372 /* Software Triggered Interrupt Register Definitions */
<> 140:97feb9bacc10 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
<> 140:97feb9bacc10 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 140:97feb9bacc10 375
<> 140:97feb9bacc10 376 /*@} end of group CMSIS_NVIC */
<> 140:97feb9bacc10 377
<> 140:97feb9bacc10 378
<> 140:97feb9bacc10 379 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 380 \defgroup CMSIS_SCB System Control Block (SCB)
<> 140:97feb9bacc10 381 \brief Type definitions for the System Control Block Registers
<> 140:97feb9bacc10 382 @{
<> 140:97feb9bacc10 383 */
<> 140:97feb9bacc10 384
<> 140:97feb9bacc10 385 /** \brief Structure type to access the System Control Block (SCB).
<> 140:97feb9bacc10 386 */
<> 140:97feb9bacc10 387 typedef struct
<> 140:97feb9bacc10 388 {
<> 140:97feb9bacc10 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 140:97feb9bacc10 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 140:97feb9bacc10 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 140:97feb9bacc10 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 140:97feb9bacc10 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 140:97feb9bacc10 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 140:97feb9bacc10 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
<> 140:97feb9bacc10 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 140:97feb9bacc10 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
<> 140:97feb9bacc10 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
<> 140:97feb9bacc10 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
<> 140:97feb9bacc10 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
<> 140:97feb9bacc10 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
<> 140:97feb9bacc10 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
<> 140:97feb9bacc10 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
<> 140:97feb9bacc10 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
<> 140:97feb9bacc10 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
<> 140:97feb9bacc10 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
<> 140:97feb9bacc10 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
<> 140:97feb9bacc10 408 uint32_t RESERVED0[5];
<> 140:97feb9bacc10 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 140:97feb9bacc10 410 uint32_t RESERVED1[129];
<> 140:97feb9bacc10 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
<> 140:97feb9bacc10 412 } SCB_Type;
<> 140:97feb9bacc10 413
<> 140:97feb9bacc10 414 /* SCB CPUID Register Definitions */
<> 140:97feb9bacc10 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 140:97feb9bacc10 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 140:97feb9bacc10 417
<> 140:97feb9bacc10 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 140:97feb9bacc10 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 140:97feb9bacc10 420
<> 140:97feb9bacc10 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 140:97feb9bacc10 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 140:97feb9bacc10 423
<> 140:97feb9bacc10 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 140:97feb9bacc10 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 140:97feb9bacc10 426
<> 140:97feb9bacc10 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 140:97feb9bacc10 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 140:97feb9bacc10 429
<> 140:97feb9bacc10 430 /* SCB Interrupt Control State Register Definitions */
<> 140:97feb9bacc10 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 140:97feb9bacc10 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 140:97feb9bacc10 433
<> 140:97feb9bacc10 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 140:97feb9bacc10 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 140:97feb9bacc10 436
<> 140:97feb9bacc10 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 140:97feb9bacc10 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 140:97feb9bacc10 439
<> 140:97feb9bacc10 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 140:97feb9bacc10 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 140:97feb9bacc10 442
<> 140:97feb9bacc10 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 140:97feb9bacc10 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 140:97feb9bacc10 445
<> 140:97feb9bacc10 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 140:97feb9bacc10 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 140:97feb9bacc10 448
<> 140:97feb9bacc10 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 140:97feb9bacc10 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 140:97feb9bacc10 451
<> 140:97feb9bacc10 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 140:97feb9bacc10 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 140:97feb9bacc10 454
<> 140:97feb9bacc10 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
<> 140:97feb9bacc10 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 140:97feb9bacc10 457
<> 140:97feb9bacc10 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 140:97feb9bacc10 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 140:97feb9bacc10 460
<> 140:97feb9bacc10 461 /* SCB Vector Table Offset Register Definitions */
<> 140:97feb9bacc10 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
<> 140:97feb9bacc10 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
<> 140:97feb9bacc10 464
<> 140:97feb9bacc10 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 140:97feb9bacc10 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 140:97feb9bacc10 467
<> 140:97feb9bacc10 468 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 140:97feb9bacc10 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 140:97feb9bacc10 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 140:97feb9bacc10 471
<> 140:97feb9bacc10 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 140:97feb9bacc10 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 140:97feb9bacc10 474
<> 140:97feb9bacc10 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 140:97feb9bacc10 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 140:97feb9bacc10 477
<> 140:97feb9bacc10 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
<> 140:97feb9bacc10 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 140:97feb9bacc10 480
<> 140:97feb9bacc10 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 140:97feb9bacc10 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 140:97feb9bacc10 483
<> 140:97feb9bacc10 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 140:97feb9bacc10 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 140:97feb9bacc10 486
<> 140:97feb9bacc10 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
<> 140:97feb9bacc10 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 140:97feb9bacc10 489
<> 140:97feb9bacc10 490 /* SCB System Control Register Definitions */
<> 140:97feb9bacc10 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 140:97feb9bacc10 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 140:97feb9bacc10 493
<> 140:97feb9bacc10 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 140:97feb9bacc10 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 140:97feb9bacc10 496
<> 140:97feb9bacc10 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 140:97feb9bacc10 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 140:97feb9bacc10 499
<> 140:97feb9bacc10 500 /* SCB Configuration Control Register Definitions */
<> 140:97feb9bacc10 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 140:97feb9bacc10 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 140:97feb9bacc10 503
<> 140:97feb9bacc10 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
<> 140:97feb9bacc10 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 140:97feb9bacc10 506
<> 140:97feb9bacc10 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
<> 140:97feb9bacc10 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 140:97feb9bacc10 509
<> 140:97feb9bacc10 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 140:97feb9bacc10 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 140:97feb9bacc10 512
<> 140:97feb9bacc10 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
<> 140:97feb9bacc10 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 140:97feb9bacc10 515
<> 140:97feb9bacc10 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
<> 140:97feb9bacc10 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 140:97feb9bacc10 518
<> 140:97feb9bacc10 519 /* SCB System Handler Control and State Register Definitions */
<> 140:97feb9bacc10 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
<> 140:97feb9bacc10 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 140:97feb9bacc10 522
<> 140:97feb9bacc10 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
<> 140:97feb9bacc10 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 140:97feb9bacc10 525
<> 140:97feb9bacc10 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
<> 140:97feb9bacc10 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 140:97feb9bacc10 528
<> 140:97feb9bacc10 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 140:97feb9bacc10 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 140:97feb9bacc10 531
<> 140:97feb9bacc10 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 140:97feb9bacc10 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 140:97feb9bacc10 534
<> 140:97feb9bacc10 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 140:97feb9bacc10 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 140:97feb9bacc10 537
<> 140:97feb9bacc10 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 140:97feb9bacc10 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 140:97feb9bacc10 540
<> 140:97feb9bacc10 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
<> 140:97feb9bacc10 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 140:97feb9bacc10 543
<> 140:97feb9bacc10 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
<> 140:97feb9bacc10 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 140:97feb9bacc10 546
<> 140:97feb9bacc10 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
<> 140:97feb9bacc10 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 140:97feb9bacc10 549
<> 140:97feb9bacc10 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
<> 140:97feb9bacc10 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 140:97feb9bacc10 552
<> 140:97feb9bacc10 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
<> 140:97feb9bacc10 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 140:97feb9bacc10 555
<> 140:97feb9bacc10 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
<> 140:97feb9bacc10 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 140:97feb9bacc10 558
<> 140:97feb9bacc10 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
<> 140:97feb9bacc10 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 140:97feb9bacc10 561
<> 140:97feb9bacc10 562 /* SCB Configurable Fault Status Registers Definitions */
<> 140:97feb9bacc10 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
<> 140:97feb9bacc10 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 140:97feb9bacc10 565
<> 140:97feb9bacc10 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
<> 140:97feb9bacc10 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 140:97feb9bacc10 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 140:97feb9bacc10 571
<> 140:97feb9bacc10 572 /* SCB Hard Fault Status Registers Definitions */
<> 140:97feb9bacc10 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
<> 140:97feb9bacc10 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 140:97feb9bacc10 575
<> 140:97feb9bacc10 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
<> 140:97feb9bacc10 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 140:97feb9bacc10 578
<> 140:97feb9bacc10 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
<> 140:97feb9bacc10 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 140:97feb9bacc10 581
<> 140:97feb9bacc10 582 /* SCB Debug Fault Status Register Definitions */
<> 140:97feb9bacc10 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
<> 140:97feb9bacc10 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 140:97feb9bacc10 585
<> 140:97feb9bacc10 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
<> 140:97feb9bacc10 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 140:97feb9bacc10 588
<> 140:97feb9bacc10 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
<> 140:97feb9bacc10 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 140:97feb9bacc10 591
<> 140:97feb9bacc10 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
<> 140:97feb9bacc10 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 140:97feb9bacc10 594
<> 140:97feb9bacc10 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
<> 140:97feb9bacc10 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 140:97feb9bacc10 597
<> 140:97feb9bacc10 598 /*@} end of group CMSIS_SCB */
<> 140:97feb9bacc10 599
<> 140:97feb9bacc10 600
<> 140:97feb9bacc10 601 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 140:97feb9bacc10 603 \brief Type definitions for the System Control and ID Register not in the SCB
<> 140:97feb9bacc10 604 @{
<> 140:97feb9bacc10 605 */
<> 140:97feb9bacc10 606
<> 140:97feb9bacc10 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 140:97feb9bacc10 608 */
<> 140:97feb9bacc10 609 typedef struct
<> 140:97feb9bacc10 610 {
<> 140:97feb9bacc10 611 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
<> 140:97feb9bacc10 613 uint32_t RESERVED1[1];
<> 140:97feb9bacc10 614 } SCnSCB_Type;
<> 140:97feb9bacc10 615
<> 140:97feb9bacc10 616 /* Interrupt Controller Type Register Definitions */
<> 140:97feb9bacc10 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
<> 140:97feb9bacc10 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 140:97feb9bacc10 619
<> 140:97feb9bacc10 620 /*@} end of group CMSIS_SCnotSCB */
<> 140:97feb9bacc10 621
<> 140:97feb9bacc10 622
<> 140:97feb9bacc10 623 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 140:97feb9bacc10 625 \brief Type definitions for the System Timer Registers.
<> 140:97feb9bacc10 626 @{
<> 140:97feb9bacc10 627 */
<> 140:97feb9bacc10 628
<> 140:97feb9bacc10 629 /** \brief Structure type to access the System Timer (SysTick).
<> 140:97feb9bacc10 630 */
<> 140:97feb9bacc10 631 typedef struct
<> 140:97feb9bacc10 632 {
<> 140:97feb9bacc10 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 140:97feb9bacc10 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 140:97feb9bacc10 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 140:97feb9bacc10 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 140:97feb9bacc10 637 } SysTick_Type;
<> 140:97feb9bacc10 638
<> 140:97feb9bacc10 639 /* SysTick Control / Status Register Definitions */
<> 140:97feb9bacc10 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 140:97feb9bacc10 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 140:97feb9bacc10 642
<> 140:97feb9bacc10 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 140:97feb9bacc10 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 140:97feb9bacc10 645
<> 140:97feb9bacc10 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 140:97feb9bacc10 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 140:97feb9bacc10 648
<> 140:97feb9bacc10 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 140:97feb9bacc10 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 140:97feb9bacc10 651
<> 140:97feb9bacc10 652 /* SysTick Reload Register Definitions */
<> 140:97feb9bacc10 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 140:97feb9bacc10 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 140:97feb9bacc10 655
<> 140:97feb9bacc10 656 /* SysTick Current Register Definitions */
<> 140:97feb9bacc10 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 140:97feb9bacc10 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 140:97feb9bacc10 659
<> 140:97feb9bacc10 660 /* SysTick Calibration Register Definitions */
<> 140:97feb9bacc10 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 140:97feb9bacc10 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 140:97feb9bacc10 663
<> 140:97feb9bacc10 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 140:97feb9bacc10 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 140:97feb9bacc10 666
<> 140:97feb9bacc10 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 140:97feb9bacc10 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 140:97feb9bacc10 669
<> 140:97feb9bacc10 670 /*@} end of group CMSIS_SysTick */
<> 140:97feb9bacc10 671
<> 140:97feb9bacc10 672
<> 140:97feb9bacc10 673 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<> 140:97feb9bacc10 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 140:97feb9bacc10 676 @{
<> 140:97feb9bacc10 677 */
<> 140:97feb9bacc10 678
<> 140:97feb9bacc10 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 140:97feb9bacc10 680 */
<> 140:97feb9bacc10 681 typedef struct
<> 140:97feb9bacc10 682 {
<> 140:97feb9bacc10 683 __O union
<> 140:97feb9bacc10 684 {
<> 140:97feb9bacc10 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
<> 140:97feb9bacc10 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
<> 140:97feb9bacc10 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
<> 140:97feb9bacc10 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
<> 140:97feb9bacc10 689 uint32_t RESERVED0[864];
<> 140:97feb9bacc10 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
<> 140:97feb9bacc10 691 uint32_t RESERVED1[15];
<> 140:97feb9bacc10 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
<> 140:97feb9bacc10 693 uint32_t RESERVED2[15];
<> 140:97feb9bacc10 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
<> 140:97feb9bacc10 695 uint32_t RESERVED3[29];
<> 140:97feb9bacc10 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
<> 140:97feb9bacc10 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
<> 140:97feb9bacc10 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
<> 140:97feb9bacc10 699 uint32_t RESERVED4[43];
<> 140:97feb9bacc10 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
<> 140:97feb9bacc10 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
<> 140:97feb9bacc10 702 uint32_t RESERVED5[6];
<> 140:97feb9bacc10 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
<> 140:97feb9bacc10 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
<> 140:97feb9bacc10 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
<> 140:97feb9bacc10 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
<> 140:97feb9bacc10 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
<> 140:97feb9bacc10 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
<> 140:97feb9bacc10 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
<> 140:97feb9bacc10 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
<> 140:97feb9bacc10 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
<> 140:97feb9bacc10 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
<> 140:97feb9bacc10 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
<> 140:97feb9bacc10 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 140:97feb9bacc10 715 } ITM_Type;
<> 140:97feb9bacc10 716
<> 140:97feb9bacc10 717 /* ITM Trace Privilege Register Definitions */
<> 140:97feb9bacc10 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
<> 140:97feb9bacc10 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 140:97feb9bacc10 720
<> 140:97feb9bacc10 721 /* ITM Trace Control Register Definitions */
<> 140:97feb9bacc10 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
<> 140:97feb9bacc10 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 140:97feb9bacc10 724
<> 140:97feb9bacc10 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
<> 140:97feb9bacc10 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 140:97feb9bacc10 727
<> 140:97feb9bacc10 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
<> 140:97feb9bacc10 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 140:97feb9bacc10 730
<> 140:97feb9bacc10 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
<> 140:97feb9bacc10 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 140:97feb9bacc10 733
<> 140:97feb9bacc10 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
<> 140:97feb9bacc10 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 140:97feb9bacc10 736
<> 140:97feb9bacc10 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
<> 140:97feb9bacc10 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 140:97feb9bacc10 739
<> 140:97feb9bacc10 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
<> 140:97feb9bacc10 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 140:97feb9bacc10 742
<> 140:97feb9bacc10 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
<> 140:97feb9bacc10 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 140:97feb9bacc10 745
<> 140:97feb9bacc10 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
<> 140:97feb9bacc10 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 140:97feb9bacc10 748
<> 140:97feb9bacc10 749 /* ITM Integration Write Register Definitions */
<> 140:97feb9bacc10 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
<> 140:97feb9bacc10 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 140:97feb9bacc10 752
<> 140:97feb9bacc10 753 /* ITM Integration Read Register Definitions */
<> 140:97feb9bacc10 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
<> 140:97feb9bacc10 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 140:97feb9bacc10 756
<> 140:97feb9bacc10 757 /* ITM Integration Mode Control Register Definitions */
<> 140:97feb9bacc10 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
<> 140:97feb9bacc10 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 140:97feb9bacc10 760
<> 140:97feb9bacc10 761 /* ITM Lock Status Register Definitions */
<> 140:97feb9bacc10 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
<> 140:97feb9bacc10 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 140:97feb9bacc10 764
<> 140:97feb9bacc10 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
<> 140:97feb9bacc10 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 140:97feb9bacc10 767
<> 140:97feb9bacc10 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
<> 140:97feb9bacc10 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 140:97feb9bacc10 770
<> 140:97feb9bacc10 771 /*@}*/ /* end of group CMSIS_ITM */
<> 140:97feb9bacc10 772
<> 140:97feb9bacc10 773
<> 140:97feb9bacc10 774 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<> 140:97feb9bacc10 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 140:97feb9bacc10 777 @{
<> 140:97feb9bacc10 778 */
<> 140:97feb9bacc10 779
<> 140:97feb9bacc10 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 140:97feb9bacc10 781 */
<> 140:97feb9bacc10 782 typedef struct
<> 140:97feb9bacc10 783 {
<> 140:97feb9bacc10 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
<> 140:97feb9bacc10 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
<> 140:97feb9bacc10 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
<> 140:97feb9bacc10 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
<> 140:97feb9bacc10 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
<> 140:97feb9bacc10 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
<> 140:97feb9bacc10 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
<> 140:97feb9bacc10 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
<> 140:97feb9bacc10 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
<> 140:97feb9bacc10 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
<> 140:97feb9bacc10 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
<> 140:97feb9bacc10 795 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
<> 140:97feb9bacc10 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
<> 140:97feb9bacc10 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
<> 140:97feb9bacc10 799 uint32_t RESERVED1[1];
<> 140:97feb9bacc10 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
<> 140:97feb9bacc10 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
<> 140:97feb9bacc10 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
<> 140:97feb9bacc10 803 uint32_t RESERVED2[1];
<> 140:97feb9bacc10 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
<> 140:97feb9bacc10 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
<> 140:97feb9bacc10 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 140:97feb9bacc10 807 } DWT_Type;
<> 140:97feb9bacc10 808
<> 140:97feb9bacc10 809 /* DWT Control Register Definitions */
<> 140:97feb9bacc10 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
<> 140:97feb9bacc10 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 140:97feb9bacc10 812
<> 140:97feb9bacc10 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
<> 140:97feb9bacc10 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 140:97feb9bacc10 815
<> 140:97feb9bacc10 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
<> 140:97feb9bacc10 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 140:97feb9bacc10 818
<> 140:97feb9bacc10 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
<> 140:97feb9bacc10 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 140:97feb9bacc10 821
<> 140:97feb9bacc10 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
<> 140:97feb9bacc10 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 140:97feb9bacc10 824
<> 140:97feb9bacc10 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
<> 140:97feb9bacc10 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 140:97feb9bacc10 827
<> 140:97feb9bacc10 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
<> 140:97feb9bacc10 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 140:97feb9bacc10 830
<> 140:97feb9bacc10 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
<> 140:97feb9bacc10 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 140:97feb9bacc10 833
<> 140:97feb9bacc10 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
<> 140:97feb9bacc10 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 140:97feb9bacc10 836
<> 140:97feb9bacc10 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
<> 140:97feb9bacc10 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 140:97feb9bacc10 839
<> 140:97feb9bacc10 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
<> 140:97feb9bacc10 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 140:97feb9bacc10 842
<> 140:97feb9bacc10 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
<> 140:97feb9bacc10 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 140:97feb9bacc10 845
<> 140:97feb9bacc10 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
<> 140:97feb9bacc10 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 140:97feb9bacc10 848
<> 140:97feb9bacc10 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
<> 140:97feb9bacc10 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 140:97feb9bacc10 851
<> 140:97feb9bacc10 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
<> 140:97feb9bacc10 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 140:97feb9bacc10 854
<> 140:97feb9bacc10 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
<> 140:97feb9bacc10 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 140:97feb9bacc10 857
<> 140:97feb9bacc10 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
<> 140:97feb9bacc10 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 140:97feb9bacc10 860
<> 140:97feb9bacc10 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
<> 140:97feb9bacc10 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 140:97feb9bacc10 863
<> 140:97feb9bacc10 864 /* DWT CPI Count Register Definitions */
<> 140:97feb9bacc10 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
<> 140:97feb9bacc10 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 140:97feb9bacc10 867
<> 140:97feb9bacc10 868 /* DWT Exception Overhead Count Register Definitions */
<> 140:97feb9bacc10 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
<> 140:97feb9bacc10 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 140:97feb9bacc10 871
<> 140:97feb9bacc10 872 /* DWT Sleep Count Register Definitions */
<> 140:97feb9bacc10 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 140:97feb9bacc10 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 140:97feb9bacc10 875
<> 140:97feb9bacc10 876 /* DWT LSU Count Register Definitions */
<> 140:97feb9bacc10 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
<> 140:97feb9bacc10 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 140:97feb9bacc10 879
<> 140:97feb9bacc10 880 /* DWT Folded-instruction Count Register Definitions */
<> 140:97feb9bacc10 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
<> 140:97feb9bacc10 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 140:97feb9bacc10 883
<> 140:97feb9bacc10 884 /* DWT Comparator Mask Register Definitions */
<> 140:97feb9bacc10 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
<> 140:97feb9bacc10 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 140:97feb9bacc10 887
<> 140:97feb9bacc10 888 /* DWT Comparator Function Register Definitions */
<> 140:97feb9bacc10 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
<> 140:97feb9bacc10 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 140:97feb9bacc10 891
<> 140:97feb9bacc10 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 140:97feb9bacc10 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 140:97feb9bacc10 894
<> 140:97feb9bacc10 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 140:97feb9bacc10 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 140:97feb9bacc10 897
<> 140:97feb9bacc10 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
<> 140:97feb9bacc10 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 140:97feb9bacc10 900
<> 140:97feb9bacc10 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
<> 140:97feb9bacc10 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 140:97feb9bacc10 903
<> 140:97feb9bacc10 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
<> 140:97feb9bacc10 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 140:97feb9bacc10 906
<> 140:97feb9bacc10 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
<> 140:97feb9bacc10 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 140:97feb9bacc10 909
<> 140:97feb9bacc10 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
<> 140:97feb9bacc10 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 140:97feb9bacc10 912
<> 140:97feb9bacc10 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
<> 140:97feb9bacc10 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 140:97feb9bacc10 915
<> 140:97feb9bacc10 916 /*@}*/ /* end of group CMSIS_DWT */
<> 140:97feb9bacc10 917
<> 140:97feb9bacc10 918
<> 140:97feb9bacc10 919 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
<> 140:97feb9bacc10 921 \brief Type definitions for the Trace Port Interface (TPI)
<> 140:97feb9bacc10 922 @{
<> 140:97feb9bacc10 923 */
<> 140:97feb9bacc10 924
<> 140:97feb9bacc10 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
<> 140:97feb9bacc10 926 */
<> 140:97feb9bacc10 927 typedef struct
<> 140:97feb9bacc10 928 {
<> 140:97feb9bacc10 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
<> 140:97feb9bacc10 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
<> 140:97feb9bacc10 931 uint32_t RESERVED0[2];
<> 140:97feb9bacc10 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
<> 140:97feb9bacc10 933 uint32_t RESERVED1[55];
<> 140:97feb9bacc10 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
<> 140:97feb9bacc10 935 uint32_t RESERVED2[131];
<> 140:97feb9bacc10 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
<> 140:97feb9bacc10 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
<> 140:97feb9bacc10 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
<> 140:97feb9bacc10 939 uint32_t RESERVED3[759];
<> 140:97feb9bacc10 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
<> 140:97feb9bacc10 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
<> 140:97feb9bacc10 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
<> 140:97feb9bacc10 943 uint32_t RESERVED4[1];
<> 140:97feb9bacc10 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
<> 140:97feb9bacc10 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
<> 140:97feb9bacc10 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
<> 140:97feb9bacc10 947 uint32_t RESERVED5[39];
<> 140:97feb9bacc10 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
<> 140:97feb9bacc10 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
<> 140:97feb9bacc10 950 uint32_t RESERVED7[8];
<> 140:97feb9bacc10 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
<> 140:97feb9bacc10 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 140:97feb9bacc10 953 } TPI_Type;
<> 140:97feb9bacc10 954
<> 140:97feb9bacc10 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
<> 140:97feb9bacc10 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
<> 140:97feb9bacc10 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 140:97feb9bacc10 958
<> 140:97feb9bacc10 959 /* TPI Selected Pin Protocol Register Definitions */
<> 140:97feb9bacc10 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
<> 140:97feb9bacc10 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 140:97feb9bacc10 962
<> 140:97feb9bacc10 963 /* TPI Formatter and Flush Status Register Definitions */
<> 140:97feb9bacc10 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
<> 140:97feb9bacc10 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 140:97feb9bacc10 966
<> 140:97feb9bacc10 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
<> 140:97feb9bacc10 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 140:97feb9bacc10 969
<> 140:97feb9bacc10 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
<> 140:97feb9bacc10 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 140:97feb9bacc10 972
<> 140:97feb9bacc10 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
<> 140:97feb9bacc10 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 140:97feb9bacc10 975
<> 140:97feb9bacc10 976 /* TPI Formatter and Flush Control Register Definitions */
<> 140:97feb9bacc10 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
<> 140:97feb9bacc10 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 140:97feb9bacc10 979
<> 140:97feb9bacc10 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
<> 140:97feb9bacc10 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 140:97feb9bacc10 982
<> 140:97feb9bacc10 983 /* TPI TRIGGER Register Definitions */
<> 140:97feb9bacc10 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
<> 140:97feb9bacc10 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 140:97feb9bacc10 986
<> 140:97feb9bacc10 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
<> 140:97feb9bacc10 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
<> 140:97feb9bacc10 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 140:97feb9bacc10 990
<> 140:97feb9bacc10 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
<> 140:97feb9bacc10 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 140:97feb9bacc10 993
<> 140:97feb9bacc10 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
<> 140:97feb9bacc10 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 140:97feb9bacc10 996
<> 140:97feb9bacc10 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
<> 140:97feb9bacc10 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 140:97feb9bacc10 999
<> 140:97feb9bacc10 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
<> 140:97feb9bacc10 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 140:97feb9bacc10 1002
<> 140:97feb9bacc10 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
<> 140:97feb9bacc10 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 140:97feb9bacc10 1005
<> 140:97feb9bacc10 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
<> 140:97feb9bacc10 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 140:97feb9bacc10 1008
<> 140:97feb9bacc10 1009 /* TPI ITATBCTR2 Register Definitions */
<> 140:97feb9bacc10 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
<> 140:97feb9bacc10 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 140:97feb9bacc10 1012
<> 140:97feb9bacc10 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
<> 140:97feb9bacc10 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
<> 140:97feb9bacc10 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 140:97feb9bacc10 1016
<> 140:97feb9bacc10 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
<> 140:97feb9bacc10 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 140:97feb9bacc10 1019
<> 140:97feb9bacc10 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
<> 140:97feb9bacc10 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 140:97feb9bacc10 1022
<> 140:97feb9bacc10 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
<> 140:97feb9bacc10 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 140:97feb9bacc10 1025
<> 140:97feb9bacc10 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
<> 140:97feb9bacc10 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 140:97feb9bacc10 1028
<> 140:97feb9bacc10 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
<> 140:97feb9bacc10 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 140:97feb9bacc10 1031
<> 140:97feb9bacc10 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
<> 140:97feb9bacc10 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 140:97feb9bacc10 1034
<> 140:97feb9bacc10 1035 /* TPI ITATBCTR0 Register Definitions */
<> 140:97feb9bacc10 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
<> 140:97feb9bacc10 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 140:97feb9bacc10 1038
<> 140:97feb9bacc10 1039 /* TPI Integration Mode Control Register Definitions */
<> 140:97feb9bacc10 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
<> 140:97feb9bacc10 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 140:97feb9bacc10 1042
<> 140:97feb9bacc10 1043 /* TPI DEVID Register Definitions */
<> 140:97feb9bacc10 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
<> 140:97feb9bacc10 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 140:97feb9bacc10 1046
<> 140:97feb9bacc10 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
<> 140:97feb9bacc10 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 140:97feb9bacc10 1049
<> 140:97feb9bacc10 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
<> 140:97feb9bacc10 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 140:97feb9bacc10 1052
<> 140:97feb9bacc10 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
<> 140:97feb9bacc10 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 140:97feb9bacc10 1055
<> 140:97feb9bacc10 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
<> 140:97feb9bacc10 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 140:97feb9bacc10 1058
<> 140:97feb9bacc10 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
<> 140:97feb9bacc10 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 140:97feb9bacc10 1061
<> 140:97feb9bacc10 1062 /* TPI DEVTYPE Register Definitions */
<> 140:97feb9bacc10 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
<> 140:97feb9bacc10 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 140:97feb9bacc10 1065
<> 140:97feb9bacc10 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
<> 140:97feb9bacc10 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 140:97feb9bacc10 1068
<> 140:97feb9bacc10 1069 /*@}*/ /* end of group CMSIS_TPI */
<> 140:97feb9bacc10 1070
<> 140:97feb9bacc10 1071
<> 140:97feb9bacc10 1072 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 1073 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 140:97feb9bacc10 1075 \brief Type definitions for the Memory Protection Unit (MPU)
<> 140:97feb9bacc10 1076 @{
<> 140:97feb9bacc10 1077 */
<> 140:97feb9bacc10 1078
<> 140:97feb9bacc10 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 140:97feb9bacc10 1080 */
<> 140:97feb9bacc10 1081 typedef struct
<> 140:97feb9bacc10 1082 {
<> 140:97feb9bacc10 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 140:97feb9bacc10 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 140:97feb9bacc10 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 140:97feb9bacc10 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 140:97feb9bacc10 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
<> 140:97feb9bacc10 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
<> 140:97feb9bacc10 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
<> 140:97feb9bacc10 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
<> 140:97feb9bacc10 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
<> 140:97feb9bacc10 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 140:97feb9bacc10 1094 } MPU_Type;
<> 140:97feb9bacc10 1095
<> 140:97feb9bacc10 1096 /* MPU Type Register */
<> 140:97feb9bacc10 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 140:97feb9bacc10 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 140:97feb9bacc10 1099
<> 140:97feb9bacc10 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 140:97feb9bacc10 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 140:97feb9bacc10 1102
<> 140:97feb9bacc10 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 140:97feb9bacc10 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 140:97feb9bacc10 1105
<> 140:97feb9bacc10 1106 /* MPU Control Register */
<> 140:97feb9bacc10 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 140:97feb9bacc10 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 140:97feb9bacc10 1109
<> 140:97feb9bacc10 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 140:97feb9bacc10 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 140:97feb9bacc10 1112
<> 140:97feb9bacc10 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 140:97feb9bacc10 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 140:97feb9bacc10 1115
<> 140:97feb9bacc10 1116 /* MPU Region Number Register */
<> 140:97feb9bacc10 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 140:97feb9bacc10 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 140:97feb9bacc10 1119
<> 140:97feb9bacc10 1120 /* MPU Region Base Address Register */
<> 140:97feb9bacc10 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
<> 140:97feb9bacc10 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 140:97feb9bacc10 1123
<> 140:97feb9bacc10 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 140:97feb9bacc10 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 140:97feb9bacc10 1126
<> 140:97feb9bacc10 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 140:97feb9bacc10 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 140:97feb9bacc10 1129
<> 140:97feb9bacc10 1130 /* MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 140:97feb9bacc10 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 140:97feb9bacc10 1133
<> 140:97feb9bacc10 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 140:97feb9bacc10 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 140:97feb9bacc10 1136
<> 140:97feb9bacc10 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 140:97feb9bacc10 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 140:97feb9bacc10 1139
<> 140:97feb9bacc10 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 140:97feb9bacc10 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 140:97feb9bacc10 1142
<> 140:97feb9bacc10 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 140:97feb9bacc10 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 140:97feb9bacc10 1145
<> 140:97feb9bacc10 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 140:97feb9bacc10 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 140:97feb9bacc10 1148
<> 140:97feb9bacc10 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 140:97feb9bacc10 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 140:97feb9bacc10 1151
<> 140:97feb9bacc10 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 140:97feb9bacc10 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 140:97feb9bacc10 1154
<> 140:97feb9bacc10 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 140:97feb9bacc10 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 140:97feb9bacc10 1157
<> 140:97feb9bacc10 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 140:97feb9bacc10 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 140:97feb9bacc10 1160
<> 140:97feb9bacc10 1161 /*@} end of group CMSIS_MPU */
<> 140:97feb9bacc10 1162 #endif
<> 140:97feb9bacc10 1163
<> 140:97feb9bacc10 1164
<> 140:97feb9bacc10 1165 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 140:97feb9bacc10 1167 \brief Type definitions for the Core Debug Registers
<> 140:97feb9bacc10 1168 @{
<> 140:97feb9bacc10 1169 */
<> 140:97feb9bacc10 1170
<> 140:97feb9bacc10 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
<> 140:97feb9bacc10 1172 */
<> 140:97feb9bacc10 1173 typedef struct
<> 140:97feb9bacc10 1174 {
<> 140:97feb9bacc10 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
<> 140:97feb9bacc10 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
<> 140:97feb9bacc10 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
<> 140:97feb9bacc10 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 140:97feb9bacc10 1179 } CoreDebug_Type;
<> 140:97feb9bacc10 1180
<> 140:97feb9bacc10 1181 /* Debug Halting Control and Status Register */
<> 140:97feb9bacc10 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
<> 140:97feb9bacc10 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 140:97feb9bacc10 1184
<> 140:97feb9bacc10 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 140:97feb9bacc10 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 140:97feb9bacc10 1187
<> 140:97feb9bacc10 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 140:97feb9bacc10 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 140:97feb9bacc10 1190
<> 140:97feb9bacc10 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 140:97feb9bacc10 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 140:97feb9bacc10 1193
<> 140:97feb9bacc10 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 140:97feb9bacc10 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 140:97feb9bacc10 1196
<> 140:97feb9bacc10 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
<> 140:97feb9bacc10 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 140:97feb9bacc10 1199
<> 140:97feb9bacc10 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 140:97feb9bacc10 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 140:97feb9bacc10 1202
<> 140:97feb9bacc10 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 140:97feb9bacc10 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 140:97feb9bacc10 1205
<> 140:97feb9bacc10 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 140:97feb9bacc10 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 140:97feb9bacc10 1208
<> 140:97feb9bacc10 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
<> 140:97feb9bacc10 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 140:97feb9bacc10 1211
<> 140:97feb9bacc10 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
<> 140:97feb9bacc10 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 140:97feb9bacc10 1214
<> 140:97feb9bacc10 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 140:97feb9bacc10 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 140:97feb9bacc10 1217
<> 140:97feb9bacc10 1218 /* Debug Core Register Selector Register */
<> 140:97feb9bacc10 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
<> 140:97feb9bacc10 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 140:97feb9bacc10 1221
<> 140:97feb9bacc10 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
<> 140:97feb9bacc10 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 140:97feb9bacc10 1224
<> 140:97feb9bacc10 1225 /* Debug Exception and Monitor Control Register */
<> 140:97feb9bacc10 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
<> 140:97feb9bacc10 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 140:97feb9bacc10 1228
<> 140:97feb9bacc10 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
<> 140:97feb9bacc10 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 140:97feb9bacc10 1231
<> 140:97feb9bacc10 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
<> 140:97feb9bacc10 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 140:97feb9bacc10 1234
<> 140:97feb9bacc10 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
<> 140:97feb9bacc10 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 140:97feb9bacc10 1237
<> 140:97feb9bacc10 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
<> 140:97feb9bacc10 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 140:97feb9bacc10 1240
<> 140:97feb9bacc10 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 140:97feb9bacc10 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 140:97feb9bacc10 1243
<> 140:97feb9bacc10 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 140:97feb9bacc10 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 140:97feb9bacc10 1246
<> 140:97feb9bacc10 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 140:97feb9bacc10 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 140:97feb9bacc10 1249
<> 140:97feb9bacc10 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 140:97feb9bacc10 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 140:97feb9bacc10 1252
<> 140:97feb9bacc10 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 140:97feb9bacc10 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 140:97feb9bacc10 1255
<> 140:97feb9bacc10 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 140:97feb9bacc10 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 140:97feb9bacc10 1258
<> 140:97feb9bacc10 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 140:97feb9bacc10 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 140:97feb9bacc10 1261
<> 140:97feb9bacc10 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 140:97feb9bacc10 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 140:97feb9bacc10 1264
<> 140:97feb9bacc10 1265 /*@} end of group CMSIS_CoreDebug */
<> 140:97feb9bacc10 1266
<> 140:97feb9bacc10 1267
<> 140:97feb9bacc10 1268 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1269 \defgroup CMSIS_core_base Core Definitions
<> 140:97feb9bacc10 1270 \brief Definitions for base addresses, unions, and structures.
<> 140:97feb9bacc10 1271 @{
<> 140:97feb9bacc10 1272 */
<> 140:97feb9bacc10 1273
<> 140:97feb9bacc10 1274 /* Memory mapping of Cortex-M3 Hardware */
<> 140:97feb9bacc10 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 140:97feb9bacc10 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
<> 140:97feb9bacc10 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
<> 140:97feb9bacc10 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
<> 140:97feb9bacc10 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
<> 140:97feb9bacc10 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 140:97feb9bacc10 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 140:97feb9bacc10 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 140:97feb9bacc10 1283
<> 140:97feb9bacc10 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 140:97feb9bacc10 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 140:97feb9bacc10 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 140:97feb9bacc10 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 140:97feb9bacc10 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
<> 140:97feb9bacc10 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
<> 140:97feb9bacc10 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
<> 140:97feb9bacc10 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 140:97feb9bacc10 1292
<> 140:97feb9bacc10 1293 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 1296 #endif
<> 140:97feb9bacc10 1297
<> 140:97feb9bacc10 1298 /*@} */
<> 140:97feb9bacc10 1299
<> 140:97feb9bacc10 1300
<> 140:97feb9bacc10 1301
<> 140:97feb9bacc10 1302 /*******************************************************************************
<> 140:97feb9bacc10 1303 * Hardware Abstraction Layer
<> 140:97feb9bacc10 1304 Core Function Interface contains:
<> 140:97feb9bacc10 1305 - Core NVIC Functions
<> 140:97feb9bacc10 1306 - Core SysTick Functions
<> 140:97feb9bacc10 1307 - Core Debug Functions
<> 140:97feb9bacc10 1308 - Core Register Access Functions
<> 140:97feb9bacc10 1309 ******************************************************************************/
<> 140:97feb9bacc10 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 140:97feb9bacc10 1311 */
<> 140:97feb9bacc10 1312
<> 140:97feb9bacc10 1313
<> 140:97feb9bacc10 1314
<> 140:97feb9bacc10 1315 /* ########################## NVIC functions #################################### */
<> 140:97feb9bacc10 1316 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 140:97feb9bacc10 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 140:97feb9bacc10 1319 @{
<> 140:97feb9bacc10 1320 */
<> 140:97feb9bacc10 1321
<> 140:97feb9bacc10 1322 /** \brief Set Priority Grouping
<> 140:97feb9bacc10 1323
<> 140:97feb9bacc10 1324 The function sets the priority grouping field using the required unlock sequence.
<> 140:97feb9bacc10 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<> 140:97feb9bacc10 1326 Only values from 0..7 are used.
<> 140:97feb9bacc10 1327 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 140:97feb9bacc10 1329
<> 140:97feb9bacc10 1330 \param [in] PriorityGroup Priority grouping field.
<> 140:97feb9bacc10 1331 */
<> 140:97feb9bacc10 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 140:97feb9bacc10 1333 {
<> 140:97feb9bacc10 1334 uint32_t reg_value;
<> 140:97feb9bacc10 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1336
<> 140:97feb9bacc10 1337 reg_value = SCB->AIRCR; /* read old register configuration */
<> 140:97feb9bacc10 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 140:97feb9bacc10 1339 reg_value = (reg_value |
<> 140:97feb9bacc10 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<> 140:97feb9bacc10 1342 SCB->AIRCR = reg_value;
<> 140:97feb9bacc10 1343 }
<> 140:97feb9bacc10 1344
<> 140:97feb9bacc10 1345
<> 140:97feb9bacc10 1346 /** \brief Get Priority Grouping
<> 140:97feb9bacc10 1347
<> 140:97feb9bacc10 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
<> 140:97feb9bacc10 1349
<> 140:97feb9bacc10 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 140:97feb9bacc10 1351 */
<> 140:97feb9bacc10 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<> 140:97feb9bacc10 1353 {
<> 140:97feb9bacc10 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 140:97feb9bacc10 1355 }
<> 140:97feb9bacc10 1356
<> 140:97feb9bacc10 1357
<> 140:97feb9bacc10 1358 /** \brief Enable External Interrupt
<> 140:97feb9bacc10 1359
<> 140:97feb9bacc10 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 1361
<> 140:97feb9bacc10 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1363 */
<> 140:97feb9bacc10 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1365 {
<> 140:97feb9bacc10 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1367 }
<> 140:97feb9bacc10 1368
<> 140:97feb9bacc10 1369
<> 140:97feb9bacc10 1370 /** \brief Disable External Interrupt
<> 140:97feb9bacc10 1371
<> 140:97feb9bacc10 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 1373
<> 140:97feb9bacc10 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1375 */
<> 140:97feb9bacc10 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1377 {
<> 140:97feb9bacc10 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1379 __DSB();
<> 140:97feb9bacc10 1380 __ISB();
<> 140:97feb9bacc10 1381 }
<> 140:97feb9bacc10 1382
<> 140:97feb9bacc10 1383
<> 140:97feb9bacc10 1384 /** \brief Get Pending Interrupt
<> 140:97feb9bacc10 1385
<> 140:97feb9bacc10 1386 The function reads the pending register in the NVIC and returns the pending bit
<> 140:97feb9bacc10 1387 for the specified interrupt.
<> 140:97feb9bacc10 1388
<> 140:97feb9bacc10 1389 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1390
<> 140:97feb9bacc10 1391 \return 0 Interrupt status is not pending.
<> 140:97feb9bacc10 1392 \return 1 Interrupt status is pending.
<> 140:97feb9bacc10 1393 */
<> 140:97feb9bacc10 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1395 {
<> 140:97feb9bacc10 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 140:97feb9bacc10 1397 }
<> 140:97feb9bacc10 1398
<> 140:97feb9bacc10 1399
<> 140:97feb9bacc10 1400 /** \brief Set Pending Interrupt
<> 140:97feb9bacc10 1401
<> 140:97feb9bacc10 1402 The function sets the pending bit of an external interrupt.
<> 140:97feb9bacc10 1403
<> 140:97feb9bacc10 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1405 */
<> 140:97feb9bacc10 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1407 {
<> 140:97feb9bacc10 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1409 }
<> 140:97feb9bacc10 1410
<> 140:97feb9bacc10 1411
<> 140:97feb9bacc10 1412 /** \brief Clear Pending Interrupt
<> 140:97feb9bacc10 1413
<> 140:97feb9bacc10 1414 The function clears the pending bit of an external interrupt.
<> 140:97feb9bacc10 1415
<> 140:97feb9bacc10 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1417 */
<> 140:97feb9bacc10 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1419 {
<> 140:97feb9bacc10 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1421 }
<> 140:97feb9bacc10 1422
<> 140:97feb9bacc10 1423
<> 140:97feb9bacc10 1424 /** \brief Get Active Interrupt
<> 140:97feb9bacc10 1425
<> 140:97feb9bacc10 1426 The function reads the active register in NVIC and returns the active bit.
<> 140:97feb9bacc10 1427
<> 140:97feb9bacc10 1428 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1429
<> 140:97feb9bacc10 1430 \return 0 Interrupt status is not active.
<> 140:97feb9bacc10 1431 \return 1 Interrupt status is active.
<> 140:97feb9bacc10 1432 */
<> 140:97feb9bacc10 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<> 140:97feb9bacc10 1434 {
<> 140:97feb9bacc10 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 140:97feb9bacc10 1436 }
<> 140:97feb9bacc10 1437
<> 140:97feb9bacc10 1438
<> 140:97feb9bacc10 1439 /** \brief Set Interrupt Priority
<> 140:97feb9bacc10 1440
<> 140:97feb9bacc10 1441 The function sets the priority of an interrupt.
<> 140:97feb9bacc10 1442
<> 140:97feb9bacc10 1443 \note The priority cannot be set for every core interrupt.
<> 140:97feb9bacc10 1444
<> 140:97feb9bacc10 1445 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1446 \param [in] priority Priority to set.
<> 140:97feb9bacc10 1447 */
<> 140:97feb9bacc10 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 140:97feb9bacc10 1449 {
<> 140:97feb9bacc10 1450 if((int32_t)IRQn < 0) {
<> 140:97feb9bacc10 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 140:97feb9bacc10 1452 }
<> 140:97feb9bacc10 1453 else {
<> 140:97feb9bacc10 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 140:97feb9bacc10 1455 }
<> 140:97feb9bacc10 1456 }
<> 140:97feb9bacc10 1457
<> 140:97feb9bacc10 1458
<> 140:97feb9bacc10 1459 /** \brief Get Interrupt Priority
<> 140:97feb9bacc10 1460
<> 140:97feb9bacc10 1461 The function reads the priority of an interrupt. The interrupt
<> 140:97feb9bacc10 1462 number can be positive to specify an external (device specific)
<> 140:97feb9bacc10 1463 interrupt, or negative to specify an internal (core) interrupt.
<> 140:97feb9bacc10 1464
<> 140:97feb9bacc10 1465
<> 140:97feb9bacc10 1466 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 140:97feb9bacc10 1468 priority bits of the microcontroller.
<> 140:97feb9bacc10 1469 */
<> 140:97feb9bacc10 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 140:97feb9bacc10 1471 {
<> 140:97feb9bacc10 1472
<> 140:97feb9bacc10 1473 if((int32_t)IRQn < 0) {
<> 140:97feb9bacc10 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 1475 }
<> 140:97feb9bacc10 1476 else {
<> 140:97feb9bacc10 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 1478 }
<> 140:97feb9bacc10 1479 }
<> 140:97feb9bacc10 1480
<> 140:97feb9bacc10 1481
<> 140:97feb9bacc10 1482 /** \brief Encode Priority
<> 140:97feb9bacc10 1483
<> 140:97feb9bacc10 1484 The function encodes the priority for an interrupt with the given priority group,
<> 140:97feb9bacc10 1485 preemptive priority value, and subpriority value.
<> 140:97feb9bacc10 1486 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 140:97feb9bacc10 1488
<> 140:97feb9bacc10 1489 \param [in] PriorityGroup Used priority group.
<> 140:97feb9bacc10 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
<> 140:97feb9bacc10 1491 \param [in] SubPriority Subpriority value (starting from 0).
<> 140:97feb9bacc10 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 140:97feb9bacc10 1493 */
<> 140:97feb9bacc10 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 140:97feb9bacc10 1495 {
<> 140:97feb9bacc10 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1497 uint32_t PreemptPriorityBits;
<> 140:97feb9bacc10 1498 uint32_t SubPriorityBits;
<> 140:97feb9bacc10 1499
<> 140:97feb9bacc10 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 140:97feb9bacc10 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 140:97feb9bacc10 1502
<> 140:97feb9bacc10 1503 return (
<> 140:97feb9bacc10 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 140:97feb9bacc10 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 140:97feb9bacc10 1506 );
<> 140:97feb9bacc10 1507 }
<> 140:97feb9bacc10 1508
<> 140:97feb9bacc10 1509
<> 140:97feb9bacc10 1510 /** \brief Decode Priority
<> 140:97feb9bacc10 1511
<> 140:97feb9bacc10 1512 The function decodes an interrupt priority value with a given priority group to
<> 140:97feb9bacc10 1513 preemptive priority value and subpriority value.
<> 140:97feb9bacc10 1514 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<> 140:97feb9bacc10 1516
<> 140:97feb9bacc10 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<> 140:97feb9bacc10 1518 \param [in] PriorityGroup Used priority group.
<> 140:97feb9bacc10 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
<> 140:97feb9bacc10 1520 \param [out] pSubPriority Subpriority value (starting from 0).
<> 140:97feb9bacc10 1521 */
<> 140:97feb9bacc10 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 140:97feb9bacc10 1523 {
<> 140:97feb9bacc10 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1525 uint32_t PreemptPriorityBits;
<> 140:97feb9bacc10 1526 uint32_t SubPriorityBits;
<> 140:97feb9bacc10 1527
<> 140:97feb9bacc10 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 140:97feb9bacc10 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 140:97feb9bacc10 1530
<> 140:97feb9bacc10 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 140:97feb9bacc10 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 140:97feb9bacc10 1533 }
<> 140:97feb9bacc10 1534
<> 140:97feb9bacc10 1535
<> 140:97feb9bacc10 1536 /** \brief System Reset
<> 140:97feb9bacc10 1537
<> 140:97feb9bacc10 1538 The function initiates a system reset request to reset the MCU.
<> 140:97feb9bacc10 1539 */
<> 140:97feb9bacc10 1540 __STATIC_INLINE void NVIC_SystemReset(void)
<> 140:97feb9bacc10 1541 {
<> 140:97feb9bacc10 1542 __DSB(); /* Ensure all outstanding memory accesses included
<> 140:97feb9bacc10 1543 buffered write are completed before reset */
<> 140:97feb9bacc10 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 140:97feb9bacc10 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 140:97feb9bacc10 1547 __DSB(); /* Ensure completion of memory access */
<> 140:97feb9bacc10 1548 while(1) { __NOP(); } /* wait until reset */
<> 140:97feb9bacc10 1549 }
<> 140:97feb9bacc10 1550
<> 140:97feb9bacc10 1551 /*@} end of CMSIS_Core_NVICFunctions */
<> 140:97feb9bacc10 1552
<> 140:97feb9bacc10 1553
<> 140:97feb9bacc10 1554
<> 140:97feb9bacc10 1555 /* ################################## SysTick function ############################################ */
<> 140:97feb9bacc10 1556 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 140:97feb9bacc10 1558 \brief Functions that configure the System.
<> 140:97feb9bacc10 1559 @{
<> 140:97feb9bacc10 1560 */
<> 140:97feb9bacc10 1561
<> 140:97feb9bacc10 1562 #if (__Vendor_SysTickConfig == 0)
<> 140:97feb9bacc10 1563
<> 140:97feb9bacc10 1564 /** \brief System Tick Configuration
<> 140:97feb9bacc10 1565
<> 140:97feb9bacc10 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 140:97feb9bacc10 1567 Counter is in free running mode to generate periodic interrupts.
<> 140:97feb9bacc10 1568
<> 140:97feb9bacc10 1569 \param [in] ticks Number of ticks between two interrupts.
<> 140:97feb9bacc10 1570
<> 140:97feb9bacc10 1571 \return 0 Function succeeded.
<> 140:97feb9bacc10 1572 \return 1 Function failed.
<> 140:97feb9bacc10 1573
<> 140:97feb9bacc10 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 140:97feb9bacc10 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 140:97feb9bacc10 1576 must contain a vendor-specific implementation of this function.
<> 140:97feb9bacc10 1577
<> 140:97feb9bacc10 1578 */
<> 140:97feb9bacc10 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 140:97feb9bacc10 1580 {
<> 140:97feb9bacc10 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 140:97feb9bacc10 1582
<> 140:97feb9bacc10 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 140:97feb9bacc10 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 140:97feb9bacc10 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 140:97feb9bacc10 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 140:97feb9bacc10 1587 SysTick_CTRL_TICKINT_Msk |
<> 140:97feb9bacc10 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 140:97feb9bacc10 1589 return (0UL); /* Function successful */
<> 140:97feb9bacc10 1590 }
<> 140:97feb9bacc10 1591
<> 140:97feb9bacc10 1592 #endif
<> 140:97feb9bacc10 1593
<> 140:97feb9bacc10 1594 /*@} end of CMSIS_Core_SysTickFunctions */
<> 140:97feb9bacc10 1595
<> 140:97feb9bacc10 1596
<> 140:97feb9bacc10 1597
<> 140:97feb9bacc10 1598 /* ##################################### Debug In/Output function ########################################### */
<> 140:97feb9bacc10 1599 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
<> 140:97feb9bacc10 1601 \brief Functions that access the ITM debug interface.
<> 140:97feb9bacc10 1602 @{
<> 140:97feb9bacc10 1603 */
<> 140:97feb9bacc10 1604
<> 140:97feb9bacc10 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
<> 140:97feb9bacc10 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 140:97feb9bacc10 1607
<> 140:97feb9bacc10 1608
<> 140:97feb9bacc10 1609 /** \brief ITM Send Character
<> 140:97feb9bacc10 1610
<> 140:97feb9bacc10 1611 The function transmits a character via the ITM channel 0, and
<> 140:97feb9bacc10 1612 \li Just returns when no debugger is connected that has booked the output.
<> 140:97feb9bacc10 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<> 140:97feb9bacc10 1614
<> 140:97feb9bacc10 1615 \param [in] ch Character to transmit.
<> 140:97feb9bacc10 1616
<> 140:97feb9bacc10 1617 \returns Character to transmit.
<> 140:97feb9bacc10 1618 */
<> 140:97feb9bacc10 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 140:97feb9bacc10 1620 {
<> 140:97feb9bacc10 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 140:97feb9bacc10 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 140:97feb9bacc10 1623 {
<> 140:97feb9bacc10 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<> 140:97feb9bacc10 1625 ITM->PORT[0].u8 = (uint8_t)ch;
<> 140:97feb9bacc10 1626 }
<> 140:97feb9bacc10 1627 return (ch);
<> 140:97feb9bacc10 1628 }
<> 140:97feb9bacc10 1629
<> 140:97feb9bacc10 1630
<> 140:97feb9bacc10 1631 /** \brief ITM Receive Character
<> 140:97feb9bacc10 1632
<> 140:97feb9bacc10 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
<> 140:97feb9bacc10 1634
<> 140:97feb9bacc10 1635 \return Received character.
<> 140:97feb9bacc10 1636 \return -1 No character pending.
<> 140:97feb9bacc10 1637 */
<> 140:97feb9bacc10 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<> 140:97feb9bacc10 1639 int32_t ch = -1; /* no character available */
<> 140:97feb9bacc10 1640
<> 140:97feb9bacc10 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<> 140:97feb9bacc10 1642 ch = ITM_RxBuffer;
<> 140:97feb9bacc10 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 140:97feb9bacc10 1644 }
<> 140:97feb9bacc10 1645
<> 140:97feb9bacc10 1646 return (ch);
<> 140:97feb9bacc10 1647 }
<> 140:97feb9bacc10 1648
<> 140:97feb9bacc10 1649
<> 140:97feb9bacc10 1650 /** \brief ITM Check Character
<> 140:97feb9bacc10 1651
<> 140:97feb9bacc10 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<> 140:97feb9bacc10 1653
<> 140:97feb9bacc10 1654 \return 0 No character available.
<> 140:97feb9bacc10 1655 \return 1 Character available.
<> 140:97feb9bacc10 1656 */
<> 140:97feb9bacc10 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
<> 140:97feb9bacc10 1658
<> 140:97feb9bacc10 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<> 140:97feb9bacc10 1660 return (0); /* no character available */
<> 140:97feb9bacc10 1661 } else {
<> 140:97feb9bacc10 1662 return (1); /* character available */
<> 140:97feb9bacc10 1663 }
<> 140:97feb9bacc10 1664 }
<> 140:97feb9bacc10 1665
<> 140:97feb9bacc10 1666 /*@} end of CMSIS_core_DebugFunctions */
<> 140:97feb9bacc10 1667
<> 140:97feb9bacc10 1668
<> 140:97feb9bacc10 1669
<> 140:97feb9bacc10 1670
<> 140:97feb9bacc10 1671 #ifdef __cplusplus
<> 140:97feb9bacc10 1672 }
<> 140:97feb9bacc10 1673 #endif
<> 140:97feb9bacc10 1674
<> 140:97feb9bacc10 1675 #endif /* __CORE_SC300_H_DEPENDANT */
<> 140:97feb9bacc10 1676
<> 140:97feb9bacc10 1677 #endif /* __CMSIS_GENERIC */