mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_cmInstr.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_cmInstr.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 140:97feb9bacc10 4 * @version V4.10
<> 140:97feb9bacc10 5 * @date 18. March 2015
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #ifndef __CORE_CMINSTR_H
<> 140:97feb9bacc10 39 #define __CORE_CMINSTR_H
<> 140:97feb9bacc10 40
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 /* ########################## Core Instruction Access ######################### */
<> 140:97feb9bacc10 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 140:97feb9bacc10 44 Access to dedicated instructions
<> 140:97feb9bacc10 45 @{
<> 140:97feb9bacc10 46 */
<> 140:97feb9bacc10 47
<> 140:97feb9bacc10 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 140:97feb9bacc10 49 /* ARM armcc specific functions */
<> 140:97feb9bacc10 50
<> 140:97feb9bacc10 51 #if (__ARMCC_VERSION < 400677)
<> 140:97feb9bacc10 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 140:97feb9bacc10 53 #endif
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55
<> 140:97feb9bacc10 56 /** \brief No Operation
<> 140:97feb9bacc10 57
<> 140:97feb9bacc10 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 140:97feb9bacc10 59 */
<> 140:97feb9bacc10 60 #define __NOP __nop
<> 140:97feb9bacc10 61
<> 140:97feb9bacc10 62
<> 140:97feb9bacc10 63 /** \brief Wait For Interrupt
<> 140:97feb9bacc10 64
<> 140:97feb9bacc10 65 Wait For Interrupt is a hint instruction that suspends execution
<> 140:97feb9bacc10 66 until one of a number of events occurs.
<> 140:97feb9bacc10 67 */
<> 140:97feb9bacc10 68 #define __WFI __wfi
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70
<> 140:97feb9bacc10 71 /** \brief Wait For Event
<> 140:97feb9bacc10 72
<> 140:97feb9bacc10 73 Wait For Event is a hint instruction that permits the processor to enter
<> 140:97feb9bacc10 74 a low-power state until one of a number of events occurs.
<> 140:97feb9bacc10 75 */
<> 140:97feb9bacc10 76 #define __WFE __wfe
<> 140:97feb9bacc10 77
<> 140:97feb9bacc10 78
<> 140:97feb9bacc10 79 /** \brief Send Event
<> 140:97feb9bacc10 80
<> 140:97feb9bacc10 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 140:97feb9bacc10 82 */
<> 140:97feb9bacc10 83 #define __SEV __sev
<> 140:97feb9bacc10 84
<> 140:97feb9bacc10 85
<> 140:97feb9bacc10 86 /** \brief Instruction Synchronization Barrier
<> 140:97feb9bacc10 87
<> 140:97feb9bacc10 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 140:97feb9bacc10 89 so that all instructions following the ISB are fetched from cache or
<> 140:97feb9bacc10 90 memory, after the instruction has been completed.
<> 140:97feb9bacc10 91 */
<> 140:97feb9bacc10 92 #define __ISB() do {\
<> 140:97feb9bacc10 93 __schedule_barrier();\
<> 140:97feb9bacc10 94 __isb(0xF);\
<> 140:97feb9bacc10 95 __schedule_barrier();\
<> 140:97feb9bacc10 96 } while (0)
<> 140:97feb9bacc10 97
<> 140:97feb9bacc10 98 /** \brief Data Synchronization Barrier
<> 140:97feb9bacc10 99
<> 140:97feb9bacc10 100 This function acts as a special kind of Data Memory Barrier.
<> 140:97feb9bacc10 101 It completes when all explicit memory accesses before this instruction complete.
<> 140:97feb9bacc10 102 */
<> 140:97feb9bacc10 103 #define __DSB() do {\
<> 140:97feb9bacc10 104 __schedule_barrier();\
<> 140:97feb9bacc10 105 __dsb(0xF);\
<> 140:97feb9bacc10 106 __schedule_barrier();\
<> 140:97feb9bacc10 107 } while (0)
<> 140:97feb9bacc10 108
<> 140:97feb9bacc10 109 /** \brief Data Memory Barrier
<> 140:97feb9bacc10 110
<> 140:97feb9bacc10 111 This function ensures the apparent order of the explicit memory operations before
<> 140:97feb9bacc10 112 and after the instruction, without ensuring their completion.
<> 140:97feb9bacc10 113 */
<> 140:97feb9bacc10 114 #define __DMB() do {\
<> 140:97feb9bacc10 115 __schedule_barrier();\
<> 140:97feb9bacc10 116 __dmb(0xF);\
<> 140:97feb9bacc10 117 __schedule_barrier();\
<> 140:97feb9bacc10 118 } while (0)
<> 140:97feb9bacc10 119
<> 140:97feb9bacc10 120 /** \brief Reverse byte order (32 bit)
<> 140:97feb9bacc10 121
<> 140:97feb9bacc10 122 This function reverses the byte order in integer value.
<> 140:97feb9bacc10 123
<> 140:97feb9bacc10 124 \param [in] value Value to reverse
<> 140:97feb9bacc10 125 \return Reversed value
<> 140:97feb9bacc10 126 */
<> 140:97feb9bacc10 127 #define __REV __rev
<> 140:97feb9bacc10 128
<> 140:97feb9bacc10 129
<> 140:97feb9bacc10 130 /** \brief Reverse byte order (16 bit)
<> 140:97feb9bacc10 131
<> 140:97feb9bacc10 132 This function reverses the byte order in two unsigned short values.
<> 140:97feb9bacc10 133
<> 140:97feb9bacc10 134 \param [in] value Value to reverse
<> 140:97feb9bacc10 135 \return Reversed value
<> 140:97feb9bacc10 136 */
<> 140:97feb9bacc10 137 #ifndef __NO_EMBEDDED_ASM
<> 140:97feb9bacc10 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 140:97feb9bacc10 139 {
<> 140:97feb9bacc10 140 rev16 r0, r0
<> 140:97feb9bacc10 141 bx lr
<> 140:97feb9bacc10 142 }
<> 140:97feb9bacc10 143 #endif
<> 140:97feb9bacc10 144
<> 140:97feb9bacc10 145 /** \brief Reverse byte order in signed short value
<> 140:97feb9bacc10 146
<> 140:97feb9bacc10 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 140:97feb9bacc10 148
<> 140:97feb9bacc10 149 \param [in] value Value to reverse
<> 140:97feb9bacc10 150 \return Reversed value
<> 140:97feb9bacc10 151 */
<> 140:97feb9bacc10 152 #ifndef __NO_EMBEDDED_ASM
<> 140:97feb9bacc10 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 140:97feb9bacc10 154 {
<> 140:97feb9bacc10 155 revsh r0, r0
<> 140:97feb9bacc10 156 bx lr
<> 140:97feb9bacc10 157 }
<> 140:97feb9bacc10 158 #endif
<> 140:97feb9bacc10 159
<> 140:97feb9bacc10 160
<> 140:97feb9bacc10 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 140:97feb9bacc10 162
<> 140:97feb9bacc10 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 140:97feb9bacc10 164
<> 140:97feb9bacc10 165 \param [in] value Value to rotate
<> 140:97feb9bacc10 166 \param [in] value Number of Bits to rotate
<> 140:97feb9bacc10 167 \return Rotated value
<> 140:97feb9bacc10 168 */
<> 140:97feb9bacc10 169 #define __ROR __ror
<> 140:97feb9bacc10 170
<> 140:97feb9bacc10 171
<> 140:97feb9bacc10 172 /** \brief Breakpoint
<> 140:97feb9bacc10 173
<> 140:97feb9bacc10 174 This function causes the processor to enter Debug state.
<> 140:97feb9bacc10 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 140:97feb9bacc10 176
<> 140:97feb9bacc10 177 \param [in] value is ignored by the processor.
<> 140:97feb9bacc10 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 140:97feb9bacc10 179 */
<> 140:97feb9bacc10 180 #define __BKPT(value) __breakpoint(value)
<> 140:97feb9bacc10 181
<> 140:97feb9bacc10 182
<> 140:97feb9bacc10 183 /** \brief Reverse bit order of value
<> 140:97feb9bacc10 184
<> 140:97feb9bacc10 185 This function reverses the bit order of the given value.
<> 140:97feb9bacc10 186
<> 140:97feb9bacc10 187 \param [in] value Value to reverse
<> 140:97feb9bacc10 188 \return Reversed value
<> 140:97feb9bacc10 189 */
<> 140:97feb9bacc10 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 140:97feb9bacc10 191 #define __RBIT __rbit
<> 140:97feb9bacc10 192 #else
<> 140:97feb9bacc10 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 140:97feb9bacc10 194 {
<> 140:97feb9bacc10 195 uint32_t result;
<> 140:97feb9bacc10 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 140:97feb9bacc10 197
<> 140:97feb9bacc10 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 140:97feb9bacc10 199 for (value >>= 1; value; value >>= 1)
<> 140:97feb9bacc10 200 {
<> 140:97feb9bacc10 201 result <<= 1;
<> 140:97feb9bacc10 202 result |= value & 1;
<> 140:97feb9bacc10 203 s--;
<> 140:97feb9bacc10 204 }
<> 140:97feb9bacc10 205 result <<= s; // shift when v's highest bits are zero
<> 140:97feb9bacc10 206 return(result);
<> 140:97feb9bacc10 207 }
<> 140:97feb9bacc10 208 #endif
<> 140:97feb9bacc10 209
<> 140:97feb9bacc10 210
<> 140:97feb9bacc10 211 /** \brief Count leading zeros
<> 140:97feb9bacc10 212
<> 140:97feb9bacc10 213 This function counts the number of leading zeros of a data value.
<> 140:97feb9bacc10 214
<> 140:97feb9bacc10 215 \param [in] value Value to count the leading zeros
<> 140:97feb9bacc10 216 \return number of leading zeros in value
<> 140:97feb9bacc10 217 */
<> 140:97feb9bacc10 218 #define __CLZ __clz
<> 140:97feb9bacc10 219
<> 140:97feb9bacc10 220
<> 140:97feb9bacc10 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 140:97feb9bacc10 222
<> 140:97feb9bacc10 223 /** \brief LDR Exclusive (8 bit)
<> 140:97feb9bacc10 224
<> 140:97feb9bacc10 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 140:97feb9bacc10 226
<> 140:97feb9bacc10 227 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 228 \return value of type uint8_t at (*ptr)
<> 140:97feb9bacc10 229 */
<> 140:97feb9bacc10 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 140:97feb9bacc10 231
<> 140:97feb9bacc10 232
<> 140:97feb9bacc10 233 /** \brief LDR Exclusive (16 bit)
<> 140:97feb9bacc10 234
<> 140:97feb9bacc10 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 140:97feb9bacc10 236
<> 140:97feb9bacc10 237 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 238 \return value of type uint16_t at (*ptr)
<> 140:97feb9bacc10 239 */
<> 140:97feb9bacc10 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 140:97feb9bacc10 241
<> 140:97feb9bacc10 242
<> 140:97feb9bacc10 243 /** \brief LDR Exclusive (32 bit)
<> 140:97feb9bacc10 244
<> 140:97feb9bacc10 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 140:97feb9bacc10 246
<> 140:97feb9bacc10 247 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 248 \return value of type uint32_t at (*ptr)
<> 140:97feb9bacc10 249 */
<> 140:97feb9bacc10 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 140:97feb9bacc10 251
<> 140:97feb9bacc10 252
<> 140:97feb9bacc10 253 /** \brief STR Exclusive (8 bit)
<> 140:97feb9bacc10 254
<> 140:97feb9bacc10 255 This function executes a exclusive STR instruction for 8 bit values.
<> 140:97feb9bacc10 256
<> 140:97feb9bacc10 257 \param [in] value Value to store
<> 140:97feb9bacc10 258 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 259 \return 0 Function succeeded
<> 140:97feb9bacc10 260 \return 1 Function failed
<> 140:97feb9bacc10 261 */
<> 140:97feb9bacc10 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 140:97feb9bacc10 263
<> 140:97feb9bacc10 264
<> 140:97feb9bacc10 265 /** \brief STR Exclusive (16 bit)
<> 140:97feb9bacc10 266
<> 140:97feb9bacc10 267 This function executes a exclusive STR instruction for 16 bit values.
<> 140:97feb9bacc10 268
<> 140:97feb9bacc10 269 \param [in] value Value to store
<> 140:97feb9bacc10 270 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 271 \return 0 Function succeeded
<> 140:97feb9bacc10 272 \return 1 Function failed
<> 140:97feb9bacc10 273 */
<> 140:97feb9bacc10 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 140:97feb9bacc10 275
<> 140:97feb9bacc10 276
<> 140:97feb9bacc10 277 /** \brief STR Exclusive (32 bit)
<> 140:97feb9bacc10 278
<> 140:97feb9bacc10 279 This function executes a exclusive STR instruction for 32 bit values.
<> 140:97feb9bacc10 280
<> 140:97feb9bacc10 281 \param [in] value Value to store
<> 140:97feb9bacc10 282 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 283 \return 0 Function succeeded
<> 140:97feb9bacc10 284 \return 1 Function failed
<> 140:97feb9bacc10 285 */
<> 140:97feb9bacc10 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 140:97feb9bacc10 287
<> 140:97feb9bacc10 288
<> 140:97feb9bacc10 289 /** \brief Remove the exclusive lock
<> 140:97feb9bacc10 290
<> 140:97feb9bacc10 291 This function removes the exclusive lock which is created by LDREX.
<> 140:97feb9bacc10 292
<> 140:97feb9bacc10 293 */
<> 140:97feb9bacc10 294 #define __CLREX __clrex
<> 140:97feb9bacc10 295
<> 140:97feb9bacc10 296
<> 140:97feb9bacc10 297 /** \brief Signed Saturate
<> 140:97feb9bacc10 298
<> 140:97feb9bacc10 299 This function saturates a signed value.
<> 140:97feb9bacc10 300
<> 140:97feb9bacc10 301 \param [in] value Value to be saturated
<> 140:97feb9bacc10 302 \param [in] sat Bit position to saturate to (1..32)
<> 140:97feb9bacc10 303 \return Saturated value
<> 140:97feb9bacc10 304 */
<> 140:97feb9bacc10 305 #define __SSAT __ssat
<> 140:97feb9bacc10 306
<> 140:97feb9bacc10 307
<> 140:97feb9bacc10 308 /** \brief Unsigned Saturate
<> 140:97feb9bacc10 309
<> 140:97feb9bacc10 310 This function saturates an unsigned value.
<> 140:97feb9bacc10 311
<> 140:97feb9bacc10 312 \param [in] value Value to be saturated
<> 140:97feb9bacc10 313 \param [in] sat Bit position to saturate to (0..31)
<> 140:97feb9bacc10 314 \return Saturated value
<> 140:97feb9bacc10 315 */
<> 140:97feb9bacc10 316 #define __USAT __usat
<> 140:97feb9bacc10 317
<> 140:97feb9bacc10 318
<> 140:97feb9bacc10 319 /** \brief Rotate Right with Extend (32 bit)
<> 140:97feb9bacc10 320
<> 140:97feb9bacc10 321 This function moves each bit of a bitstring right by one bit.
<> 140:97feb9bacc10 322 The carry input is shifted in at the left end of the bitstring.
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324 \param [in] value Value to rotate
<> 140:97feb9bacc10 325 \return Rotated value
<> 140:97feb9bacc10 326 */
<> 140:97feb9bacc10 327 #ifndef __NO_EMBEDDED_ASM
<> 140:97feb9bacc10 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 140:97feb9bacc10 329 {
<> 140:97feb9bacc10 330 rrx r0, r0
<> 140:97feb9bacc10 331 bx lr
<> 140:97feb9bacc10 332 }
<> 140:97feb9bacc10 333 #endif
<> 140:97feb9bacc10 334
<> 140:97feb9bacc10 335
<> 140:97feb9bacc10 336 /** \brief LDRT Unprivileged (8 bit)
<> 140:97feb9bacc10 337
<> 140:97feb9bacc10 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 140:97feb9bacc10 339
<> 140:97feb9bacc10 340 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 341 \return value of type uint8_t at (*ptr)
<> 140:97feb9bacc10 342 */
<> 140:97feb9bacc10 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 140:97feb9bacc10 344
<> 140:97feb9bacc10 345
<> 140:97feb9bacc10 346 /** \brief LDRT Unprivileged (16 bit)
<> 140:97feb9bacc10 347
<> 140:97feb9bacc10 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 140:97feb9bacc10 349
<> 140:97feb9bacc10 350 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 351 \return value of type uint16_t at (*ptr)
<> 140:97feb9bacc10 352 */
<> 140:97feb9bacc10 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 140:97feb9bacc10 354
<> 140:97feb9bacc10 355
<> 140:97feb9bacc10 356 /** \brief LDRT Unprivileged (32 bit)
<> 140:97feb9bacc10 357
<> 140:97feb9bacc10 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 140:97feb9bacc10 359
<> 140:97feb9bacc10 360 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 361 \return value of type uint32_t at (*ptr)
<> 140:97feb9bacc10 362 */
<> 140:97feb9bacc10 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 140:97feb9bacc10 364
<> 140:97feb9bacc10 365
<> 140:97feb9bacc10 366 /** \brief STRT Unprivileged (8 bit)
<> 140:97feb9bacc10 367
<> 140:97feb9bacc10 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 140:97feb9bacc10 369
<> 140:97feb9bacc10 370 \param [in] value Value to store
<> 140:97feb9bacc10 371 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 372 */
<> 140:97feb9bacc10 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 140:97feb9bacc10 374
<> 140:97feb9bacc10 375
<> 140:97feb9bacc10 376 /** \brief STRT Unprivileged (16 bit)
<> 140:97feb9bacc10 377
<> 140:97feb9bacc10 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 140:97feb9bacc10 379
<> 140:97feb9bacc10 380 \param [in] value Value to store
<> 140:97feb9bacc10 381 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 382 */
<> 140:97feb9bacc10 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 140:97feb9bacc10 384
<> 140:97feb9bacc10 385
<> 140:97feb9bacc10 386 /** \brief STRT Unprivileged (32 bit)
<> 140:97feb9bacc10 387
<> 140:97feb9bacc10 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 140:97feb9bacc10 389
<> 140:97feb9bacc10 390 \param [in] value Value to store
<> 140:97feb9bacc10 391 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 392 */
<> 140:97feb9bacc10 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 140:97feb9bacc10 394
<> 140:97feb9bacc10 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 140:97feb9bacc10 396
<> 140:97feb9bacc10 397
<> 140:97feb9bacc10 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 140:97feb9bacc10 399 /* GNU gcc specific functions */
<> 140:97feb9bacc10 400
<> 140:97feb9bacc10 401 /* Define macros for porting to both thumb1 and thumb2.
<> 140:97feb9bacc10 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 140:97feb9bacc10 403 * Otherwise, use general registers, specified by constrant "r" */
<> 140:97feb9bacc10 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 140:97feb9bacc10 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 140:97feb9bacc10 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 140:97feb9bacc10 407 #else
<> 140:97feb9bacc10 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 140:97feb9bacc10 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 140:97feb9bacc10 410 #endif
<> 140:97feb9bacc10 411
<> 140:97feb9bacc10 412 /** \brief No Operation
<> 140:97feb9bacc10 413
<> 140:97feb9bacc10 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 140:97feb9bacc10 415 */
<> 140:97feb9bacc10 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 140:97feb9bacc10 417 {
<> 140:97feb9bacc10 418 __ASM volatile ("nop");
<> 140:97feb9bacc10 419 }
<> 140:97feb9bacc10 420
<> 140:97feb9bacc10 421
<> 140:97feb9bacc10 422 /** \brief Wait For Interrupt
<> 140:97feb9bacc10 423
<> 140:97feb9bacc10 424 Wait For Interrupt is a hint instruction that suspends execution
<> 140:97feb9bacc10 425 until one of a number of events occurs.
<> 140:97feb9bacc10 426 */
<> 140:97feb9bacc10 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 140:97feb9bacc10 428 {
<> 140:97feb9bacc10 429 __ASM volatile ("wfi");
<> 140:97feb9bacc10 430 }
<> 140:97feb9bacc10 431
<> 140:97feb9bacc10 432
<> 140:97feb9bacc10 433 /** \brief Wait For Event
<> 140:97feb9bacc10 434
<> 140:97feb9bacc10 435 Wait For Event is a hint instruction that permits the processor to enter
<> 140:97feb9bacc10 436 a low-power state until one of a number of events occurs.
<> 140:97feb9bacc10 437 */
<> 140:97feb9bacc10 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 140:97feb9bacc10 439 {
<> 140:97feb9bacc10 440 __ASM volatile ("wfe");
<> 140:97feb9bacc10 441 }
<> 140:97feb9bacc10 442
<> 140:97feb9bacc10 443
<> 140:97feb9bacc10 444 /** \brief Send Event
<> 140:97feb9bacc10 445
<> 140:97feb9bacc10 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 140:97feb9bacc10 447 */
<> 140:97feb9bacc10 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 140:97feb9bacc10 449 {
<> 140:97feb9bacc10 450 __ASM volatile ("sev");
<> 140:97feb9bacc10 451 }
<> 140:97feb9bacc10 452
<> 140:97feb9bacc10 453
<> 140:97feb9bacc10 454 /** \brief Instruction Synchronization Barrier
<> 140:97feb9bacc10 455
<> 140:97feb9bacc10 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 140:97feb9bacc10 457 so that all instructions following the ISB are fetched from cache or
<> 140:97feb9bacc10 458 memory, after the instruction has been completed.
<> 140:97feb9bacc10 459 */
<> 140:97feb9bacc10 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 140:97feb9bacc10 461 {
<> 140:97feb9bacc10 462 __ASM volatile ("isb 0xF":::"memory");
<> 140:97feb9bacc10 463 }
<> 140:97feb9bacc10 464
<> 140:97feb9bacc10 465
<> 140:97feb9bacc10 466 /** \brief Data Synchronization Barrier
<> 140:97feb9bacc10 467
<> 140:97feb9bacc10 468 This function acts as a special kind of Data Memory Barrier.
<> 140:97feb9bacc10 469 It completes when all explicit memory accesses before this instruction complete.
<> 140:97feb9bacc10 470 */
<> 140:97feb9bacc10 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 140:97feb9bacc10 472 {
<> 140:97feb9bacc10 473 __ASM volatile ("dsb 0xF":::"memory");
<> 140:97feb9bacc10 474 }
<> 140:97feb9bacc10 475
<> 140:97feb9bacc10 476
<> 140:97feb9bacc10 477 /** \brief Data Memory Barrier
<> 140:97feb9bacc10 478
<> 140:97feb9bacc10 479 This function ensures the apparent order of the explicit memory operations before
<> 140:97feb9bacc10 480 and after the instruction, without ensuring their completion.
<> 140:97feb9bacc10 481 */
<> 140:97feb9bacc10 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 140:97feb9bacc10 483 {
<> 140:97feb9bacc10 484 __ASM volatile ("dmb 0xF":::"memory");
<> 140:97feb9bacc10 485 }
<> 140:97feb9bacc10 486
<> 140:97feb9bacc10 487
<> 140:97feb9bacc10 488 /** \brief Reverse byte order (32 bit)
<> 140:97feb9bacc10 489
<> 140:97feb9bacc10 490 This function reverses the byte order in integer value.
<> 140:97feb9bacc10 491
<> 140:97feb9bacc10 492 \param [in] value Value to reverse
<> 140:97feb9bacc10 493 \return Reversed value
<> 140:97feb9bacc10 494 */
<> 140:97feb9bacc10 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 140:97feb9bacc10 496 {
<> 140:97feb9bacc10 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 140:97feb9bacc10 498 return __builtin_bswap32(value);
<> 140:97feb9bacc10 499 #else
<> 140:97feb9bacc10 500 uint32_t result;
<> 140:97feb9bacc10 501
<> 140:97feb9bacc10 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 140:97feb9bacc10 503 return(result);
<> 140:97feb9bacc10 504 #endif
<> 140:97feb9bacc10 505 }
<> 140:97feb9bacc10 506
<> 140:97feb9bacc10 507
<> 140:97feb9bacc10 508 /** \brief Reverse byte order (16 bit)
<> 140:97feb9bacc10 509
<> 140:97feb9bacc10 510 This function reverses the byte order in two unsigned short values.
<> 140:97feb9bacc10 511
<> 140:97feb9bacc10 512 \param [in] value Value to reverse
<> 140:97feb9bacc10 513 \return Reversed value
<> 140:97feb9bacc10 514 */
<> 140:97feb9bacc10 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 140:97feb9bacc10 516 {
<> 140:97feb9bacc10 517 uint32_t result;
<> 140:97feb9bacc10 518
<> 140:97feb9bacc10 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 140:97feb9bacc10 520 return(result);
<> 140:97feb9bacc10 521 }
<> 140:97feb9bacc10 522
<> 140:97feb9bacc10 523
<> 140:97feb9bacc10 524 /** \brief Reverse byte order in signed short value
<> 140:97feb9bacc10 525
<> 140:97feb9bacc10 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 140:97feb9bacc10 527
<> 140:97feb9bacc10 528 \param [in] value Value to reverse
<> 140:97feb9bacc10 529 \return Reversed value
<> 140:97feb9bacc10 530 */
<> 140:97feb9bacc10 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 140:97feb9bacc10 532 {
<> 140:97feb9bacc10 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 140:97feb9bacc10 534 return (short)__builtin_bswap16(value);
<> 140:97feb9bacc10 535 #else
<> 140:97feb9bacc10 536 uint32_t result;
<> 140:97feb9bacc10 537
<> 140:97feb9bacc10 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 140:97feb9bacc10 539 return(result);
<> 140:97feb9bacc10 540 #endif
<> 140:97feb9bacc10 541 }
<> 140:97feb9bacc10 542
<> 140:97feb9bacc10 543
<> 140:97feb9bacc10 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 140:97feb9bacc10 545
<> 140:97feb9bacc10 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 140:97feb9bacc10 547
<> 140:97feb9bacc10 548 \param [in] value Value to rotate
<> 140:97feb9bacc10 549 \param [in] value Number of Bits to rotate
<> 140:97feb9bacc10 550 \return Rotated value
<> 140:97feb9bacc10 551 */
<> 140:97feb9bacc10 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 140:97feb9bacc10 553 {
<> 140:97feb9bacc10 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 140:97feb9bacc10 555 }
<> 140:97feb9bacc10 556
<> 140:97feb9bacc10 557
<> 140:97feb9bacc10 558 /** \brief Breakpoint
<> 140:97feb9bacc10 559
<> 140:97feb9bacc10 560 This function causes the processor to enter Debug state.
<> 140:97feb9bacc10 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 140:97feb9bacc10 562
<> 140:97feb9bacc10 563 \param [in] value is ignored by the processor.
<> 140:97feb9bacc10 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 140:97feb9bacc10 565 */
<> 140:97feb9bacc10 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 140:97feb9bacc10 567
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 /** \brief Reverse bit order of value
<> 140:97feb9bacc10 570
<> 140:97feb9bacc10 571 This function reverses the bit order of the given value.
<> 140:97feb9bacc10 572
<> 140:97feb9bacc10 573 \param [in] value Value to reverse
<> 140:97feb9bacc10 574 \return Reversed value
<> 140:97feb9bacc10 575 */
<> 140:97feb9bacc10 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 140:97feb9bacc10 577 {
<> 140:97feb9bacc10 578 uint32_t result;
<> 140:97feb9bacc10 579
<> 140:97feb9bacc10 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 140:97feb9bacc10 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 140:97feb9bacc10 582 #else
<> 140:97feb9bacc10 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 140:97feb9bacc10 584
<> 140:97feb9bacc10 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 140:97feb9bacc10 586 for (value >>= 1; value; value >>= 1)
<> 140:97feb9bacc10 587 {
<> 140:97feb9bacc10 588 result <<= 1;
<> 140:97feb9bacc10 589 result |= value & 1;
<> 140:97feb9bacc10 590 s--;
<> 140:97feb9bacc10 591 }
<> 140:97feb9bacc10 592 result <<= s; // shift when v's highest bits are zero
<> 140:97feb9bacc10 593 #endif
<> 140:97feb9bacc10 594 return(result);
<> 140:97feb9bacc10 595 }
<> 140:97feb9bacc10 596
<> 140:97feb9bacc10 597
<> 140:97feb9bacc10 598 /** \brief Count leading zeros
<> 140:97feb9bacc10 599
<> 140:97feb9bacc10 600 This function counts the number of leading zeros of a data value.
<> 140:97feb9bacc10 601
<> 140:97feb9bacc10 602 \param [in] value Value to count the leading zeros
<> 140:97feb9bacc10 603 \return number of leading zeros in value
<> 140:97feb9bacc10 604 */
<> 140:97feb9bacc10 605 #define __CLZ __builtin_clz
<> 140:97feb9bacc10 606
<> 140:97feb9bacc10 607
<> 140:97feb9bacc10 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 140:97feb9bacc10 609
<> 140:97feb9bacc10 610 /** \brief LDR Exclusive (8 bit)
<> 140:97feb9bacc10 611
<> 140:97feb9bacc10 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 140:97feb9bacc10 613
<> 140:97feb9bacc10 614 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 615 \return value of type uint8_t at (*ptr)
<> 140:97feb9bacc10 616 */
<> 140:97feb9bacc10 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 140:97feb9bacc10 618 {
<> 140:97feb9bacc10 619 uint32_t result;
<> 140:97feb9bacc10 620
<> 140:97feb9bacc10 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 140:97feb9bacc10 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 623 #else
<> 140:97feb9bacc10 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 140:97feb9bacc10 625 accepted by assembler. So has to use following less efficient pattern.
<> 140:97feb9bacc10 626 */
<> 140:97feb9bacc10 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 140:97feb9bacc10 628 #endif
<> 140:97feb9bacc10 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 140:97feb9bacc10 630 }
<> 140:97feb9bacc10 631
<> 140:97feb9bacc10 632
<> 140:97feb9bacc10 633 /** \brief LDR Exclusive (16 bit)
<> 140:97feb9bacc10 634
<> 140:97feb9bacc10 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 140:97feb9bacc10 636
<> 140:97feb9bacc10 637 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 638 \return value of type uint16_t at (*ptr)
<> 140:97feb9bacc10 639 */
<> 140:97feb9bacc10 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 140:97feb9bacc10 641 {
<> 140:97feb9bacc10 642 uint32_t result;
<> 140:97feb9bacc10 643
<> 140:97feb9bacc10 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 140:97feb9bacc10 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 646 #else
<> 140:97feb9bacc10 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 140:97feb9bacc10 648 accepted by assembler. So has to use following less efficient pattern.
<> 140:97feb9bacc10 649 */
<> 140:97feb9bacc10 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 140:97feb9bacc10 651 #endif
<> 140:97feb9bacc10 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 140:97feb9bacc10 653 }
<> 140:97feb9bacc10 654
<> 140:97feb9bacc10 655
<> 140:97feb9bacc10 656 /** \brief LDR Exclusive (32 bit)
<> 140:97feb9bacc10 657
<> 140:97feb9bacc10 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 140:97feb9bacc10 659
<> 140:97feb9bacc10 660 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 661 \return value of type uint32_t at (*ptr)
<> 140:97feb9bacc10 662 */
<> 140:97feb9bacc10 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 140:97feb9bacc10 664 {
<> 140:97feb9bacc10 665 uint32_t result;
<> 140:97feb9bacc10 666
<> 140:97feb9bacc10 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 668 return(result);
<> 140:97feb9bacc10 669 }
<> 140:97feb9bacc10 670
<> 140:97feb9bacc10 671
<> 140:97feb9bacc10 672 /** \brief STR Exclusive (8 bit)
<> 140:97feb9bacc10 673
<> 140:97feb9bacc10 674 This function executes a exclusive STR instruction for 8 bit values.
<> 140:97feb9bacc10 675
<> 140:97feb9bacc10 676 \param [in] value Value to store
<> 140:97feb9bacc10 677 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 678 \return 0 Function succeeded
<> 140:97feb9bacc10 679 \return 1 Function failed
<> 140:97feb9bacc10 680 */
<> 140:97feb9bacc10 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 140:97feb9bacc10 682 {
<> 140:97feb9bacc10 683 uint32_t result;
<> 140:97feb9bacc10 684
<> 140:97feb9bacc10 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 140:97feb9bacc10 686 return(result);
<> 140:97feb9bacc10 687 }
<> 140:97feb9bacc10 688
<> 140:97feb9bacc10 689
<> 140:97feb9bacc10 690 /** \brief STR Exclusive (16 bit)
<> 140:97feb9bacc10 691
<> 140:97feb9bacc10 692 This function executes a exclusive STR instruction for 16 bit values.
<> 140:97feb9bacc10 693
<> 140:97feb9bacc10 694 \param [in] value Value to store
<> 140:97feb9bacc10 695 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 696 \return 0 Function succeeded
<> 140:97feb9bacc10 697 \return 1 Function failed
<> 140:97feb9bacc10 698 */
<> 140:97feb9bacc10 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 140:97feb9bacc10 700 {
<> 140:97feb9bacc10 701 uint32_t result;
<> 140:97feb9bacc10 702
<> 140:97feb9bacc10 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 140:97feb9bacc10 704 return(result);
<> 140:97feb9bacc10 705 }
<> 140:97feb9bacc10 706
<> 140:97feb9bacc10 707
<> 140:97feb9bacc10 708 /** \brief STR Exclusive (32 bit)
<> 140:97feb9bacc10 709
<> 140:97feb9bacc10 710 This function executes a exclusive STR instruction for 32 bit values.
<> 140:97feb9bacc10 711
<> 140:97feb9bacc10 712 \param [in] value Value to store
<> 140:97feb9bacc10 713 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 714 \return 0 Function succeeded
<> 140:97feb9bacc10 715 \return 1 Function failed
<> 140:97feb9bacc10 716 */
<> 140:97feb9bacc10 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 140:97feb9bacc10 718 {
<> 140:97feb9bacc10 719 uint32_t result;
<> 140:97feb9bacc10 720
<> 140:97feb9bacc10 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 140:97feb9bacc10 722 return(result);
<> 140:97feb9bacc10 723 }
<> 140:97feb9bacc10 724
<> 140:97feb9bacc10 725
<> 140:97feb9bacc10 726 /** \brief Remove the exclusive lock
<> 140:97feb9bacc10 727
<> 140:97feb9bacc10 728 This function removes the exclusive lock which is created by LDREX.
<> 140:97feb9bacc10 729
<> 140:97feb9bacc10 730 */
<> 140:97feb9bacc10 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 140:97feb9bacc10 732 {
<> 140:97feb9bacc10 733 __ASM volatile ("clrex" ::: "memory");
<> 140:97feb9bacc10 734 }
<> 140:97feb9bacc10 735
<> 140:97feb9bacc10 736
<> 140:97feb9bacc10 737 /** \brief Signed Saturate
<> 140:97feb9bacc10 738
<> 140:97feb9bacc10 739 This function saturates a signed value.
<> 140:97feb9bacc10 740
<> 140:97feb9bacc10 741 \param [in] value Value to be saturated
<> 140:97feb9bacc10 742 \param [in] sat Bit position to saturate to (1..32)
<> 140:97feb9bacc10 743 \return Saturated value
<> 140:97feb9bacc10 744 */
<> 140:97feb9bacc10 745 #define __SSAT(ARG1,ARG2) \
<> 140:97feb9bacc10 746 ({ \
<> 140:97feb9bacc10 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 140:97feb9bacc10 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 140:97feb9bacc10 749 __RES; \
<> 140:97feb9bacc10 750 })
<> 140:97feb9bacc10 751
<> 140:97feb9bacc10 752
<> 140:97feb9bacc10 753 /** \brief Unsigned Saturate
<> 140:97feb9bacc10 754
<> 140:97feb9bacc10 755 This function saturates an unsigned value.
<> 140:97feb9bacc10 756
<> 140:97feb9bacc10 757 \param [in] value Value to be saturated
<> 140:97feb9bacc10 758 \param [in] sat Bit position to saturate to (0..31)
<> 140:97feb9bacc10 759 \return Saturated value
<> 140:97feb9bacc10 760 */
<> 140:97feb9bacc10 761 #define __USAT(ARG1,ARG2) \
<> 140:97feb9bacc10 762 ({ \
<> 140:97feb9bacc10 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 140:97feb9bacc10 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 140:97feb9bacc10 765 __RES; \
<> 140:97feb9bacc10 766 })
<> 140:97feb9bacc10 767
<> 140:97feb9bacc10 768
<> 140:97feb9bacc10 769 /** \brief Rotate Right with Extend (32 bit)
<> 140:97feb9bacc10 770
<> 140:97feb9bacc10 771 This function moves each bit of a bitstring right by one bit.
<> 140:97feb9bacc10 772 The carry input is shifted in at the left end of the bitstring.
<> 140:97feb9bacc10 773
<> 140:97feb9bacc10 774 \param [in] value Value to rotate
<> 140:97feb9bacc10 775 \return Rotated value
<> 140:97feb9bacc10 776 */
<> 140:97feb9bacc10 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 140:97feb9bacc10 778 {
<> 140:97feb9bacc10 779 uint32_t result;
<> 140:97feb9bacc10 780
<> 140:97feb9bacc10 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 140:97feb9bacc10 782 return(result);
<> 140:97feb9bacc10 783 }
<> 140:97feb9bacc10 784
<> 140:97feb9bacc10 785
<> 140:97feb9bacc10 786 /** \brief LDRT Unprivileged (8 bit)
<> 140:97feb9bacc10 787
<> 140:97feb9bacc10 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 140:97feb9bacc10 789
<> 140:97feb9bacc10 790 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 791 \return value of type uint8_t at (*ptr)
<> 140:97feb9bacc10 792 */
<> 140:97feb9bacc10 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 140:97feb9bacc10 794 {
<> 140:97feb9bacc10 795 uint32_t result;
<> 140:97feb9bacc10 796
<> 140:97feb9bacc10 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 140:97feb9bacc10 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 799 #else
<> 140:97feb9bacc10 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 140:97feb9bacc10 801 accepted by assembler. So has to use following less efficient pattern.
<> 140:97feb9bacc10 802 */
<> 140:97feb9bacc10 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 140:97feb9bacc10 804 #endif
<> 140:97feb9bacc10 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 140:97feb9bacc10 806 }
<> 140:97feb9bacc10 807
<> 140:97feb9bacc10 808
<> 140:97feb9bacc10 809 /** \brief LDRT Unprivileged (16 bit)
<> 140:97feb9bacc10 810
<> 140:97feb9bacc10 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 140:97feb9bacc10 812
<> 140:97feb9bacc10 813 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 814 \return value of type uint16_t at (*ptr)
<> 140:97feb9bacc10 815 */
<> 140:97feb9bacc10 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 140:97feb9bacc10 817 {
<> 140:97feb9bacc10 818 uint32_t result;
<> 140:97feb9bacc10 819
<> 140:97feb9bacc10 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 140:97feb9bacc10 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 822 #else
<> 140:97feb9bacc10 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 140:97feb9bacc10 824 accepted by assembler. So has to use following less efficient pattern.
<> 140:97feb9bacc10 825 */
<> 140:97feb9bacc10 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 140:97feb9bacc10 827 #endif
<> 140:97feb9bacc10 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 140:97feb9bacc10 829 }
<> 140:97feb9bacc10 830
<> 140:97feb9bacc10 831
<> 140:97feb9bacc10 832 /** \brief LDRT Unprivileged (32 bit)
<> 140:97feb9bacc10 833
<> 140:97feb9bacc10 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 140:97feb9bacc10 835
<> 140:97feb9bacc10 836 \param [in] ptr Pointer to data
<> 140:97feb9bacc10 837 \return value of type uint32_t at (*ptr)
<> 140:97feb9bacc10 838 */
<> 140:97feb9bacc10 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 140:97feb9bacc10 840 {
<> 140:97feb9bacc10 841 uint32_t result;
<> 140:97feb9bacc10 842
<> 140:97feb9bacc10 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 140:97feb9bacc10 844 return(result);
<> 140:97feb9bacc10 845 }
<> 140:97feb9bacc10 846
<> 140:97feb9bacc10 847
<> 140:97feb9bacc10 848 /** \brief STRT Unprivileged (8 bit)
<> 140:97feb9bacc10 849
<> 140:97feb9bacc10 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 140:97feb9bacc10 851
<> 140:97feb9bacc10 852 \param [in] value Value to store
<> 140:97feb9bacc10 853 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 854 */
<> 140:97feb9bacc10 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 140:97feb9bacc10 856 {
<> 140:97feb9bacc10 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 140:97feb9bacc10 858 }
<> 140:97feb9bacc10 859
<> 140:97feb9bacc10 860
<> 140:97feb9bacc10 861 /** \brief STRT Unprivileged (16 bit)
<> 140:97feb9bacc10 862
<> 140:97feb9bacc10 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 140:97feb9bacc10 864
<> 140:97feb9bacc10 865 \param [in] value Value to store
<> 140:97feb9bacc10 866 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 867 */
<> 140:97feb9bacc10 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 140:97feb9bacc10 869 {
<> 140:97feb9bacc10 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 140:97feb9bacc10 871 }
<> 140:97feb9bacc10 872
<> 140:97feb9bacc10 873
<> 140:97feb9bacc10 874 /** \brief STRT Unprivileged (32 bit)
<> 140:97feb9bacc10 875
<> 140:97feb9bacc10 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 140:97feb9bacc10 877
<> 140:97feb9bacc10 878 \param [in] value Value to store
<> 140:97feb9bacc10 879 \param [in] ptr Pointer to location
<> 140:97feb9bacc10 880 */
<> 140:97feb9bacc10 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 140:97feb9bacc10 882 {
<> 140:97feb9bacc10 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 140:97feb9bacc10 884 }
<> 140:97feb9bacc10 885
<> 140:97feb9bacc10 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 140:97feb9bacc10 887
<> 140:97feb9bacc10 888
<> 140:97feb9bacc10 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 140:97feb9bacc10 890 /* IAR iccarm specific functions */
<> 140:97feb9bacc10 891 #include <cmsis_iar.h>
<> 140:97feb9bacc10 892
<> 140:97feb9bacc10 893
<> 140:97feb9bacc10 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 140:97feb9bacc10 895 /* TI CCS specific functions */
<> 140:97feb9bacc10 896 #include <cmsis_ccs.h>
<> 140:97feb9bacc10 897
<> 140:97feb9bacc10 898
<> 140:97feb9bacc10 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 140:97feb9bacc10 900 /* TASKING carm specific functions */
<> 140:97feb9bacc10 901 /*
<> 140:97feb9bacc10 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 140:97feb9bacc10 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 140:97feb9bacc10 904 * Including the CMSIS ones.
<> 140:97feb9bacc10 905 */
<> 140:97feb9bacc10 906
<> 140:97feb9bacc10 907
<> 140:97feb9bacc10 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 140:97feb9bacc10 909 /* Cosmic specific functions */
<> 140:97feb9bacc10 910 #include <cmsis_csm.h>
<> 140:97feb9bacc10 911
<> 140:97feb9bacc10 912 #endif
<> 140:97feb9bacc10 913
<> 140:97feb9bacc10 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 140:97feb9bacc10 915
<> 140:97feb9bacc10 916 #endif /* __CORE_CMINSTR_H */