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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_cmFunc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_cmFunc.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 140:97feb9bacc10 4 * @version V4.10
<> 140:97feb9bacc10 5 * @date 18. March 2015
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #ifndef __CORE_CMFUNC_H
<> 140:97feb9bacc10 39 #define __CORE_CMFUNC_H
<> 140:97feb9bacc10 40
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 /* ########################### Core Function Access ########################### */
<> 140:97feb9bacc10 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 140:97feb9bacc10 45 @{
<> 140:97feb9bacc10 46 */
<> 140:97feb9bacc10 47
<> 140:97feb9bacc10 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 140:97feb9bacc10 49 /* ARM armcc specific functions */
<> 140:97feb9bacc10 50
<> 140:97feb9bacc10 51 #if (__ARMCC_VERSION < 400677)
<> 140:97feb9bacc10 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 140:97feb9bacc10 53 #endif
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 /* intrinsic void __enable_irq(); */
<> 140:97feb9bacc10 56 /* intrinsic void __disable_irq(); */
<> 140:97feb9bacc10 57
<> 140:97feb9bacc10 58 /** \brief Get Control Register
<> 140:97feb9bacc10 59
<> 140:97feb9bacc10 60 This function returns the content of the Control Register.
<> 140:97feb9bacc10 61
<> 140:97feb9bacc10 62 \return Control Register value
<> 140:97feb9bacc10 63 */
<> 140:97feb9bacc10 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 140:97feb9bacc10 65 {
<> 140:97feb9bacc10 66 register uint32_t __regControl __ASM("control");
<> 140:97feb9bacc10 67 return(__regControl);
<> 140:97feb9bacc10 68 }
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70
<> 140:97feb9bacc10 71 /** \brief Set Control Register
<> 140:97feb9bacc10 72
<> 140:97feb9bacc10 73 This function writes the given value to the Control Register.
<> 140:97feb9bacc10 74
<> 140:97feb9bacc10 75 \param [in] control Control Register value to set
<> 140:97feb9bacc10 76 */
<> 140:97feb9bacc10 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 140:97feb9bacc10 78 {
<> 140:97feb9bacc10 79 register uint32_t __regControl __ASM("control");
<> 140:97feb9bacc10 80 __regControl = control;
<> 140:97feb9bacc10 81 }
<> 140:97feb9bacc10 82
<> 140:97feb9bacc10 83
<> 140:97feb9bacc10 84 /** \brief Get IPSR Register
<> 140:97feb9bacc10 85
<> 140:97feb9bacc10 86 This function returns the content of the IPSR Register.
<> 140:97feb9bacc10 87
<> 140:97feb9bacc10 88 \return IPSR Register value
<> 140:97feb9bacc10 89 */
<> 140:97feb9bacc10 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 140:97feb9bacc10 91 {
<> 140:97feb9bacc10 92 register uint32_t __regIPSR __ASM("ipsr");
<> 140:97feb9bacc10 93 return(__regIPSR);
<> 140:97feb9bacc10 94 }
<> 140:97feb9bacc10 95
<> 140:97feb9bacc10 96
<> 140:97feb9bacc10 97 /** \brief Get APSR Register
<> 140:97feb9bacc10 98
<> 140:97feb9bacc10 99 This function returns the content of the APSR Register.
<> 140:97feb9bacc10 100
<> 140:97feb9bacc10 101 \return APSR Register value
<> 140:97feb9bacc10 102 */
<> 140:97feb9bacc10 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 140:97feb9bacc10 104 {
<> 140:97feb9bacc10 105 register uint32_t __regAPSR __ASM("apsr");
<> 140:97feb9bacc10 106 return(__regAPSR);
<> 140:97feb9bacc10 107 }
<> 140:97feb9bacc10 108
<> 140:97feb9bacc10 109
<> 140:97feb9bacc10 110 /** \brief Get xPSR Register
<> 140:97feb9bacc10 111
<> 140:97feb9bacc10 112 This function returns the content of the xPSR Register.
<> 140:97feb9bacc10 113
<> 140:97feb9bacc10 114 \return xPSR Register value
<> 140:97feb9bacc10 115 */
<> 140:97feb9bacc10 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 140:97feb9bacc10 117 {
<> 140:97feb9bacc10 118 register uint32_t __regXPSR __ASM("xpsr");
<> 140:97feb9bacc10 119 return(__regXPSR);
<> 140:97feb9bacc10 120 }
<> 140:97feb9bacc10 121
<> 140:97feb9bacc10 122
<> 140:97feb9bacc10 123 /** \brief Get Process Stack Pointer
<> 140:97feb9bacc10 124
<> 140:97feb9bacc10 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 140:97feb9bacc10 126
<> 140:97feb9bacc10 127 \return PSP Register value
<> 140:97feb9bacc10 128 */
<> 140:97feb9bacc10 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 140:97feb9bacc10 130 {
<> 140:97feb9bacc10 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 140:97feb9bacc10 132 return(__regProcessStackPointer);
<> 140:97feb9bacc10 133 }
<> 140:97feb9bacc10 134
<> 140:97feb9bacc10 135
<> 140:97feb9bacc10 136 /** \brief Set Process Stack Pointer
<> 140:97feb9bacc10 137
<> 140:97feb9bacc10 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 140:97feb9bacc10 139
<> 140:97feb9bacc10 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 140:97feb9bacc10 141 */
<> 140:97feb9bacc10 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 140:97feb9bacc10 143 {
<> 140:97feb9bacc10 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 140:97feb9bacc10 145 __regProcessStackPointer = topOfProcStack;
<> 140:97feb9bacc10 146 }
<> 140:97feb9bacc10 147
<> 140:97feb9bacc10 148
<> 140:97feb9bacc10 149 /** \brief Get Main Stack Pointer
<> 140:97feb9bacc10 150
<> 140:97feb9bacc10 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 140:97feb9bacc10 152
<> 140:97feb9bacc10 153 \return MSP Register value
<> 140:97feb9bacc10 154 */
<> 140:97feb9bacc10 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 140:97feb9bacc10 156 {
<> 140:97feb9bacc10 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 140:97feb9bacc10 158 return(__regMainStackPointer);
<> 140:97feb9bacc10 159 }
<> 140:97feb9bacc10 160
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 /** \brief Set Main Stack Pointer
<> 140:97feb9bacc10 163
<> 140:97feb9bacc10 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 140:97feb9bacc10 165
<> 140:97feb9bacc10 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 140:97feb9bacc10 167 */
<> 140:97feb9bacc10 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 140:97feb9bacc10 169 {
<> 140:97feb9bacc10 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 140:97feb9bacc10 171 __regMainStackPointer = topOfMainStack;
<> 140:97feb9bacc10 172 }
<> 140:97feb9bacc10 173
<> 140:97feb9bacc10 174
<> 140:97feb9bacc10 175 /** \brief Get Priority Mask
<> 140:97feb9bacc10 176
<> 140:97feb9bacc10 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 140:97feb9bacc10 178
<> 140:97feb9bacc10 179 \return Priority Mask value
<> 140:97feb9bacc10 180 */
<> 140:97feb9bacc10 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 140:97feb9bacc10 182 {
<> 140:97feb9bacc10 183 register uint32_t __regPriMask __ASM("primask");
<> 140:97feb9bacc10 184 return(__regPriMask);
<> 140:97feb9bacc10 185 }
<> 140:97feb9bacc10 186
<> 140:97feb9bacc10 187
<> 140:97feb9bacc10 188 /** \brief Set Priority Mask
<> 140:97feb9bacc10 189
<> 140:97feb9bacc10 190 This function assigns the given value to the Priority Mask Register.
<> 140:97feb9bacc10 191
<> 140:97feb9bacc10 192 \param [in] priMask Priority Mask
<> 140:97feb9bacc10 193 */
<> 140:97feb9bacc10 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 140:97feb9bacc10 195 {
<> 140:97feb9bacc10 196 register uint32_t __regPriMask __ASM("primask");
<> 140:97feb9bacc10 197 __regPriMask = (priMask);
<> 140:97feb9bacc10 198 }
<> 140:97feb9bacc10 199
<> 140:97feb9bacc10 200
<> 140:97feb9bacc10 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 140:97feb9bacc10 202
<> 140:97feb9bacc10 203 /** \brief Enable FIQ
<> 140:97feb9bacc10 204
<> 140:97feb9bacc10 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 140:97feb9bacc10 206 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 207 */
<> 140:97feb9bacc10 208 #define __enable_fault_irq __enable_fiq
<> 140:97feb9bacc10 209
<> 140:97feb9bacc10 210
<> 140:97feb9bacc10 211 /** \brief Disable FIQ
<> 140:97feb9bacc10 212
<> 140:97feb9bacc10 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 140:97feb9bacc10 214 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 215 */
<> 140:97feb9bacc10 216 #define __disable_fault_irq __disable_fiq
<> 140:97feb9bacc10 217
<> 140:97feb9bacc10 218
<> 140:97feb9bacc10 219 /** \brief Get Base Priority
<> 140:97feb9bacc10 220
<> 140:97feb9bacc10 221 This function returns the current value of the Base Priority register.
<> 140:97feb9bacc10 222
<> 140:97feb9bacc10 223 \return Base Priority register value
<> 140:97feb9bacc10 224 */
<> 140:97feb9bacc10 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 140:97feb9bacc10 226 {
<> 140:97feb9bacc10 227 register uint32_t __regBasePri __ASM("basepri");
<> 140:97feb9bacc10 228 return(__regBasePri);
<> 140:97feb9bacc10 229 }
<> 140:97feb9bacc10 230
<> 140:97feb9bacc10 231
<> 140:97feb9bacc10 232 /** \brief Set Base Priority
<> 140:97feb9bacc10 233
<> 140:97feb9bacc10 234 This function assigns the given value to the Base Priority register.
<> 140:97feb9bacc10 235
<> 140:97feb9bacc10 236 \param [in] basePri Base Priority value to set
<> 140:97feb9bacc10 237 */
<> 140:97feb9bacc10 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 140:97feb9bacc10 239 {
<> 140:97feb9bacc10 240 register uint32_t __regBasePri __ASM("basepri");
<> 140:97feb9bacc10 241 __regBasePri = (basePri & 0xff);
<> 140:97feb9bacc10 242 }
<> 140:97feb9bacc10 243
<> 140:97feb9bacc10 244
<> 140:97feb9bacc10 245 /** \brief Set Base Priority with condition
<> 140:97feb9bacc10 246
<> 140:97feb9bacc10 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 140:97feb9bacc10 248 or the new value increases the BASEPRI priority level.
<> 140:97feb9bacc10 249
<> 140:97feb9bacc10 250 \param [in] basePri Base Priority value to set
<> 140:97feb9bacc10 251 */
<> 140:97feb9bacc10 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 140:97feb9bacc10 253 {
<> 140:97feb9bacc10 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 140:97feb9bacc10 255 __regBasePriMax = (basePri & 0xff);
<> 140:97feb9bacc10 256 }
<> 140:97feb9bacc10 257
<> 140:97feb9bacc10 258
<> 140:97feb9bacc10 259 /** \brief Get Fault Mask
<> 140:97feb9bacc10 260
<> 140:97feb9bacc10 261 This function returns the current value of the Fault Mask register.
<> 140:97feb9bacc10 262
<> 140:97feb9bacc10 263 \return Fault Mask register value
<> 140:97feb9bacc10 264 */
<> 140:97feb9bacc10 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 140:97feb9bacc10 266 {
<> 140:97feb9bacc10 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 140:97feb9bacc10 268 return(__regFaultMask);
<> 140:97feb9bacc10 269 }
<> 140:97feb9bacc10 270
<> 140:97feb9bacc10 271
<> 140:97feb9bacc10 272 /** \brief Set Fault Mask
<> 140:97feb9bacc10 273
<> 140:97feb9bacc10 274 This function assigns the given value to the Fault Mask register.
<> 140:97feb9bacc10 275
<> 140:97feb9bacc10 276 \param [in] faultMask Fault Mask value to set
<> 140:97feb9bacc10 277 */
<> 140:97feb9bacc10 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 140:97feb9bacc10 279 {
<> 140:97feb9bacc10 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 140:97feb9bacc10 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 140:97feb9bacc10 282 }
<> 140:97feb9bacc10 283
<> 140:97feb9bacc10 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 140:97feb9bacc10 285
<> 140:97feb9bacc10 286
<> 140:97feb9bacc10 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 140:97feb9bacc10 288
<> 140:97feb9bacc10 289 /** \brief Get FPSCR
<> 140:97feb9bacc10 290
<> 140:97feb9bacc10 291 This function returns the current value of the Floating Point Status/Control register.
<> 140:97feb9bacc10 292
<> 140:97feb9bacc10 293 \return Floating Point Status/Control register value
<> 140:97feb9bacc10 294 */
<> 140:97feb9bacc10 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 140:97feb9bacc10 296 {
<> 140:97feb9bacc10 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 298 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 299 return(__regfpscr);
<> 140:97feb9bacc10 300 #else
<> 140:97feb9bacc10 301 return(0);
<> 140:97feb9bacc10 302 #endif
<> 140:97feb9bacc10 303 }
<> 140:97feb9bacc10 304
<> 140:97feb9bacc10 305
<> 140:97feb9bacc10 306 /** \brief Set FPSCR
<> 140:97feb9bacc10 307
<> 140:97feb9bacc10 308 This function assigns the given value to the Floating Point Status/Control register.
<> 140:97feb9bacc10 309
<> 140:97feb9bacc10 310 \param [in] fpscr Floating Point Status/Control value to set
<> 140:97feb9bacc10 311 */
<> 140:97feb9bacc10 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 140:97feb9bacc10 313 {
<> 140:97feb9bacc10 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 315 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 316 __regfpscr = (fpscr);
<> 140:97feb9bacc10 317 #endif
<> 140:97feb9bacc10 318 }
<> 140:97feb9bacc10 319
<> 140:97feb9bacc10 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 140:97feb9bacc10 321
<> 140:97feb9bacc10 322
<> 140:97feb9bacc10 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 140:97feb9bacc10 324 /* GNU gcc specific functions */
<> 140:97feb9bacc10 325
<> 140:97feb9bacc10 326 /** \brief Enable IRQ Interrupts
<> 140:97feb9bacc10 327
<> 140:97feb9bacc10 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 140:97feb9bacc10 329 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 330 */
<> 140:97feb9bacc10 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 140:97feb9bacc10 332 {
<> 140:97feb9bacc10 333 __ASM volatile ("cpsie i" : : : "memory");
<> 140:97feb9bacc10 334 }
<> 140:97feb9bacc10 335
<> 140:97feb9bacc10 336
<> 140:97feb9bacc10 337 /** \brief Disable IRQ Interrupts
<> 140:97feb9bacc10 338
<> 140:97feb9bacc10 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 140:97feb9bacc10 340 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 341 */
<> 140:97feb9bacc10 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 140:97feb9bacc10 343 {
<> 140:97feb9bacc10 344 __ASM volatile ("cpsid i" : : : "memory");
<> 140:97feb9bacc10 345 }
<> 140:97feb9bacc10 346
<> 140:97feb9bacc10 347
<> 140:97feb9bacc10 348 /** \brief Get Control Register
<> 140:97feb9bacc10 349
<> 140:97feb9bacc10 350 This function returns the content of the Control Register.
<> 140:97feb9bacc10 351
<> 140:97feb9bacc10 352 \return Control Register value
<> 140:97feb9bacc10 353 */
<> 140:97feb9bacc10 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 140:97feb9bacc10 355 {
<> 140:97feb9bacc10 356 uint32_t result;
<> 140:97feb9bacc10 357
<> 140:97feb9bacc10 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 140:97feb9bacc10 359 return(result);
<> 140:97feb9bacc10 360 }
<> 140:97feb9bacc10 361
<> 140:97feb9bacc10 362
<> 140:97feb9bacc10 363 /** \brief Set Control Register
<> 140:97feb9bacc10 364
<> 140:97feb9bacc10 365 This function writes the given value to the Control Register.
<> 140:97feb9bacc10 366
<> 140:97feb9bacc10 367 \param [in] control Control Register value to set
<> 140:97feb9bacc10 368 */
<> 140:97feb9bacc10 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 140:97feb9bacc10 370 {
<> 140:97feb9bacc10 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 140:97feb9bacc10 372 }
<> 140:97feb9bacc10 373
<> 140:97feb9bacc10 374
<> 140:97feb9bacc10 375 /** \brief Get IPSR Register
<> 140:97feb9bacc10 376
<> 140:97feb9bacc10 377 This function returns the content of the IPSR Register.
<> 140:97feb9bacc10 378
<> 140:97feb9bacc10 379 \return IPSR Register value
<> 140:97feb9bacc10 380 */
<> 140:97feb9bacc10 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 140:97feb9bacc10 382 {
<> 140:97feb9bacc10 383 uint32_t result;
<> 140:97feb9bacc10 384
<> 140:97feb9bacc10 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 140:97feb9bacc10 386 return(result);
<> 140:97feb9bacc10 387 }
<> 140:97feb9bacc10 388
<> 140:97feb9bacc10 389
<> 140:97feb9bacc10 390 /** \brief Get APSR Register
<> 140:97feb9bacc10 391
<> 140:97feb9bacc10 392 This function returns the content of the APSR Register.
<> 140:97feb9bacc10 393
<> 140:97feb9bacc10 394 \return APSR Register value
<> 140:97feb9bacc10 395 */
<> 140:97feb9bacc10 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 140:97feb9bacc10 397 {
<> 140:97feb9bacc10 398 uint32_t result;
<> 140:97feb9bacc10 399
<> 140:97feb9bacc10 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 140:97feb9bacc10 401 return(result);
<> 140:97feb9bacc10 402 }
<> 140:97feb9bacc10 403
<> 140:97feb9bacc10 404
<> 140:97feb9bacc10 405 /** \brief Get xPSR Register
<> 140:97feb9bacc10 406
<> 140:97feb9bacc10 407 This function returns the content of the xPSR Register.
<> 140:97feb9bacc10 408
<> 140:97feb9bacc10 409 \return xPSR Register value
<> 140:97feb9bacc10 410 */
<> 140:97feb9bacc10 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 140:97feb9bacc10 412 {
<> 140:97feb9bacc10 413 uint32_t result;
<> 140:97feb9bacc10 414
<> 140:97feb9bacc10 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 140:97feb9bacc10 416 return(result);
<> 140:97feb9bacc10 417 }
<> 140:97feb9bacc10 418
<> 140:97feb9bacc10 419
<> 140:97feb9bacc10 420 /** \brief Get Process Stack Pointer
<> 140:97feb9bacc10 421
<> 140:97feb9bacc10 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 140:97feb9bacc10 423
<> 140:97feb9bacc10 424 \return PSP Register value
<> 140:97feb9bacc10 425 */
<> 140:97feb9bacc10 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 140:97feb9bacc10 427 {
<> 140:97feb9bacc10 428 register uint32_t result;
<> 140:97feb9bacc10 429
<> 140:97feb9bacc10 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 140:97feb9bacc10 431 return(result);
<> 140:97feb9bacc10 432 }
<> 140:97feb9bacc10 433
<> 140:97feb9bacc10 434
<> 140:97feb9bacc10 435 /** \brief Set Process Stack Pointer
<> 140:97feb9bacc10 436
<> 140:97feb9bacc10 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 140:97feb9bacc10 438
<> 140:97feb9bacc10 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 140:97feb9bacc10 440 */
<> 140:97feb9bacc10 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 140:97feb9bacc10 442 {
<> 140:97feb9bacc10 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 140:97feb9bacc10 444 }
<> 140:97feb9bacc10 445
<> 140:97feb9bacc10 446
<> 140:97feb9bacc10 447 /** \brief Get Main Stack Pointer
<> 140:97feb9bacc10 448
<> 140:97feb9bacc10 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 140:97feb9bacc10 450
<> 140:97feb9bacc10 451 \return MSP Register value
<> 140:97feb9bacc10 452 */
<> 140:97feb9bacc10 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 140:97feb9bacc10 454 {
<> 140:97feb9bacc10 455 register uint32_t result;
<> 140:97feb9bacc10 456
<> 140:97feb9bacc10 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 140:97feb9bacc10 458 return(result);
<> 140:97feb9bacc10 459 }
<> 140:97feb9bacc10 460
<> 140:97feb9bacc10 461
<> 140:97feb9bacc10 462 /** \brief Set Main Stack Pointer
<> 140:97feb9bacc10 463
<> 140:97feb9bacc10 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 140:97feb9bacc10 465
<> 140:97feb9bacc10 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 140:97feb9bacc10 467 */
<> 140:97feb9bacc10 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 140:97feb9bacc10 469 {
<> 140:97feb9bacc10 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 140:97feb9bacc10 471 }
<> 140:97feb9bacc10 472
<> 140:97feb9bacc10 473
<> 140:97feb9bacc10 474 /** \brief Get Priority Mask
<> 140:97feb9bacc10 475
<> 140:97feb9bacc10 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 140:97feb9bacc10 477
<> 140:97feb9bacc10 478 \return Priority Mask value
<> 140:97feb9bacc10 479 */
<> 140:97feb9bacc10 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 140:97feb9bacc10 481 {
<> 140:97feb9bacc10 482 uint32_t result;
<> 140:97feb9bacc10 483
<> 140:97feb9bacc10 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 140:97feb9bacc10 485 return(result);
<> 140:97feb9bacc10 486 }
<> 140:97feb9bacc10 487
<> 140:97feb9bacc10 488
<> 140:97feb9bacc10 489 /** \brief Set Priority Mask
<> 140:97feb9bacc10 490
<> 140:97feb9bacc10 491 This function assigns the given value to the Priority Mask Register.
<> 140:97feb9bacc10 492
<> 140:97feb9bacc10 493 \param [in] priMask Priority Mask
<> 140:97feb9bacc10 494 */
<> 140:97feb9bacc10 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 140:97feb9bacc10 496 {
<> 140:97feb9bacc10 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 140:97feb9bacc10 498 }
<> 140:97feb9bacc10 499
<> 140:97feb9bacc10 500
<> 140:97feb9bacc10 501 #if (__CORTEX_M >= 0x03)
<> 140:97feb9bacc10 502
<> 140:97feb9bacc10 503 /** \brief Enable FIQ
<> 140:97feb9bacc10 504
<> 140:97feb9bacc10 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 140:97feb9bacc10 506 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 507 */
<> 140:97feb9bacc10 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 140:97feb9bacc10 509 {
<> 140:97feb9bacc10 510 __ASM volatile ("cpsie f" : : : "memory");
<> 140:97feb9bacc10 511 }
<> 140:97feb9bacc10 512
<> 140:97feb9bacc10 513
<> 140:97feb9bacc10 514 /** \brief Disable FIQ
<> 140:97feb9bacc10 515
<> 140:97feb9bacc10 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 140:97feb9bacc10 517 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 518 */
<> 140:97feb9bacc10 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 140:97feb9bacc10 520 {
<> 140:97feb9bacc10 521 __ASM volatile ("cpsid f" : : : "memory");
<> 140:97feb9bacc10 522 }
<> 140:97feb9bacc10 523
<> 140:97feb9bacc10 524
<> 140:97feb9bacc10 525 /** \brief Get Base Priority
<> 140:97feb9bacc10 526
<> 140:97feb9bacc10 527 This function returns the current value of the Base Priority register.
<> 140:97feb9bacc10 528
<> 140:97feb9bacc10 529 \return Base Priority register value
<> 140:97feb9bacc10 530 */
<> 140:97feb9bacc10 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 140:97feb9bacc10 532 {
<> 140:97feb9bacc10 533 uint32_t result;
<> 140:97feb9bacc10 534
<> 140:97feb9bacc10 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 140:97feb9bacc10 536 return(result);
<> 140:97feb9bacc10 537 }
<> 140:97feb9bacc10 538
<> 140:97feb9bacc10 539
<> 140:97feb9bacc10 540 /** \brief Set Base Priority
<> 140:97feb9bacc10 541
<> 140:97feb9bacc10 542 This function assigns the given value to the Base Priority register.
<> 140:97feb9bacc10 543
<> 140:97feb9bacc10 544 \param [in] basePri Base Priority value to set
<> 140:97feb9bacc10 545 */
<> 140:97feb9bacc10 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 140:97feb9bacc10 547 {
<> 140:97feb9bacc10 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 140:97feb9bacc10 549 }
<> 140:97feb9bacc10 550
<> 140:97feb9bacc10 551
<> 140:97feb9bacc10 552 /** \brief Set Base Priority with condition
<> 140:97feb9bacc10 553
<> 140:97feb9bacc10 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 140:97feb9bacc10 555 or the new value increases the BASEPRI priority level.
<> 140:97feb9bacc10 556
<> 140:97feb9bacc10 557 \param [in] basePri Base Priority value to set
<> 140:97feb9bacc10 558 */
<> 140:97feb9bacc10 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 140:97feb9bacc10 560 {
<> 140:97feb9bacc10 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 140:97feb9bacc10 562 }
<> 140:97feb9bacc10 563
<> 140:97feb9bacc10 564
<> 140:97feb9bacc10 565 /** \brief Get Fault Mask
<> 140:97feb9bacc10 566
<> 140:97feb9bacc10 567 This function returns the current value of the Fault Mask register.
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 \return Fault Mask register value
<> 140:97feb9bacc10 570 */
<> 140:97feb9bacc10 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 140:97feb9bacc10 572 {
<> 140:97feb9bacc10 573 uint32_t result;
<> 140:97feb9bacc10 574
<> 140:97feb9bacc10 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 140:97feb9bacc10 576 return(result);
<> 140:97feb9bacc10 577 }
<> 140:97feb9bacc10 578
<> 140:97feb9bacc10 579
<> 140:97feb9bacc10 580 /** \brief Set Fault Mask
<> 140:97feb9bacc10 581
<> 140:97feb9bacc10 582 This function assigns the given value to the Fault Mask register.
<> 140:97feb9bacc10 583
<> 140:97feb9bacc10 584 \param [in] faultMask Fault Mask value to set
<> 140:97feb9bacc10 585 */
<> 140:97feb9bacc10 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 140:97feb9bacc10 587 {
<> 140:97feb9bacc10 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 140:97feb9bacc10 589 }
<> 140:97feb9bacc10 590
<> 140:97feb9bacc10 591 #endif /* (__CORTEX_M >= 0x03) */
<> 140:97feb9bacc10 592
<> 140:97feb9bacc10 593
<> 140:97feb9bacc10 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 140:97feb9bacc10 595
<> 140:97feb9bacc10 596 /** \brief Get FPSCR
<> 140:97feb9bacc10 597
<> 140:97feb9bacc10 598 This function returns the current value of the Floating Point Status/Control register.
<> 140:97feb9bacc10 599
<> 140:97feb9bacc10 600 \return Floating Point Status/Control register value
<> 140:97feb9bacc10 601 */
<> 140:97feb9bacc10 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 140:97feb9bacc10 603 {
<> 140:97feb9bacc10 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 605 uint32_t result;
<> 140:97feb9bacc10 606
<> 140:97feb9bacc10 607 /* Empty asm statement works as a scheduling barrier */
<> 140:97feb9bacc10 608 __ASM volatile ("");
<> 140:97feb9bacc10 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 140:97feb9bacc10 610 __ASM volatile ("");
<> 140:97feb9bacc10 611 return(result);
<> 140:97feb9bacc10 612 #else
<> 140:97feb9bacc10 613 return(0);
<> 140:97feb9bacc10 614 #endif
<> 140:97feb9bacc10 615 }
<> 140:97feb9bacc10 616
<> 140:97feb9bacc10 617
<> 140:97feb9bacc10 618 /** \brief Set FPSCR
<> 140:97feb9bacc10 619
<> 140:97feb9bacc10 620 This function assigns the given value to the Floating Point Status/Control register.
<> 140:97feb9bacc10 621
<> 140:97feb9bacc10 622 \param [in] fpscr Floating Point Status/Control value to set
<> 140:97feb9bacc10 623 */
<> 140:97feb9bacc10 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 140:97feb9bacc10 625 {
<> 140:97feb9bacc10 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 627 /* Empty asm statement works as a scheduling barrier */
<> 140:97feb9bacc10 628 __ASM volatile ("");
<> 140:97feb9bacc10 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 140:97feb9bacc10 630 __ASM volatile ("");
<> 140:97feb9bacc10 631 #endif
<> 140:97feb9bacc10 632 }
<> 140:97feb9bacc10 633
<> 140:97feb9bacc10 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 140:97feb9bacc10 635
<> 140:97feb9bacc10 636
<> 140:97feb9bacc10 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 140:97feb9bacc10 638 /* IAR iccarm specific functions */
<> 140:97feb9bacc10 639 #include <cmsis_iar.h>
<> 140:97feb9bacc10 640
<> 140:97feb9bacc10 641
<> 140:97feb9bacc10 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 140:97feb9bacc10 643 /* TI CCS specific functions */
<> 140:97feb9bacc10 644 #include <cmsis_ccs.h>
<> 140:97feb9bacc10 645
<> 140:97feb9bacc10 646
<> 140:97feb9bacc10 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 140:97feb9bacc10 648 /* TASKING carm specific functions */
<> 140:97feb9bacc10 649 /*
<> 140:97feb9bacc10 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 140:97feb9bacc10 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 140:97feb9bacc10 652 * Including the CMSIS ones.
<> 140:97feb9bacc10 653 */
<> 140:97feb9bacc10 654
<> 140:97feb9bacc10 655
<> 140:97feb9bacc10 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 140:97feb9bacc10 657 /* Cosmic specific functions */
<> 140:97feb9bacc10 658 #include <cmsis_csm.h>
<> 140:97feb9bacc10 659
<> 140:97feb9bacc10 660 #endif
<> 140:97feb9bacc10 661
<> 140:97feb9bacc10 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 140:97feb9bacc10 663
<> 140:97feb9bacc10 664 #endif /* __CORE_CMFUNC_H */