The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Child:
145:64910690c574
Release 140 of the mbed library

Ports for Upcoming Targets

3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841
3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992

Fixes and Changes

3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951
4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021
3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979
3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990
4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003
4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012
4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020
4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065
4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014
4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030
4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109
3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_cm7.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
<> 140:97feb9bacc10 4 * @version V4.10
<> 140:97feb9bacc10 5 * @date 18. March 2015
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #if defined ( __ICCARM__ )
<> 140:97feb9bacc10 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 140:97feb9bacc10 40 #endif
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 #ifndef __CORE_CM7_H_GENERIC
<> 140:97feb9bacc10 43 #define __CORE_CM7_H_GENERIC
<> 140:97feb9bacc10 44
<> 140:97feb9bacc10 45 #ifdef __cplusplus
<> 140:97feb9bacc10 46 extern "C" {
<> 140:97feb9bacc10 47 #endif
<> 140:97feb9bacc10 48
<> 140:97feb9bacc10 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 140:97feb9bacc10 50 CMSIS violates the following MISRA-C:2004 rules:
<> 140:97feb9bacc10 51
<> 140:97feb9bacc10 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 140:97feb9bacc10 53 Function definitions in header files are used to allow 'inlining'.
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 140:97feb9bacc10 56 Unions are used for effective representation of core registers.
<> 140:97feb9bacc10 57
<> 140:97feb9bacc10 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 140:97feb9bacc10 59 Function-like macros are used to allow more efficient code.
<> 140:97feb9bacc10 60 */
<> 140:97feb9bacc10 61
<> 140:97feb9bacc10 62
<> 140:97feb9bacc10 63 /*******************************************************************************
<> 140:97feb9bacc10 64 * CMSIS definitions
<> 140:97feb9bacc10 65 ******************************************************************************/
<> 140:97feb9bacc10 66 /** \ingroup Cortex_M7
<> 140:97feb9bacc10 67 @{
<> 140:97feb9bacc10 68 */
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70 /* CMSIS CM7 definitions */
<> 140:97feb9bacc10 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 140:97feb9bacc10 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 140:97feb9bacc10 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
<> 140:97feb9bacc10 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 140:97feb9bacc10 75
<> 140:97feb9bacc10 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
<> 140:97feb9bacc10 77
<> 140:97feb9bacc10 78
<> 140:97feb9bacc10 79 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 140:97feb9bacc10 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 140:97feb9bacc10 82 #define __STATIC_INLINE static __inline
<> 140:97feb9bacc10 83
<> 140:97feb9bacc10 84 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 140:97feb9bacc10 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 140:97feb9bacc10 87 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 88
<> 140:97feb9bacc10 89 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 140:97feb9bacc10 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 140:97feb9bacc10 92 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 93
<> 140:97feb9bacc10 94 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 140:97feb9bacc10 96 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 97
<> 140:97feb9bacc10 98 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 140:97feb9bacc10 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 140:97feb9bacc10 101 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 102
<> 140:97feb9bacc10 103 #elif defined ( __CSMC__ )
<> 140:97feb9bacc10 104 #define __packed
<> 140:97feb9bacc10 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 140:97feb9bacc10 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 140:97feb9bacc10 107 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 108
<> 140:97feb9bacc10 109 #endif
<> 140:97feb9bacc10 110
<> 140:97feb9bacc10 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 140:97feb9bacc10 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 140:97feb9bacc10 113 */
<> 140:97feb9bacc10 114 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 115 #if defined __TARGET_FPU_VFP
<> 140:97feb9bacc10 116 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 117 #define __FPU_USED 1
<> 140:97feb9bacc10 118 #else
<> 140:97feb9bacc10 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 120 #define __FPU_USED 0
<> 140:97feb9bacc10 121 #endif
<> 140:97feb9bacc10 122 #else
<> 140:97feb9bacc10 123 #define __FPU_USED 0
<> 140:97feb9bacc10 124 #endif
<> 140:97feb9bacc10 125
<> 140:97feb9bacc10 126 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 140:97feb9bacc10 128 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 129 #define __FPU_USED 1
<> 140:97feb9bacc10 130 #else
<> 140:97feb9bacc10 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 132 #define __FPU_USED 0
<> 140:97feb9bacc10 133 #endif
<> 140:97feb9bacc10 134 #else
<> 140:97feb9bacc10 135 #define __FPU_USED 0
<> 140:97feb9bacc10 136 #endif
<> 140:97feb9bacc10 137
<> 140:97feb9bacc10 138 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 139 #if defined __ARMVFP__
<> 140:97feb9bacc10 140 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 141 #define __FPU_USED 1
<> 140:97feb9bacc10 142 #else
<> 140:97feb9bacc10 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 144 #define __FPU_USED 0
<> 140:97feb9bacc10 145 #endif
<> 140:97feb9bacc10 146 #else
<> 140:97feb9bacc10 147 #define __FPU_USED 0
<> 140:97feb9bacc10 148 #endif
<> 140:97feb9bacc10 149
<> 140:97feb9bacc10 150 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 151 #if defined __TI_VFP_SUPPORT__
<> 140:97feb9bacc10 152 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 153 #define __FPU_USED 1
<> 140:97feb9bacc10 154 #else
<> 140:97feb9bacc10 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 156 #define __FPU_USED 0
<> 140:97feb9bacc10 157 #endif
<> 140:97feb9bacc10 158 #else
<> 140:97feb9bacc10 159 #define __FPU_USED 0
<> 140:97feb9bacc10 160 #endif
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 163 #if defined __FPU_VFP__
<> 140:97feb9bacc10 164 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 165 #define __FPU_USED 1
<> 140:97feb9bacc10 166 #else
<> 140:97feb9bacc10 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 168 #define __FPU_USED 0
<> 140:97feb9bacc10 169 #endif
<> 140:97feb9bacc10 170 #else
<> 140:97feb9bacc10 171 #define __FPU_USED 0
<> 140:97feb9bacc10 172 #endif
<> 140:97feb9bacc10 173
<> 140:97feb9bacc10 174 #elif defined ( __CSMC__ ) /* Cosmic */
<> 140:97feb9bacc10 175 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 140:97feb9bacc10 176 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 177 #define __FPU_USED 1
<> 140:97feb9bacc10 178 #else
<> 140:97feb9bacc10 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 180 #define __FPU_USED 0
<> 140:97feb9bacc10 181 #endif
<> 140:97feb9bacc10 182 #else
<> 140:97feb9bacc10 183 #define __FPU_USED 0
<> 140:97feb9bacc10 184 #endif
<> 140:97feb9bacc10 185 #endif
<> 140:97feb9bacc10 186
<> 140:97feb9bacc10 187 #include <stdint.h> /* standard types definitions */
<> 140:97feb9bacc10 188 #include <core_cmInstr.h> /* Core Instruction Access */
<> 140:97feb9bacc10 189 #include <core_cmFunc.h> /* Core Function Access */
<> 140:97feb9bacc10 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
<> 140:97feb9bacc10 191
<> 140:97feb9bacc10 192 #ifdef __cplusplus
<> 140:97feb9bacc10 193 }
<> 140:97feb9bacc10 194 #endif
<> 140:97feb9bacc10 195
<> 140:97feb9bacc10 196 #endif /* __CORE_CM7_H_GENERIC */
<> 140:97feb9bacc10 197
<> 140:97feb9bacc10 198 #ifndef __CMSIS_GENERIC
<> 140:97feb9bacc10 199
<> 140:97feb9bacc10 200 #ifndef __CORE_CM7_H_DEPENDANT
<> 140:97feb9bacc10 201 #define __CORE_CM7_H_DEPENDANT
<> 140:97feb9bacc10 202
<> 140:97feb9bacc10 203 #ifdef __cplusplus
<> 140:97feb9bacc10 204 extern "C" {
<> 140:97feb9bacc10 205 #endif
<> 140:97feb9bacc10 206
<> 140:97feb9bacc10 207 /* check device defines and use defaults */
<> 140:97feb9bacc10 208 #if defined __CHECK_DEVICE_DEFINES
<> 140:97feb9bacc10 209 #ifndef __CM7_REV
<> 140:97feb9bacc10 210 #define __CM7_REV 0x0000
<> 140:97feb9bacc10 211 #warning "__CM7_REV not defined in device header file; using default!"
<> 140:97feb9bacc10 212 #endif
<> 140:97feb9bacc10 213
<> 140:97feb9bacc10 214 #ifndef __FPU_PRESENT
<> 140:97feb9bacc10 215 #define __FPU_PRESENT 0
<> 140:97feb9bacc10 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 217 #endif
<> 140:97feb9bacc10 218
<> 140:97feb9bacc10 219 #ifndef __MPU_PRESENT
<> 140:97feb9bacc10 220 #define __MPU_PRESENT 0
<> 140:97feb9bacc10 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 222 #endif
<> 140:97feb9bacc10 223
<> 140:97feb9bacc10 224 #ifndef __ICACHE_PRESENT
<> 140:97feb9bacc10 225 #define __ICACHE_PRESENT 0
<> 140:97feb9bacc10 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 227 #endif
<> 140:97feb9bacc10 228
<> 140:97feb9bacc10 229 #ifndef __DCACHE_PRESENT
<> 140:97feb9bacc10 230 #define __DCACHE_PRESENT 0
<> 140:97feb9bacc10 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 232 #endif
<> 140:97feb9bacc10 233
<> 140:97feb9bacc10 234 #ifndef __DTCM_PRESENT
<> 140:97feb9bacc10 235 #define __DTCM_PRESENT 0
<> 140:97feb9bacc10 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 237 #endif
<> 140:97feb9bacc10 238
<> 140:97feb9bacc10 239 #ifndef __NVIC_PRIO_BITS
<> 140:97feb9bacc10 240 #define __NVIC_PRIO_BITS 3
<> 140:97feb9bacc10 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 140:97feb9bacc10 242 #endif
<> 140:97feb9bacc10 243
<> 140:97feb9bacc10 244 #ifndef __Vendor_SysTickConfig
<> 140:97feb9bacc10 245 #define __Vendor_SysTickConfig 0
<> 140:97feb9bacc10 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 140:97feb9bacc10 247 #endif
<> 140:97feb9bacc10 248 #endif
<> 140:97feb9bacc10 249
<> 140:97feb9bacc10 250 /* IO definitions (access restrictions to peripheral registers) */
<> 140:97feb9bacc10 251 /**
<> 140:97feb9bacc10 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 140:97feb9bacc10 253
<> 140:97feb9bacc10 254 <strong>IO Type Qualifiers</strong> are used
<> 140:97feb9bacc10 255 \li to specify the access to peripheral variables.
<> 140:97feb9bacc10 256 \li for automatic generation of peripheral register debug information.
<> 140:97feb9bacc10 257 */
<> 140:97feb9bacc10 258 #ifdef __cplusplus
<> 140:97feb9bacc10 259 #define __I volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 260 #else
<> 140:97feb9bacc10 261 #define __I volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 262 #endif
<> 140:97feb9bacc10 263 #define __O volatile /*!< Defines 'write only' permissions */
<> 140:97feb9bacc10 264 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 265
<> 140:97feb9bacc10 266 #ifdef __cplusplus
<> 140:97feb9bacc10 267 #define __IM volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 268 #else
<> 140:97feb9bacc10 269 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 270 #endif
<> 140:97feb9bacc10 271 #define __OM volatile /*!< Defines 'write only' permissions */
<> 140:97feb9bacc10 272 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 273
<> 140:97feb9bacc10 274 /*@} end of group Cortex_M7 */
<> 140:97feb9bacc10 275
<> 140:97feb9bacc10 276
<> 140:97feb9bacc10 277
<> 140:97feb9bacc10 278 /*******************************************************************************
<> 140:97feb9bacc10 279 * Register Abstraction
<> 140:97feb9bacc10 280 Core Register contain:
<> 140:97feb9bacc10 281 - Core Register
<> 140:97feb9bacc10 282 - Core NVIC Register
<> 140:97feb9bacc10 283 - Core SCB Register
<> 140:97feb9bacc10 284 - Core SysTick Register
<> 140:97feb9bacc10 285 - Core Debug Register
<> 140:97feb9bacc10 286 - Core MPU Register
<> 140:97feb9bacc10 287 - Core FPU Register
<> 140:97feb9bacc10 288 ******************************************************************************/
<> 140:97feb9bacc10 289 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 140:97feb9bacc10 290 \brief Type definitions and defines for Cortex-M processor based devices.
<> 140:97feb9bacc10 291 */
<> 140:97feb9bacc10 292
<> 140:97feb9bacc10 293 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 294 \defgroup CMSIS_CORE Status and Control Registers
<> 140:97feb9bacc10 295 \brief Core Register type definitions.
<> 140:97feb9bacc10 296 @{
<> 140:97feb9bacc10 297 */
<> 140:97feb9bacc10 298
<> 140:97feb9bacc10 299 /** \brief Union type to access the Application Program Status Register (APSR).
<> 140:97feb9bacc10 300 */
<> 140:97feb9bacc10 301 typedef union
<> 140:97feb9bacc10 302 {
<> 140:97feb9bacc10 303 struct
<> 140:97feb9bacc10 304 {
<> 140:97feb9bacc10 305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 140:97feb9bacc10 306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 140:97feb9bacc10 307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
<> 140:97feb9bacc10 308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 140:97feb9bacc10 309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 313 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 314 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 315 } APSR_Type;
<> 140:97feb9bacc10 316
<> 140:97feb9bacc10 317 /* APSR Register Definitions */
<> 140:97feb9bacc10 318 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 140:97feb9bacc10 319 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 140:97feb9bacc10 320
<> 140:97feb9bacc10 321 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 140:97feb9bacc10 322 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 140:97feb9bacc10 325 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 140:97feb9bacc10 326
<> 140:97feb9bacc10 327 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 140:97feb9bacc10 328 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 140:97feb9bacc10 329
<> 140:97feb9bacc10 330 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
<> 140:97feb9bacc10 331 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 140:97feb9bacc10 332
<> 140:97feb9bacc10 333 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
<> 140:97feb9bacc10 334 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
<> 140:97feb9bacc10 335
<> 140:97feb9bacc10 336
<> 140:97feb9bacc10 337 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 140:97feb9bacc10 338 */
<> 140:97feb9bacc10 339 typedef union
<> 140:97feb9bacc10 340 {
<> 140:97feb9bacc10 341 struct
<> 140:97feb9bacc10 342 {
<> 140:97feb9bacc10 343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 140:97feb9bacc10 345 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 346 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 347 } IPSR_Type;
<> 140:97feb9bacc10 348
<> 140:97feb9bacc10 349 /* IPSR Register Definitions */
<> 140:97feb9bacc10 350 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 140:97feb9bacc10 351 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 140:97feb9bacc10 352
<> 140:97feb9bacc10 353
<> 140:97feb9bacc10 354 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 140:97feb9bacc10 355 */
<> 140:97feb9bacc10 356 typedef union
<> 140:97feb9bacc10 357 {
<> 140:97feb9bacc10 358 struct
<> 140:97feb9bacc10 359 {
<> 140:97feb9bacc10 360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
<> 140:97feb9bacc10 362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 140:97feb9bacc10 363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
<> 140:97feb9bacc10 364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 140:97feb9bacc10 365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
<> 140:97feb9bacc10 366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 140:97feb9bacc10 367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 371 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 372 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 373 } xPSR_Type;
<> 140:97feb9bacc10 374
<> 140:97feb9bacc10 375 /* xPSR Register Definitions */
<> 140:97feb9bacc10 376 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 140:97feb9bacc10 377 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 140:97feb9bacc10 378
<> 140:97feb9bacc10 379 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 140:97feb9bacc10 380 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 140:97feb9bacc10 381
<> 140:97feb9bacc10 382 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 140:97feb9bacc10 383 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 140:97feb9bacc10 384
<> 140:97feb9bacc10 385 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 140:97feb9bacc10 386 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 140:97feb9bacc10 387
<> 140:97feb9bacc10 388 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
<> 140:97feb9bacc10 389 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 140:97feb9bacc10 390
<> 140:97feb9bacc10 391 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
<> 140:97feb9bacc10 392 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
<> 140:97feb9bacc10 393
<> 140:97feb9bacc10 394 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 140:97feb9bacc10 395 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 140:97feb9bacc10 396
<> 140:97feb9bacc10 397 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
<> 140:97feb9bacc10 398 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
<> 140:97feb9bacc10 399
<> 140:97feb9bacc10 400 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 140:97feb9bacc10 401 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 140:97feb9bacc10 402
<> 140:97feb9bacc10 403
<> 140:97feb9bacc10 404 /** \brief Union type to access the Control Registers (CONTROL).
<> 140:97feb9bacc10 405 */
<> 140:97feb9bacc10 406 typedef union
<> 140:97feb9bacc10 407 {
<> 140:97feb9bacc10 408 struct
<> 140:97feb9bacc10 409 {
<> 140:97feb9bacc10 410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 140:97feb9bacc10 411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 140:97feb9bacc10 412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
<> 140:97feb9bacc10 413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
<> 140:97feb9bacc10 414 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 415 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 416 } CONTROL_Type;
<> 140:97feb9bacc10 417
<> 140:97feb9bacc10 418 /* CONTROL Register Definitions */
<> 140:97feb9bacc10 419 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
<> 140:97feb9bacc10 420 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
<> 140:97feb9bacc10 421
<> 140:97feb9bacc10 422 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 140:97feb9bacc10 423 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 140:97feb9bacc10 424
<> 140:97feb9bacc10 425 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 140:97feb9bacc10 426 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 140:97feb9bacc10 427
<> 140:97feb9bacc10 428 /*@} end of group CMSIS_CORE */
<> 140:97feb9bacc10 429
<> 140:97feb9bacc10 430
<> 140:97feb9bacc10 431 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 140:97feb9bacc10 433 \brief Type definitions for the NVIC Registers
<> 140:97feb9bacc10 434 @{
<> 140:97feb9bacc10 435 */
<> 140:97feb9bacc10 436
<> 140:97feb9bacc10 437 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 140:97feb9bacc10 438 */
<> 140:97feb9bacc10 439 typedef struct
<> 140:97feb9bacc10 440 {
<> 140:97feb9bacc10 441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 140:97feb9bacc10 442 uint32_t RESERVED0[24];
<> 140:97feb9bacc10 443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 140:97feb9bacc10 444 uint32_t RSERVED1[24];
<> 140:97feb9bacc10 445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 140:97feb9bacc10 446 uint32_t RESERVED2[24];
<> 140:97feb9bacc10 447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 140:97feb9bacc10 448 uint32_t RESERVED3[24];
<> 140:97feb9bacc10 449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
<> 140:97feb9bacc10 450 uint32_t RESERVED4[56];
<> 140:97feb9bacc10 451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
<> 140:97feb9bacc10 452 uint32_t RESERVED5[644];
<> 140:97feb9bacc10 453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 140:97feb9bacc10 454 } NVIC_Type;
<> 140:97feb9bacc10 455
<> 140:97feb9bacc10 456 /* Software Triggered Interrupt Register Definitions */
<> 140:97feb9bacc10 457 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
<> 140:97feb9bacc10 458 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 140:97feb9bacc10 459
<> 140:97feb9bacc10 460 /*@} end of group CMSIS_NVIC */
<> 140:97feb9bacc10 461
<> 140:97feb9bacc10 462
<> 140:97feb9bacc10 463 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 464 \defgroup CMSIS_SCB System Control Block (SCB)
<> 140:97feb9bacc10 465 \brief Type definitions for the System Control Block Registers
<> 140:97feb9bacc10 466 @{
<> 140:97feb9bacc10 467 */
<> 140:97feb9bacc10 468
<> 140:97feb9bacc10 469 /** \brief Structure type to access the System Control Block (SCB).
<> 140:97feb9bacc10 470 */
<> 140:97feb9bacc10 471 typedef struct
<> 140:97feb9bacc10 472 {
<> 140:97feb9bacc10 473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 140:97feb9bacc10 474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 140:97feb9bacc10 475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 140:97feb9bacc10 476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 140:97feb9bacc10 477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 140:97feb9bacc10 478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 140:97feb9bacc10 479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
<> 140:97feb9bacc10 480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 140:97feb9bacc10 481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
<> 140:97feb9bacc10 482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
<> 140:97feb9bacc10 483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
<> 140:97feb9bacc10 484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
<> 140:97feb9bacc10 485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
<> 140:97feb9bacc10 486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
<> 140:97feb9bacc10 487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
<> 140:97feb9bacc10 488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
<> 140:97feb9bacc10 489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
<> 140:97feb9bacc10 490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
<> 140:97feb9bacc10 491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
<> 140:97feb9bacc10 492 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
<> 140:97feb9bacc10 494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
<> 140:97feb9bacc10 495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
<> 140:97feb9bacc10 496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
<> 140:97feb9bacc10 497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 140:97feb9bacc10 498 uint32_t RESERVED3[93];
<> 140:97feb9bacc10 499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
<> 140:97feb9bacc10 500 uint32_t RESERVED4[15];
<> 140:97feb9bacc10 501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
<> 140:97feb9bacc10 502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
<> 140:97feb9bacc10 503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
<> 140:97feb9bacc10 504 uint32_t RESERVED5[1];
<> 140:97feb9bacc10 505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
<> 140:97feb9bacc10 506 uint32_t RESERVED6[1];
<> 140:97feb9bacc10 507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
<> 140:97feb9bacc10 508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
<> 140:97feb9bacc10 509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
<> 140:97feb9bacc10 510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
<> 140:97feb9bacc10 511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
<> 140:97feb9bacc10 512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
<> 140:97feb9bacc10 513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
<> 140:97feb9bacc10 514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
<> 140:97feb9bacc10 515 uint32_t RESERVED7[6];
<> 140:97feb9bacc10 516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
<> 140:97feb9bacc10 517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
<> 140:97feb9bacc10 518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
<> 140:97feb9bacc10 519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
<> 140:97feb9bacc10 520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
<> 140:97feb9bacc10 521 uint32_t RESERVED8[1];
<> 140:97feb9bacc10 522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
<> 140:97feb9bacc10 523 } SCB_Type;
<> 140:97feb9bacc10 524
<> 140:97feb9bacc10 525 /* SCB CPUID Register Definitions */
<> 140:97feb9bacc10 526 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 140:97feb9bacc10 527 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 140:97feb9bacc10 528
<> 140:97feb9bacc10 529 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 140:97feb9bacc10 530 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 140:97feb9bacc10 531
<> 140:97feb9bacc10 532 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 140:97feb9bacc10 533 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 140:97feb9bacc10 534
<> 140:97feb9bacc10 535 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 140:97feb9bacc10 536 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 140:97feb9bacc10 537
<> 140:97feb9bacc10 538 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 140:97feb9bacc10 539 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 140:97feb9bacc10 540
<> 140:97feb9bacc10 541 /* SCB Interrupt Control State Register Definitions */
<> 140:97feb9bacc10 542 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 140:97feb9bacc10 543 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 140:97feb9bacc10 544
<> 140:97feb9bacc10 545 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 140:97feb9bacc10 546 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 140:97feb9bacc10 547
<> 140:97feb9bacc10 548 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 140:97feb9bacc10 549 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 140:97feb9bacc10 550
<> 140:97feb9bacc10 551 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 140:97feb9bacc10 552 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 140:97feb9bacc10 553
<> 140:97feb9bacc10 554 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 140:97feb9bacc10 555 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 140:97feb9bacc10 556
<> 140:97feb9bacc10 557 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 140:97feb9bacc10 558 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 140:97feb9bacc10 559
<> 140:97feb9bacc10 560 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 140:97feb9bacc10 561 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 140:97feb9bacc10 562
<> 140:97feb9bacc10 563 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 140:97feb9bacc10 564 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 140:97feb9bacc10 565
<> 140:97feb9bacc10 566 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
<> 140:97feb9bacc10 567 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 140:97feb9bacc10 570 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 140:97feb9bacc10 571
<> 140:97feb9bacc10 572 /* SCB Vector Table Offset Register Definitions */
<> 140:97feb9bacc10 573 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 140:97feb9bacc10 574 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 140:97feb9bacc10 575
<> 140:97feb9bacc10 576 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 140:97feb9bacc10 577 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 140:97feb9bacc10 578 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 140:97feb9bacc10 579
<> 140:97feb9bacc10 580 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 140:97feb9bacc10 581 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 140:97feb9bacc10 582
<> 140:97feb9bacc10 583 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 140:97feb9bacc10 584 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 140:97feb9bacc10 585
<> 140:97feb9bacc10 586 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
<> 140:97feb9bacc10 587 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 140:97feb9bacc10 588
<> 140:97feb9bacc10 589 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 140:97feb9bacc10 590 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 140:97feb9bacc10 591
<> 140:97feb9bacc10 592 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 140:97feb9bacc10 593 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 140:97feb9bacc10 594
<> 140:97feb9bacc10 595 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
<> 140:97feb9bacc10 596 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 140:97feb9bacc10 597
<> 140:97feb9bacc10 598 /* SCB System Control Register Definitions */
<> 140:97feb9bacc10 599 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 140:97feb9bacc10 600 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 140:97feb9bacc10 601
<> 140:97feb9bacc10 602 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 140:97feb9bacc10 603 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 140:97feb9bacc10 604
<> 140:97feb9bacc10 605 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 140:97feb9bacc10 606 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 140:97feb9bacc10 607
<> 140:97feb9bacc10 608 /* SCB Configuration Control Register Definitions */
<> 140:97feb9bacc10 609 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
<> 140:97feb9bacc10 610 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
<> 140:97feb9bacc10 611
<> 140:97feb9bacc10 612 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
<> 140:97feb9bacc10 613 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
<> 140:97feb9bacc10 614
<> 140:97feb9bacc10 615 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
<> 140:97feb9bacc10 616 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
<> 140:97feb9bacc10 617
<> 140:97feb9bacc10 618 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 140:97feb9bacc10 619 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 140:97feb9bacc10 620
<> 140:97feb9bacc10 621 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
<> 140:97feb9bacc10 622 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 140:97feb9bacc10 623
<> 140:97feb9bacc10 624 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
<> 140:97feb9bacc10 625 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 140:97feb9bacc10 626
<> 140:97feb9bacc10 627 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 140:97feb9bacc10 628 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 140:97feb9bacc10 629
<> 140:97feb9bacc10 630 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
<> 140:97feb9bacc10 631 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 140:97feb9bacc10 632
<> 140:97feb9bacc10 633 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
<> 140:97feb9bacc10 634 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 140:97feb9bacc10 635
<> 140:97feb9bacc10 636 /* SCB System Handler Control and State Register Definitions */
<> 140:97feb9bacc10 637 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
<> 140:97feb9bacc10 638 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 140:97feb9bacc10 639
<> 140:97feb9bacc10 640 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
<> 140:97feb9bacc10 641 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 140:97feb9bacc10 642
<> 140:97feb9bacc10 643 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
<> 140:97feb9bacc10 644 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 140:97feb9bacc10 645
<> 140:97feb9bacc10 646 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 140:97feb9bacc10 647 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 140:97feb9bacc10 648
<> 140:97feb9bacc10 649 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 140:97feb9bacc10 650 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 140:97feb9bacc10 651
<> 140:97feb9bacc10 652 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 140:97feb9bacc10 653 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 140:97feb9bacc10 654
<> 140:97feb9bacc10 655 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 140:97feb9bacc10 656 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 140:97feb9bacc10 657
<> 140:97feb9bacc10 658 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
<> 140:97feb9bacc10 659 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 140:97feb9bacc10 660
<> 140:97feb9bacc10 661 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
<> 140:97feb9bacc10 662 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 140:97feb9bacc10 663
<> 140:97feb9bacc10 664 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
<> 140:97feb9bacc10 665 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 140:97feb9bacc10 666
<> 140:97feb9bacc10 667 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
<> 140:97feb9bacc10 668 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 140:97feb9bacc10 669
<> 140:97feb9bacc10 670 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
<> 140:97feb9bacc10 671 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 140:97feb9bacc10 672
<> 140:97feb9bacc10 673 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
<> 140:97feb9bacc10 674 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 140:97feb9bacc10 675
<> 140:97feb9bacc10 676 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
<> 140:97feb9bacc10 677 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 140:97feb9bacc10 678
<> 140:97feb9bacc10 679 /* SCB Configurable Fault Status Registers Definitions */
<> 140:97feb9bacc10 680 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
<> 140:97feb9bacc10 681 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 140:97feb9bacc10 682
<> 140:97feb9bacc10 683 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
<> 140:97feb9bacc10 684 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 140:97feb9bacc10 685
<> 140:97feb9bacc10 686 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 140:97feb9bacc10 687 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 140:97feb9bacc10 688
<> 140:97feb9bacc10 689 /* SCB Hard Fault Status Registers Definitions */
<> 140:97feb9bacc10 690 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
<> 140:97feb9bacc10 691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 140:97feb9bacc10 692
<> 140:97feb9bacc10 693 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
<> 140:97feb9bacc10 694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 140:97feb9bacc10 695
<> 140:97feb9bacc10 696 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
<> 140:97feb9bacc10 697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 140:97feb9bacc10 698
<> 140:97feb9bacc10 699 /* SCB Debug Fault Status Register Definitions */
<> 140:97feb9bacc10 700 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
<> 140:97feb9bacc10 701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 140:97feb9bacc10 702
<> 140:97feb9bacc10 703 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
<> 140:97feb9bacc10 704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 140:97feb9bacc10 705
<> 140:97feb9bacc10 706 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
<> 140:97feb9bacc10 707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 140:97feb9bacc10 708
<> 140:97feb9bacc10 709 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
<> 140:97feb9bacc10 710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 140:97feb9bacc10 711
<> 140:97feb9bacc10 712 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
<> 140:97feb9bacc10 713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 140:97feb9bacc10 714
<> 140:97feb9bacc10 715 /* Cache Level ID register */
<> 140:97feb9bacc10 716 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
<> 140:97feb9bacc10 717 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
<> 140:97feb9bacc10 718
<> 140:97feb9bacc10 719 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
<> 140:97feb9bacc10 720 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
<> 140:97feb9bacc10 721
<> 140:97feb9bacc10 722 /* Cache Type register */
<> 140:97feb9bacc10 723 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
<> 140:97feb9bacc10 724 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
<> 140:97feb9bacc10 725
<> 140:97feb9bacc10 726 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
<> 140:97feb9bacc10 727 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
<> 140:97feb9bacc10 728
<> 140:97feb9bacc10 729 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
<> 140:97feb9bacc10 730 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
<> 140:97feb9bacc10 731
<> 140:97feb9bacc10 732 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
<> 140:97feb9bacc10 733 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
<> 140:97feb9bacc10 734
<> 140:97feb9bacc10 735 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
<> 140:97feb9bacc10 736 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
<> 140:97feb9bacc10 737
<> 140:97feb9bacc10 738 /* Cache Size ID Register */
<> 140:97feb9bacc10 739 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
<> 140:97feb9bacc10 740 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
<> 140:97feb9bacc10 741
<> 140:97feb9bacc10 742 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
<> 140:97feb9bacc10 743 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
<> 140:97feb9bacc10 744
<> 140:97feb9bacc10 745 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
<> 140:97feb9bacc10 746 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
<> 140:97feb9bacc10 747
<> 140:97feb9bacc10 748 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
<> 140:97feb9bacc10 749 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
<> 140:97feb9bacc10 750
<> 140:97feb9bacc10 751 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
<> 140:97feb9bacc10 752 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
<> 140:97feb9bacc10 753
<> 140:97feb9bacc10 754 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
<> 140:97feb9bacc10 755 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
<> 140:97feb9bacc10 756
<> 140:97feb9bacc10 757 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
<> 140:97feb9bacc10 758 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
<> 140:97feb9bacc10 759
<> 140:97feb9bacc10 760 /* Cache Size Selection Register */
<> 140:97feb9bacc10 761 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
<> 140:97feb9bacc10 762 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
<> 140:97feb9bacc10 763
<> 140:97feb9bacc10 764 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
<> 140:97feb9bacc10 765 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
<> 140:97feb9bacc10 766
<> 140:97feb9bacc10 767 /* SCB Software Triggered Interrupt Register */
<> 140:97feb9bacc10 768 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
<> 140:97feb9bacc10 769 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
<> 140:97feb9bacc10 770
<> 140:97feb9bacc10 771 /* Instruction Tightly-Coupled Memory Control Register*/
<> 140:97feb9bacc10 772 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
<> 140:97feb9bacc10 773 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
<> 140:97feb9bacc10 774
<> 140:97feb9bacc10 775 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
<> 140:97feb9bacc10 776 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
<> 140:97feb9bacc10 777
<> 140:97feb9bacc10 778 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
<> 140:97feb9bacc10 779 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
<> 140:97feb9bacc10 780
<> 140:97feb9bacc10 781 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
<> 140:97feb9bacc10 782 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
<> 140:97feb9bacc10 783
<> 140:97feb9bacc10 784 /* Data Tightly-Coupled Memory Control Registers */
<> 140:97feb9bacc10 785 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
<> 140:97feb9bacc10 786 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
<> 140:97feb9bacc10 787
<> 140:97feb9bacc10 788 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
<> 140:97feb9bacc10 789 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
<> 140:97feb9bacc10 790
<> 140:97feb9bacc10 791 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
<> 140:97feb9bacc10 792 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
<> 140:97feb9bacc10 793
<> 140:97feb9bacc10 794 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
<> 140:97feb9bacc10 795 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
<> 140:97feb9bacc10 796
<> 140:97feb9bacc10 797 /* AHBP Control Register */
<> 140:97feb9bacc10 798 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
<> 140:97feb9bacc10 799 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
<> 140:97feb9bacc10 800
<> 140:97feb9bacc10 801 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
<> 140:97feb9bacc10 802 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
<> 140:97feb9bacc10 803
<> 140:97feb9bacc10 804 /* L1 Cache Control Register */
<> 140:97feb9bacc10 805 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
<> 140:97feb9bacc10 806 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
<> 140:97feb9bacc10 807
<> 140:97feb9bacc10 808 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
<> 140:97feb9bacc10 809 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
<> 140:97feb9bacc10 810
<> 140:97feb9bacc10 811 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
<> 140:97feb9bacc10 812 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
<> 140:97feb9bacc10 813
<> 140:97feb9bacc10 814 /* AHBS control register */
<> 140:97feb9bacc10 815 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
<> 140:97feb9bacc10 816 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
<> 140:97feb9bacc10 817
<> 140:97feb9bacc10 818 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
<> 140:97feb9bacc10 819 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
<> 140:97feb9bacc10 820
<> 140:97feb9bacc10 821 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
<> 140:97feb9bacc10 822 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
<> 140:97feb9bacc10 823
<> 140:97feb9bacc10 824 /* Auxiliary Bus Fault Status Register */
<> 140:97feb9bacc10 825 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
<> 140:97feb9bacc10 826 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
<> 140:97feb9bacc10 827
<> 140:97feb9bacc10 828 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
<> 140:97feb9bacc10 829 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
<> 140:97feb9bacc10 830
<> 140:97feb9bacc10 831 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
<> 140:97feb9bacc10 832 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
<> 140:97feb9bacc10 833
<> 140:97feb9bacc10 834 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
<> 140:97feb9bacc10 835 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
<> 140:97feb9bacc10 836
<> 140:97feb9bacc10 837 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
<> 140:97feb9bacc10 838 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
<> 140:97feb9bacc10 839
<> 140:97feb9bacc10 840 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
<> 140:97feb9bacc10 841 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
<> 140:97feb9bacc10 842
<> 140:97feb9bacc10 843 /*@} end of group CMSIS_SCB */
<> 140:97feb9bacc10 844
<> 140:97feb9bacc10 845
<> 140:97feb9bacc10 846 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 140:97feb9bacc10 848 \brief Type definitions for the System Control and ID Register not in the SCB
<> 140:97feb9bacc10 849 @{
<> 140:97feb9bacc10 850 */
<> 140:97feb9bacc10 851
<> 140:97feb9bacc10 852 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 140:97feb9bacc10 853 */
<> 140:97feb9bacc10 854 typedef struct
<> 140:97feb9bacc10 855 {
<> 140:97feb9bacc10 856 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
<> 140:97feb9bacc10 858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 140:97feb9bacc10 859 } SCnSCB_Type;
<> 140:97feb9bacc10 860
<> 140:97feb9bacc10 861 /* Interrupt Controller Type Register Definitions */
<> 140:97feb9bacc10 862 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
<> 140:97feb9bacc10 863 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 140:97feb9bacc10 864
<> 140:97feb9bacc10 865 /* Auxiliary Control Register Definitions */
<> 140:97feb9bacc10 866 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
<> 140:97feb9bacc10 867 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
<> 140:97feb9bacc10 868
<> 140:97feb9bacc10 869 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
<> 140:97feb9bacc10 870 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
<> 140:97feb9bacc10 871
<> 140:97feb9bacc10 872 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
<> 140:97feb9bacc10 873 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
<> 140:97feb9bacc10 874
<> 140:97feb9bacc10 875 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
<> 140:97feb9bacc10 876 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
<> 140:97feb9bacc10 877
<> 140:97feb9bacc10 878 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
<> 140:97feb9bacc10 879 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 140:97feb9bacc10 880
<> 140:97feb9bacc10 881 /*@} end of group CMSIS_SCnotSCB */
<> 140:97feb9bacc10 882
<> 140:97feb9bacc10 883
<> 140:97feb9bacc10 884 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 885 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 140:97feb9bacc10 886 \brief Type definitions for the System Timer Registers.
<> 140:97feb9bacc10 887 @{
<> 140:97feb9bacc10 888 */
<> 140:97feb9bacc10 889
<> 140:97feb9bacc10 890 /** \brief Structure type to access the System Timer (SysTick).
<> 140:97feb9bacc10 891 */
<> 140:97feb9bacc10 892 typedef struct
<> 140:97feb9bacc10 893 {
<> 140:97feb9bacc10 894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 140:97feb9bacc10 895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 140:97feb9bacc10 896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 140:97feb9bacc10 897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 140:97feb9bacc10 898 } SysTick_Type;
<> 140:97feb9bacc10 899
<> 140:97feb9bacc10 900 /* SysTick Control / Status Register Definitions */
<> 140:97feb9bacc10 901 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 140:97feb9bacc10 902 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 140:97feb9bacc10 903
<> 140:97feb9bacc10 904 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 140:97feb9bacc10 905 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 140:97feb9bacc10 906
<> 140:97feb9bacc10 907 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 140:97feb9bacc10 908 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 140:97feb9bacc10 909
<> 140:97feb9bacc10 910 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 140:97feb9bacc10 911 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 140:97feb9bacc10 912
<> 140:97feb9bacc10 913 /* SysTick Reload Register Definitions */
<> 140:97feb9bacc10 914 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 140:97feb9bacc10 915 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 140:97feb9bacc10 916
<> 140:97feb9bacc10 917 /* SysTick Current Register Definitions */
<> 140:97feb9bacc10 918 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 140:97feb9bacc10 919 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 140:97feb9bacc10 920
<> 140:97feb9bacc10 921 /* SysTick Calibration Register Definitions */
<> 140:97feb9bacc10 922 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 140:97feb9bacc10 923 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 140:97feb9bacc10 924
<> 140:97feb9bacc10 925 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 140:97feb9bacc10 926 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 140:97feb9bacc10 927
<> 140:97feb9bacc10 928 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 140:97feb9bacc10 929 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 140:97feb9bacc10 930
<> 140:97feb9bacc10 931 /*@} end of group CMSIS_SysTick */
<> 140:97feb9bacc10 932
<> 140:97feb9bacc10 933
<> 140:97feb9bacc10 934 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<> 140:97feb9bacc10 936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 140:97feb9bacc10 937 @{
<> 140:97feb9bacc10 938 */
<> 140:97feb9bacc10 939
<> 140:97feb9bacc10 940 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 140:97feb9bacc10 941 */
<> 140:97feb9bacc10 942 typedef struct
<> 140:97feb9bacc10 943 {
<> 140:97feb9bacc10 944 __O union
<> 140:97feb9bacc10 945 {
<> 140:97feb9bacc10 946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
<> 140:97feb9bacc10 947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
<> 140:97feb9bacc10 948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
<> 140:97feb9bacc10 949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
<> 140:97feb9bacc10 950 uint32_t RESERVED0[864];
<> 140:97feb9bacc10 951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
<> 140:97feb9bacc10 952 uint32_t RESERVED1[15];
<> 140:97feb9bacc10 953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
<> 140:97feb9bacc10 954 uint32_t RESERVED2[15];
<> 140:97feb9bacc10 955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
<> 140:97feb9bacc10 956 uint32_t RESERVED3[29];
<> 140:97feb9bacc10 957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
<> 140:97feb9bacc10 958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
<> 140:97feb9bacc10 959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
<> 140:97feb9bacc10 960 uint32_t RESERVED4[43];
<> 140:97feb9bacc10 961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
<> 140:97feb9bacc10 962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
<> 140:97feb9bacc10 963 uint32_t RESERVED5[6];
<> 140:97feb9bacc10 964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
<> 140:97feb9bacc10 965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
<> 140:97feb9bacc10 966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
<> 140:97feb9bacc10 967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
<> 140:97feb9bacc10 968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
<> 140:97feb9bacc10 969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
<> 140:97feb9bacc10 970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
<> 140:97feb9bacc10 971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
<> 140:97feb9bacc10 972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
<> 140:97feb9bacc10 973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
<> 140:97feb9bacc10 974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
<> 140:97feb9bacc10 975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 140:97feb9bacc10 976 } ITM_Type;
<> 140:97feb9bacc10 977
<> 140:97feb9bacc10 978 /* ITM Trace Privilege Register Definitions */
<> 140:97feb9bacc10 979 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
<> 140:97feb9bacc10 980 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 140:97feb9bacc10 981
<> 140:97feb9bacc10 982 /* ITM Trace Control Register Definitions */
<> 140:97feb9bacc10 983 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
<> 140:97feb9bacc10 984 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 140:97feb9bacc10 985
<> 140:97feb9bacc10 986 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
<> 140:97feb9bacc10 987 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 140:97feb9bacc10 988
<> 140:97feb9bacc10 989 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
<> 140:97feb9bacc10 990 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 140:97feb9bacc10 991
<> 140:97feb9bacc10 992 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
<> 140:97feb9bacc10 993 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 140:97feb9bacc10 994
<> 140:97feb9bacc10 995 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
<> 140:97feb9bacc10 996 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 140:97feb9bacc10 997
<> 140:97feb9bacc10 998 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
<> 140:97feb9bacc10 999 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 140:97feb9bacc10 1000
<> 140:97feb9bacc10 1001 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
<> 140:97feb9bacc10 1002 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 140:97feb9bacc10 1003
<> 140:97feb9bacc10 1004 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
<> 140:97feb9bacc10 1005 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 140:97feb9bacc10 1006
<> 140:97feb9bacc10 1007 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
<> 140:97feb9bacc10 1008 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 140:97feb9bacc10 1009
<> 140:97feb9bacc10 1010 /* ITM Integration Write Register Definitions */
<> 140:97feb9bacc10 1011 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
<> 140:97feb9bacc10 1012 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 140:97feb9bacc10 1013
<> 140:97feb9bacc10 1014 /* ITM Integration Read Register Definitions */
<> 140:97feb9bacc10 1015 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
<> 140:97feb9bacc10 1016 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 140:97feb9bacc10 1017
<> 140:97feb9bacc10 1018 /* ITM Integration Mode Control Register Definitions */
<> 140:97feb9bacc10 1019 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
<> 140:97feb9bacc10 1020 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 140:97feb9bacc10 1021
<> 140:97feb9bacc10 1022 /* ITM Lock Status Register Definitions */
<> 140:97feb9bacc10 1023 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
<> 140:97feb9bacc10 1024 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 140:97feb9bacc10 1025
<> 140:97feb9bacc10 1026 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
<> 140:97feb9bacc10 1027 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 140:97feb9bacc10 1028
<> 140:97feb9bacc10 1029 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
<> 140:97feb9bacc10 1030 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 140:97feb9bacc10 1031
<> 140:97feb9bacc10 1032 /*@}*/ /* end of group CMSIS_ITM */
<> 140:97feb9bacc10 1033
<> 140:97feb9bacc10 1034
<> 140:97feb9bacc10 1035 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<> 140:97feb9bacc10 1037 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 140:97feb9bacc10 1038 @{
<> 140:97feb9bacc10 1039 */
<> 140:97feb9bacc10 1040
<> 140:97feb9bacc10 1041 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 140:97feb9bacc10 1042 */
<> 140:97feb9bacc10 1043 typedef struct
<> 140:97feb9bacc10 1044 {
<> 140:97feb9bacc10 1045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
<> 140:97feb9bacc10 1046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
<> 140:97feb9bacc10 1047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
<> 140:97feb9bacc10 1048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
<> 140:97feb9bacc10 1049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
<> 140:97feb9bacc10 1050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
<> 140:97feb9bacc10 1051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
<> 140:97feb9bacc10 1052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
<> 140:97feb9bacc10 1053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
<> 140:97feb9bacc10 1054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
<> 140:97feb9bacc10 1055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
<> 140:97feb9bacc10 1056 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 1057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
<> 140:97feb9bacc10 1058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
<> 140:97feb9bacc10 1059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
<> 140:97feb9bacc10 1060 uint32_t RESERVED1[1];
<> 140:97feb9bacc10 1061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
<> 140:97feb9bacc10 1062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
<> 140:97feb9bacc10 1063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
<> 140:97feb9bacc10 1064 uint32_t RESERVED2[1];
<> 140:97feb9bacc10 1065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
<> 140:97feb9bacc10 1066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
<> 140:97feb9bacc10 1067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 140:97feb9bacc10 1068 uint32_t RESERVED3[981];
<> 140:97feb9bacc10 1069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
<> 140:97feb9bacc10 1070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
<> 140:97feb9bacc10 1071 } DWT_Type;
<> 140:97feb9bacc10 1072
<> 140:97feb9bacc10 1073 /* DWT Control Register Definitions */
<> 140:97feb9bacc10 1074 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
<> 140:97feb9bacc10 1075 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 140:97feb9bacc10 1076
<> 140:97feb9bacc10 1077 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
<> 140:97feb9bacc10 1078 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 140:97feb9bacc10 1079
<> 140:97feb9bacc10 1080 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
<> 140:97feb9bacc10 1081 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 140:97feb9bacc10 1082
<> 140:97feb9bacc10 1083 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
<> 140:97feb9bacc10 1084 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 140:97feb9bacc10 1085
<> 140:97feb9bacc10 1086 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
<> 140:97feb9bacc10 1087 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 140:97feb9bacc10 1088
<> 140:97feb9bacc10 1089 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
<> 140:97feb9bacc10 1090 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 140:97feb9bacc10 1091
<> 140:97feb9bacc10 1092 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
<> 140:97feb9bacc10 1093 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 140:97feb9bacc10 1094
<> 140:97feb9bacc10 1095 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
<> 140:97feb9bacc10 1096 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 140:97feb9bacc10 1097
<> 140:97feb9bacc10 1098 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
<> 140:97feb9bacc10 1099 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 140:97feb9bacc10 1100
<> 140:97feb9bacc10 1101 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
<> 140:97feb9bacc10 1102 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 140:97feb9bacc10 1103
<> 140:97feb9bacc10 1104 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
<> 140:97feb9bacc10 1105 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 140:97feb9bacc10 1106
<> 140:97feb9bacc10 1107 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
<> 140:97feb9bacc10 1108 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 140:97feb9bacc10 1109
<> 140:97feb9bacc10 1110 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
<> 140:97feb9bacc10 1111 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 140:97feb9bacc10 1112
<> 140:97feb9bacc10 1113 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
<> 140:97feb9bacc10 1114 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 140:97feb9bacc10 1115
<> 140:97feb9bacc10 1116 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
<> 140:97feb9bacc10 1117 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 140:97feb9bacc10 1118
<> 140:97feb9bacc10 1119 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
<> 140:97feb9bacc10 1120 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 140:97feb9bacc10 1121
<> 140:97feb9bacc10 1122 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
<> 140:97feb9bacc10 1123 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 140:97feb9bacc10 1124
<> 140:97feb9bacc10 1125 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
<> 140:97feb9bacc10 1126 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 140:97feb9bacc10 1127
<> 140:97feb9bacc10 1128 /* DWT CPI Count Register Definitions */
<> 140:97feb9bacc10 1129 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
<> 140:97feb9bacc10 1130 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 140:97feb9bacc10 1131
<> 140:97feb9bacc10 1132 /* DWT Exception Overhead Count Register Definitions */
<> 140:97feb9bacc10 1133 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
<> 140:97feb9bacc10 1134 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 140:97feb9bacc10 1135
<> 140:97feb9bacc10 1136 /* DWT Sleep Count Register Definitions */
<> 140:97feb9bacc10 1137 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 140:97feb9bacc10 1138 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 140:97feb9bacc10 1139
<> 140:97feb9bacc10 1140 /* DWT LSU Count Register Definitions */
<> 140:97feb9bacc10 1141 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
<> 140:97feb9bacc10 1142 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 140:97feb9bacc10 1143
<> 140:97feb9bacc10 1144 /* DWT Folded-instruction Count Register Definitions */
<> 140:97feb9bacc10 1145 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
<> 140:97feb9bacc10 1146 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 140:97feb9bacc10 1147
<> 140:97feb9bacc10 1148 /* DWT Comparator Mask Register Definitions */
<> 140:97feb9bacc10 1149 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
<> 140:97feb9bacc10 1150 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 140:97feb9bacc10 1151
<> 140:97feb9bacc10 1152 /* DWT Comparator Function Register Definitions */
<> 140:97feb9bacc10 1153 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
<> 140:97feb9bacc10 1154 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 140:97feb9bacc10 1155
<> 140:97feb9bacc10 1156 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 140:97feb9bacc10 1157 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 140:97feb9bacc10 1158
<> 140:97feb9bacc10 1159 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 140:97feb9bacc10 1160 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 140:97feb9bacc10 1161
<> 140:97feb9bacc10 1162 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
<> 140:97feb9bacc10 1163 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 140:97feb9bacc10 1164
<> 140:97feb9bacc10 1165 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
<> 140:97feb9bacc10 1166 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 140:97feb9bacc10 1167
<> 140:97feb9bacc10 1168 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
<> 140:97feb9bacc10 1169 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 140:97feb9bacc10 1170
<> 140:97feb9bacc10 1171 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
<> 140:97feb9bacc10 1172 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 140:97feb9bacc10 1173
<> 140:97feb9bacc10 1174 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
<> 140:97feb9bacc10 1175 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 140:97feb9bacc10 1176
<> 140:97feb9bacc10 1177 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
<> 140:97feb9bacc10 1178 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 140:97feb9bacc10 1179
<> 140:97feb9bacc10 1180 /*@}*/ /* end of group CMSIS_DWT */
<> 140:97feb9bacc10 1181
<> 140:97feb9bacc10 1182
<> 140:97feb9bacc10 1183 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1184 \defgroup CMSIS_TPI Trace Port Interface (TPI)
<> 140:97feb9bacc10 1185 \brief Type definitions for the Trace Port Interface (TPI)
<> 140:97feb9bacc10 1186 @{
<> 140:97feb9bacc10 1187 */
<> 140:97feb9bacc10 1188
<> 140:97feb9bacc10 1189 /** \brief Structure type to access the Trace Port Interface Register (TPI).
<> 140:97feb9bacc10 1190 */
<> 140:97feb9bacc10 1191 typedef struct
<> 140:97feb9bacc10 1192 {
<> 140:97feb9bacc10 1193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
<> 140:97feb9bacc10 1194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
<> 140:97feb9bacc10 1195 uint32_t RESERVED0[2];
<> 140:97feb9bacc10 1196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
<> 140:97feb9bacc10 1197 uint32_t RESERVED1[55];
<> 140:97feb9bacc10 1198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
<> 140:97feb9bacc10 1199 uint32_t RESERVED2[131];
<> 140:97feb9bacc10 1200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
<> 140:97feb9bacc10 1201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
<> 140:97feb9bacc10 1202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
<> 140:97feb9bacc10 1203 uint32_t RESERVED3[759];
<> 140:97feb9bacc10 1204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
<> 140:97feb9bacc10 1205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
<> 140:97feb9bacc10 1206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
<> 140:97feb9bacc10 1207 uint32_t RESERVED4[1];
<> 140:97feb9bacc10 1208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
<> 140:97feb9bacc10 1209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
<> 140:97feb9bacc10 1210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
<> 140:97feb9bacc10 1211 uint32_t RESERVED5[39];
<> 140:97feb9bacc10 1212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
<> 140:97feb9bacc10 1213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
<> 140:97feb9bacc10 1214 uint32_t RESERVED7[8];
<> 140:97feb9bacc10 1215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
<> 140:97feb9bacc10 1216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 140:97feb9bacc10 1217 } TPI_Type;
<> 140:97feb9bacc10 1218
<> 140:97feb9bacc10 1219 /* TPI Asynchronous Clock Prescaler Register Definitions */
<> 140:97feb9bacc10 1220 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
<> 140:97feb9bacc10 1221 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 140:97feb9bacc10 1222
<> 140:97feb9bacc10 1223 /* TPI Selected Pin Protocol Register Definitions */
<> 140:97feb9bacc10 1224 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
<> 140:97feb9bacc10 1225 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 140:97feb9bacc10 1226
<> 140:97feb9bacc10 1227 /* TPI Formatter and Flush Status Register Definitions */
<> 140:97feb9bacc10 1228 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
<> 140:97feb9bacc10 1229 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 140:97feb9bacc10 1230
<> 140:97feb9bacc10 1231 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
<> 140:97feb9bacc10 1232 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 140:97feb9bacc10 1233
<> 140:97feb9bacc10 1234 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
<> 140:97feb9bacc10 1235 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 140:97feb9bacc10 1236
<> 140:97feb9bacc10 1237 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
<> 140:97feb9bacc10 1238 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 140:97feb9bacc10 1239
<> 140:97feb9bacc10 1240 /* TPI Formatter and Flush Control Register Definitions */
<> 140:97feb9bacc10 1241 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
<> 140:97feb9bacc10 1242 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 140:97feb9bacc10 1243
<> 140:97feb9bacc10 1244 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
<> 140:97feb9bacc10 1245 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 140:97feb9bacc10 1246
<> 140:97feb9bacc10 1247 /* TPI TRIGGER Register Definitions */
<> 140:97feb9bacc10 1248 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
<> 140:97feb9bacc10 1249 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 140:97feb9bacc10 1250
<> 140:97feb9bacc10 1251 /* TPI Integration ETM Data Register Definitions (FIFO0) */
<> 140:97feb9bacc10 1252 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
<> 140:97feb9bacc10 1253 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 140:97feb9bacc10 1254
<> 140:97feb9bacc10 1255 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
<> 140:97feb9bacc10 1256 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 140:97feb9bacc10 1257
<> 140:97feb9bacc10 1258 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
<> 140:97feb9bacc10 1259 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 140:97feb9bacc10 1260
<> 140:97feb9bacc10 1261 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
<> 140:97feb9bacc10 1262 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 140:97feb9bacc10 1263
<> 140:97feb9bacc10 1264 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
<> 140:97feb9bacc10 1265 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 140:97feb9bacc10 1266
<> 140:97feb9bacc10 1267 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
<> 140:97feb9bacc10 1268 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 140:97feb9bacc10 1269
<> 140:97feb9bacc10 1270 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
<> 140:97feb9bacc10 1271 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 140:97feb9bacc10 1272
<> 140:97feb9bacc10 1273 /* TPI ITATBCTR2 Register Definitions */
<> 140:97feb9bacc10 1274 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
<> 140:97feb9bacc10 1275 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 140:97feb9bacc10 1276
<> 140:97feb9bacc10 1277 /* TPI Integration ITM Data Register Definitions (FIFO1) */
<> 140:97feb9bacc10 1278 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
<> 140:97feb9bacc10 1279 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 140:97feb9bacc10 1280
<> 140:97feb9bacc10 1281 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
<> 140:97feb9bacc10 1282 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 140:97feb9bacc10 1283
<> 140:97feb9bacc10 1284 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
<> 140:97feb9bacc10 1285 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 140:97feb9bacc10 1286
<> 140:97feb9bacc10 1287 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
<> 140:97feb9bacc10 1288 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 140:97feb9bacc10 1289
<> 140:97feb9bacc10 1290 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
<> 140:97feb9bacc10 1291 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 140:97feb9bacc10 1292
<> 140:97feb9bacc10 1293 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
<> 140:97feb9bacc10 1294 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 140:97feb9bacc10 1295
<> 140:97feb9bacc10 1296 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
<> 140:97feb9bacc10 1297 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 140:97feb9bacc10 1298
<> 140:97feb9bacc10 1299 /* TPI ITATBCTR0 Register Definitions */
<> 140:97feb9bacc10 1300 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
<> 140:97feb9bacc10 1301 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 140:97feb9bacc10 1302
<> 140:97feb9bacc10 1303 /* TPI Integration Mode Control Register Definitions */
<> 140:97feb9bacc10 1304 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
<> 140:97feb9bacc10 1305 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 140:97feb9bacc10 1306
<> 140:97feb9bacc10 1307 /* TPI DEVID Register Definitions */
<> 140:97feb9bacc10 1308 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
<> 140:97feb9bacc10 1309 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 140:97feb9bacc10 1310
<> 140:97feb9bacc10 1311 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
<> 140:97feb9bacc10 1312 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 140:97feb9bacc10 1313
<> 140:97feb9bacc10 1314 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
<> 140:97feb9bacc10 1315 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 140:97feb9bacc10 1316
<> 140:97feb9bacc10 1317 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
<> 140:97feb9bacc10 1318 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 140:97feb9bacc10 1319
<> 140:97feb9bacc10 1320 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
<> 140:97feb9bacc10 1321 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 140:97feb9bacc10 1322
<> 140:97feb9bacc10 1323 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
<> 140:97feb9bacc10 1324 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 140:97feb9bacc10 1325
<> 140:97feb9bacc10 1326 /* TPI DEVTYPE Register Definitions */
<> 140:97feb9bacc10 1327 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
<> 140:97feb9bacc10 1328 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 140:97feb9bacc10 1329
<> 140:97feb9bacc10 1330 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
<> 140:97feb9bacc10 1331 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 140:97feb9bacc10 1332
<> 140:97feb9bacc10 1333 /*@}*/ /* end of group CMSIS_TPI */
<> 140:97feb9bacc10 1334
<> 140:97feb9bacc10 1335
<> 140:97feb9bacc10 1336 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 1337 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1338 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 140:97feb9bacc10 1339 \brief Type definitions for the Memory Protection Unit (MPU)
<> 140:97feb9bacc10 1340 @{
<> 140:97feb9bacc10 1341 */
<> 140:97feb9bacc10 1342
<> 140:97feb9bacc10 1343 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 140:97feb9bacc10 1344 */
<> 140:97feb9bacc10 1345 typedef struct
<> 140:97feb9bacc10 1346 {
<> 140:97feb9bacc10 1347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 140:97feb9bacc10 1348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 140:97feb9bacc10 1349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 140:97feb9bacc10 1350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 140:97feb9bacc10 1351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 1352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
<> 140:97feb9bacc10 1353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
<> 140:97feb9bacc10 1354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
<> 140:97feb9bacc10 1355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
<> 140:97feb9bacc10 1356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
<> 140:97feb9bacc10 1357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 140:97feb9bacc10 1358 } MPU_Type;
<> 140:97feb9bacc10 1359
<> 140:97feb9bacc10 1360 /* MPU Type Register */
<> 140:97feb9bacc10 1361 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 140:97feb9bacc10 1362 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 140:97feb9bacc10 1363
<> 140:97feb9bacc10 1364 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 140:97feb9bacc10 1365 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 140:97feb9bacc10 1366
<> 140:97feb9bacc10 1367 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 140:97feb9bacc10 1368 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 140:97feb9bacc10 1369
<> 140:97feb9bacc10 1370 /* MPU Control Register */
<> 140:97feb9bacc10 1371 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 140:97feb9bacc10 1372 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 140:97feb9bacc10 1373
<> 140:97feb9bacc10 1374 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 140:97feb9bacc10 1375 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 140:97feb9bacc10 1376
<> 140:97feb9bacc10 1377 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 140:97feb9bacc10 1378 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 140:97feb9bacc10 1379
<> 140:97feb9bacc10 1380 /* MPU Region Number Register */
<> 140:97feb9bacc10 1381 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 140:97feb9bacc10 1382 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 140:97feb9bacc10 1383
<> 140:97feb9bacc10 1384 /* MPU Region Base Address Register */
<> 140:97feb9bacc10 1385 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
<> 140:97feb9bacc10 1386 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 140:97feb9bacc10 1387
<> 140:97feb9bacc10 1388 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 140:97feb9bacc10 1389 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 140:97feb9bacc10 1390
<> 140:97feb9bacc10 1391 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 140:97feb9bacc10 1392 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 140:97feb9bacc10 1393
<> 140:97feb9bacc10 1394 /* MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 1395 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 140:97feb9bacc10 1396 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 140:97feb9bacc10 1397
<> 140:97feb9bacc10 1398 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 140:97feb9bacc10 1399 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 140:97feb9bacc10 1400
<> 140:97feb9bacc10 1401 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 140:97feb9bacc10 1402 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 140:97feb9bacc10 1403
<> 140:97feb9bacc10 1404 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 140:97feb9bacc10 1405 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 140:97feb9bacc10 1406
<> 140:97feb9bacc10 1407 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 140:97feb9bacc10 1408 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 140:97feb9bacc10 1409
<> 140:97feb9bacc10 1410 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 140:97feb9bacc10 1411 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 140:97feb9bacc10 1412
<> 140:97feb9bacc10 1413 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 140:97feb9bacc10 1414 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 140:97feb9bacc10 1415
<> 140:97feb9bacc10 1416 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 140:97feb9bacc10 1417 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 140:97feb9bacc10 1418
<> 140:97feb9bacc10 1419 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 140:97feb9bacc10 1420 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 140:97feb9bacc10 1421
<> 140:97feb9bacc10 1422 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 140:97feb9bacc10 1423 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 140:97feb9bacc10 1424
<> 140:97feb9bacc10 1425 /*@} end of group CMSIS_MPU */
<> 140:97feb9bacc10 1426 #endif
<> 140:97feb9bacc10 1427
<> 140:97feb9bacc10 1428
<> 140:97feb9bacc10 1429 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 1430 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1431 \defgroup CMSIS_FPU Floating Point Unit (FPU)
<> 140:97feb9bacc10 1432 \brief Type definitions for the Floating Point Unit (FPU)
<> 140:97feb9bacc10 1433 @{
<> 140:97feb9bacc10 1434 */
<> 140:97feb9bacc10 1435
<> 140:97feb9bacc10 1436 /** \brief Structure type to access the Floating Point Unit (FPU).
<> 140:97feb9bacc10 1437 */
<> 140:97feb9bacc10 1438 typedef struct
<> 140:97feb9bacc10 1439 {
<> 140:97feb9bacc10 1440 uint32_t RESERVED0[1];
<> 140:97feb9bacc10 1441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
<> 140:97feb9bacc10 1442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
<> 140:97feb9bacc10 1443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
<> 140:97feb9bacc10 1444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
<> 140:97feb9bacc10 1445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
<> 140:97feb9bacc10 1446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
<> 140:97feb9bacc10 1447 } FPU_Type;
<> 140:97feb9bacc10 1448
<> 140:97feb9bacc10 1449 /* Floating-Point Context Control Register */
<> 140:97feb9bacc10 1450 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
<> 140:97feb9bacc10 1451 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
<> 140:97feb9bacc10 1452
<> 140:97feb9bacc10 1453 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
<> 140:97feb9bacc10 1454 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
<> 140:97feb9bacc10 1455
<> 140:97feb9bacc10 1456 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
<> 140:97feb9bacc10 1457 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
<> 140:97feb9bacc10 1458
<> 140:97feb9bacc10 1459 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
<> 140:97feb9bacc10 1460 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
<> 140:97feb9bacc10 1461
<> 140:97feb9bacc10 1462 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
<> 140:97feb9bacc10 1463 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
<> 140:97feb9bacc10 1464
<> 140:97feb9bacc10 1465 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
<> 140:97feb9bacc10 1466 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
<> 140:97feb9bacc10 1467
<> 140:97feb9bacc10 1468 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
<> 140:97feb9bacc10 1469 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
<> 140:97feb9bacc10 1470
<> 140:97feb9bacc10 1471 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
<> 140:97feb9bacc10 1472 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
<> 140:97feb9bacc10 1473
<> 140:97feb9bacc10 1474 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
<> 140:97feb9bacc10 1475 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
<> 140:97feb9bacc10 1476
<> 140:97feb9bacc10 1477 /* Floating-Point Context Address Register */
<> 140:97feb9bacc10 1478 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
<> 140:97feb9bacc10 1479 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
<> 140:97feb9bacc10 1480
<> 140:97feb9bacc10 1481 /* Floating-Point Default Status Control Register */
<> 140:97feb9bacc10 1482 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
<> 140:97feb9bacc10 1483 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
<> 140:97feb9bacc10 1484
<> 140:97feb9bacc10 1485 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
<> 140:97feb9bacc10 1486 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
<> 140:97feb9bacc10 1487
<> 140:97feb9bacc10 1488 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
<> 140:97feb9bacc10 1489 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
<> 140:97feb9bacc10 1490
<> 140:97feb9bacc10 1491 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
<> 140:97feb9bacc10 1492 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
<> 140:97feb9bacc10 1493
<> 140:97feb9bacc10 1494 /* Media and FP Feature Register 0 */
<> 140:97feb9bacc10 1495 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
<> 140:97feb9bacc10 1496 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
<> 140:97feb9bacc10 1497
<> 140:97feb9bacc10 1498 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
<> 140:97feb9bacc10 1499 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
<> 140:97feb9bacc10 1500
<> 140:97feb9bacc10 1501 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
<> 140:97feb9bacc10 1502 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
<> 140:97feb9bacc10 1503
<> 140:97feb9bacc10 1504 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
<> 140:97feb9bacc10 1505 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
<> 140:97feb9bacc10 1506
<> 140:97feb9bacc10 1507 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
<> 140:97feb9bacc10 1508 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
<> 140:97feb9bacc10 1509
<> 140:97feb9bacc10 1510 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
<> 140:97feb9bacc10 1511 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
<> 140:97feb9bacc10 1512
<> 140:97feb9bacc10 1513 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
<> 140:97feb9bacc10 1514 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
<> 140:97feb9bacc10 1515
<> 140:97feb9bacc10 1516 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
<> 140:97feb9bacc10 1517 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
<> 140:97feb9bacc10 1518
<> 140:97feb9bacc10 1519 /* Media and FP Feature Register 1 */
<> 140:97feb9bacc10 1520 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
<> 140:97feb9bacc10 1521 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
<> 140:97feb9bacc10 1522
<> 140:97feb9bacc10 1523 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
<> 140:97feb9bacc10 1524 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
<> 140:97feb9bacc10 1525
<> 140:97feb9bacc10 1526 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
<> 140:97feb9bacc10 1527 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
<> 140:97feb9bacc10 1528
<> 140:97feb9bacc10 1529 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
<> 140:97feb9bacc10 1530 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
<> 140:97feb9bacc10 1531
<> 140:97feb9bacc10 1532 /* Media and FP Feature Register 2 */
<> 140:97feb9bacc10 1533
<> 140:97feb9bacc10 1534 /*@} end of group CMSIS_FPU */
<> 140:97feb9bacc10 1535 #endif
<> 140:97feb9bacc10 1536
<> 140:97feb9bacc10 1537
<> 140:97feb9bacc10 1538 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 140:97feb9bacc10 1540 \brief Type definitions for the Core Debug Registers
<> 140:97feb9bacc10 1541 @{
<> 140:97feb9bacc10 1542 */
<> 140:97feb9bacc10 1543
<> 140:97feb9bacc10 1544 /** \brief Structure type to access the Core Debug Register (CoreDebug).
<> 140:97feb9bacc10 1545 */
<> 140:97feb9bacc10 1546 typedef struct
<> 140:97feb9bacc10 1547 {
<> 140:97feb9bacc10 1548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
<> 140:97feb9bacc10 1549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
<> 140:97feb9bacc10 1550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
<> 140:97feb9bacc10 1551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 140:97feb9bacc10 1552 } CoreDebug_Type;
<> 140:97feb9bacc10 1553
<> 140:97feb9bacc10 1554 /* Debug Halting Control and Status Register */
<> 140:97feb9bacc10 1555 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
<> 140:97feb9bacc10 1556 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 140:97feb9bacc10 1557
<> 140:97feb9bacc10 1558 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 140:97feb9bacc10 1559 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 140:97feb9bacc10 1560
<> 140:97feb9bacc10 1561 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 140:97feb9bacc10 1562 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 140:97feb9bacc10 1563
<> 140:97feb9bacc10 1564 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 140:97feb9bacc10 1565 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 140:97feb9bacc10 1566
<> 140:97feb9bacc10 1567 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 140:97feb9bacc10 1568 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 140:97feb9bacc10 1569
<> 140:97feb9bacc10 1570 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
<> 140:97feb9bacc10 1571 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 140:97feb9bacc10 1572
<> 140:97feb9bacc10 1573 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 140:97feb9bacc10 1574 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 140:97feb9bacc10 1575
<> 140:97feb9bacc10 1576 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 140:97feb9bacc10 1577 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 140:97feb9bacc10 1578
<> 140:97feb9bacc10 1579 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 140:97feb9bacc10 1580 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 140:97feb9bacc10 1581
<> 140:97feb9bacc10 1582 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
<> 140:97feb9bacc10 1583 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 140:97feb9bacc10 1584
<> 140:97feb9bacc10 1585 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
<> 140:97feb9bacc10 1586 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 140:97feb9bacc10 1587
<> 140:97feb9bacc10 1588 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 140:97feb9bacc10 1589 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 140:97feb9bacc10 1590
<> 140:97feb9bacc10 1591 /* Debug Core Register Selector Register */
<> 140:97feb9bacc10 1592 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
<> 140:97feb9bacc10 1593 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 140:97feb9bacc10 1594
<> 140:97feb9bacc10 1595 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
<> 140:97feb9bacc10 1596 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 140:97feb9bacc10 1597
<> 140:97feb9bacc10 1598 /* Debug Exception and Monitor Control Register */
<> 140:97feb9bacc10 1599 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
<> 140:97feb9bacc10 1600 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 140:97feb9bacc10 1601
<> 140:97feb9bacc10 1602 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
<> 140:97feb9bacc10 1603 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 140:97feb9bacc10 1604
<> 140:97feb9bacc10 1605 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
<> 140:97feb9bacc10 1606 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 140:97feb9bacc10 1607
<> 140:97feb9bacc10 1608 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
<> 140:97feb9bacc10 1609 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 140:97feb9bacc10 1610
<> 140:97feb9bacc10 1611 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
<> 140:97feb9bacc10 1612 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 140:97feb9bacc10 1613
<> 140:97feb9bacc10 1614 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 140:97feb9bacc10 1615 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 140:97feb9bacc10 1616
<> 140:97feb9bacc10 1617 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 140:97feb9bacc10 1618 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 140:97feb9bacc10 1619
<> 140:97feb9bacc10 1620 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 140:97feb9bacc10 1621 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 140:97feb9bacc10 1622
<> 140:97feb9bacc10 1623 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 140:97feb9bacc10 1624 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 140:97feb9bacc10 1625
<> 140:97feb9bacc10 1626 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 140:97feb9bacc10 1627 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 140:97feb9bacc10 1628
<> 140:97feb9bacc10 1629 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 140:97feb9bacc10 1630 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 140:97feb9bacc10 1631
<> 140:97feb9bacc10 1632 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 140:97feb9bacc10 1633 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 140:97feb9bacc10 1634
<> 140:97feb9bacc10 1635 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 140:97feb9bacc10 1636 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 140:97feb9bacc10 1637
<> 140:97feb9bacc10 1638 /*@} end of group CMSIS_CoreDebug */
<> 140:97feb9bacc10 1639
<> 140:97feb9bacc10 1640
<> 140:97feb9bacc10 1641 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 1642 \defgroup CMSIS_core_base Core Definitions
<> 140:97feb9bacc10 1643 \brief Definitions for base addresses, unions, and structures.
<> 140:97feb9bacc10 1644 @{
<> 140:97feb9bacc10 1645 */
<> 140:97feb9bacc10 1646
<> 140:97feb9bacc10 1647 /* Memory mapping of Cortex-M4 Hardware */
<> 140:97feb9bacc10 1648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 140:97feb9bacc10 1649 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
<> 140:97feb9bacc10 1650 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
<> 140:97feb9bacc10 1651 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
<> 140:97feb9bacc10 1652 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
<> 140:97feb9bacc10 1653 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 140:97feb9bacc10 1654 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 140:97feb9bacc10 1655 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 140:97feb9bacc10 1656
<> 140:97feb9bacc10 1657 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 140:97feb9bacc10 1658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 140:97feb9bacc10 1659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 140:97feb9bacc10 1660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 140:97feb9bacc10 1661 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
<> 140:97feb9bacc10 1662 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
<> 140:97feb9bacc10 1663 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
<> 140:97feb9bacc10 1664 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 140:97feb9bacc10 1665
<> 140:97feb9bacc10 1666 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 1667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 1668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 1669 #endif
<> 140:97feb9bacc10 1670
<> 140:97feb9bacc10 1671 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 1672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
<> 140:97feb9bacc10 1673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
<> 140:97feb9bacc10 1674 #endif
<> 140:97feb9bacc10 1675
<> 140:97feb9bacc10 1676 /*@} */
<> 140:97feb9bacc10 1677
<> 140:97feb9bacc10 1678
<> 140:97feb9bacc10 1679
<> 140:97feb9bacc10 1680 /*******************************************************************************
<> 140:97feb9bacc10 1681 * Hardware Abstraction Layer
<> 140:97feb9bacc10 1682 Core Function Interface contains:
<> 140:97feb9bacc10 1683 - Core NVIC Functions
<> 140:97feb9bacc10 1684 - Core SysTick Functions
<> 140:97feb9bacc10 1685 - Core Debug Functions
<> 140:97feb9bacc10 1686 - Core Register Access Functions
<> 140:97feb9bacc10 1687 ******************************************************************************/
<> 140:97feb9bacc10 1688 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 140:97feb9bacc10 1689 */
<> 140:97feb9bacc10 1690
<> 140:97feb9bacc10 1691
<> 140:97feb9bacc10 1692
<> 140:97feb9bacc10 1693 /* ########################## NVIC functions #################################### */
<> 140:97feb9bacc10 1694 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 140:97feb9bacc10 1696 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 140:97feb9bacc10 1697 @{
<> 140:97feb9bacc10 1698 */
<> 140:97feb9bacc10 1699
<> 140:97feb9bacc10 1700 /** \brief Set Priority Grouping
<> 140:97feb9bacc10 1701
<> 140:97feb9bacc10 1702 The function sets the priority grouping field using the required unlock sequence.
<> 140:97feb9bacc10 1703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<> 140:97feb9bacc10 1704 Only values from 0..7 are used.
<> 140:97feb9bacc10 1705 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 140:97feb9bacc10 1707
<> 140:97feb9bacc10 1708 \param [in] PriorityGroup Priority grouping field.
<> 140:97feb9bacc10 1709 */
<> 140:97feb9bacc10 1710 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 140:97feb9bacc10 1711 {
<> 140:97feb9bacc10 1712 uint32_t reg_value;
<> 140:97feb9bacc10 1713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1714
<> 140:97feb9bacc10 1715 reg_value = SCB->AIRCR; /* read old register configuration */
<> 140:97feb9bacc10 1716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 140:97feb9bacc10 1717 reg_value = (reg_value |
<> 140:97feb9bacc10 1718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 1719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<> 140:97feb9bacc10 1720 SCB->AIRCR = reg_value;
<> 140:97feb9bacc10 1721 }
<> 140:97feb9bacc10 1722
<> 140:97feb9bacc10 1723
<> 140:97feb9bacc10 1724 /** \brief Get Priority Grouping
<> 140:97feb9bacc10 1725
<> 140:97feb9bacc10 1726 The function reads the priority grouping field from the NVIC Interrupt Controller.
<> 140:97feb9bacc10 1727
<> 140:97feb9bacc10 1728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 140:97feb9bacc10 1729 */
<> 140:97feb9bacc10 1730 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<> 140:97feb9bacc10 1731 {
<> 140:97feb9bacc10 1732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 140:97feb9bacc10 1733 }
<> 140:97feb9bacc10 1734
<> 140:97feb9bacc10 1735
<> 140:97feb9bacc10 1736 /** \brief Enable External Interrupt
<> 140:97feb9bacc10 1737
<> 140:97feb9bacc10 1738 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 1739
<> 140:97feb9bacc10 1740 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1741 */
<> 140:97feb9bacc10 1742 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1743 {
<> 140:97feb9bacc10 1744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1745 }
<> 140:97feb9bacc10 1746
<> 140:97feb9bacc10 1747
<> 140:97feb9bacc10 1748 /** \brief Disable External Interrupt
<> 140:97feb9bacc10 1749
<> 140:97feb9bacc10 1750 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 1751
<> 140:97feb9bacc10 1752 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1753 */
<> 140:97feb9bacc10 1754 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1755 {
<> 140:97feb9bacc10 1756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1757 __DSB();
<> 140:97feb9bacc10 1758 __ISB();
<> 140:97feb9bacc10 1759 }
<> 140:97feb9bacc10 1760
<> 140:97feb9bacc10 1761
<> 140:97feb9bacc10 1762 /** \brief Get Pending Interrupt
<> 140:97feb9bacc10 1763
<> 140:97feb9bacc10 1764 The function reads the pending register in the NVIC and returns the pending bit
<> 140:97feb9bacc10 1765 for the specified interrupt.
<> 140:97feb9bacc10 1766
<> 140:97feb9bacc10 1767 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1768
<> 140:97feb9bacc10 1769 \return 0 Interrupt status is not pending.
<> 140:97feb9bacc10 1770 \return 1 Interrupt status is pending.
<> 140:97feb9bacc10 1771 */
<> 140:97feb9bacc10 1772 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1773 {
<> 140:97feb9bacc10 1774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 140:97feb9bacc10 1775 }
<> 140:97feb9bacc10 1776
<> 140:97feb9bacc10 1777
<> 140:97feb9bacc10 1778 /** \brief Set Pending Interrupt
<> 140:97feb9bacc10 1779
<> 140:97feb9bacc10 1780 The function sets the pending bit of an external interrupt.
<> 140:97feb9bacc10 1781
<> 140:97feb9bacc10 1782 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1783 */
<> 140:97feb9bacc10 1784 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1785 {
<> 140:97feb9bacc10 1786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1787 }
<> 140:97feb9bacc10 1788
<> 140:97feb9bacc10 1789
<> 140:97feb9bacc10 1790 /** \brief Clear Pending Interrupt
<> 140:97feb9bacc10 1791
<> 140:97feb9bacc10 1792 The function clears the pending bit of an external interrupt.
<> 140:97feb9bacc10 1793
<> 140:97feb9bacc10 1794 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 1795 */
<> 140:97feb9bacc10 1796 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 1797 {
<> 140:97feb9bacc10 1798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 1799 }
<> 140:97feb9bacc10 1800
<> 140:97feb9bacc10 1801
<> 140:97feb9bacc10 1802 /** \brief Get Active Interrupt
<> 140:97feb9bacc10 1803
<> 140:97feb9bacc10 1804 The function reads the active register in NVIC and returns the active bit.
<> 140:97feb9bacc10 1805
<> 140:97feb9bacc10 1806 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1807
<> 140:97feb9bacc10 1808 \return 0 Interrupt status is not active.
<> 140:97feb9bacc10 1809 \return 1 Interrupt status is active.
<> 140:97feb9bacc10 1810 */
<> 140:97feb9bacc10 1811 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<> 140:97feb9bacc10 1812 {
<> 140:97feb9bacc10 1813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 140:97feb9bacc10 1814 }
<> 140:97feb9bacc10 1815
<> 140:97feb9bacc10 1816
<> 140:97feb9bacc10 1817 /** \brief Set Interrupt Priority
<> 140:97feb9bacc10 1818
<> 140:97feb9bacc10 1819 The function sets the priority of an interrupt.
<> 140:97feb9bacc10 1820
<> 140:97feb9bacc10 1821 \note The priority cannot be set for every core interrupt.
<> 140:97feb9bacc10 1822
<> 140:97feb9bacc10 1823 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1824 \param [in] priority Priority to set.
<> 140:97feb9bacc10 1825 */
<> 140:97feb9bacc10 1826 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 140:97feb9bacc10 1827 {
<> 140:97feb9bacc10 1828 if((int32_t)IRQn < 0) {
<> 140:97feb9bacc10 1829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 140:97feb9bacc10 1830 }
<> 140:97feb9bacc10 1831 else {
<> 140:97feb9bacc10 1832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 140:97feb9bacc10 1833 }
<> 140:97feb9bacc10 1834 }
<> 140:97feb9bacc10 1835
<> 140:97feb9bacc10 1836
<> 140:97feb9bacc10 1837 /** \brief Get Interrupt Priority
<> 140:97feb9bacc10 1838
<> 140:97feb9bacc10 1839 The function reads the priority of an interrupt. The interrupt
<> 140:97feb9bacc10 1840 number can be positive to specify an external (device specific)
<> 140:97feb9bacc10 1841 interrupt, or negative to specify an internal (core) interrupt.
<> 140:97feb9bacc10 1842
<> 140:97feb9bacc10 1843
<> 140:97feb9bacc10 1844 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 1845 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 140:97feb9bacc10 1846 priority bits of the microcontroller.
<> 140:97feb9bacc10 1847 */
<> 140:97feb9bacc10 1848 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 140:97feb9bacc10 1849 {
<> 140:97feb9bacc10 1850
<> 140:97feb9bacc10 1851 if((int32_t)IRQn < 0) {
<> 140:97feb9bacc10 1852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 1853 }
<> 140:97feb9bacc10 1854 else {
<> 140:97feb9bacc10 1855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 1856 }
<> 140:97feb9bacc10 1857 }
<> 140:97feb9bacc10 1858
<> 140:97feb9bacc10 1859
<> 140:97feb9bacc10 1860 /** \brief Encode Priority
<> 140:97feb9bacc10 1861
<> 140:97feb9bacc10 1862 The function encodes the priority for an interrupt with the given priority group,
<> 140:97feb9bacc10 1863 preemptive priority value, and subpriority value.
<> 140:97feb9bacc10 1864 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 140:97feb9bacc10 1866
<> 140:97feb9bacc10 1867 \param [in] PriorityGroup Used priority group.
<> 140:97feb9bacc10 1868 \param [in] PreemptPriority Preemptive priority value (starting from 0).
<> 140:97feb9bacc10 1869 \param [in] SubPriority Subpriority value (starting from 0).
<> 140:97feb9bacc10 1870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 140:97feb9bacc10 1871 */
<> 140:97feb9bacc10 1872 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 140:97feb9bacc10 1873 {
<> 140:97feb9bacc10 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1875 uint32_t PreemptPriorityBits;
<> 140:97feb9bacc10 1876 uint32_t SubPriorityBits;
<> 140:97feb9bacc10 1877
<> 140:97feb9bacc10 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 140:97feb9bacc10 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 140:97feb9bacc10 1880
<> 140:97feb9bacc10 1881 return (
<> 140:97feb9bacc10 1882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 140:97feb9bacc10 1883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 140:97feb9bacc10 1884 );
<> 140:97feb9bacc10 1885 }
<> 140:97feb9bacc10 1886
<> 140:97feb9bacc10 1887
<> 140:97feb9bacc10 1888 /** \brief Decode Priority
<> 140:97feb9bacc10 1889
<> 140:97feb9bacc10 1890 The function decodes an interrupt priority value with a given priority group to
<> 140:97feb9bacc10 1891 preemptive priority value and subpriority value.
<> 140:97feb9bacc10 1892 In case of a conflict between priority grouping and available
<> 140:97feb9bacc10 1893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<> 140:97feb9bacc10 1894
<> 140:97feb9bacc10 1895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<> 140:97feb9bacc10 1896 \param [in] PriorityGroup Used priority group.
<> 140:97feb9bacc10 1897 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
<> 140:97feb9bacc10 1898 \param [out] pSubPriority Subpriority value (starting from 0).
<> 140:97feb9bacc10 1899 */
<> 140:97feb9bacc10 1900 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 140:97feb9bacc10 1901 {
<> 140:97feb9bacc10 1902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 140:97feb9bacc10 1903 uint32_t PreemptPriorityBits;
<> 140:97feb9bacc10 1904 uint32_t SubPriorityBits;
<> 140:97feb9bacc10 1905
<> 140:97feb9bacc10 1906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 140:97feb9bacc10 1907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 140:97feb9bacc10 1908
<> 140:97feb9bacc10 1909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 140:97feb9bacc10 1910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 140:97feb9bacc10 1911 }
<> 140:97feb9bacc10 1912
<> 140:97feb9bacc10 1913
<> 140:97feb9bacc10 1914 /** \brief System Reset
<> 140:97feb9bacc10 1915
<> 140:97feb9bacc10 1916 The function initiates a system reset request to reset the MCU.
<> 140:97feb9bacc10 1917 */
<> 140:97feb9bacc10 1918 __STATIC_INLINE void NVIC_SystemReset(void)
<> 140:97feb9bacc10 1919 {
<> 140:97feb9bacc10 1920 __DSB(); /* Ensure all outstanding memory accesses included
<> 140:97feb9bacc10 1921 buffered write are completed before reset */
<> 140:97feb9bacc10 1922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 1923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 140:97feb9bacc10 1924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 140:97feb9bacc10 1925 __DSB(); /* Ensure completion of memory access */
<> 140:97feb9bacc10 1926 while(1) { __NOP(); } /* wait until reset */
<> 140:97feb9bacc10 1927 }
<> 140:97feb9bacc10 1928
<> 140:97feb9bacc10 1929 /*@} end of CMSIS_Core_NVICFunctions */
<> 140:97feb9bacc10 1930
<> 140:97feb9bacc10 1931
<> 140:97feb9bacc10 1932 /* ########################## FPU functions #################################### */
<> 140:97feb9bacc10 1933 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1934 \defgroup CMSIS_Core_FpuFunctions FPU Functions
<> 140:97feb9bacc10 1935 \brief Function that provides FPU type.
<> 140:97feb9bacc10 1936 @{
<> 140:97feb9bacc10 1937 */
<> 140:97feb9bacc10 1938
<> 140:97feb9bacc10 1939 /**
<> 140:97feb9bacc10 1940 \fn uint32_t SCB_GetFPUType(void)
<> 140:97feb9bacc10 1941 \brief get FPU type
<> 140:97feb9bacc10 1942 \returns
<> 140:97feb9bacc10 1943 - \b 0: No FPU
<> 140:97feb9bacc10 1944 - \b 1: Single precision FPU
<> 140:97feb9bacc10 1945 - \b 2: Double + Single precision FPU
<> 140:97feb9bacc10 1946 */
<> 140:97feb9bacc10 1947 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
<> 140:97feb9bacc10 1948 {
<> 140:97feb9bacc10 1949 uint32_t mvfr0;
<> 140:97feb9bacc10 1950
<> 140:97feb9bacc10 1951 mvfr0 = SCB->MVFR0;
<> 140:97feb9bacc10 1952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
<> 140:97feb9bacc10 1953 return 2UL; // Double + Single precision FPU
<> 140:97feb9bacc10 1954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
<> 140:97feb9bacc10 1955 return 1UL; // Single precision FPU
<> 140:97feb9bacc10 1956 } else {
<> 140:97feb9bacc10 1957 return 0UL; // No FPU
<> 140:97feb9bacc10 1958 }
<> 140:97feb9bacc10 1959 }
<> 140:97feb9bacc10 1960
<> 140:97feb9bacc10 1961
<> 140:97feb9bacc10 1962 /*@} end of CMSIS_Core_FpuFunctions */
<> 140:97feb9bacc10 1963
<> 140:97feb9bacc10 1964
<> 140:97feb9bacc10 1965
<> 140:97feb9bacc10 1966 /* ########################## Cache functions #################################### */
<> 140:97feb9bacc10 1967 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 1968 \defgroup CMSIS_Core_CacheFunctions Cache Functions
<> 140:97feb9bacc10 1969 \brief Functions that configure Instruction and Data cache.
<> 140:97feb9bacc10 1970 @{
<> 140:97feb9bacc10 1971 */
<> 140:97feb9bacc10 1972
<> 140:97feb9bacc10 1973 /* Cache Size ID Register Macros */
<> 140:97feb9bacc10 1974 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
<> 140:97feb9bacc10 1975 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
<> 140:97feb9bacc10 1976 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
<> 140:97feb9bacc10 1977
<> 140:97feb9bacc10 1978
<> 140:97feb9bacc10 1979 /** \brief Enable I-Cache
<> 140:97feb9bacc10 1980
<> 140:97feb9bacc10 1981 The function turns on I-Cache
<> 140:97feb9bacc10 1982 */
<> 140:97feb9bacc10 1983 __STATIC_INLINE void SCB_EnableICache (void)
<> 140:97feb9bacc10 1984 {
<> 140:97feb9bacc10 1985 #if (__ICACHE_PRESENT == 1)
<> 140:97feb9bacc10 1986 __DSB();
<> 140:97feb9bacc10 1987 __ISB();
<> 140:97feb9bacc10 1988 SCB->ICIALLU = 0UL; // invalidate I-Cache
<> 140:97feb9bacc10 1989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
<> 140:97feb9bacc10 1990 __DSB();
<> 140:97feb9bacc10 1991 __ISB();
<> 140:97feb9bacc10 1992 #endif
<> 140:97feb9bacc10 1993 }
<> 140:97feb9bacc10 1994
<> 140:97feb9bacc10 1995
<> 140:97feb9bacc10 1996 /** \brief Disable I-Cache
<> 140:97feb9bacc10 1997
<> 140:97feb9bacc10 1998 The function turns off I-Cache
<> 140:97feb9bacc10 1999 */
<> 140:97feb9bacc10 2000 __STATIC_INLINE void SCB_DisableICache (void)
<> 140:97feb9bacc10 2001 {
<> 140:97feb9bacc10 2002 #if (__ICACHE_PRESENT == 1)
<> 140:97feb9bacc10 2003 __DSB();
<> 140:97feb9bacc10 2004 __ISB();
<> 140:97feb9bacc10 2005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
<> 140:97feb9bacc10 2006 SCB->ICIALLU = 0UL; // invalidate I-Cache
<> 140:97feb9bacc10 2007 __DSB();
<> 140:97feb9bacc10 2008 __ISB();
<> 140:97feb9bacc10 2009 #endif
<> 140:97feb9bacc10 2010 }
<> 140:97feb9bacc10 2011
<> 140:97feb9bacc10 2012
<> 140:97feb9bacc10 2013 /** \brief Invalidate I-Cache
<> 140:97feb9bacc10 2014
<> 140:97feb9bacc10 2015 The function invalidates I-Cache
<> 140:97feb9bacc10 2016 */
<> 140:97feb9bacc10 2017 __STATIC_INLINE void SCB_InvalidateICache (void)
<> 140:97feb9bacc10 2018 {
<> 140:97feb9bacc10 2019 #if (__ICACHE_PRESENT == 1)
<> 140:97feb9bacc10 2020 __DSB();
<> 140:97feb9bacc10 2021 __ISB();
<> 140:97feb9bacc10 2022 SCB->ICIALLU = 0UL;
<> 140:97feb9bacc10 2023 __DSB();
<> 140:97feb9bacc10 2024 __ISB();
<> 140:97feb9bacc10 2025 #endif
<> 140:97feb9bacc10 2026 }
<> 140:97feb9bacc10 2027
<> 140:97feb9bacc10 2028
<> 140:97feb9bacc10 2029 /** \brief Enable D-Cache
<> 140:97feb9bacc10 2030
<> 140:97feb9bacc10 2031 The function turns on D-Cache
<> 140:97feb9bacc10 2032 */
<> 140:97feb9bacc10 2033 __STATIC_INLINE void SCB_EnableDCache (void)
<> 140:97feb9bacc10 2034 {
<> 140:97feb9bacc10 2035 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2036 uint32_t ccsidr, sshift, wshift, sw;
<> 140:97feb9bacc10 2037 uint32_t sets, ways;
<> 140:97feb9bacc10 2038
<> 140:97feb9bacc10 2039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
<> 140:97feb9bacc10 2040 ccsidr = SCB->CCSIDR;
<> 140:97feb9bacc10 2041 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<> 140:97feb9bacc10 2042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<> 140:97feb9bacc10 2043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<> 140:97feb9bacc10 2044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<> 140:97feb9bacc10 2045
<> 140:97feb9bacc10 2046 __DSB();
<> 140:97feb9bacc10 2047
<> 140:97feb9bacc10 2048 do { // invalidate D-Cache
<> 140:97feb9bacc10 2049 uint32_t tmpways = ways;
<> 140:97feb9bacc10 2050 do {
<> 140:97feb9bacc10 2051 sw = ((tmpways << wshift) | (sets << sshift));
<> 140:97feb9bacc10 2052 SCB->DCISW = sw;
<> 140:97feb9bacc10 2053 } while(tmpways--);
<> 140:97feb9bacc10 2054 } while(sets--);
<> 140:97feb9bacc10 2055 __DSB();
<> 140:97feb9bacc10 2056
<> 140:97feb9bacc10 2057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
<> 140:97feb9bacc10 2058
<> 140:97feb9bacc10 2059 __DSB();
<> 140:97feb9bacc10 2060 __ISB();
<> 140:97feb9bacc10 2061 #endif
<> 140:97feb9bacc10 2062 }
<> 140:97feb9bacc10 2063
<> 140:97feb9bacc10 2064
<> 140:97feb9bacc10 2065 /** \brief Disable D-Cache
<> 140:97feb9bacc10 2066
<> 140:97feb9bacc10 2067 The function turns off D-Cache
<> 140:97feb9bacc10 2068 */
<> 140:97feb9bacc10 2069 __STATIC_INLINE void SCB_DisableDCache (void)
<> 140:97feb9bacc10 2070 {
<> 140:97feb9bacc10 2071 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2072 uint32_t ccsidr, sshift, wshift, sw;
<> 140:97feb9bacc10 2073 uint32_t sets, ways;
<> 140:97feb9bacc10 2074
<> 140:97feb9bacc10 2075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
<> 140:97feb9bacc10 2076 ccsidr = SCB->CCSIDR;
<> 140:97feb9bacc10 2077 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<> 140:97feb9bacc10 2078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<> 140:97feb9bacc10 2079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<> 140:97feb9bacc10 2080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<> 140:97feb9bacc10 2081
<> 140:97feb9bacc10 2082 __DSB();
<> 140:97feb9bacc10 2083
<> 140:97feb9bacc10 2084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
<> 140:97feb9bacc10 2085
<> 140:97feb9bacc10 2086 do { // clean & invalidate D-Cache
<> 140:97feb9bacc10 2087 uint32_t tmpways = ways;
<> 140:97feb9bacc10 2088 do {
<> 140:97feb9bacc10 2089 sw = ((tmpways << wshift) | (sets << sshift));
<> 140:97feb9bacc10 2090 SCB->DCCISW = sw;
<> 140:97feb9bacc10 2091 } while(tmpways--);
<> 140:97feb9bacc10 2092 } while(sets--);
<> 140:97feb9bacc10 2093
<> 140:97feb9bacc10 2094
<> 140:97feb9bacc10 2095 __DSB();
<> 140:97feb9bacc10 2096 __ISB();
<> 140:97feb9bacc10 2097 #endif
<> 140:97feb9bacc10 2098 }
<> 140:97feb9bacc10 2099
<> 140:97feb9bacc10 2100
<> 140:97feb9bacc10 2101 /** \brief Invalidate D-Cache
<> 140:97feb9bacc10 2102
<> 140:97feb9bacc10 2103 The function invalidates D-Cache
<> 140:97feb9bacc10 2104 */
<> 140:97feb9bacc10 2105 __STATIC_INLINE void SCB_InvalidateDCache (void)
<> 140:97feb9bacc10 2106 {
<> 140:97feb9bacc10 2107 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2108 uint32_t ccsidr, sshift, wshift, sw;
<> 140:97feb9bacc10 2109 uint32_t sets, ways;
<> 140:97feb9bacc10 2110
<> 140:97feb9bacc10 2111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
<> 140:97feb9bacc10 2112 ccsidr = SCB->CCSIDR;
<> 140:97feb9bacc10 2113 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<> 140:97feb9bacc10 2114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<> 140:97feb9bacc10 2115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<> 140:97feb9bacc10 2116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<> 140:97feb9bacc10 2117
<> 140:97feb9bacc10 2118 __DSB();
<> 140:97feb9bacc10 2119
<> 140:97feb9bacc10 2120 do { // invalidate D-Cache
<> 140:97feb9bacc10 2121 uint32_t tmpways = ways;
<> 140:97feb9bacc10 2122 do {
<> 140:97feb9bacc10 2123 sw = ((tmpways << wshift) | (sets << sshift));
<> 140:97feb9bacc10 2124 SCB->DCISW = sw;
<> 140:97feb9bacc10 2125 } while(tmpways--);
<> 140:97feb9bacc10 2126 } while(sets--);
<> 140:97feb9bacc10 2127
<> 140:97feb9bacc10 2128 __DSB();
<> 140:97feb9bacc10 2129 __ISB();
<> 140:97feb9bacc10 2130 #endif
<> 140:97feb9bacc10 2131 }
<> 140:97feb9bacc10 2132
<> 140:97feb9bacc10 2133
<> 140:97feb9bacc10 2134 /** \brief Clean D-Cache
<> 140:97feb9bacc10 2135
<> 140:97feb9bacc10 2136 The function cleans D-Cache
<> 140:97feb9bacc10 2137 */
<> 140:97feb9bacc10 2138 __STATIC_INLINE void SCB_CleanDCache (void)
<> 140:97feb9bacc10 2139 {
<> 140:97feb9bacc10 2140 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2141 uint32_t ccsidr, sshift, wshift, sw;
<> 140:97feb9bacc10 2142 uint32_t sets, ways;
<> 140:97feb9bacc10 2143
<> 140:97feb9bacc10 2144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
<> 140:97feb9bacc10 2145 ccsidr = SCB->CCSIDR;
<> 140:97feb9bacc10 2146 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<> 140:97feb9bacc10 2147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<> 140:97feb9bacc10 2148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<> 140:97feb9bacc10 2149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<> 140:97feb9bacc10 2150
<> 140:97feb9bacc10 2151 __DSB();
<> 140:97feb9bacc10 2152
<> 140:97feb9bacc10 2153 do { // clean D-Cache
<> 140:97feb9bacc10 2154 uint32_t tmpways = ways;
<> 140:97feb9bacc10 2155 do {
<> 140:97feb9bacc10 2156 sw = ((tmpways << wshift) | (sets << sshift));
<> 140:97feb9bacc10 2157 SCB->DCCSW = sw;
<> 140:97feb9bacc10 2158 } while(tmpways--);
<> 140:97feb9bacc10 2159 } while(sets--);
<> 140:97feb9bacc10 2160
<> 140:97feb9bacc10 2161 __DSB();
<> 140:97feb9bacc10 2162 __ISB();
<> 140:97feb9bacc10 2163 #endif
<> 140:97feb9bacc10 2164 }
<> 140:97feb9bacc10 2165
<> 140:97feb9bacc10 2166
<> 140:97feb9bacc10 2167 /** \brief Clean & Invalidate D-Cache
<> 140:97feb9bacc10 2168
<> 140:97feb9bacc10 2169 The function cleans and Invalidates D-Cache
<> 140:97feb9bacc10 2170 */
<> 140:97feb9bacc10 2171 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
<> 140:97feb9bacc10 2172 {
<> 140:97feb9bacc10 2173 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2174 uint32_t ccsidr, sshift, wshift, sw;
<> 140:97feb9bacc10 2175 uint32_t sets, ways;
<> 140:97feb9bacc10 2176
<> 140:97feb9bacc10 2177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
<> 140:97feb9bacc10 2178 ccsidr = SCB->CCSIDR;
<> 140:97feb9bacc10 2179 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
<> 140:97feb9bacc10 2180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
<> 140:97feb9bacc10 2181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
<> 140:97feb9bacc10 2182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
<> 140:97feb9bacc10 2183
<> 140:97feb9bacc10 2184 __DSB();
<> 140:97feb9bacc10 2185
<> 140:97feb9bacc10 2186 do { // clean & invalidate D-Cache
<> 140:97feb9bacc10 2187 uint32_t tmpways = ways;
<> 140:97feb9bacc10 2188 do {
<> 140:97feb9bacc10 2189 sw = ((tmpways << wshift) | (sets << sshift));
<> 140:97feb9bacc10 2190 SCB->DCCISW = sw;
<> 140:97feb9bacc10 2191 } while(tmpways--);
<> 140:97feb9bacc10 2192 } while(sets--);
<> 140:97feb9bacc10 2193
<> 140:97feb9bacc10 2194 __DSB();
<> 140:97feb9bacc10 2195 __ISB();
<> 140:97feb9bacc10 2196 #endif
<> 140:97feb9bacc10 2197 }
<> 140:97feb9bacc10 2198
<> 140:97feb9bacc10 2199
<> 140:97feb9bacc10 2200 /**
<> 140:97feb9bacc10 2201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2202 \brief D-Cache Invalidate by address
<> 140:97feb9bacc10 2203 \param[in] addr address (aligned to 32-byte boundary)
<> 140:97feb9bacc10 2204 \param[in] dsize size of memory block (in number of bytes)
<> 140:97feb9bacc10 2205 */
<> 140:97feb9bacc10 2206 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2207 {
<> 140:97feb9bacc10 2208 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2209 int32_t op_size = dsize;
<> 140:97feb9bacc10 2210 uint32_t op_addr = (uint32_t)addr;
<> 140:97feb9bacc10 2211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<> 140:97feb9bacc10 2212
<> 140:97feb9bacc10 2213 __DSB();
<> 140:97feb9bacc10 2214
<> 140:97feb9bacc10 2215 while (op_size > 0) {
<> 140:97feb9bacc10 2216 SCB->DCIMVAC = op_addr;
<> 140:97feb9bacc10 2217 op_addr += linesize;
<> 140:97feb9bacc10 2218 op_size -= (int32_t)linesize;
<> 140:97feb9bacc10 2219 }
<> 140:97feb9bacc10 2220
<> 140:97feb9bacc10 2221 __DSB();
<> 140:97feb9bacc10 2222 __ISB();
<> 140:97feb9bacc10 2223 #endif
<> 140:97feb9bacc10 2224 }
<> 140:97feb9bacc10 2225
<> 140:97feb9bacc10 2226
<> 140:97feb9bacc10 2227 /**
<> 140:97feb9bacc10 2228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2229 \brief D-Cache Clean by address
<> 140:97feb9bacc10 2230 \param[in] addr address (aligned to 32-byte boundary)
<> 140:97feb9bacc10 2231 \param[in] dsize size of memory block (in number of bytes)
<> 140:97feb9bacc10 2232 */
<> 140:97feb9bacc10 2233 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2234 {
<> 140:97feb9bacc10 2235 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2236 int32_t op_size = dsize;
<> 140:97feb9bacc10 2237 uint32_t op_addr = (uint32_t) addr;
<> 140:97feb9bacc10 2238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<> 140:97feb9bacc10 2239
<> 140:97feb9bacc10 2240 __DSB();
<> 140:97feb9bacc10 2241
<> 140:97feb9bacc10 2242 while (op_size > 0) {
<> 140:97feb9bacc10 2243 SCB->DCCMVAC = op_addr;
<> 140:97feb9bacc10 2244 op_addr += linesize;
<> 140:97feb9bacc10 2245 op_size -= (int32_t)linesize;
<> 140:97feb9bacc10 2246 }
<> 140:97feb9bacc10 2247
<> 140:97feb9bacc10 2248 __DSB();
<> 140:97feb9bacc10 2249 __ISB();
<> 140:97feb9bacc10 2250 #endif
<> 140:97feb9bacc10 2251 }
<> 140:97feb9bacc10 2252
<> 140:97feb9bacc10 2253
<> 140:97feb9bacc10 2254 /**
<> 140:97feb9bacc10 2255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2256 \brief D-Cache Clean and Invalidate by address
<> 140:97feb9bacc10 2257 \param[in] addr address (aligned to 32-byte boundary)
<> 140:97feb9bacc10 2258 \param[in] dsize size of memory block (in number of bytes)
<> 140:97feb9bacc10 2259 */
<> 140:97feb9bacc10 2260 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<> 140:97feb9bacc10 2261 {
<> 140:97feb9bacc10 2262 #if (__DCACHE_PRESENT == 1)
<> 140:97feb9bacc10 2263 int32_t op_size = dsize;
<> 140:97feb9bacc10 2264 uint32_t op_addr = (uint32_t) addr;
<> 140:97feb9bacc10 2265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
<> 140:97feb9bacc10 2266
<> 140:97feb9bacc10 2267 __DSB();
<> 140:97feb9bacc10 2268
<> 140:97feb9bacc10 2269 while (op_size > 0) {
<> 140:97feb9bacc10 2270 SCB->DCCIMVAC = op_addr;
<> 140:97feb9bacc10 2271 op_addr += linesize;
<> 140:97feb9bacc10 2272 op_size -= (int32_t)linesize;
<> 140:97feb9bacc10 2273 }
<> 140:97feb9bacc10 2274
<> 140:97feb9bacc10 2275 __DSB();
<> 140:97feb9bacc10 2276 __ISB();
<> 140:97feb9bacc10 2277 #endif
<> 140:97feb9bacc10 2278 }
<> 140:97feb9bacc10 2279
<> 140:97feb9bacc10 2280
<> 140:97feb9bacc10 2281 /*@} end of CMSIS_Core_CacheFunctions */
<> 140:97feb9bacc10 2282
<> 140:97feb9bacc10 2283
<> 140:97feb9bacc10 2284
<> 140:97feb9bacc10 2285 /* ################################## SysTick function ############################################ */
<> 140:97feb9bacc10 2286 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 2287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 140:97feb9bacc10 2288 \brief Functions that configure the System.
<> 140:97feb9bacc10 2289 @{
<> 140:97feb9bacc10 2290 */
<> 140:97feb9bacc10 2291
<> 140:97feb9bacc10 2292 #if (__Vendor_SysTickConfig == 0)
<> 140:97feb9bacc10 2293
<> 140:97feb9bacc10 2294 /** \brief System Tick Configuration
<> 140:97feb9bacc10 2295
<> 140:97feb9bacc10 2296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 140:97feb9bacc10 2297 Counter is in free running mode to generate periodic interrupts.
<> 140:97feb9bacc10 2298
<> 140:97feb9bacc10 2299 \param [in] ticks Number of ticks between two interrupts.
<> 140:97feb9bacc10 2300
<> 140:97feb9bacc10 2301 \return 0 Function succeeded.
<> 140:97feb9bacc10 2302 \return 1 Function failed.
<> 140:97feb9bacc10 2303
<> 140:97feb9bacc10 2304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 140:97feb9bacc10 2305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 140:97feb9bacc10 2306 must contain a vendor-specific implementation of this function.
<> 140:97feb9bacc10 2307
<> 140:97feb9bacc10 2308 */
<> 140:97feb9bacc10 2309 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 140:97feb9bacc10 2310 {
<> 140:97feb9bacc10 2311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 140:97feb9bacc10 2312
<> 140:97feb9bacc10 2313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 140:97feb9bacc10 2314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 140:97feb9bacc10 2315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 140:97feb9bacc10 2316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 140:97feb9bacc10 2317 SysTick_CTRL_TICKINT_Msk |
<> 140:97feb9bacc10 2318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 140:97feb9bacc10 2319 return (0UL); /* Function successful */
<> 140:97feb9bacc10 2320 }
<> 140:97feb9bacc10 2321
<> 140:97feb9bacc10 2322 #endif
<> 140:97feb9bacc10 2323
<> 140:97feb9bacc10 2324 /*@} end of CMSIS_Core_SysTickFunctions */
<> 140:97feb9bacc10 2325
<> 140:97feb9bacc10 2326
<> 140:97feb9bacc10 2327
<> 140:97feb9bacc10 2328 /* ##################################### Debug In/Output function ########################################### */
<> 140:97feb9bacc10 2329 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 2330 \defgroup CMSIS_core_DebugFunctions ITM Functions
<> 140:97feb9bacc10 2331 \brief Functions that access the ITM debug interface.
<> 140:97feb9bacc10 2332 @{
<> 140:97feb9bacc10 2333 */
<> 140:97feb9bacc10 2334
<> 140:97feb9bacc10 2335 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
<> 140:97feb9bacc10 2336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 140:97feb9bacc10 2337
<> 140:97feb9bacc10 2338
<> 140:97feb9bacc10 2339 /** \brief ITM Send Character
<> 140:97feb9bacc10 2340
<> 140:97feb9bacc10 2341 The function transmits a character via the ITM channel 0, and
<> 140:97feb9bacc10 2342 \li Just returns when no debugger is connected that has booked the output.
<> 140:97feb9bacc10 2343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<> 140:97feb9bacc10 2344
<> 140:97feb9bacc10 2345 \param [in] ch Character to transmit.
<> 140:97feb9bacc10 2346
<> 140:97feb9bacc10 2347 \returns Character to transmit.
<> 140:97feb9bacc10 2348 */
<> 140:97feb9bacc10 2349 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 140:97feb9bacc10 2350 {
<> 140:97feb9bacc10 2351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 140:97feb9bacc10 2352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 140:97feb9bacc10 2353 {
<> 140:97feb9bacc10 2354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<> 140:97feb9bacc10 2355 ITM->PORT[0].u8 = (uint8_t)ch;
<> 140:97feb9bacc10 2356 }
<> 140:97feb9bacc10 2357 return (ch);
<> 140:97feb9bacc10 2358 }
<> 140:97feb9bacc10 2359
<> 140:97feb9bacc10 2360
<> 140:97feb9bacc10 2361 /** \brief ITM Receive Character
<> 140:97feb9bacc10 2362
<> 140:97feb9bacc10 2363 The function inputs a character via the external variable \ref ITM_RxBuffer.
<> 140:97feb9bacc10 2364
<> 140:97feb9bacc10 2365 \return Received character.
<> 140:97feb9bacc10 2366 \return -1 No character pending.
<> 140:97feb9bacc10 2367 */
<> 140:97feb9bacc10 2368 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<> 140:97feb9bacc10 2369 int32_t ch = -1; /* no character available */
<> 140:97feb9bacc10 2370
<> 140:97feb9bacc10 2371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<> 140:97feb9bacc10 2372 ch = ITM_RxBuffer;
<> 140:97feb9bacc10 2373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 140:97feb9bacc10 2374 }
<> 140:97feb9bacc10 2375
<> 140:97feb9bacc10 2376 return (ch);
<> 140:97feb9bacc10 2377 }
<> 140:97feb9bacc10 2378
<> 140:97feb9bacc10 2379
<> 140:97feb9bacc10 2380 /** \brief ITM Check Character
<> 140:97feb9bacc10 2381
<> 140:97feb9bacc10 2382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<> 140:97feb9bacc10 2383
<> 140:97feb9bacc10 2384 \return 0 No character available.
<> 140:97feb9bacc10 2385 \return 1 Character available.
<> 140:97feb9bacc10 2386 */
<> 140:97feb9bacc10 2387 __STATIC_INLINE int32_t ITM_CheckChar (void) {
<> 140:97feb9bacc10 2388
<> 140:97feb9bacc10 2389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<> 140:97feb9bacc10 2390 return (0); /* no character available */
<> 140:97feb9bacc10 2391 } else {
<> 140:97feb9bacc10 2392 return (1); /* character available */
<> 140:97feb9bacc10 2393 }
<> 140:97feb9bacc10 2394 }
<> 140:97feb9bacc10 2395
<> 140:97feb9bacc10 2396 /*@} end of CMSIS_core_DebugFunctions */
<> 140:97feb9bacc10 2397
<> 140:97feb9bacc10 2398
<> 140:97feb9bacc10 2399
<> 140:97feb9bacc10 2400
<> 140:97feb9bacc10 2401 #ifdef __cplusplus
<> 140:97feb9bacc10 2402 }
<> 140:97feb9bacc10 2403 #endif
<> 140:97feb9bacc10 2404
<> 140:97feb9bacc10 2405 #endif /* __CORE_CM7_H_DEPENDANT */
<> 140:97feb9bacc10 2406
<> 140:97feb9bacc10 2407 #endif /* __CMSIS_GENERIC */