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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_ca_mmu.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 ;/**************************************************************************//**
<> 140:97feb9bacc10 2 ; * @file core_ca_mmu.h
<> 140:97feb9bacc10 3 ; * @brief MMU Startup File for A9_MP Device Series
<> 140:97feb9bacc10 4 ; * @version V1.01
<> 140:97feb9bacc10 5 ; * @date 10 Sept 2014
<> 140:97feb9bacc10 6 ; *
<> 140:97feb9bacc10 7 ; * @note
<> 140:97feb9bacc10 8 ; *
<> 140:97feb9bacc10 9 ; ******************************************************************************/
<> 140:97feb9bacc10 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
<> 140:97feb9bacc10 11 ;
<> 140:97feb9bacc10 12 ; All rights reserved.
<> 140:97feb9bacc10 13 ; Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 ; modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 ; - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 ; notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 ; - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 ; notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 ; documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 ; - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 ; to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 ; specific prior written permission.
<> 140:97feb9bacc10 23 ; *
<> 140:97feb9bacc10 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 ; POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ; ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37 #ifdef __cplusplus
<> 140:97feb9bacc10 38 extern "C" {
<> 140:97feb9bacc10 39 #endif
<> 140:97feb9bacc10 40
<> 140:97feb9bacc10 41 #ifndef _MMU_FUNC_H
<> 140:97feb9bacc10 42 #define _MMU_FUNC_H
<> 140:97feb9bacc10 43
<> 140:97feb9bacc10 44 #define SECTION_DESCRIPTOR (0x2)
<> 140:97feb9bacc10 45 #define SECTION_MASK (0xFFFFFFFC)
<> 140:97feb9bacc10 46
<> 140:97feb9bacc10 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
<> 140:97feb9bacc10 48 #define SECTION_B_SHIFT (2)
<> 140:97feb9bacc10 49 #define SECTION_C_SHIFT (3)
<> 140:97feb9bacc10 50 #define SECTION_TEX0_SHIFT (12)
<> 140:97feb9bacc10 51 #define SECTION_TEX1_SHIFT (13)
<> 140:97feb9bacc10 52 #define SECTION_TEX2_SHIFT (14)
<> 140:97feb9bacc10 53
<> 140:97feb9bacc10 54 #define SECTION_XN_MASK (0xFFFFFFEF)
<> 140:97feb9bacc10 55 #define SECTION_XN_SHIFT (4)
<> 140:97feb9bacc10 56
<> 140:97feb9bacc10 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
<> 140:97feb9bacc10 58 #define SECTION_DOMAIN_SHIFT (5)
<> 140:97feb9bacc10 59
<> 140:97feb9bacc10 60 #define SECTION_P_MASK (0xFFFFFDFF)
<> 140:97feb9bacc10 61 #define SECTION_P_SHIFT (9)
<> 140:97feb9bacc10 62
<> 140:97feb9bacc10 63 #define SECTION_AP_MASK (0xFFFF73FF)
<> 140:97feb9bacc10 64 #define SECTION_AP_SHIFT (10)
<> 140:97feb9bacc10 65 #define SECTION_AP2_SHIFT (15)
<> 140:97feb9bacc10 66
<> 140:97feb9bacc10 67 #define SECTION_S_MASK (0xFFFEFFFF)
<> 140:97feb9bacc10 68 #define SECTION_S_SHIFT (16)
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70 #define SECTION_NG_MASK (0xFFFDFFFF)
<> 140:97feb9bacc10 71 #define SECTION_NG_SHIFT (17)
<> 140:97feb9bacc10 72
<> 140:97feb9bacc10 73 #define SECTION_NS_MASK (0xFFF7FFFF)
<> 140:97feb9bacc10 74 #define SECTION_NS_SHIFT (19)
<> 140:97feb9bacc10 75
<> 140:97feb9bacc10 76
<> 140:97feb9bacc10 77 #define PAGE_L1_DESCRIPTOR (0x1)
<> 140:97feb9bacc10 78 #define PAGE_L1_MASK (0xFFFFFFFC)
<> 140:97feb9bacc10 79
<> 140:97feb9bacc10 80 #define PAGE_L2_4K_DESC (0x2)
<> 140:97feb9bacc10 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
<> 140:97feb9bacc10 82
<> 140:97feb9bacc10 83 #define PAGE_L2_64K_DESC (0x1)
<> 140:97feb9bacc10 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
<> 140:97feb9bacc10 85
<> 140:97feb9bacc10 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
<> 140:97feb9bacc10 87 #define PAGE_4K_B_SHIFT (2)
<> 140:97feb9bacc10 88 #define PAGE_4K_C_SHIFT (3)
<> 140:97feb9bacc10 89 #define PAGE_4K_TEX0_SHIFT (6)
<> 140:97feb9bacc10 90 #define PAGE_4K_TEX1_SHIFT (7)
<> 140:97feb9bacc10 91 #define PAGE_4K_TEX2_SHIFT (8)
<> 140:97feb9bacc10 92
<> 140:97feb9bacc10 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
<> 140:97feb9bacc10 94 #define PAGE_64K_B_SHIFT (2)
<> 140:97feb9bacc10 95 #define PAGE_64K_C_SHIFT (3)
<> 140:97feb9bacc10 96 #define PAGE_64K_TEX0_SHIFT (12)
<> 140:97feb9bacc10 97 #define PAGE_64K_TEX1_SHIFT (13)
<> 140:97feb9bacc10 98 #define PAGE_64K_TEX2_SHIFT (14)
<> 140:97feb9bacc10 99
<> 140:97feb9bacc10 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
<> 140:97feb9bacc10 101 #define PAGE_B_SHIFT (2)
<> 140:97feb9bacc10 102 #define PAGE_C_SHIFT (3)
<> 140:97feb9bacc10 103 #define PAGE_TEX_SHIFT (12)
<> 140:97feb9bacc10 104
<> 140:97feb9bacc10 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
<> 140:97feb9bacc10 106 #define PAGE_XN_4K_SHIFT (0)
<> 140:97feb9bacc10 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
<> 140:97feb9bacc10 108 #define PAGE_XN_64K_SHIFT (15)
<> 140:97feb9bacc10 109
<> 140:97feb9bacc10 110
<> 140:97feb9bacc10 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
<> 140:97feb9bacc10 112 #define PAGE_DOMAIN_SHIFT (5)
<> 140:97feb9bacc10 113
<> 140:97feb9bacc10 114 #define PAGE_P_MASK (0xFFFFFDFF)
<> 140:97feb9bacc10 115 #define PAGE_P_SHIFT (9)
<> 140:97feb9bacc10 116
<> 140:97feb9bacc10 117 #define PAGE_AP_MASK (0xFFFFFDCF)
<> 140:97feb9bacc10 118 #define PAGE_AP_SHIFT (4)
<> 140:97feb9bacc10 119 #define PAGE_AP2_SHIFT (9)
<> 140:97feb9bacc10 120
<> 140:97feb9bacc10 121 #define PAGE_S_MASK (0xFFFFFBFF)
<> 140:97feb9bacc10 122 #define PAGE_S_SHIFT (10)
<> 140:97feb9bacc10 123
<> 140:97feb9bacc10 124 #define PAGE_NG_MASK (0xFFFFF7FF)
<> 140:97feb9bacc10 125 #define PAGE_NG_SHIFT (11)
<> 140:97feb9bacc10 126
<> 140:97feb9bacc10 127 #define PAGE_NS_MASK (0xFFFFFFF7)
<> 140:97feb9bacc10 128 #define PAGE_NS_SHIFT (3)
<> 140:97feb9bacc10 129
<> 140:97feb9bacc10 130 #define OFFSET_1M (0x00100000)
<> 140:97feb9bacc10 131 #define OFFSET_64K (0x00010000)
<> 140:97feb9bacc10 132 #define OFFSET_4K (0x00001000)
<> 140:97feb9bacc10 133
<> 140:97feb9bacc10 134 #define DESCRIPTOR_FAULT (0x00000000)
<> 140:97feb9bacc10 135
<> 140:97feb9bacc10 136 /* ########################### MMU Function Access ########################### */
<> 140:97feb9bacc10 137 /** \ingroup MMU_FunctionInterface
<> 140:97feb9bacc10 138 \defgroup MMU_Functions MMU Functions Interface
<> 140:97feb9bacc10 139 @{
<> 140:97feb9bacc10 140 */
<> 140:97feb9bacc10 141
<> 140:97feb9bacc10 142 /* Attributes enumerations */
<> 140:97feb9bacc10 143
<> 140:97feb9bacc10 144 /* Region size attributes */
<> 140:97feb9bacc10 145 typedef enum
<> 140:97feb9bacc10 146 {
<> 140:97feb9bacc10 147 SECTION,
<> 140:97feb9bacc10 148 PAGE_4k,
<> 140:97feb9bacc10 149 PAGE_64k,
<> 140:97feb9bacc10 150 } mmu_region_size_Type;
<> 140:97feb9bacc10 151
<> 140:97feb9bacc10 152 /* Region type attributes */
<> 140:97feb9bacc10 153 typedef enum
<> 140:97feb9bacc10 154 {
<> 140:97feb9bacc10 155 NORMAL,
<> 140:97feb9bacc10 156 DEVICE,
<> 140:97feb9bacc10 157 SHARED_DEVICE,
<> 140:97feb9bacc10 158 NON_SHARED_DEVICE,
<> 140:97feb9bacc10 159 STRONGLY_ORDERED
<> 140:97feb9bacc10 160 } mmu_memory_Type;
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 /* Region cacheability attributes */
<> 140:97feb9bacc10 163 typedef enum
<> 140:97feb9bacc10 164 {
<> 140:97feb9bacc10 165 NON_CACHEABLE,
<> 140:97feb9bacc10 166 WB_WA,
<> 140:97feb9bacc10 167 WT,
<> 140:97feb9bacc10 168 WB_NO_WA,
<> 140:97feb9bacc10 169 } mmu_cacheability_Type;
<> 140:97feb9bacc10 170
<> 140:97feb9bacc10 171 /* Region parity check attributes */
<> 140:97feb9bacc10 172 typedef enum
<> 140:97feb9bacc10 173 {
<> 140:97feb9bacc10 174 ECC_DISABLED,
<> 140:97feb9bacc10 175 ECC_ENABLED,
<> 140:97feb9bacc10 176 } mmu_ecc_check_Type;
<> 140:97feb9bacc10 177
<> 140:97feb9bacc10 178 /* Region execution attributes */
<> 140:97feb9bacc10 179 typedef enum
<> 140:97feb9bacc10 180 {
<> 140:97feb9bacc10 181 EXECUTE,
<> 140:97feb9bacc10 182 NON_EXECUTE,
<> 140:97feb9bacc10 183 } mmu_execute_Type;
<> 140:97feb9bacc10 184
<> 140:97feb9bacc10 185 /* Region global attributes */
<> 140:97feb9bacc10 186 typedef enum
<> 140:97feb9bacc10 187 {
<> 140:97feb9bacc10 188 GLOBAL,
<> 140:97feb9bacc10 189 NON_GLOBAL,
<> 140:97feb9bacc10 190 } mmu_global_Type;
<> 140:97feb9bacc10 191
<> 140:97feb9bacc10 192 /* Region shareability attributes */
<> 140:97feb9bacc10 193 typedef enum
<> 140:97feb9bacc10 194 {
<> 140:97feb9bacc10 195 NON_SHARED,
<> 140:97feb9bacc10 196 SHARED,
<> 140:97feb9bacc10 197 } mmu_shared_Type;
<> 140:97feb9bacc10 198
<> 140:97feb9bacc10 199 /* Region security attributes */
<> 140:97feb9bacc10 200 typedef enum
<> 140:97feb9bacc10 201 {
<> 140:97feb9bacc10 202 SECURE,
<> 140:97feb9bacc10 203 NON_SECURE,
<> 140:97feb9bacc10 204 } mmu_secure_Type;
<> 140:97feb9bacc10 205
<> 140:97feb9bacc10 206 /* Region access attributes */
<> 140:97feb9bacc10 207 typedef enum
<> 140:97feb9bacc10 208 {
<> 140:97feb9bacc10 209 NO_ACCESS,
<> 140:97feb9bacc10 210 RW,
<> 140:97feb9bacc10 211 READ,
<> 140:97feb9bacc10 212 } mmu_access_Type;
<> 140:97feb9bacc10 213
<> 140:97feb9bacc10 214 /* Memory Region definition */
<> 140:97feb9bacc10 215 typedef struct RegionStruct {
<> 140:97feb9bacc10 216 mmu_region_size_Type rg_t;
<> 140:97feb9bacc10 217 mmu_memory_Type mem_t;
<> 140:97feb9bacc10 218 uint8_t domain;
<> 140:97feb9bacc10 219 mmu_cacheability_Type inner_norm_t;
<> 140:97feb9bacc10 220 mmu_cacheability_Type outer_norm_t;
<> 140:97feb9bacc10 221 mmu_ecc_check_Type e_t;
<> 140:97feb9bacc10 222 mmu_execute_Type xn_t;
<> 140:97feb9bacc10 223 mmu_global_Type g_t;
<> 140:97feb9bacc10 224 mmu_secure_Type sec_t;
<> 140:97feb9bacc10 225 mmu_access_Type priv_t;
<> 140:97feb9bacc10 226 mmu_access_Type user_t;
<> 140:97feb9bacc10 227 mmu_shared_Type sh_t;
<> 140:97feb9bacc10 228
<> 140:97feb9bacc10 229 } mmu_region_attributes_Type;
<> 140:97feb9bacc10 230
<> 140:97feb9bacc10 231 /** \brief Set section execution-never attribute
<> 140:97feb9bacc10 232
<> 140:97feb9bacc10 233 The function sets section execution-never attribute
<> 140:97feb9bacc10 234
<> 140:97feb9bacc10 235 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
<> 140:97feb9bacc10 237
<> 140:97feb9bacc10 238 \return 0
<> 140:97feb9bacc10 239 */
<> 140:97feb9bacc10 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
<> 140:97feb9bacc10 241 {
<> 140:97feb9bacc10 242 *descriptor_l1 &= SECTION_XN_MASK;
<> 140:97feb9bacc10 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
<> 140:97feb9bacc10 244 return 0;
<> 140:97feb9bacc10 245 }
<> 140:97feb9bacc10 246
<> 140:97feb9bacc10 247 /** \brief Set section domain
<> 140:97feb9bacc10 248
<> 140:97feb9bacc10 249 The function sets section domain
<> 140:97feb9bacc10 250
<> 140:97feb9bacc10 251 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 252 \param [in] domain Section domain
<> 140:97feb9bacc10 253
<> 140:97feb9bacc10 254 \return 0
<> 140:97feb9bacc10 255 */
<> 140:97feb9bacc10 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
<> 140:97feb9bacc10 257 {
<> 140:97feb9bacc10 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
<> 140:97feb9bacc10 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
<> 140:97feb9bacc10 260 return 0;
<> 140:97feb9bacc10 261 }
<> 140:97feb9bacc10 262
<> 140:97feb9bacc10 263 /** \brief Set section parity check
<> 140:97feb9bacc10 264
<> 140:97feb9bacc10 265 The function sets section parity check
<> 140:97feb9bacc10 266
<> 140:97feb9bacc10 267 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 140:97feb9bacc10 269
<> 140:97feb9bacc10 270 \return 0
<> 140:97feb9bacc10 271 */
<> 140:97feb9bacc10 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 140:97feb9bacc10 273 {
<> 140:97feb9bacc10 274 *descriptor_l1 &= SECTION_P_MASK;
<> 140:97feb9bacc10 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 140:97feb9bacc10 276 return 0;
<> 140:97feb9bacc10 277 }
<> 140:97feb9bacc10 278
<> 140:97feb9bacc10 279 /** \brief Set section access privileges
<> 140:97feb9bacc10 280
<> 140:97feb9bacc10 281 The function sets section access privileges
<> 140:97feb9bacc10 282
<> 140:97feb9bacc10 283 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 140:97feb9bacc10 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 140:97feb9bacc10 286 \param [in] afe Access flag enable
<> 140:97feb9bacc10 287
<> 140:97feb9bacc10 288 \return 0
<> 140:97feb9bacc10 289 */
<> 140:97feb9bacc10 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 140:97feb9bacc10 291 {
<> 140:97feb9bacc10 292 uint32_t ap = 0;
<> 140:97feb9bacc10 293
<> 140:97feb9bacc10 294 if (afe == 0) { //full access
<> 140:97feb9bacc10 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 140:97feb9bacc10 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 140:97feb9bacc10 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 140:97feb9bacc10 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 140:97feb9bacc10 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 140:97feb9bacc10 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 140:97feb9bacc10 301 }
<> 140:97feb9bacc10 302
<> 140:97feb9bacc10 303 else { //Simplified access
<> 140:97feb9bacc10 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 140:97feb9bacc10 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 140:97feb9bacc10 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 140:97feb9bacc10 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 140:97feb9bacc10 308 }
<> 140:97feb9bacc10 309
<> 140:97feb9bacc10 310 *descriptor_l1 &= SECTION_AP_MASK;
<> 140:97feb9bacc10 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
<> 140:97feb9bacc10 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
<> 140:97feb9bacc10 313
<> 140:97feb9bacc10 314 return 0;
<> 140:97feb9bacc10 315 }
<> 140:97feb9bacc10 316
<> 140:97feb9bacc10 317 /** \brief Set section shareability
<> 140:97feb9bacc10 318
<> 140:97feb9bacc10 319 The function sets section shareability
<> 140:97feb9bacc10 320
<> 140:97feb9bacc10 321 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324 \return 0
<> 140:97feb9bacc10 325 */
<> 140:97feb9bacc10 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
<> 140:97feb9bacc10 327 {
<> 140:97feb9bacc10 328 *descriptor_l1 &= SECTION_S_MASK;
<> 140:97feb9bacc10 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
<> 140:97feb9bacc10 330 return 0;
<> 140:97feb9bacc10 331 }
<> 140:97feb9bacc10 332
<> 140:97feb9bacc10 333 /** \brief Set section Global attribute
<> 140:97feb9bacc10 334
<> 140:97feb9bacc10 335 The function sets section Global attribute
<> 140:97feb9bacc10 336
<> 140:97feb9bacc10 337 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
<> 140:97feb9bacc10 339
<> 140:97feb9bacc10 340 \return 0
<> 140:97feb9bacc10 341 */
<> 140:97feb9bacc10 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
<> 140:97feb9bacc10 343 {
<> 140:97feb9bacc10 344 *descriptor_l1 &= SECTION_NG_MASK;
<> 140:97feb9bacc10 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
<> 140:97feb9bacc10 346 return 0;
<> 140:97feb9bacc10 347 }
<> 140:97feb9bacc10 348
<> 140:97feb9bacc10 349 /** \brief Set section Security attribute
<> 140:97feb9bacc10 350
<> 140:97feb9bacc10 351 The function sets section Global attribute
<> 140:97feb9bacc10 352
<> 140:97feb9bacc10 353 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
<> 140:97feb9bacc10 355
<> 140:97feb9bacc10 356 \return 0
<> 140:97feb9bacc10 357 */
<> 140:97feb9bacc10 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 140:97feb9bacc10 359 {
<> 140:97feb9bacc10 360 *descriptor_l1 &= SECTION_NS_MASK;
<> 140:97feb9bacc10 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
<> 140:97feb9bacc10 362 return 0;
<> 140:97feb9bacc10 363 }
<> 140:97feb9bacc10 364
<> 140:97feb9bacc10 365 /* Page 4k or 64k */
<> 140:97feb9bacc10 366 /** \brief Set 4k/64k page execution-never attribute
<> 140:97feb9bacc10 367
<> 140:97feb9bacc10 368 The function sets 4k/64k page execution-never attribute
<> 140:97feb9bacc10 369
<> 140:97feb9bacc10 370 \param [out] descriptor_l2 L2 descriptor.
<> 140:97feb9bacc10 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
<> 140:97feb9bacc10 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
<> 140:97feb9bacc10 373
<> 140:97feb9bacc10 374 \return 0
<> 140:97feb9bacc10 375 */
<> 140:97feb9bacc10 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
<> 140:97feb9bacc10 377 {
<> 140:97feb9bacc10 378 if (page == PAGE_4k)
<> 140:97feb9bacc10 379 {
<> 140:97feb9bacc10 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
<> 140:97feb9bacc10 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
<> 140:97feb9bacc10 382 }
<> 140:97feb9bacc10 383 else
<> 140:97feb9bacc10 384 {
<> 140:97feb9bacc10 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
<> 140:97feb9bacc10 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
<> 140:97feb9bacc10 387 }
<> 140:97feb9bacc10 388 return 0;
<> 140:97feb9bacc10 389 }
<> 140:97feb9bacc10 390
<> 140:97feb9bacc10 391 /** \brief Set 4k/64k page domain
<> 140:97feb9bacc10 392
<> 140:97feb9bacc10 393 The function sets 4k/64k page domain
<> 140:97feb9bacc10 394
<> 140:97feb9bacc10 395 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 396 \param [in] domain Page domain
<> 140:97feb9bacc10 397
<> 140:97feb9bacc10 398 \return 0
<> 140:97feb9bacc10 399 */
<> 140:97feb9bacc10 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
<> 140:97feb9bacc10 401 {
<> 140:97feb9bacc10 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
<> 140:97feb9bacc10 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
<> 140:97feb9bacc10 404 return 0;
<> 140:97feb9bacc10 405 }
<> 140:97feb9bacc10 406
<> 140:97feb9bacc10 407 /** \brief Set 4k/64k page parity check
<> 140:97feb9bacc10 408
<> 140:97feb9bacc10 409 The function sets 4k/64k page parity check
<> 140:97feb9bacc10 410
<> 140:97feb9bacc10 411 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
<> 140:97feb9bacc10 413
<> 140:97feb9bacc10 414 \return 0
<> 140:97feb9bacc10 415 */
<> 140:97feb9bacc10 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
<> 140:97feb9bacc10 417 {
<> 140:97feb9bacc10 418 *descriptor_l1 &= SECTION_P_MASK;
<> 140:97feb9bacc10 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
<> 140:97feb9bacc10 420 return 0;
<> 140:97feb9bacc10 421 }
<> 140:97feb9bacc10 422
<> 140:97feb9bacc10 423 /** \brief Set 4k/64k page access privileges
<> 140:97feb9bacc10 424
<> 140:97feb9bacc10 425 The function sets 4k/64k page access privileges
<> 140:97feb9bacc10 426
<> 140:97feb9bacc10 427 \param [out] descriptor_l2 L2 descriptor.
<> 140:97feb9bacc10 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
<> 140:97feb9bacc10 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
<> 140:97feb9bacc10 430 \param [in] afe Access flag enable
<> 140:97feb9bacc10 431
<> 140:97feb9bacc10 432 \return 0
<> 140:97feb9bacc10 433 */
<> 140:97feb9bacc10 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
<> 140:97feb9bacc10 435 {
<> 140:97feb9bacc10 436 uint32_t ap = 0;
<> 140:97feb9bacc10 437
<> 140:97feb9bacc10 438 if (afe == 0) { //full access
<> 140:97feb9bacc10 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
<> 140:97feb9bacc10 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 140:97feb9bacc10 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
<> 140:97feb9bacc10 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 140:97feb9bacc10 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 140:97feb9bacc10 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
<> 140:97feb9bacc10 445 }
<> 140:97feb9bacc10 446
<> 140:97feb9bacc10 447 else { //Simplified access
<> 140:97feb9bacc10 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
<> 140:97feb9bacc10 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
<> 140:97feb9bacc10 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
<> 140:97feb9bacc10 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
<> 140:97feb9bacc10 452 }
<> 140:97feb9bacc10 453
<> 140:97feb9bacc10 454 *descriptor_l2 &= PAGE_AP_MASK;
<> 140:97feb9bacc10 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
<> 140:97feb9bacc10 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
<> 140:97feb9bacc10 457
<> 140:97feb9bacc10 458 return 0;
<> 140:97feb9bacc10 459 }
<> 140:97feb9bacc10 460
<> 140:97feb9bacc10 461 /** \brief Set 4k/64k page shareability
<> 140:97feb9bacc10 462
<> 140:97feb9bacc10 463 The function sets 4k/64k page shareability
<> 140:97feb9bacc10 464
<> 140:97feb9bacc10 465 \param [out] descriptor_l2 L2 descriptor.
<> 140:97feb9bacc10 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
<> 140:97feb9bacc10 467
<> 140:97feb9bacc10 468 \return 0
<> 140:97feb9bacc10 469 */
<> 140:97feb9bacc10 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
<> 140:97feb9bacc10 471 {
<> 140:97feb9bacc10 472 *descriptor_l2 &= PAGE_S_MASK;
<> 140:97feb9bacc10 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
<> 140:97feb9bacc10 474 return 0;
<> 140:97feb9bacc10 475 }
<> 140:97feb9bacc10 476
<> 140:97feb9bacc10 477 /** \brief Set 4k/64k page Global attribute
<> 140:97feb9bacc10 478
<> 140:97feb9bacc10 479 The function sets 4k/64k page Global attribute
<> 140:97feb9bacc10 480
<> 140:97feb9bacc10 481 \param [out] descriptor_l2 L2 descriptor.
<> 140:97feb9bacc10 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
<> 140:97feb9bacc10 483
<> 140:97feb9bacc10 484 \return 0
<> 140:97feb9bacc10 485 */
<> 140:97feb9bacc10 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
<> 140:97feb9bacc10 487 {
<> 140:97feb9bacc10 488 *descriptor_l2 &= PAGE_NG_MASK;
<> 140:97feb9bacc10 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
<> 140:97feb9bacc10 490 return 0;
<> 140:97feb9bacc10 491 }
<> 140:97feb9bacc10 492
<> 140:97feb9bacc10 493 /** \brief Set 4k/64k page Security attribute
<> 140:97feb9bacc10 494
<> 140:97feb9bacc10 495 The function sets 4k/64k page Global attribute
<> 140:97feb9bacc10 496
<> 140:97feb9bacc10 497 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
<> 140:97feb9bacc10 499
<> 140:97feb9bacc10 500 \return 0
<> 140:97feb9bacc10 501 */
<> 140:97feb9bacc10 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
<> 140:97feb9bacc10 503 {
<> 140:97feb9bacc10 504 *descriptor_l1 &= PAGE_NS_MASK;
<> 140:97feb9bacc10 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
<> 140:97feb9bacc10 506 return 0;
<> 140:97feb9bacc10 507 }
<> 140:97feb9bacc10 508
<> 140:97feb9bacc10 509
<> 140:97feb9bacc10 510 /** \brief Set Section memory attributes
<> 140:97feb9bacc10 511
<> 140:97feb9bacc10 512 The function sets section memory attributes
<> 140:97feb9bacc10 513
<> 140:97feb9bacc10 514 \param [out] descriptor_l1 L1 descriptor.
<> 140:97feb9bacc10 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 140:97feb9bacc10 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 140:97feb9bacc10 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 140:97feb9bacc10 518
<> 140:97feb9bacc10 519 \return 0
<> 140:97feb9bacc10 520 */
<> 140:97feb9bacc10 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
<> 140:97feb9bacc10 522 {
<> 140:97feb9bacc10 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
<> 140:97feb9bacc10 524
<> 140:97feb9bacc10 525 if (STRONGLY_ORDERED == mem)
<> 140:97feb9bacc10 526 {
<> 140:97feb9bacc10 527 return 0;
<> 140:97feb9bacc10 528 }
<> 140:97feb9bacc10 529 else if (SHARED_DEVICE == mem)
<> 140:97feb9bacc10 530 {
<> 140:97feb9bacc10 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 140:97feb9bacc10 532 }
<> 140:97feb9bacc10 533 else if (NON_SHARED_DEVICE == mem)
<> 140:97feb9bacc10 534 {
<> 140:97feb9bacc10 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
<> 140:97feb9bacc10 536 }
<> 140:97feb9bacc10 537 else if (NORMAL == mem)
<> 140:97feb9bacc10 538 {
<> 140:97feb9bacc10 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
<> 140:97feb9bacc10 540 switch(inner)
<> 140:97feb9bacc10 541 {
<> 140:97feb9bacc10 542 case NON_CACHEABLE:
<> 140:97feb9bacc10 543 break;
<> 140:97feb9bacc10 544 case WB_WA:
<> 140:97feb9bacc10 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
<> 140:97feb9bacc10 546 break;
<> 140:97feb9bacc10 547 case WT:
<> 140:97feb9bacc10 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
<> 140:97feb9bacc10 549 break;
<> 140:97feb9bacc10 550 case WB_NO_WA:
<> 140:97feb9bacc10 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
<> 140:97feb9bacc10 552 break;
<> 140:97feb9bacc10 553 }
<> 140:97feb9bacc10 554 switch(outer)
<> 140:97feb9bacc10 555 {
<> 140:97feb9bacc10 556 case NON_CACHEABLE:
<> 140:97feb9bacc10 557 break;
<> 140:97feb9bacc10 558 case WB_WA:
<> 140:97feb9bacc10 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
<> 140:97feb9bacc10 560 break;
<> 140:97feb9bacc10 561 case WT:
<> 140:97feb9bacc10 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
<> 140:97feb9bacc10 563 break;
<> 140:97feb9bacc10 564 case WB_NO_WA:
<> 140:97feb9bacc10 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
<> 140:97feb9bacc10 566 break;
<> 140:97feb9bacc10 567 }
<> 140:97feb9bacc10 568 }
<> 140:97feb9bacc10 569
<> 140:97feb9bacc10 570 return 0;
<> 140:97feb9bacc10 571 }
<> 140:97feb9bacc10 572
<> 140:97feb9bacc10 573 /** \brief Set 4k/64k page memory attributes
<> 140:97feb9bacc10 574
<> 140:97feb9bacc10 575 The function sets 4k/64k page memory attributes
<> 140:97feb9bacc10 576
<> 140:97feb9bacc10 577 \param [out] descriptor_l2 L2 descriptor.
<> 140:97feb9bacc10 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
<> 140:97feb9bacc10 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 140:97feb9bacc10 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
<> 140:97feb9bacc10 581
<> 140:97feb9bacc10 582 \return 0
<> 140:97feb9bacc10 583 */
<> 140:97feb9bacc10 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
<> 140:97feb9bacc10 585 {
<> 140:97feb9bacc10 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
<> 140:97feb9bacc10 587
<> 140:97feb9bacc10 588 if (page == PAGE_64k)
<> 140:97feb9bacc10 589 {
<> 140:97feb9bacc10 590 //same as section
<> 140:97feb9bacc10 591 __memory_section(descriptor_l2, mem, outer, inner);
<> 140:97feb9bacc10 592 }
<> 140:97feb9bacc10 593 else
<> 140:97feb9bacc10 594 {
<> 140:97feb9bacc10 595 if (STRONGLY_ORDERED == mem)
<> 140:97feb9bacc10 596 {
<> 140:97feb9bacc10 597 return 0;
<> 140:97feb9bacc10 598 }
<> 140:97feb9bacc10 599 else if (SHARED_DEVICE == mem)
<> 140:97feb9bacc10 600 {
<> 140:97feb9bacc10 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 140:97feb9bacc10 602 }
<> 140:97feb9bacc10 603 else if (NON_SHARED_DEVICE == mem)
<> 140:97feb9bacc10 604 {
<> 140:97feb9bacc10 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
<> 140:97feb9bacc10 606 }
<> 140:97feb9bacc10 607 else if (NORMAL == mem)
<> 140:97feb9bacc10 608 {
<> 140:97feb9bacc10 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
<> 140:97feb9bacc10 610 switch(inner)
<> 140:97feb9bacc10 611 {
<> 140:97feb9bacc10 612 case NON_CACHEABLE:
<> 140:97feb9bacc10 613 break;
<> 140:97feb9bacc10 614 case WB_WA:
<> 140:97feb9bacc10 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
<> 140:97feb9bacc10 616 break;
<> 140:97feb9bacc10 617 case WT:
<> 140:97feb9bacc10 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
<> 140:97feb9bacc10 619 break;
<> 140:97feb9bacc10 620 case WB_NO_WA:
<> 140:97feb9bacc10 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
<> 140:97feb9bacc10 622 break;
<> 140:97feb9bacc10 623 }
<> 140:97feb9bacc10 624 switch(outer)
<> 140:97feb9bacc10 625 {
<> 140:97feb9bacc10 626 case NON_CACHEABLE:
<> 140:97feb9bacc10 627 break;
<> 140:97feb9bacc10 628 case WB_WA:
<> 140:97feb9bacc10 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
<> 140:97feb9bacc10 630 break;
<> 140:97feb9bacc10 631 case WT:
<> 140:97feb9bacc10 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
<> 140:97feb9bacc10 633 break;
<> 140:97feb9bacc10 634 case WB_NO_WA:
<> 140:97feb9bacc10 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
<> 140:97feb9bacc10 636 break;
<> 140:97feb9bacc10 637 }
<> 140:97feb9bacc10 638 }
<> 140:97feb9bacc10 639 }
<> 140:97feb9bacc10 640
<> 140:97feb9bacc10 641 return 0;
<> 140:97feb9bacc10 642 }
<> 140:97feb9bacc10 643
<> 140:97feb9bacc10 644 /** \brief Create a L1 section descriptor
<> 140:97feb9bacc10 645
<> 140:97feb9bacc10 646 The function creates a section descriptor.
<> 140:97feb9bacc10 647
<> 140:97feb9bacc10 648 Assumptions:
<> 140:97feb9bacc10 649 - 16MB super sections not supported
<> 140:97feb9bacc10 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 140:97feb9bacc10 651 - Functions always return 0
<> 140:97feb9bacc10 652
<> 140:97feb9bacc10 653 \param [out] descriptor L1 descriptor
<> 140:97feb9bacc10 654 \param [out] descriptor2 L2 descriptor
<> 140:97feb9bacc10 655 \param [in] reg Section attributes
<> 140:97feb9bacc10 656
<> 140:97feb9bacc10 657 \return 0
<> 140:97feb9bacc10 658 */
<> 140:97feb9bacc10 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
<> 140:97feb9bacc10 660 {
<> 140:97feb9bacc10 661 *descriptor = 0;
<> 140:97feb9bacc10 662
<> 140:97feb9bacc10 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
<> 140:97feb9bacc10 664 __xn_section(descriptor,reg.xn_t);
<> 140:97feb9bacc10 665 __domain_section(descriptor, reg.domain);
<> 140:97feb9bacc10 666 __p_section(descriptor, reg.e_t);
<> 140:97feb9bacc10 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
<> 140:97feb9bacc10 668 __shared_section(descriptor,reg.sh_t);
<> 140:97feb9bacc10 669 __global_section(descriptor,reg.g_t);
<> 140:97feb9bacc10 670 __secure_section(descriptor,reg.sec_t);
<> 140:97feb9bacc10 671 *descriptor &= SECTION_MASK;
<> 140:97feb9bacc10 672 *descriptor |= SECTION_DESCRIPTOR;
<> 140:97feb9bacc10 673
<> 140:97feb9bacc10 674 return 0;
<> 140:97feb9bacc10 675
<> 140:97feb9bacc10 676 }
<> 140:97feb9bacc10 677
<> 140:97feb9bacc10 678
<> 140:97feb9bacc10 679 /** \brief Create a L1 and L2 4k/64k page descriptor
<> 140:97feb9bacc10 680
<> 140:97feb9bacc10 681 The function creates a 4k/64k page descriptor.
<> 140:97feb9bacc10 682 Assumptions:
<> 140:97feb9bacc10 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
<> 140:97feb9bacc10 684 - Functions always return 0
<> 140:97feb9bacc10 685
<> 140:97feb9bacc10 686 \param [out] descriptor L1 descriptor
<> 140:97feb9bacc10 687 \param [out] descriptor2 L2 descriptor
<> 140:97feb9bacc10 688 \param [in] reg 4k/64k page attributes
<> 140:97feb9bacc10 689
<> 140:97feb9bacc10 690 \return 0
<> 140:97feb9bacc10 691 */
<> 140:97feb9bacc10 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
<> 140:97feb9bacc10 693 {
<> 140:97feb9bacc10 694 *descriptor = 0;
<> 140:97feb9bacc10 695 *descriptor2 = 0;
<> 140:97feb9bacc10 696
<> 140:97feb9bacc10 697 switch (reg.rg_t)
<> 140:97feb9bacc10 698 {
<> 140:97feb9bacc10 699 case PAGE_4k:
<> 140:97feb9bacc10 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
<> 140:97feb9bacc10 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
<> 140:97feb9bacc10 702 __domain_page(descriptor, reg.domain);
<> 140:97feb9bacc10 703 __p_page(descriptor, reg.e_t);
<> 140:97feb9bacc10 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 140:97feb9bacc10 705 __shared_page(descriptor2,reg.sh_t);
<> 140:97feb9bacc10 706 __global_page(descriptor2,reg.g_t);
<> 140:97feb9bacc10 707 __secure_page(descriptor,reg.sec_t);
<> 140:97feb9bacc10 708 *descriptor &= PAGE_L1_MASK;
<> 140:97feb9bacc10 709 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 140:97feb9bacc10 710 *descriptor2 &= PAGE_L2_4K_MASK;
<> 140:97feb9bacc10 711 *descriptor2 |= PAGE_L2_4K_DESC;
<> 140:97feb9bacc10 712 break;
<> 140:97feb9bacc10 713
<> 140:97feb9bacc10 714 case PAGE_64k:
<> 140:97feb9bacc10 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
<> 140:97feb9bacc10 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
<> 140:97feb9bacc10 717 __domain_page(descriptor, reg.domain);
<> 140:97feb9bacc10 718 __p_page(descriptor, reg.e_t);
<> 140:97feb9bacc10 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
<> 140:97feb9bacc10 720 __shared_page(descriptor2,reg.sh_t);
<> 140:97feb9bacc10 721 __global_page(descriptor2,reg.g_t);
<> 140:97feb9bacc10 722 __secure_page(descriptor,reg.sec_t);
<> 140:97feb9bacc10 723 *descriptor &= PAGE_L1_MASK;
<> 140:97feb9bacc10 724 *descriptor |= PAGE_L1_DESCRIPTOR;
<> 140:97feb9bacc10 725 *descriptor2 &= PAGE_L2_64K_MASK;
<> 140:97feb9bacc10 726 *descriptor2 |= PAGE_L2_64K_DESC;
<> 140:97feb9bacc10 727 break;
<> 140:97feb9bacc10 728
<> 140:97feb9bacc10 729 case SECTION:
<> 140:97feb9bacc10 730 //error
<> 140:97feb9bacc10 731 break;
<> 140:97feb9bacc10 732
<> 140:97feb9bacc10 733 }
<> 140:97feb9bacc10 734
<> 140:97feb9bacc10 735 return 0;
<> 140:97feb9bacc10 736
<> 140:97feb9bacc10 737 }
<> 140:97feb9bacc10 738
<> 140:97feb9bacc10 739 /** \brief Create a 1MB Section
<> 140:97feb9bacc10 740
<> 140:97feb9bacc10 741 \param [in] ttb Translation table base address
<> 140:97feb9bacc10 742 \param [in] base_address Section base address
<> 140:97feb9bacc10 743 \param [in] count Number of sections to create
<> 140:97feb9bacc10 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 140:97feb9bacc10 745
<> 140:97feb9bacc10 746 */
<> 140:97feb9bacc10 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
<> 140:97feb9bacc10 748 {
<> 140:97feb9bacc10 749 uint32_t offset;
<> 140:97feb9bacc10 750 uint32_t entry;
<> 140:97feb9bacc10 751 uint32_t i;
<> 140:97feb9bacc10 752
<> 140:97feb9bacc10 753 offset = base_address >> 20;
<> 140:97feb9bacc10 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
<> 140:97feb9bacc10 755
<> 140:97feb9bacc10 756 //4 bytes aligned
<> 140:97feb9bacc10 757 ttb = ttb + offset;
<> 140:97feb9bacc10 758
<> 140:97feb9bacc10 759 for (i = 0; i < count; i++ )
<> 140:97feb9bacc10 760 {
<> 140:97feb9bacc10 761 //4 bytes aligned
<> 140:97feb9bacc10 762 *ttb++ = entry;
<> 140:97feb9bacc10 763 entry += OFFSET_1M;
<> 140:97feb9bacc10 764 }
<> 140:97feb9bacc10 765 }
<> 140:97feb9bacc10 766
<> 140:97feb9bacc10 767 /** \brief Create a 4k page entry
<> 140:97feb9bacc10 768
<> 140:97feb9bacc10 769 \param [in] ttb L1 table base address
<> 140:97feb9bacc10 770 \param [in] base_address 4k base address
<> 140:97feb9bacc10 771 \param [in] count Number of 4k pages to create
<> 140:97feb9bacc10 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 140:97feb9bacc10 773 \param [in] ttb_l2 L2 table base address
<> 140:97feb9bacc10 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 140:97feb9bacc10 775
<> 140:97feb9bacc10 776 */
<> 140:97feb9bacc10 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 140:97feb9bacc10 778 {
<> 140:97feb9bacc10 779
<> 140:97feb9bacc10 780 uint32_t offset, offset2;
<> 140:97feb9bacc10 781 uint32_t entry, entry2;
<> 140:97feb9bacc10 782 uint32_t i;
<> 140:97feb9bacc10 783
<> 140:97feb9bacc10 784
<> 140:97feb9bacc10 785 offset = base_address >> 20;
<> 140:97feb9bacc10 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 140:97feb9bacc10 787
<> 140:97feb9bacc10 788 //4 bytes aligned
<> 140:97feb9bacc10 789 ttb += offset;
<> 140:97feb9bacc10 790 //create l1_entry
<> 140:97feb9bacc10 791 *ttb = entry;
<> 140:97feb9bacc10 792
<> 140:97feb9bacc10 793 offset2 = (base_address & 0xff000) >> 12;
<> 140:97feb9bacc10 794 ttb_l2 += offset2;
<> 140:97feb9bacc10 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
<> 140:97feb9bacc10 796 for (i = 0; i < count; i++ )
<> 140:97feb9bacc10 797 {
<> 140:97feb9bacc10 798 //4 bytes aligned
<> 140:97feb9bacc10 799 *ttb_l2++ = entry2;
<> 140:97feb9bacc10 800 entry2 += OFFSET_4K;
<> 140:97feb9bacc10 801 }
<> 140:97feb9bacc10 802 }
<> 140:97feb9bacc10 803
<> 140:97feb9bacc10 804 /** \brief Create a 64k page entry
<> 140:97feb9bacc10 805
<> 140:97feb9bacc10 806 \param [in] ttb L1 table base address
<> 140:97feb9bacc10 807 \param [in] base_address 64k base address
<> 140:97feb9bacc10 808 \param [in] count Number of 64k pages to create
<> 140:97feb9bacc10 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
<> 140:97feb9bacc10 810 \param [in] ttb_l2 L2 table base address
<> 140:97feb9bacc10 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
<> 140:97feb9bacc10 812
<> 140:97feb9bacc10 813 */
<> 140:97feb9bacc10 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
<> 140:97feb9bacc10 815 {
<> 140:97feb9bacc10 816 uint32_t offset, offset2;
<> 140:97feb9bacc10 817 uint32_t entry, entry2;
<> 140:97feb9bacc10 818 uint32_t i,j;
<> 140:97feb9bacc10 819
<> 140:97feb9bacc10 820
<> 140:97feb9bacc10 821 offset = base_address >> 20;
<> 140:97feb9bacc10 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
<> 140:97feb9bacc10 823
<> 140:97feb9bacc10 824 //4 bytes aligned
<> 140:97feb9bacc10 825 ttb += offset;
<> 140:97feb9bacc10 826 //create l1_entry
<> 140:97feb9bacc10 827 *ttb = entry;
<> 140:97feb9bacc10 828
<> 140:97feb9bacc10 829 offset2 = (base_address & 0xff000) >> 12;
<> 140:97feb9bacc10 830 ttb_l2 += offset2;
<> 140:97feb9bacc10 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
<> 140:97feb9bacc10 832 for (i = 0; i < count; i++ )
<> 140:97feb9bacc10 833 {
<> 140:97feb9bacc10 834 //create 16 entries
<> 140:97feb9bacc10 835 for (j = 0; j < 16; j++)
<> 140:97feb9bacc10 836 //4 bytes aligned
<> 140:97feb9bacc10 837 *ttb_l2++ = entry2;
<> 140:97feb9bacc10 838 entry2 += OFFSET_64K;
<> 140:97feb9bacc10 839 }
<> 140:97feb9bacc10 840 }
<> 140:97feb9bacc10 841
<> 140:97feb9bacc10 842 /*@} end of MMU_Functions */
<> 140:97feb9bacc10 843 #endif
<> 140:97feb9bacc10 844
<> 140:97feb9bacc10 845 #ifdef __cplusplus
<> 140:97feb9bacc10 846 }
<> 140:97feb9bacc10 847 #endif