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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_caFunc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_caFunc.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-A Core Function Access Header File
<> 140:97feb9bacc10 4 * @version V3.10
<> 140:97feb9bacc10 5 * @date 30 Oct 2013
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #ifndef __CORE_CAFUNC_H__
<> 140:97feb9bacc10 39 #define __CORE_CAFUNC_H__
<> 140:97feb9bacc10 40
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 /* ########################### Core Function Access ########################### */
<> 140:97feb9bacc10 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 140:97feb9bacc10 45 @{
<> 140:97feb9bacc10 46 */
<> 140:97feb9bacc10 47
<> 140:97feb9bacc10 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 140:97feb9bacc10 49 /* ARM armcc specific functions */
<> 140:97feb9bacc10 50
<> 140:97feb9bacc10 51 #if (__ARMCC_VERSION < 400677)
<> 140:97feb9bacc10 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 140:97feb9bacc10 53 #endif
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 #define MODE_USR 0x10
<> 140:97feb9bacc10 56 #define MODE_FIQ 0x11
<> 140:97feb9bacc10 57 #define MODE_IRQ 0x12
<> 140:97feb9bacc10 58 #define MODE_SVC 0x13
<> 140:97feb9bacc10 59 #define MODE_MON 0x16
<> 140:97feb9bacc10 60 #define MODE_ABT 0x17
<> 140:97feb9bacc10 61 #define MODE_HYP 0x1A
<> 140:97feb9bacc10 62 #define MODE_UND 0x1B
<> 140:97feb9bacc10 63 #define MODE_SYS 0x1F
<> 140:97feb9bacc10 64
<> 140:97feb9bacc10 65 /** \brief Get APSR Register
<> 140:97feb9bacc10 66
<> 140:97feb9bacc10 67 This function returns the content of the APSR Register.
<> 140:97feb9bacc10 68
<> 140:97feb9bacc10 69 \return APSR Register value
<> 140:97feb9bacc10 70 */
<> 140:97feb9bacc10 71 __STATIC_INLINE uint32_t __get_APSR(void)
<> 140:97feb9bacc10 72 {
<> 140:97feb9bacc10 73 register uint32_t __regAPSR __ASM("apsr");
<> 140:97feb9bacc10 74 return(__regAPSR);
<> 140:97feb9bacc10 75 }
<> 140:97feb9bacc10 76
<> 140:97feb9bacc10 77
<> 140:97feb9bacc10 78 /** \brief Get CPSR Register
<> 140:97feb9bacc10 79
<> 140:97feb9bacc10 80 This function returns the content of the CPSR Register.
<> 140:97feb9bacc10 81
<> 140:97feb9bacc10 82 \return CPSR Register value
<> 140:97feb9bacc10 83 */
<> 140:97feb9bacc10 84 __STATIC_INLINE uint32_t __get_CPSR(void)
<> 140:97feb9bacc10 85 {
<> 140:97feb9bacc10 86 register uint32_t __regCPSR __ASM("cpsr");
<> 140:97feb9bacc10 87 return(__regCPSR);
<> 140:97feb9bacc10 88 }
<> 140:97feb9bacc10 89
<> 140:97feb9bacc10 90 /** \brief Set Stack Pointer
<> 140:97feb9bacc10 91
<> 140:97feb9bacc10 92 This function assigns the given value to the current stack pointer.
<> 140:97feb9bacc10 93
<> 140:97feb9bacc10 94 \param [in] topOfStack Stack Pointer value to set
<> 140:97feb9bacc10 95 */
<> 140:97feb9bacc10 96 register uint32_t __regSP __ASM("sp");
<> 140:97feb9bacc10 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 140:97feb9bacc10 98 {
<> 140:97feb9bacc10 99 __regSP = topOfStack;
<> 140:97feb9bacc10 100 }
<> 140:97feb9bacc10 101
<> 140:97feb9bacc10 102
<> 140:97feb9bacc10 103 /** \brief Get link register
<> 140:97feb9bacc10 104
<> 140:97feb9bacc10 105 This function returns the value of the link register
<> 140:97feb9bacc10 106
<> 140:97feb9bacc10 107 \return Value of link register
<> 140:97feb9bacc10 108 */
<> 140:97feb9bacc10 109 register uint32_t __reglr __ASM("lr");
<> 140:97feb9bacc10 110 __STATIC_INLINE uint32_t __get_LR(void)
<> 140:97feb9bacc10 111 {
<> 140:97feb9bacc10 112 return(__reglr);
<> 140:97feb9bacc10 113 }
<> 140:97feb9bacc10 114
<> 140:97feb9bacc10 115 /** \brief Set link register
<> 140:97feb9bacc10 116
<> 140:97feb9bacc10 117 This function sets the value of the link register
<> 140:97feb9bacc10 118
<> 140:97feb9bacc10 119 \param [in] lr LR value to set
<> 140:97feb9bacc10 120 */
<> 140:97feb9bacc10 121 __STATIC_INLINE void __set_LR(uint32_t lr)
<> 140:97feb9bacc10 122 {
<> 140:97feb9bacc10 123 __reglr = lr;
<> 140:97feb9bacc10 124 }
<> 140:97feb9bacc10 125
<> 140:97feb9bacc10 126 /** \brief Set Process Stack Pointer
<> 140:97feb9bacc10 127
<> 140:97feb9bacc10 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 140:97feb9bacc10 129
<> 140:97feb9bacc10 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 140:97feb9bacc10 131 */
<> 140:97feb9bacc10 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
<> 140:97feb9bacc10 133 {
<> 140:97feb9bacc10 134 ARM
<> 140:97feb9bacc10 135 PRESERVE8
<> 140:97feb9bacc10 136
<> 140:97feb9bacc10 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
<> 140:97feb9bacc10 138 MRS R1, CPSR
<> 140:97feb9bacc10 139 CPS #MODE_SYS ;no effect in USR mode
<> 140:97feb9bacc10 140 MOV SP, R0
<> 140:97feb9bacc10 141 MSR CPSR_c, R1 ;no effect in USR mode
<> 140:97feb9bacc10 142 ISB
<> 140:97feb9bacc10 143 BX LR
<> 140:97feb9bacc10 144
<> 140:97feb9bacc10 145 }
<> 140:97feb9bacc10 146
<> 140:97feb9bacc10 147 /** \brief Set User Mode
<> 140:97feb9bacc10 148
<> 140:97feb9bacc10 149 This function changes the processor state to User Mode
<> 140:97feb9bacc10 150 */
<> 140:97feb9bacc10 151 __STATIC_ASM void __set_CPS_USR(void)
<> 140:97feb9bacc10 152 {
<> 140:97feb9bacc10 153 ARM
<> 140:97feb9bacc10 154
<> 140:97feb9bacc10 155 CPS #MODE_USR
<> 140:97feb9bacc10 156 BX LR
<> 140:97feb9bacc10 157 }
<> 140:97feb9bacc10 158
<> 140:97feb9bacc10 159
<> 140:97feb9bacc10 160 /** \brief Enable FIQ
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 140:97feb9bacc10 163 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 164 */
<> 140:97feb9bacc10 165 #define __enable_fault_irq __enable_fiq
<> 140:97feb9bacc10 166
<> 140:97feb9bacc10 167
<> 140:97feb9bacc10 168 /** \brief Disable FIQ
<> 140:97feb9bacc10 169
<> 140:97feb9bacc10 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 140:97feb9bacc10 171 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 172 */
<> 140:97feb9bacc10 173 #define __disable_fault_irq __disable_fiq
<> 140:97feb9bacc10 174
<> 140:97feb9bacc10 175
<> 140:97feb9bacc10 176 /** \brief Get FPSCR
<> 140:97feb9bacc10 177
<> 140:97feb9bacc10 178 This function returns the current value of the Floating Point Status/Control register.
<> 140:97feb9bacc10 179
<> 140:97feb9bacc10 180 \return Floating Point Status/Control register value
<> 140:97feb9bacc10 181 */
<> 140:97feb9bacc10 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 140:97feb9bacc10 183 {
<> 140:97feb9bacc10 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 185 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 186 return(__regfpscr);
<> 140:97feb9bacc10 187 #else
<> 140:97feb9bacc10 188 return(0);
<> 140:97feb9bacc10 189 #endif
<> 140:97feb9bacc10 190 }
<> 140:97feb9bacc10 191
<> 140:97feb9bacc10 192
<> 140:97feb9bacc10 193 /** \brief Set FPSCR
<> 140:97feb9bacc10 194
<> 140:97feb9bacc10 195 This function assigns the given value to the Floating Point Status/Control register.
<> 140:97feb9bacc10 196
<> 140:97feb9bacc10 197 \param [in] fpscr Floating Point Status/Control value to set
<> 140:97feb9bacc10 198 */
<> 140:97feb9bacc10 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 140:97feb9bacc10 200 {
<> 140:97feb9bacc10 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 202 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 203 __regfpscr = (fpscr);
<> 140:97feb9bacc10 204 #endif
<> 140:97feb9bacc10 205 }
<> 140:97feb9bacc10 206
<> 140:97feb9bacc10 207 /** \brief Get FPEXC
<> 140:97feb9bacc10 208
<> 140:97feb9bacc10 209 This function returns the current value of the Floating Point Exception Control register.
<> 140:97feb9bacc10 210
<> 140:97feb9bacc10 211 \return Floating Point Exception Control register value
<> 140:97feb9bacc10 212 */
<> 140:97feb9bacc10 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 140:97feb9bacc10 214 {
<> 140:97feb9bacc10 215 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 216 register uint32_t __regfpexc __ASM("fpexc");
<> 140:97feb9bacc10 217 return(__regfpexc);
<> 140:97feb9bacc10 218 #else
<> 140:97feb9bacc10 219 return(0);
<> 140:97feb9bacc10 220 #endif
<> 140:97feb9bacc10 221 }
<> 140:97feb9bacc10 222
<> 140:97feb9bacc10 223
<> 140:97feb9bacc10 224 /** \brief Set FPEXC
<> 140:97feb9bacc10 225
<> 140:97feb9bacc10 226 This function assigns the given value to the Floating Point Exception Control register.
<> 140:97feb9bacc10 227
<> 140:97feb9bacc10 228 \param [in] fpscr Floating Point Exception Control value to set
<> 140:97feb9bacc10 229 */
<> 140:97feb9bacc10 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 140:97feb9bacc10 231 {
<> 140:97feb9bacc10 232 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 233 register uint32_t __regfpexc __ASM("fpexc");
<> 140:97feb9bacc10 234 __regfpexc = (fpexc);
<> 140:97feb9bacc10 235 #endif
<> 140:97feb9bacc10 236 }
<> 140:97feb9bacc10 237
<> 140:97feb9bacc10 238 /** \brief Get CPACR
<> 140:97feb9bacc10 239
<> 140:97feb9bacc10 240 This function returns the current value of the Coprocessor Access Control register.
<> 140:97feb9bacc10 241
<> 140:97feb9bacc10 242 \return Coprocessor Access Control register value
<> 140:97feb9bacc10 243 */
<> 140:97feb9bacc10 244 __STATIC_INLINE uint32_t __get_CPACR(void)
<> 140:97feb9bacc10 245 {
<> 140:97feb9bacc10 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 140:97feb9bacc10 247 return __regCPACR;
<> 140:97feb9bacc10 248 }
<> 140:97feb9bacc10 249
<> 140:97feb9bacc10 250 /** \brief Set CPACR
<> 140:97feb9bacc10 251
<> 140:97feb9bacc10 252 This function assigns the given value to the Coprocessor Access Control register.
<> 140:97feb9bacc10 253
<> 140:97feb9bacc10 254 \param [in] cpacr Coprocessor Acccess Control value to set
<> 140:97feb9bacc10 255 */
<> 140:97feb9bacc10 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 140:97feb9bacc10 257 {
<> 140:97feb9bacc10 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 140:97feb9bacc10 259 __regCPACR = cpacr;
<> 140:97feb9bacc10 260 __ISB();
<> 140:97feb9bacc10 261 }
<> 140:97feb9bacc10 262
<> 140:97feb9bacc10 263 /** \brief Get CBAR
<> 140:97feb9bacc10 264
<> 140:97feb9bacc10 265 This function returns the value of the Configuration Base Address register.
<> 140:97feb9bacc10 266
<> 140:97feb9bacc10 267 \return Configuration Base Address register value
<> 140:97feb9bacc10 268 */
<> 140:97feb9bacc10 269 __STATIC_INLINE uint32_t __get_CBAR() {
<> 140:97feb9bacc10 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 140:97feb9bacc10 271 return(__regCBAR);
<> 140:97feb9bacc10 272 }
<> 140:97feb9bacc10 273
<> 140:97feb9bacc10 274 /** \brief Get TTBR0
<> 140:97feb9bacc10 275
<> 140:97feb9bacc10 276 This function returns the value of the Translation Table Base Register 0.
<> 140:97feb9bacc10 277
<> 140:97feb9bacc10 278 \return Translation Table Base Register 0 value
<> 140:97feb9bacc10 279 */
<> 140:97feb9bacc10 280 __STATIC_INLINE uint32_t __get_TTBR0() {
<> 140:97feb9bacc10 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 140:97feb9bacc10 282 return(__regTTBR0);
<> 140:97feb9bacc10 283 }
<> 140:97feb9bacc10 284
<> 140:97feb9bacc10 285 /** \brief Set TTBR0
<> 140:97feb9bacc10 286
<> 140:97feb9bacc10 287 This function assigns the given value to the Translation Table Base Register 0.
<> 140:97feb9bacc10 288
<> 140:97feb9bacc10 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 140:97feb9bacc10 290 */
<> 140:97feb9bacc10 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 140:97feb9bacc10 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 140:97feb9bacc10 293 __regTTBR0 = ttbr0;
<> 140:97feb9bacc10 294 __ISB();
<> 140:97feb9bacc10 295 }
<> 140:97feb9bacc10 296
<> 140:97feb9bacc10 297 /** \brief Get DACR
<> 140:97feb9bacc10 298
<> 140:97feb9bacc10 299 This function returns the value of the Domain Access Control Register.
<> 140:97feb9bacc10 300
<> 140:97feb9bacc10 301 \return Domain Access Control Register value
<> 140:97feb9bacc10 302 */
<> 140:97feb9bacc10 303 __STATIC_INLINE uint32_t __get_DACR() {
<> 140:97feb9bacc10 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 140:97feb9bacc10 305 return(__regDACR);
<> 140:97feb9bacc10 306 }
<> 140:97feb9bacc10 307
<> 140:97feb9bacc10 308 /** \brief Set DACR
<> 140:97feb9bacc10 309
<> 140:97feb9bacc10 310 This function assigns the given value to the Domain Access Control Register.
<> 140:97feb9bacc10 311
<> 140:97feb9bacc10 312 \param [in] dacr Domain Access Control Register value to set
<> 140:97feb9bacc10 313 */
<> 140:97feb9bacc10 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 140:97feb9bacc10 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 140:97feb9bacc10 316 __regDACR = dacr;
<> 140:97feb9bacc10 317 __ISB();
<> 140:97feb9bacc10 318 }
<> 140:97feb9bacc10 319
<> 140:97feb9bacc10 320 /******************************** Cache and BTAC enable ****************************************************/
<> 140:97feb9bacc10 321
<> 140:97feb9bacc10 322 /** \brief Set SCTLR
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324 This function assigns the given value to the System Control Register.
<> 140:97feb9bacc10 325
<> 140:97feb9bacc10 326 \param [in] sctlr System Control Register value to set
<> 140:97feb9bacc10 327 */
<> 140:97feb9bacc10 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 140:97feb9bacc10 329 {
<> 140:97feb9bacc10 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 140:97feb9bacc10 331 __regSCTLR = sctlr;
<> 140:97feb9bacc10 332 }
<> 140:97feb9bacc10 333
<> 140:97feb9bacc10 334 /** \brief Get SCTLR
<> 140:97feb9bacc10 335
<> 140:97feb9bacc10 336 This function returns the value of the System Control Register.
<> 140:97feb9bacc10 337
<> 140:97feb9bacc10 338 \return System Control Register value
<> 140:97feb9bacc10 339 */
<> 140:97feb9bacc10 340 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 140:97feb9bacc10 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 140:97feb9bacc10 342 return(__regSCTLR);
<> 140:97feb9bacc10 343 }
<> 140:97feb9bacc10 344
<> 140:97feb9bacc10 345 /** \brief Enable Caches
<> 140:97feb9bacc10 346
<> 140:97feb9bacc10 347 Enable Caches
<> 140:97feb9bacc10 348 */
<> 140:97feb9bacc10 349 __STATIC_INLINE void __enable_caches(void) {
<> 140:97feb9bacc10 350 // Set I bit 12 to enable I Cache
<> 140:97feb9bacc10 351 // Set C bit 2 to enable D Cache
<> 140:97feb9bacc10 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 140:97feb9bacc10 353 }
<> 140:97feb9bacc10 354
<> 140:97feb9bacc10 355 /** \brief Disable Caches
<> 140:97feb9bacc10 356
<> 140:97feb9bacc10 357 Disable Caches
<> 140:97feb9bacc10 358 */
<> 140:97feb9bacc10 359 __STATIC_INLINE void __disable_caches(void) {
<> 140:97feb9bacc10 360 // Clear I bit 12 to disable I Cache
<> 140:97feb9bacc10 361 // Clear C bit 2 to disable D Cache
<> 140:97feb9bacc10 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 140:97feb9bacc10 363 __ISB();
<> 140:97feb9bacc10 364 }
<> 140:97feb9bacc10 365
<> 140:97feb9bacc10 366 /** \brief Enable BTAC
<> 140:97feb9bacc10 367
<> 140:97feb9bacc10 368 Enable BTAC
<> 140:97feb9bacc10 369 */
<> 140:97feb9bacc10 370 __STATIC_INLINE void __enable_btac(void) {
<> 140:97feb9bacc10 371 // Set Z bit 11 to enable branch prediction
<> 140:97feb9bacc10 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 140:97feb9bacc10 373 __ISB();
<> 140:97feb9bacc10 374 }
<> 140:97feb9bacc10 375
<> 140:97feb9bacc10 376 /** \brief Disable BTAC
<> 140:97feb9bacc10 377
<> 140:97feb9bacc10 378 Disable BTAC
<> 140:97feb9bacc10 379 */
<> 140:97feb9bacc10 380 __STATIC_INLINE void __disable_btac(void) {
<> 140:97feb9bacc10 381 // Clear Z bit 11 to disable branch prediction
<> 140:97feb9bacc10 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 140:97feb9bacc10 383 }
<> 140:97feb9bacc10 384
<> 140:97feb9bacc10 385
<> 140:97feb9bacc10 386 /** \brief Enable MMU
<> 140:97feb9bacc10 387
<> 140:97feb9bacc10 388 Enable MMU
<> 140:97feb9bacc10 389 */
<> 140:97feb9bacc10 390 __STATIC_INLINE void __enable_mmu(void) {
<> 140:97feb9bacc10 391 // Set M bit 0 to enable the MMU
<> 140:97feb9bacc10 392 // Set AFE bit to enable simplified access permissions model
<> 140:97feb9bacc10 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 140:97feb9bacc10 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 140:97feb9bacc10 395 __ISB();
<> 140:97feb9bacc10 396 }
<> 140:97feb9bacc10 397
<> 140:97feb9bacc10 398 /** \brief Disable MMU
<> 140:97feb9bacc10 399
<> 140:97feb9bacc10 400 Disable MMU
<> 140:97feb9bacc10 401 */
<> 140:97feb9bacc10 402 __STATIC_INLINE void __disable_mmu(void) {
<> 140:97feb9bacc10 403 // Clear M bit 0 to disable the MMU
<> 140:97feb9bacc10 404 __set_SCTLR( __get_SCTLR() & ~1);
<> 140:97feb9bacc10 405 __ISB();
<> 140:97feb9bacc10 406 }
<> 140:97feb9bacc10 407
<> 140:97feb9bacc10 408 /******************************** TLB maintenance operations ************************************************/
<> 140:97feb9bacc10 409 /** \brief Invalidate the whole tlb
<> 140:97feb9bacc10 410
<> 140:97feb9bacc10 411 TLBIALL. Invalidate the whole tlb
<> 140:97feb9bacc10 412 */
<> 140:97feb9bacc10 413
<> 140:97feb9bacc10 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 140:97feb9bacc10 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 140:97feb9bacc10 416 __TLBIALL = 0;
<> 140:97feb9bacc10 417 __DSB();
<> 140:97feb9bacc10 418 __ISB();
<> 140:97feb9bacc10 419 }
<> 140:97feb9bacc10 420
<> 140:97feb9bacc10 421 /******************************** BTB maintenance operations ************************************************/
<> 140:97feb9bacc10 422 /** \brief Invalidate entire branch predictor array
<> 140:97feb9bacc10 423
<> 140:97feb9bacc10 424 BPIALL. Branch Predictor Invalidate All.
<> 140:97feb9bacc10 425 */
<> 140:97feb9bacc10 426
<> 140:97feb9bacc10 427 __STATIC_INLINE void __v7_inv_btac(void) {
<> 140:97feb9bacc10 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 140:97feb9bacc10 429 __BPIALL = 0;
<> 140:97feb9bacc10 430 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 431 __ISB(); //ensure instruction fetch path sees new state
<> 140:97feb9bacc10 432 }
<> 140:97feb9bacc10 433
<> 140:97feb9bacc10 434
<> 140:97feb9bacc10 435 /******************************** L1 cache operations ******************************************************/
<> 140:97feb9bacc10 436
<> 140:97feb9bacc10 437 /** \brief Invalidate the whole I$
<> 140:97feb9bacc10 438
<> 140:97feb9bacc10 439 ICIALLU. Instruction Cache Invalidate All to PoU
<> 140:97feb9bacc10 440 */
<> 140:97feb9bacc10 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 140:97feb9bacc10 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 140:97feb9bacc10 443 __ICIALLU = 0;
<> 140:97feb9bacc10 444 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 445 __ISB(); //ensure instruction fetch path sees new I cache state
<> 140:97feb9bacc10 446 }
<> 140:97feb9bacc10 447
<> 140:97feb9bacc10 448 /** \brief Clean D$ by MVA
<> 140:97feb9bacc10 449
<> 140:97feb9bacc10 450 DCCMVAC. Data cache clean by MVA to PoC
<> 140:97feb9bacc10 451 */
<> 140:97feb9bacc10 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 140:97feb9bacc10 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 140:97feb9bacc10 454 __DCCMVAC = (uint32_t)va;
<> 140:97feb9bacc10 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 456 }
<> 140:97feb9bacc10 457
<> 140:97feb9bacc10 458 /** \brief Invalidate D$ by MVA
<> 140:97feb9bacc10 459
<> 140:97feb9bacc10 460 DCIMVAC. Data cache invalidate by MVA to PoC
<> 140:97feb9bacc10 461 */
<> 140:97feb9bacc10 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 140:97feb9bacc10 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 140:97feb9bacc10 464 __DCIMVAC = (uint32_t)va;
<> 140:97feb9bacc10 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 466 }
<> 140:97feb9bacc10 467
<> 140:97feb9bacc10 468 /** \brief Clean and Invalidate D$ by MVA
<> 140:97feb9bacc10 469
<> 140:97feb9bacc10 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 140:97feb9bacc10 471 */
<> 140:97feb9bacc10 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 140:97feb9bacc10 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 140:97feb9bacc10 474 __DCCIMVAC = (uint32_t)va;
<> 140:97feb9bacc10 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 476 }
<> 140:97feb9bacc10 477
<> 140:97feb9bacc10 478 /** \brief Clean and Invalidate the entire data or unified cache
<> 140:97feb9bacc10 479
<> 140:97feb9bacc10 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 140:97feb9bacc10 481 */
<> 140:97feb9bacc10 482 #pragma push
<> 140:97feb9bacc10 483 #pragma arm
<> 140:97feb9bacc10 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
<> 140:97feb9bacc10 485 ARM
<> 140:97feb9bacc10 486
<> 140:97feb9bacc10 487 PUSH {R4-R11}
<> 140:97feb9bacc10 488
<> 140:97feb9bacc10 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
<> 140:97feb9bacc10 490 ANDS R3, R6, #0x07000000 // Extract coherency level
<> 140:97feb9bacc10 491 MOV R3, R3, LSR #23 // Total cache levels << 1
<> 140:97feb9bacc10 492 BEQ Finished // If 0, no need to clean
<> 140:97feb9bacc10 493
<> 140:97feb9bacc10 494 MOV R10, #0 // R10 holds current cache level << 1
<> 140:97feb9bacc10 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
<> 140:97feb9bacc10 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
<> 140:97feb9bacc10 497 AND R1, R1, #7 // Isolate those lower 3 bits
<> 140:97feb9bacc10 498 CMP R1, #2
<> 140:97feb9bacc10 499 BLT Skip // No cache or only instruction cache at this level
<> 140:97feb9bacc10 500
<> 140:97feb9bacc10 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
<> 140:97feb9bacc10 502 ISB // ISB to sync the change to the CacheSizeID reg
<> 140:97feb9bacc10 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
<> 140:97feb9bacc10 504 AND R2, R1, #7 // Extract the line length field
<> 140:97feb9bacc10 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
<> 140:97feb9bacc10 506 LDR R4, =0x3FF
<> 140:97feb9bacc10 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
<> 140:97feb9bacc10 508 CLZ R5, R4 // R5 is the bit position of the way size increment
<> 140:97feb9bacc10 509 LDR R7, =0x7FFF
<> 140:97feb9bacc10 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
<> 140:97feb9bacc10 511
<> 140:97feb9bacc10 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
<> 140:97feb9bacc10 513
<> 140:97feb9bacc10 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
<> 140:97feb9bacc10 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
<> 140:97feb9bacc10 516 CMP R0, #0
<> 140:97feb9bacc10 517 BNE Dccsw
<> 140:97feb9bacc10 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
<> 140:97feb9bacc10 519 B cont
<> 140:97feb9bacc10 520 Dccsw CMP R0, #1
<> 140:97feb9bacc10 521 BNE Dccisw
<> 140:97feb9bacc10 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
<> 140:97feb9bacc10 523 B cont
<> 140:97feb9bacc10 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
<> 140:97feb9bacc10 525 cont SUBS R9, R9, #1 // Decrement the Way number
<> 140:97feb9bacc10 526 BGE Loop3
<> 140:97feb9bacc10 527 SUBS R7, R7, #1 // Decrement the Set number
<> 140:97feb9bacc10 528 BGE Loop2
<> 140:97feb9bacc10 529 Skip ADD R10, R10, #2 // Increment the cache number
<> 140:97feb9bacc10 530 CMP R3, R10
<> 140:97feb9bacc10 531 BGT Loop1
<> 140:97feb9bacc10 532
<> 140:97feb9bacc10 533 Finished
<> 140:97feb9bacc10 534 DSB
<> 140:97feb9bacc10 535 POP {R4-R11}
<> 140:97feb9bacc10 536 BX lr
<> 140:97feb9bacc10 537
<> 140:97feb9bacc10 538 }
<> 140:97feb9bacc10 539 #pragma pop
<> 140:97feb9bacc10 540
<> 140:97feb9bacc10 541
<> 140:97feb9bacc10 542 /** \brief Invalidate the whole D$
<> 140:97feb9bacc10 543
<> 140:97feb9bacc10 544 DCISW. Invalidate by Set/Way
<> 140:97feb9bacc10 545 */
<> 140:97feb9bacc10 546
<> 140:97feb9bacc10 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 140:97feb9bacc10 548 __v7_all_cache(0);
<> 140:97feb9bacc10 549 }
<> 140:97feb9bacc10 550
<> 140:97feb9bacc10 551 /** \brief Clean the whole D$
<> 140:97feb9bacc10 552
<> 140:97feb9bacc10 553 DCCSW. Clean by Set/Way
<> 140:97feb9bacc10 554 */
<> 140:97feb9bacc10 555
<> 140:97feb9bacc10 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 140:97feb9bacc10 557 __v7_all_cache(1);
<> 140:97feb9bacc10 558 }
<> 140:97feb9bacc10 559
<> 140:97feb9bacc10 560 /** \brief Clean and invalidate the whole D$
<> 140:97feb9bacc10 561
<> 140:97feb9bacc10 562 DCCISW. Clean and Invalidate by Set/Way
<> 140:97feb9bacc10 563 */
<> 140:97feb9bacc10 564
<> 140:97feb9bacc10 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 140:97feb9bacc10 566 __v7_all_cache(2);
<> 140:97feb9bacc10 567 }
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 #include "core_ca_mmu.h"
<> 140:97feb9bacc10 570
<> 140:97feb9bacc10 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
<> 140:97feb9bacc10 572
<> 140:97feb9bacc10 573 #define __inline inline
<> 140:97feb9bacc10 574
<> 140:97feb9bacc10 575 inline static uint32_t __disable_irq_iar() {
<> 140:97feb9bacc10 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
<> 140:97feb9bacc10 577 __disable_irq();
<> 140:97feb9bacc10 578 return irq_dis;
<> 140:97feb9bacc10 579 }
<> 140:97feb9bacc10 580
<> 140:97feb9bacc10 581 #define MODE_USR 0x10
<> 140:97feb9bacc10 582 #define MODE_FIQ 0x11
<> 140:97feb9bacc10 583 #define MODE_IRQ 0x12
<> 140:97feb9bacc10 584 #define MODE_SVC 0x13
<> 140:97feb9bacc10 585 #define MODE_MON 0x16
<> 140:97feb9bacc10 586 #define MODE_ABT 0x17
<> 140:97feb9bacc10 587 #define MODE_HYP 0x1A
<> 140:97feb9bacc10 588 #define MODE_UND 0x1B
<> 140:97feb9bacc10 589 #define MODE_SYS 0x1F
<> 140:97feb9bacc10 590
<> 140:97feb9bacc10 591 /** \brief Set Process Stack Pointer
<> 140:97feb9bacc10 592
<> 140:97feb9bacc10 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 140:97feb9bacc10 594
<> 140:97feb9bacc10 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 140:97feb9bacc10 596 */
<> 140:97feb9bacc10 597 // from rt_CMSIS.c
<> 140:97feb9bacc10 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
<> 140:97feb9bacc10 599 __asm(
<> 140:97feb9bacc10 600 " ARM\n"
<> 140:97feb9bacc10 601 // " PRESERVE8\n"
<> 140:97feb9bacc10 602
<> 140:97feb9bacc10 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
<> 140:97feb9bacc10 604 " MRS R1, CPSR \n"
<> 140:97feb9bacc10 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
<> 140:97feb9bacc10 606 " MOV SP, R0 \n"
<> 140:97feb9bacc10 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
<> 140:97feb9bacc10 608 " ISB \n"
<> 140:97feb9bacc10 609 " BX LR \n");
<> 140:97feb9bacc10 610 }
<> 140:97feb9bacc10 611
<> 140:97feb9bacc10 612 /** \brief Set User Mode
<> 140:97feb9bacc10 613
<> 140:97feb9bacc10 614 This function changes the processor state to User Mode
<> 140:97feb9bacc10 615 */
<> 140:97feb9bacc10 616 // from rt_CMSIS.c
<> 140:97feb9bacc10 617 __arm static inline void __set_CPS_USR(void) {
<> 140:97feb9bacc10 618 __asm(
<> 140:97feb9bacc10 619 " ARM \n"
<> 140:97feb9bacc10 620
<> 140:97feb9bacc10 621 " CPS #0x10 \n" // MODE_USR
<> 140:97feb9bacc10 622 " BX LR\n");
<> 140:97feb9bacc10 623 }
<> 140:97feb9bacc10 624
<> 140:97feb9bacc10 625 /** \brief Set TTBR0
<> 140:97feb9bacc10 626
<> 140:97feb9bacc10 627 This function assigns the given value to the Translation Table Base Register 0.
<> 140:97feb9bacc10 628
<> 140:97feb9bacc10 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 140:97feb9bacc10 630 */
<> 140:97feb9bacc10 631 // from mmu_Renesas_RZ_A1.c
<> 140:97feb9bacc10 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 140:97feb9bacc10 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
<> 140:97feb9bacc10 634 __ISB();
<> 140:97feb9bacc10 635 }
<> 140:97feb9bacc10 636
<> 140:97feb9bacc10 637 /** \brief Set DACR
<> 140:97feb9bacc10 638
<> 140:97feb9bacc10 639 This function assigns the given value to the Domain Access Control Register.
<> 140:97feb9bacc10 640
<> 140:97feb9bacc10 641 \param [in] dacr Domain Access Control Register value to set
<> 140:97feb9bacc10 642 */
<> 140:97feb9bacc10 643 // from mmu_Renesas_RZ_A1.c
<> 140:97feb9bacc10 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 140:97feb9bacc10 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
<> 140:97feb9bacc10 646 __ISB();
<> 140:97feb9bacc10 647 }
<> 140:97feb9bacc10 648
<> 140:97feb9bacc10 649
<> 140:97feb9bacc10 650 /******************************** Cache and BTAC enable ****************************************************/
<> 140:97feb9bacc10 651 /** \brief Set SCTLR
<> 140:97feb9bacc10 652
<> 140:97feb9bacc10 653 This function assigns the given value to the System Control Register.
<> 140:97feb9bacc10 654
<> 140:97feb9bacc10 655 \param [in] sctlr System Control Register value to set
<> 140:97feb9bacc10 656 */
<> 140:97feb9bacc10 657 // from __enable_mmu()
<> 140:97feb9bacc10 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
<> 140:97feb9bacc10 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
<> 140:97feb9bacc10 660 }
<> 140:97feb9bacc10 661
<> 140:97feb9bacc10 662 /** \brief Get SCTLR
<> 140:97feb9bacc10 663
<> 140:97feb9bacc10 664 This function returns the value of the System Control Register.
<> 140:97feb9bacc10 665
<> 140:97feb9bacc10 666 \return System Control Register value
<> 140:97feb9bacc10 667 */
<> 140:97feb9bacc10 668 // from __enable_mmu()
<> 140:97feb9bacc10 669 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 140:97feb9bacc10 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
<> 140:97feb9bacc10 671 return __regSCTLR;
<> 140:97feb9bacc10 672 }
<> 140:97feb9bacc10 673
<> 140:97feb9bacc10 674 /** \brief Enable Caches
<> 140:97feb9bacc10 675
<> 140:97feb9bacc10 676 Enable Caches
<> 140:97feb9bacc10 677 */
<> 140:97feb9bacc10 678 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 679 __STATIC_INLINE void __enable_caches(void) {
<> 140:97feb9bacc10 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 140:97feb9bacc10 681 }
<> 140:97feb9bacc10 682
<> 140:97feb9bacc10 683 /** \brief Enable BTAC
<> 140:97feb9bacc10 684
<> 140:97feb9bacc10 685 Enable BTAC
<> 140:97feb9bacc10 686 */
<> 140:97feb9bacc10 687 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 688 __STATIC_INLINE void __enable_btac(void) {
<> 140:97feb9bacc10 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 140:97feb9bacc10 690 __ISB();
<> 140:97feb9bacc10 691 }
<> 140:97feb9bacc10 692
<> 140:97feb9bacc10 693 /** \brief Enable MMU
<> 140:97feb9bacc10 694
<> 140:97feb9bacc10 695 Enable MMU
<> 140:97feb9bacc10 696 */
<> 140:97feb9bacc10 697 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 698 __STATIC_INLINE void __enable_mmu(void) {
<> 140:97feb9bacc10 699 // Set M bit 0 to enable the MMU
<> 140:97feb9bacc10 700 // Set AFE bit to enable simplified access permissions model
<> 140:97feb9bacc10 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 140:97feb9bacc10 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 140:97feb9bacc10 703 __ISB();
<> 140:97feb9bacc10 704 }
<> 140:97feb9bacc10 705
<> 140:97feb9bacc10 706 /******************************** TLB maintenance operations ************************************************/
<> 140:97feb9bacc10 707 /** \brief Invalidate the whole tlb
<> 140:97feb9bacc10 708
<> 140:97feb9bacc10 709 TLBIALL. Invalidate the whole tlb
<> 140:97feb9bacc10 710 */
<> 140:97feb9bacc10 711 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 140:97feb9bacc10 713 uint32_t val = 0;
<> 140:97feb9bacc10 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
<> 140:97feb9bacc10 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
<> 140:97feb9bacc10 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
<> 140:97feb9bacc10 717 __DSB();
<> 140:97feb9bacc10 718 __ISB();
<> 140:97feb9bacc10 719 }
<> 140:97feb9bacc10 720
<> 140:97feb9bacc10 721 /******************************** BTB maintenance operations ************************************************/
<> 140:97feb9bacc10 722 /** \brief Invalidate entire branch predictor array
<> 140:97feb9bacc10 723
<> 140:97feb9bacc10 724 BPIALL. Branch Predictor Invalidate All.
<> 140:97feb9bacc10 725 */
<> 140:97feb9bacc10 726 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 727 __STATIC_INLINE void __v7_inv_btac(void) {
<> 140:97feb9bacc10 728 uint32_t val = 0;
<> 140:97feb9bacc10 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
<> 140:97feb9bacc10 730 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 731 __ISB(); //ensure instruction fetch path sees new state
<> 140:97feb9bacc10 732 }
<> 140:97feb9bacc10 733
<> 140:97feb9bacc10 734
<> 140:97feb9bacc10 735 /******************************** L1 cache operations ******************************************************/
<> 140:97feb9bacc10 736
<> 140:97feb9bacc10 737 /** \brief Invalidate the whole I$
<> 140:97feb9bacc10 738
<> 140:97feb9bacc10 739 ICIALLU. Instruction Cache Invalidate All to PoU
<> 140:97feb9bacc10 740 */
<> 140:97feb9bacc10 741 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 140:97feb9bacc10 743 uint32_t val = 0;
<> 140:97feb9bacc10 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
<> 140:97feb9bacc10 745 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 746 __ISB(); //ensure instruction fetch path sees new I cache state
<> 140:97feb9bacc10 747 }
<> 140:97feb9bacc10 748
<> 140:97feb9bacc10 749 // from __v7_inv_dcache_all()
<> 140:97feb9bacc10 750 __arm static inline void __v7_all_cache(uint32_t op) {
<> 140:97feb9bacc10 751 __asm(
<> 140:97feb9bacc10 752 " ARM \n"
<> 140:97feb9bacc10 753
<> 140:97feb9bacc10 754 " PUSH {R4-R11} \n"
<> 140:97feb9bacc10 755
<> 140:97feb9bacc10 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
<> 140:97feb9bacc10 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
<> 140:97feb9bacc10 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
<> 140:97feb9bacc10 759 " BEQ Finished\n" // If 0, no need to clean
<> 140:97feb9bacc10 760
<> 140:97feb9bacc10 761 " MOV R10, #0\n" // R10 holds current cache level << 1
<> 140:97feb9bacc10 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
<> 140:97feb9bacc10 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
<> 140:97feb9bacc10 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
<> 140:97feb9bacc10 765 " CMP R1, #2 \n"
<> 140:97feb9bacc10 766 " BLT Skip \n" // No cache or only instruction cache at this level
<> 140:97feb9bacc10 767
<> 140:97feb9bacc10 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
<> 140:97feb9bacc10 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
<> 140:97feb9bacc10 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
<> 140:97feb9bacc10 771 " AND R2, R1, #7 \n" // Extract the line length field
<> 140:97feb9bacc10 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
<> 140:97feb9bacc10 773 " movw R4, #0x3FF \n"
<> 140:97feb9bacc10 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
<> 140:97feb9bacc10 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
<> 140:97feb9bacc10 776 " movw R7, #0x7FFF \n"
<> 140:97feb9bacc10 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
<> 140:97feb9bacc10 778
<> 140:97feb9bacc10 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
<> 140:97feb9bacc10 780
<> 140:97feb9bacc10 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
<> 140:97feb9bacc10 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
<> 140:97feb9bacc10 783 " CMP R0, #0 \n"
<> 140:97feb9bacc10 784 " BNE Dccsw \n"
<> 140:97feb9bacc10 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
<> 140:97feb9bacc10 786 " B cont \n"
<> 140:97feb9bacc10 787 "Dccsw: CMP R0, #1 \n"
<> 140:97feb9bacc10 788 " BNE Dccisw \n"
<> 140:97feb9bacc10 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
<> 140:97feb9bacc10 790 " B cont \n"
<> 140:97feb9bacc10 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
<> 140:97feb9bacc10 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
<> 140:97feb9bacc10 793 " BGE Loop3 \n"
<> 140:97feb9bacc10 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
<> 140:97feb9bacc10 795 " BGE Loop2 \n"
<> 140:97feb9bacc10 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
<> 140:97feb9bacc10 797 " CMP R3, R10 \n"
<> 140:97feb9bacc10 798 " BGT Loop1 \n"
<> 140:97feb9bacc10 799
<> 140:97feb9bacc10 800 "Finished: \n"
<> 140:97feb9bacc10 801 " DSB \n"
<> 140:97feb9bacc10 802 " POP {R4-R11} \n"
<> 140:97feb9bacc10 803 " BX lr \n" );
<> 140:97feb9bacc10 804 }
<> 140:97feb9bacc10 805
<> 140:97feb9bacc10 806 /** \brief Invalidate the whole D$
<> 140:97feb9bacc10 807
<> 140:97feb9bacc10 808 DCISW. Invalidate by Set/Way
<> 140:97feb9bacc10 809 */
<> 140:97feb9bacc10 810 // from system_Renesas_RZ_A1.c
<> 140:97feb9bacc10 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 140:97feb9bacc10 812 __v7_all_cache(0);
<> 140:97feb9bacc10 813 }
<> 140:97feb9bacc10 814 /** \brief Clean the whole D$
<> 140:97feb9bacc10 815
<> 140:97feb9bacc10 816 DCCSW. Clean by Set/Way
<> 140:97feb9bacc10 817 */
<> 140:97feb9bacc10 818
<> 140:97feb9bacc10 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 140:97feb9bacc10 820 __v7_all_cache(1);
<> 140:97feb9bacc10 821 }
<> 140:97feb9bacc10 822
<> 140:97feb9bacc10 823 /** \brief Clean and invalidate the whole D$
<> 140:97feb9bacc10 824
<> 140:97feb9bacc10 825 DCCISW. Clean and Invalidate by Set/Way
<> 140:97feb9bacc10 826 */
<> 140:97feb9bacc10 827
<> 140:97feb9bacc10 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 140:97feb9bacc10 829 __v7_all_cache(2);
<> 140:97feb9bacc10 830 }
<> 140:97feb9bacc10 831 /** \brief Clean and Invalidate D$ by MVA
<> 140:97feb9bacc10 832
<> 140:97feb9bacc10 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 140:97feb9bacc10 834 */
<> 140:97feb9bacc10 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 140:97feb9bacc10 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
<> 140:97feb9bacc10 837 __DMB();
<> 140:97feb9bacc10 838 }
<> 140:97feb9bacc10 839
<> 140:97feb9bacc10 840 #include "core_ca_mmu.h"
<> 140:97feb9bacc10 841
<> 140:97feb9bacc10 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
<> 140:97feb9bacc10 843 /* GNU gcc specific functions */
<> 140:97feb9bacc10 844
<> 140:97feb9bacc10 845 #define MODE_USR 0x10
<> 140:97feb9bacc10 846 #define MODE_FIQ 0x11
<> 140:97feb9bacc10 847 #define MODE_IRQ 0x12
<> 140:97feb9bacc10 848 #define MODE_SVC 0x13
<> 140:97feb9bacc10 849 #define MODE_MON 0x16
<> 140:97feb9bacc10 850 #define MODE_ABT 0x17
<> 140:97feb9bacc10 851 #define MODE_HYP 0x1A
<> 140:97feb9bacc10 852 #define MODE_UND 0x1B
<> 140:97feb9bacc10 853 #define MODE_SYS 0x1F
<> 140:97feb9bacc10 854
<> 140:97feb9bacc10 855
<> 140:97feb9bacc10 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 140:97feb9bacc10 857 {
<> 140:97feb9bacc10 858 __ASM volatile ("cpsie i");
<> 140:97feb9bacc10 859 }
<> 140:97feb9bacc10 860
<> 140:97feb9bacc10 861 /** \brief Disable IRQ Interrupts
<> 140:97feb9bacc10 862
<> 140:97feb9bacc10 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 140:97feb9bacc10 864 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 865 */
<> 140:97feb9bacc10 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
<> 140:97feb9bacc10 867 {
<> 140:97feb9bacc10 868 uint32_t result;
<> 140:97feb9bacc10 869
<> 140:97feb9bacc10 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
<> 140:97feb9bacc10 871 __ASM volatile ("cpsid i");
<> 140:97feb9bacc10 872 return(result & 0x80);
<> 140:97feb9bacc10 873 }
<> 140:97feb9bacc10 874
<> 140:97feb9bacc10 875
<> 140:97feb9bacc10 876 /** \brief Get APSR Register
<> 140:97feb9bacc10 877
<> 140:97feb9bacc10 878 This function returns the content of the APSR Register.
<> 140:97feb9bacc10 879
<> 140:97feb9bacc10 880 \return APSR Register value
<> 140:97feb9bacc10 881 */
<> 140:97feb9bacc10 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 140:97feb9bacc10 883 {
<> 140:97feb9bacc10 884 #if 1
<> 140:97feb9bacc10 885 register uint32_t __regAPSR;
<> 140:97feb9bacc10 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
<> 140:97feb9bacc10 887 #else
<> 140:97feb9bacc10 888 register uint32_t __regAPSR __ASM("apsr");
<> 140:97feb9bacc10 889 #endif
<> 140:97feb9bacc10 890 return(__regAPSR);
<> 140:97feb9bacc10 891 }
<> 140:97feb9bacc10 892
<> 140:97feb9bacc10 893
<> 140:97feb9bacc10 894 /** \brief Get CPSR Register
<> 140:97feb9bacc10 895
<> 140:97feb9bacc10 896 This function returns the content of the CPSR Register.
<> 140:97feb9bacc10 897
<> 140:97feb9bacc10 898 \return CPSR Register value
<> 140:97feb9bacc10 899 */
<> 140:97feb9bacc10 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
<> 140:97feb9bacc10 901 {
<> 140:97feb9bacc10 902 #if 1
<> 140:97feb9bacc10 903 register uint32_t __regCPSR;
<> 140:97feb9bacc10 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
<> 140:97feb9bacc10 905 #else
<> 140:97feb9bacc10 906 register uint32_t __regCPSR __ASM("cpsr");
<> 140:97feb9bacc10 907 #endif
<> 140:97feb9bacc10 908 return(__regCPSR);
<> 140:97feb9bacc10 909 }
<> 140:97feb9bacc10 910
<> 140:97feb9bacc10 911 #if 0
<> 140:97feb9bacc10 912 /** \brief Set Stack Pointer
<> 140:97feb9bacc10 913
<> 140:97feb9bacc10 914 This function assigns the given value to the current stack pointer.
<> 140:97feb9bacc10 915
<> 140:97feb9bacc10 916 \param [in] topOfStack Stack Pointer value to set
<> 140:97feb9bacc10 917 */
<> 140:97feb9bacc10 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 140:97feb9bacc10 919 {
<> 140:97feb9bacc10 920 register uint32_t __regSP __ASM("sp");
<> 140:97feb9bacc10 921 __regSP = topOfStack;
<> 140:97feb9bacc10 922 }
<> 140:97feb9bacc10 923 #endif
<> 140:97feb9bacc10 924
<> 140:97feb9bacc10 925 /** \brief Get link register
<> 140:97feb9bacc10 926
<> 140:97feb9bacc10 927 This function returns the value of the link register
<> 140:97feb9bacc10 928
<> 140:97feb9bacc10 929 \return Value of link register
<> 140:97feb9bacc10 930 */
<> 140:97feb9bacc10 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
<> 140:97feb9bacc10 932 {
<> 140:97feb9bacc10 933 register uint32_t __reglr __ASM("lr");
<> 140:97feb9bacc10 934 return(__reglr);
<> 140:97feb9bacc10 935 }
<> 140:97feb9bacc10 936
<> 140:97feb9bacc10 937 #if 0
<> 140:97feb9bacc10 938 /** \brief Set link register
<> 140:97feb9bacc10 939
<> 140:97feb9bacc10 940 This function sets the value of the link register
<> 140:97feb9bacc10 941
<> 140:97feb9bacc10 942 \param [in] lr LR value to set
<> 140:97feb9bacc10 943 */
<> 140:97feb9bacc10 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
<> 140:97feb9bacc10 945 {
<> 140:97feb9bacc10 946 register uint32_t __reglr __ASM("lr");
<> 140:97feb9bacc10 947 __reglr = lr;
<> 140:97feb9bacc10 948 }
<> 140:97feb9bacc10 949 #endif
<> 140:97feb9bacc10 950
<> 140:97feb9bacc10 951 /** \brief Set Process Stack Pointer
<> 140:97feb9bacc10 952
<> 140:97feb9bacc10 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 140:97feb9bacc10 954
<> 140:97feb9bacc10 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 140:97feb9bacc10 956 */
<> 140:97feb9bacc10 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 140:97feb9bacc10 958 {
<> 140:97feb9bacc10 959 __asm__ volatile (
<> 140:97feb9bacc10 960 ".ARM;"
<> 140:97feb9bacc10 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
<> 140:97feb9bacc10 962
<> 140:97feb9bacc10 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
<> 140:97feb9bacc10 964 "MRS R1, CPSR;"
<> 140:97feb9bacc10 965 "CPS %0;" /* ;no effect in USR mode */
<> 140:97feb9bacc10 966 "MOV SP, R0;"
<> 140:97feb9bacc10 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
<> 140:97feb9bacc10 968 "ISB;"
<> 140:97feb9bacc10 969 //"BX LR;"
<> 140:97feb9bacc10 970 :
<> 140:97feb9bacc10 971 : "i"(MODE_SYS)
<> 140:97feb9bacc10 972 : "r0", "r1");
<> 140:97feb9bacc10 973 return;
<> 140:97feb9bacc10 974 }
<> 140:97feb9bacc10 975
<> 140:97feb9bacc10 976 /** \brief Set User Mode
<> 140:97feb9bacc10 977
<> 140:97feb9bacc10 978 This function changes the processor state to User Mode
<> 140:97feb9bacc10 979 */
<> 140:97feb9bacc10 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
<> 140:97feb9bacc10 981 {
<> 140:97feb9bacc10 982 __asm__ volatile (
<> 140:97feb9bacc10 983 ".ARM;"
<> 140:97feb9bacc10 984
<> 140:97feb9bacc10 985 "CPS %0;"
<> 140:97feb9bacc10 986 //"BX LR;"
<> 140:97feb9bacc10 987 :
<> 140:97feb9bacc10 988 : "i"(MODE_USR)
<> 140:97feb9bacc10 989 : );
<> 140:97feb9bacc10 990 return;
<> 140:97feb9bacc10 991 }
<> 140:97feb9bacc10 992
<> 140:97feb9bacc10 993
<> 140:97feb9bacc10 994 /** \brief Enable FIQ
<> 140:97feb9bacc10 995
<> 140:97feb9bacc10 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 140:97feb9bacc10 997 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 998 */
<> 140:97feb9bacc10 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
<> 140:97feb9bacc10 1000
<> 140:97feb9bacc10 1001
<> 140:97feb9bacc10 1002 /** \brief Disable FIQ
<> 140:97feb9bacc10 1003
<> 140:97feb9bacc10 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 140:97feb9bacc10 1005 Can only be executed in Privileged modes.
<> 140:97feb9bacc10 1006 */
<> 140:97feb9bacc10 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
<> 140:97feb9bacc10 1008
<> 140:97feb9bacc10 1009
<> 140:97feb9bacc10 1010 /** \brief Get FPSCR
<> 140:97feb9bacc10 1011
<> 140:97feb9bacc10 1012 This function returns the current value of the Floating Point Status/Control register.
<> 140:97feb9bacc10 1013
<> 140:97feb9bacc10 1014 \return Floating Point Status/Control register value
<> 140:97feb9bacc10 1015 */
<> 140:97feb9bacc10 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 140:97feb9bacc10 1017 {
<> 140:97feb9bacc10 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 1019 #if 1
<> 140:97feb9bacc10 1020 uint32_t result;
<> 140:97feb9bacc10 1021
<> 140:97feb9bacc10 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
<> 140:97feb9bacc10 1023 return (result);
<> 140:97feb9bacc10 1024 #else
<> 140:97feb9bacc10 1025 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 1026 return(__regfpscr);
<> 140:97feb9bacc10 1027 #endif
<> 140:97feb9bacc10 1028 #else
<> 140:97feb9bacc10 1029 return(0);
<> 140:97feb9bacc10 1030 #endif
<> 140:97feb9bacc10 1031 }
<> 140:97feb9bacc10 1032
<> 140:97feb9bacc10 1033
<> 140:97feb9bacc10 1034 /** \brief Set FPSCR
<> 140:97feb9bacc10 1035
<> 140:97feb9bacc10 1036 This function assigns the given value to the Floating Point Status/Control register.
<> 140:97feb9bacc10 1037
<> 140:97feb9bacc10 1038 \param [in] fpscr Floating Point Status/Control value to set
<> 140:97feb9bacc10 1039 */
<> 140:97feb9bacc10 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 140:97feb9bacc10 1041 {
<> 140:97feb9bacc10 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 140:97feb9bacc10 1043 #if 1
<> 140:97feb9bacc10 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
<> 140:97feb9bacc10 1045 #else
<> 140:97feb9bacc10 1046 register uint32_t __regfpscr __ASM("fpscr");
<> 140:97feb9bacc10 1047 __regfpscr = (fpscr);
<> 140:97feb9bacc10 1048 #endif
<> 140:97feb9bacc10 1049 #endif
<> 140:97feb9bacc10 1050 }
<> 140:97feb9bacc10 1051
<> 140:97feb9bacc10 1052 /** \brief Get FPEXC
<> 140:97feb9bacc10 1053
<> 140:97feb9bacc10 1054 This function returns the current value of the Floating Point Exception Control register.
<> 140:97feb9bacc10 1055
<> 140:97feb9bacc10 1056 \return Floating Point Exception Control register value
<> 140:97feb9bacc10 1057 */
<> 140:97feb9bacc10 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 140:97feb9bacc10 1059 {
<> 140:97feb9bacc10 1060 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 1061 #if 1
<> 140:97feb9bacc10 1062 uint32_t result;
<> 140:97feb9bacc10 1063
<> 140:97feb9bacc10 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
<> 140:97feb9bacc10 1065 return (result);
<> 140:97feb9bacc10 1066 #else
<> 140:97feb9bacc10 1067 register uint32_t __regfpexc __ASM("fpexc");
<> 140:97feb9bacc10 1068 return(__regfpexc);
<> 140:97feb9bacc10 1069 #endif
<> 140:97feb9bacc10 1070 #else
<> 140:97feb9bacc10 1071 return(0);
<> 140:97feb9bacc10 1072 #endif
<> 140:97feb9bacc10 1073 }
<> 140:97feb9bacc10 1074
<> 140:97feb9bacc10 1075
<> 140:97feb9bacc10 1076 /** \brief Set FPEXC
<> 140:97feb9bacc10 1077
<> 140:97feb9bacc10 1078 This function assigns the given value to the Floating Point Exception Control register.
<> 140:97feb9bacc10 1079
<> 140:97feb9bacc10 1080 \param [in] fpscr Floating Point Exception Control value to set
<> 140:97feb9bacc10 1081 */
<> 140:97feb9bacc10 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 140:97feb9bacc10 1083 {
<> 140:97feb9bacc10 1084 #if (__FPU_PRESENT == 1)
<> 140:97feb9bacc10 1085 #if 1
<> 140:97feb9bacc10 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
<> 140:97feb9bacc10 1087 #else
<> 140:97feb9bacc10 1088 register uint32_t __regfpexc __ASM("fpexc");
<> 140:97feb9bacc10 1089 __regfpexc = (fpexc);
<> 140:97feb9bacc10 1090 #endif
<> 140:97feb9bacc10 1091 #endif
<> 140:97feb9bacc10 1092 }
<> 140:97feb9bacc10 1093
<> 140:97feb9bacc10 1094 /** \brief Get CPACR
<> 140:97feb9bacc10 1095
<> 140:97feb9bacc10 1096 This function returns the current value of the Coprocessor Access Control register.
<> 140:97feb9bacc10 1097
<> 140:97feb9bacc10 1098 \return Coprocessor Access Control register value
<> 140:97feb9bacc10 1099 */
<> 140:97feb9bacc10 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
<> 140:97feb9bacc10 1101 {
<> 140:97feb9bacc10 1102 #if 1
<> 140:97feb9bacc10 1103 register uint32_t __regCPACR;
<> 140:97feb9bacc10 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
<> 140:97feb9bacc10 1105 #else
<> 140:97feb9bacc10 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 140:97feb9bacc10 1107 #endif
<> 140:97feb9bacc10 1108 return __regCPACR;
<> 140:97feb9bacc10 1109 }
<> 140:97feb9bacc10 1110
<> 140:97feb9bacc10 1111 /** \brief Set CPACR
<> 140:97feb9bacc10 1112
<> 140:97feb9bacc10 1113 This function assigns the given value to the Coprocessor Access Control register.
<> 140:97feb9bacc10 1114
<> 140:97feb9bacc10 1115 \param [in] cpacr Coprocessor Acccess Control value to set
<> 140:97feb9bacc10 1116 */
<> 140:97feb9bacc10 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 140:97feb9bacc10 1118 {
<> 140:97feb9bacc10 1119 #if 1
<> 140:97feb9bacc10 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
<> 140:97feb9bacc10 1121 #else
<> 140:97feb9bacc10 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 140:97feb9bacc10 1123 __regCPACR = cpacr;
<> 140:97feb9bacc10 1124 #endif
<> 140:97feb9bacc10 1125 __ISB();
<> 140:97feb9bacc10 1126 }
<> 140:97feb9bacc10 1127
<> 140:97feb9bacc10 1128 /** \brief Get CBAR
<> 140:97feb9bacc10 1129
<> 140:97feb9bacc10 1130 This function returns the value of the Configuration Base Address register.
<> 140:97feb9bacc10 1131
<> 140:97feb9bacc10 1132 \return Configuration Base Address register value
<> 140:97feb9bacc10 1133 */
<> 140:97feb9bacc10 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
<> 140:97feb9bacc10 1135 #if 1
<> 140:97feb9bacc10 1136 register uint32_t __regCBAR;
<> 140:97feb9bacc10 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
<> 140:97feb9bacc10 1138 #else
<> 140:97feb9bacc10 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 140:97feb9bacc10 1140 #endif
<> 140:97feb9bacc10 1141 return(__regCBAR);
<> 140:97feb9bacc10 1142 }
<> 140:97feb9bacc10 1143
<> 140:97feb9bacc10 1144 /** \brief Get TTBR0
<> 140:97feb9bacc10 1145
<> 140:97feb9bacc10 1146 This function returns the value of the Translation Table Base Register 0.
<> 140:97feb9bacc10 1147
<> 140:97feb9bacc10 1148 \return Translation Table Base Register 0 value
<> 140:97feb9bacc10 1149 */
<> 140:97feb9bacc10 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
<> 140:97feb9bacc10 1151 #if 1
<> 140:97feb9bacc10 1152 register uint32_t __regTTBR0;
<> 140:97feb9bacc10 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
<> 140:97feb9bacc10 1154 #else
<> 140:97feb9bacc10 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 140:97feb9bacc10 1156 #endif
<> 140:97feb9bacc10 1157 return(__regTTBR0);
<> 140:97feb9bacc10 1158 }
<> 140:97feb9bacc10 1159
<> 140:97feb9bacc10 1160 /** \brief Set TTBR0
<> 140:97feb9bacc10 1161
<> 140:97feb9bacc10 1162 This function assigns the given value to the Translation Table Base Register 0.
<> 140:97feb9bacc10 1163
<> 140:97feb9bacc10 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 140:97feb9bacc10 1165 */
<> 140:97feb9bacc10 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 140:97feb9bacc10 1167 #if 1
<> 140:97feb9bacc10 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
<> 140:97feb9bacc10 1169 #else
<> 140:97feb9bacc10 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 140:97feb9bacc10 1171 __regTTBR0 = ttbr0;
<> 140:97feb9bacc10 1172 #endif
<> 140:97feb9bacc10 1173 __ISB();
<> 140:97feb9bacc10 1174 }
<> 140:97feb9bacc10 1175
<> 140:97feb9bacc10 1176 /** \brief Get DACR
<> 140:97feb9bacc10 1177
<> 140:97feb9bacc10 1178 This function returns the value of the Domain Access Control Register.
<> 140:97feb9bacc10 1179
<> 140:97feb9bacc10 1180 \return Domain Access Control Register value
<> 140:97feb9bacc10 1181 */
<> 140:97feb9bacc10 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
<> 140:97feb9bacc10 1183 #if 1
<> 140:97feb9bacc10 1184 register uint32_t __regDACR;
<> 140:97feb9bacc10 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
<> 140:97feb9bacc10 1186 #else
<> 140:97feb9bacc10 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 140:97feb9bacc10 1188 #endif
<> 140:97feb9bacc10 1189 return(__regDACR);
<> 140:97feb9bacc10 1190 }
<> 140:97feb9bacc10 1191
<> 140:97feb9bacc10 1192 /** \brief Set DACR
<> 140:97feb9bacc10 1193
<> 140:97feb9bacc10 1194 This function assigns the given value to the Domain Access Control Register.
<> 140:97feb9bacc10 1195
<> 140:97feb9bacc10 1196 \param [in] dacr Domain Access Control Register value to set
<> 140:97feb9bacc10 1197 */
<> 140:97feb9bacc10 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 140:97feb9bacc10 1199 #if 1
<> 140:97feb9bacc10 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
<> 140:97feb9bacc10 1201 #else
<> 140:97feb9bacc10 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 140:97feb9bacc10 1203 __regDACR = dacr;
<> 140:97feb9bacc10 1204 #endif
<> 140:97feb9bacc10 1205 __ISB();
<> 140:97feb9bacc10 1206 }
<> 140:97feb9bacc10 1207
<> 140:97feb9bacc10 1208 /******************************** Cache and BTAC enable ****************************************************/
<> 140:97feb9bacc10 1209
<> 140:97feb9bacc10 1210 /** \brief Set SCTLR
<> 140:97feb9bacc10 1211
<> 140:97feb9bacc10 1212 This function assigns the given value to the System Control Register.
<> 140:97feb9bacc10 1213
<> 140:97feb9bacc10 1214 \param [in] sctlr System Control Register value to set
<> 140:97feb9bacc10 1215 */
<> 140:97feb9bacc10 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 140:97feb9bacc10 1217 {
<> 140:97feb9bacc10 1218 #if 1
<> 140:97feb9bacc10 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
<> 140:97feb9bacc10 1220 #else
<> 140:97feb9bacc10 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 140:97feb9bacc10 1222 __regSCTLR = sctlr;
<> 140:97feb9bacc10 1223 #endif
<> 140:97feb9bacc10 1224 }
<> 140:97feb9bacc10 1225
<> 140:97feb9bacc10 1226 /** \brief Get SCTLR
<> 140:97feb9bacc10 1227
<> 140:97feb9bacc10 1228 This function returns the value of the System Control Register.
<> 140:97feb9bacc10 1229
<> 140:97feb9bacc10 1230 \return System Control Register value
<> 140:97feb9bacc10 1231 */
<> 140:97feb9bacc10 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
<> 140:97feb9bacc10 1233 #if 1
<> 140:97feb9bacc10 1234 register uint32_t __regSCTLR;
<> 140:97feb9bacc10 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
<> 140:97feb9bacc10 1236 #else
<> 140:97feb9bacc10 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 140:97feb9bacc10 1238 #endif
<> 140:97feb9bacc10 1239 return(__regSCTLR);
<> 140:97feb9bacc10 1240 }
<> 140:97feb9bacc10 1241
<> 140:97feb9bacc10 1242 /** \brief Enable Caches
<> 140:97feb9bacc10 1243
<> 140:97feb9bacc10 1244 Enable Caches
<> 140:97feb9bacc10 1245 */
<> 140:97feb9bacc10 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
<> 140:97feb9bacc10 1247 // Set I bit 12 to enable I Cache
<> 140:97feb9bacc10 1248 // Set C bit 2 to enable D Cache
<> 140:97feb9bacc10 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 140:97feb9bacc10 1250 }
<> 140:97feb9bacc10 1251
<> 140:97feb9bacc10 1252 /** \brief Disable Caches
<> 140:97feb9bacc10 1253
<> 140:97feb9bacc10 1254 Disable Caches
<> 140:97feb9bacc10 1255 */
<> 140:97feb9bacc10 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
<> 140:97feb9bacc10 1257 // Clear I bit 12 to disable I Cache
<> 140:97feb9bacc10 1258 // Clear C bit 2 to disable D Cache
<> 140:97feb9bacc10 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 140:97feb9bacc10 1260 __ISB();
<> 140:97feb9bacc10 1261 }
<> 140:97feb9bacc10 1262
<> 140:97feb9bacc10 1263 /** \brief Enable BTAC
<> 140:97feb9bacc10 1264
<> 140:97feb9bacc10 1265 Enable BTAC
<> 140:97feb9bacc10 1266 */
<> 140:97feb9bacc10 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
<> 140:97feb9bacc10 1268 // Set Z bit 11 to enable branch prediction
<> 140:97feb9bacc10 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 140:97feb9bacc10 1270 __ISB();
<> 140:97feb9bacc10 1271 }
<> 140:97feb9bacc10 1272
<> 140:97feb9bacc10 1273 /** \brief Disable BTAC
<> 140:97feb9bacc10 1274
<> 140:97feb9bacc10 1275 Disable BTAC
<> 140:97feb9bacc10 1276 */
<> 140:97feb9bacc10 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
<> 140:97feb9bacc10 1278 // Clear Z bit 11 to disable branch prediction
<> 140:97feb9bacc10 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 140:97feb9bacc10 1280 }
<> 140:97feb9bacc10 1281
<> 140:97feb9bacc10 1282
<> 140:97feb9bacc10 1283 /** \brief Enable MMU
<> 140:97feb9bacc10 1284
<> 140:97feb9bacc10 1285 Enable MMU
<> 140:97feb9bacc10 1286 */
<> 140:97feb9bacc10 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
<> 140:97feb9bacc10 1288 // Set M bit 0 to enable the MMU
<> 140:97feb9bacc10 1289 // Set AFE bit to enable simplified access permissions model
<> 140:97feb9bacc10 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 140:97feb9bacc10 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 140:97feb9bacc10 1292 __ISB();
<> 140:97feb9bacc10 1293 }
<> 140:97feb9bacc10 1294
<> 140:97feb9bacc10 1295 /** \brief Disable MMU
<> 140:97feb9bacc10 1296
<> 140:97feb9bacc10 1297 Disable MMU
<> 140:97feb9bacc10 1298 */
<> 140:97feb9bacc10 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
<> 140:97feb9bacc10 1300 // Clear M bit 0 to disable the MMU
<> 140:97feb9bacc10 1301 __set_SCTLR( __get_SCTLR() & ~1);
<> 140:97feb9bacc10 1302 __ISB();
<> 140:97feb9bacc10 1303 }
<> 140:97feb9bacc10 1304
<> 140:97feb9bacc10 1305 /******************************** TLB maintenance operations ************************************************/
<> 140:97feb9bacc10 1306 /** \brief Invalidate the whole tlb
<> 140:97feb9bacc10 1307
<> 140:97feb9bacc10 1308 TLBIALL. Invalidate the whole tlb
<> 140:97feb9bacc10 1309 */
<> 140:97feb9bacc10 1310
<> 140:97feb9bacc10 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 140:97feb9bacc10 1312 #if 1
<> 140:97feb9bacc10 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
<> 140:97feb9bacc10 1314 #else
<> 140:97feb9bacc10 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 140:97feb9bacc10 1316 __TLBIALL = 0;
<> 140:97feb9bacc10 1317 #endif
<> 140:97feb9bacc10 1318 __DSB();
<> 140:97feb9bacc10 1319 __ISB();
<> 140:97feb9bacc10 1320 }
<> 140:97feb9bacc10 1321
<> 140:97feb9bacc10 1322 /******************************** BTB maintenance operations ************************************************/
<> 140:97feb9bacc10 1323 /** \brief Invalidate entire branch predictor array
<> 140:97feb9bacc10 1324
<> 140:97feb9bacc10 1325 BPIALL. Branch Predictor Invalidate All.
<> 140:97feb9bacc10 1326 */
<> 140:97feb9bacc10 1327
<> 140:97feb9bacc10 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
<> 140:97feb9bacc10 1329 #if 1
<> 140:97feb9bacc10 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
<> 140:97feb9bacc10 1331 #else
<> 140:97feb9bacc10 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 140:97feb9bacc10 1333 __BPIALL = 0;
<> 140:97feb9bacc10 1334 #endif
<> 140:97feb9bacc10 1335 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 1336 __ISB(); //ensure instruction fetch path sees new state
<> 140:97feb9bacc10 1337 }
<> 140:97feb9bacc10 1338
<> 140:97feb9bacc10 1339
<> 140:97feb9bacc10 1340 /******************************** L1 cache operations ******************************************************/
<> 140:97feb9bacc10 1341
<> 140:97feb9bacc10 1342 /** \brief Invalidate the whole I$
<> 140:97feb9bacc10 1343
<> 140:97feb9bacc10 1344 ICIALLU. Instruction Cache Invalidate All to PoU
<> 140:97feb9bacc10 1345 */
<> 140:97feb9bacc10 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 140:97feb9bacc10 1347 #if 1
<> 140:97feb9bacc10 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
<> 140:97feb9bacc10 1349 #else
<> 140:97feb9bacc10 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 140:97feb9bacc10 1351 __ICIALLU = 0;
<> 140:97feb9bacc10 1352 #endif
<> 140:97feb9bacc10 1353 __DSB(); //ensure completion of the invalidation
<> 140:97feb9bacc10 1354 __ISB(); //ensure instruction fetch path sees new I cache state
<> 140:97feb9bacc10 1355 }
<> 140:97feb9bacc10 1356
<> 140:97feb9bacc10 1357 /** \brief Clean D$ by MVA
<> 140:97feb9bacc10 1358
<> 140:97feb9bacc10 1359 DCCMVAC. Data cache clean by MVA to PoC
<> 140:97feb9bacc10 1360 */
<> 140:97feb9bacc10 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 140:97feb9bacc10 1362 #if 1
<> 140:97feb9bacc10 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
<> 140:97feb9bacc10 1364 #else
<> 140:97feb9bacc10 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 140:97feb9bacc10 1366 __DCCMVAC = (uint32_t)va;
<> 140:97feb9bacc10 1367 #endif
<> 140:97feb9bacc10 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 1369 }
<> 140:97feb9bacc10 1370
<> 140:97feb9bacc10 1371 /** \brief Invalidate D$ by MVA
<> 140:97feb9bacc10 1372
<> 140:97feb9bacc10 1373 DCIMVAC. Data cache invalidate by MVA to PoC
<> 140:97feb9bacc10 1374 */
<> 140:97feb9bacc10 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 140:97feb9bacc10 1376 #if 1
<> 140:97feb9bacc10 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
<> 140:97feb9bacc10 1378 #else
<> 140:97feb9bacc10 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 140:97feb9bacc10 1380 __DCIMVAC = (uint32_t)va;
<> 140:97feb9bacc10 1381 #endif
<> 140:97feb9bacc10 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 1383 }
<> 140:97feb9bacc10 1384
<> 140:97feb9bacc10 1385 /** \brief Clean and Invalidate D$ by MVA
<> 140:97feb9bacc10 1386
<> 140:97feb9bacc10 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 140:97feb9bacc10 1388 */
<> 140:97feb9bacc10 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 140:97feb9bacc10 1390 #if 1
<> 140:97feb9bacc10 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
<> 140:97feb9bacc10 1392 #else
<> 140:97feb9bacc10 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 140:97feb9bacc10 1394 __DCCIMVAC = (uint32_t)va;
<> 140:97feb9bacc10 1395 #endif
<> 140:97feb9bacc10 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 140:97feb9bacc10 1397 }
<> 140:97feb9bacc10 1398
<> 140:97feb9bacc10 1399 /** \brief Clean and Invalidate the entire data or unified cache
<> 140:97feb9bacc10 1400
<> 140:97feb9bacc10 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 140:97feb9bacc10 1402 */
<> 140:97feb9bacc10 1403 extern void __v7_all_cache(uint32_t op);
<> 140:97feb9bacc10 1404
<> 140:97feb9bacc10 1405
<> 140:97feb9bacc10 1406 /** \brief Invalidate the whole D$
<> 140:97feb9bacc10 1407
<> 140:97feb9bacc10 1408 DCISW. Invalidate by Set/Way
<> 140:97feb9bacc10 1409 */
<> 140:97feb9bacc10 1410
<> 140:97feb9bacc10 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 140:97feb9bacc10 1412 __v7_all_cache(0);
<> 140:97feb9bacc10 1413 }
<> 140:97feb9bacc10 1414
<> 140:97feb9bacc10 1415 /** \brief Clean the whole D$
<> 140:97feb9bacc10 1416
<> 140:97feb9bacc10 1417 DCCSW. Clean by Set/Way
<> 140:97feb9bacc10 1418 */
<> 140:97feb9bacc10 1419
<> 140:97feb9bacc10 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 140:97feb9bacc10 1421 __v7_all_cache(1);
<> 140:97feb9bacc10 1422 }
<> 140:97feb9bacc10 1423
<> 140:97feb9bacc10 1424 /** \brief Clean and invalidate the whole D$
<> 140:97feb9bacc10 1425
<> 140:97feb9bacc10 1426 DCCISW. Clean and Invalidate by Set/Way
<> 140:97feb9bacc10 1427 */
<> 140:97feb9bacc10 1428
<> 140:97feb9bacc10 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 140:97feb9bacc10 1430 __v7_all_cache(2);
<> 140:97feb9bacc10 1431 }
<> 140:97feb9bacc10 1432
<> 140:97feb9bacc10 1433 #include "core_ca_mmu.h"
<> 140:97feb9bacc10 1434
<> 140:97feb9bacc10 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
<> 140:97feb9bacc10 1436
<> 140:97feb9bacc10 1437 #error TASKING Compiler support not implemented for Cortex-A
<> 140:97feb9bacc10 1438
<> 140:97feb9bacc10 1439 #endif
<> 140:97feb9bacc10 1440
<> 140:97feb9bacc10 1441 /*@} end of CMSIS_Core_RegAccFunctions */
<> 140:97feb9bacc10 1442
<> 140:97feb9bacc10 1443
<> 140:97feb9bacc10 1444 #endif /* __CORE_CAFUNC_H__ */