mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51822/core_cmInstr.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
110:165afa46840b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cmInstr.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #ifndef __CORE_CMINSTR_H
emilmont 80:8e73be2a2ac1 39 #define __CORE_CMINSTR_H
emilmont 80:8e73be2a2ac1 40
emilmont 80:8e73be2a2ac1 41
emilmont 80:8e73be2a2ac1 42 /* ########################## Core Instruction Access ######################### */
emilmont 80:8e73be2a2ac1 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 80:8e73be2a2ac1 44 Access to dedicated instructions
emilmont 80:8e73be2a2ac1 45 @{
emilmont 80:8e73be2a2ac1 46 */
emilmont 80:8e73be2a2ac1 47
emilmont 80:8e73be2a2ac1 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 80:8e73be2a2ac1 49 /* ARM armcc specific functions */
emilmont 80:8e73be2a2ac1 50
emilmont 80:8e73be2a2ac1 51 #if (__ARMCC_VERSION < 400677)
emilmont 80:8e73be2a2ac1 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 80:8e73be2a2ac1 53 #endif
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55
emilmont 80:8e73be2a2ac1 56 /** \brief No Operation
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 80:8e73be2a2ac1 59 */
emilmont 80:8e73be2a2ac1 60 #define __NOP __nop
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /** \brief Wait For Interrupt
emilmont 80:8e73be2a2ac1 64
emilmont 80:8e73be2a2ac1 65 Wait For Interrupt is a hint instruction that suspends execution
emilmont 80:8e73be2a2ac1 66 until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 67 */
emilmont 80:8e73be2a2ac1 68 #define __WFI __wfi
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70
emilmont 80:8e73be2a2ac1 71 /** \brief Wait For Event
emilmont 80:8e73be2a2ac1 72
emilmont 80:8e73be2a2ac1 73 Wait For Event is a hint instruction that permits the processor to enter
emilmont 80:8e73be2a2ac1 74 a low-power state until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 75 */
emilmont 80:8e73be2a2ac1 76 #define __WFE __wfe
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 /** \brief Send Event
emilmont 80:8e73be2a2ac1 80
emilmont 80:8e73be2a2ac1 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 80:8e73be2a2ac1 82 */
emilmont 80:8e73be2a2ac1 83 #define __SEV __sev
emilmont 80:8e73be2a2ac1 84
emilmont 80:8e73be2a2ac1 85
emilmont 80:8e73be2a2ac1 86 /** \brief Instruction Synchronization Barrier
emilmont 80:8e73be2a2ac1 87
emilmont 80:8e73be2a2ac1 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 80:8e73be2a2ac1 89 so that all instructions following the ISB are fetched from cache or
emilmont 80:8e73be2a2ac1 90 memory, after the instruction has been completed.
emilmont 80:8e73be2a2ac1 91 */
Kojto 110:165afa46840b 92 #define __ISB() do {\
Kojto 110:165afa46840b 93 __schedule_barrier();\
Kojto 110:165afa46840b 94 __isb(0xF);\
Kojto 110:165afa46840b 95 __schedule_barrier();\
Kojto 110:165afa46840b 96 } while (0)
emilmont 80:8e73be2a2ac1 97
emilmont 80:8e73be2a2ac1 98 /** \brief Data Synchronization Barrier
emilmont 80:8e73be2a2ac1 99
emilmont 80:8e73be2a2ac1 100 This function acts as a special kind of Data Memory Barrier.
emilmont 80:8e73be2a2ac1 101 It completes when all explicit memory accesses before this instruction complete.
emilmont 80:8e73be2a2ac1 102 */
Kojto 110:165afa46840b 103 #define __DSB() do {\
Kojto 110:165afa46840b 104 __schedule_barrier();\
Kojto 110:165afa46840b 105 __dsb(0xF);\
Kojto 110:165afa46840b 106 __schedule_barrier();\
Kojto 110:165afa46840b 107 } while (0)
emilmont 80:8e73be2a2ac1 108
emilmont 80:8e73be2a2ac1 109 /** \brief Data Memory Barrier
emilmont 80:8e73be2a2ac1 110
emilmont 80:8e73be2a2ac1 111 This function ensures the apparent order of the explicit memory operations before
emilmont 80:8e73be2a2ac1 112 and after the instruction, without ensuring their completion.
emilmont 80:8e73be2a2ac1 113 */
Kojto 110:165afa46840b 114 #define __DMB() do {\
Kojto 110:165afa46840b 115 __schedule_barrier();\
Kojto 110:165afa46840b 116 __dmb(0xF);\
Kojto 110:165afa46840b 117 __schedule_barrier();\
Kojto 110:165afa46840b 118 } while (0)
emilmont 80:8e73be2a2ac1 119
emilmont 80:8e73be2a2ac1 120 /** \brief Reverse byte order (32 bit)
emilmont 80:8e73be2a2ac1 121
emilmont 80:8e73be2a2ac1 122 This function reverses the byte order in integer value.
emilmont 80:8e73be2a2ac1 123
emilmont 80:8e73be2a2ac1 124 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 125 \return Reversed value
emilmont 80:8e73be2a2ac1 126 */
emilmont 80:8e73be2a2ac1 127 #define __REV __rev
emilmont 80:8e73be2a2ac1 128
emilmont 80:8e73be2a2ac1 129
emilmont 80:8e73be2a2ac1 130 /** \brief Reverse byte order (16 bit)
emilmont 80:8e73be2a2ac1 131
emilmont 80:8e73be2a2ac1 132 This function reverses the byte order in two unsigned short values.
emilmont 80:8e73be2a2ac1 133
emilmont 80:8e73be2a2ac1 134 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 135 \return Reversed value
emilmont 80:8e73be2a2ac1 136 */
emilmont 80:8e73be2a2ac1 137 #ifndef __NO_EMBEDDED_ASM
emilmont 80:8e73be2a2ac1 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 80:8e73be2a2ac1 139 {
emilmont 80:8e73be2a2ac1 140 rev16 r0, r0
emilmont 80:8e73be2a2ac1 141 bx lr
emilmont 80:8e73be2a2ac1 142 }
emilmont 80:8e73be2a2ac1 143 #endif
emilmont 80:8e73be2a2ac1 144
emilmont 80:8e73be2a2ac1 145 /** \brief Reverse byte order in signed short value
emilmont 80:8e73be2a2ac1 146
emilmont 80:8e73be2a2ac1 147 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 80:8e73be2a2ac1 148
emilmont 80:8e73be2a2ac1 149 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 150 \return Reversed value
emilmont 80:8e73be2a2ac1 151 */
emilmont 80:8e73be2a2ac1 152 #ifndef __NO_EMBEDDED_ASM
emilmont 80:8e73be2a2ac1 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 80:8e73be2a2ac1 154 {
emilmont 80:8e73be2a2ac1 155 revsh r0, r0
emilmont 80:8e73be2a2ac1 156 bx lr
emilmont 80:8e73be2a2ac1 157 }
emilmont 80:8e73be2a2ac1 158 #endif
emilmont 80:8e73be2a2ac1 159
emilmont 80:8e73be2a2ac1 160
emilmont 80:8e73be2a2ac1 161 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 80:8e73be2a2ac1 162
emilmont 80:8e73be2a2ac1 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 80:8e73be2a2ac1 164
emilmont 80:8e73be2a2ac1 165 \param [in] value Value to rotate
emilmont 80:8e73be2a2ac1 166 \param [in] value Number of Bits to rotate
emilmont 80:8e73be2a2ac1 167 \return Rotated value
emilmont 80:8e73be2a2ac1 168 */
emilmont 80:8e73be2a2ac1 169 #define __ROR __ror
emilmont 80:8e73be2a2ac1 170
emilmont 80:8e73be2a2ac1 171
emilmont 80:8e73be2a2ac1 172 /** \brief Breakpoint
emilmont 80:8e73be2a2ac1 173
emilmont 80:8e73be2a2ac1 174 This function causes the processor to enter Debug state.
emilmont 80:8e73be2a2ac1 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 80:8e73be2a2ac1 176
emilmont 80:8e73be2a2ac1 177 \param [in] value is ignored by the processor.
emilmont 80:8e73be2a2ac1 178 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 80:8e73be2a2ac1 179 */
emilmont 80:8e73be2a2ac1 180 #define __BKPT(value) __breakpoint(value)
emilmont 80:8e73be2a2ac1 181
emilmont 80:8e73be2a2ac1 182
emilmont 80:8e73be2a2ac1 183 /** \brief Reverse bit order of value
emilmont 80:8e73be2a2ac1 184
emilmont 80:8e73be2a2ac1 185 This function reverses the bit order of the given value.
emilmont 80:8e73be2a2ac1 186
emilmont 80:8e73be2a2ac1 187 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 188 \return Reversed value
emilmont 80:8e73be2a2ac1 189 */
Kojto 110:165afa46840b 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Kojto 110:165afa46840b 191 #define __RBIT __rbit
Kojto 110:165afa46840b 192 #else
Kojto 110:165afa46840b 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
Kojto 110:165afa46840b 194 {
Kojto 110:165afa46840b 195 uint32_t result;
Kojto 110:165afa46840b 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
emilmont 80:8e73be2a2ac1 197
Kojto 110:165afa46840b 198 result = value; // r will be reversed bits of v; first get LSB of v
Kojto 110:165afa46840b 199 for (value >>= 1; value; value >>= 1)
Kojto 110:165afa46840b 200 {
Kojto 110:165afa46840b 201 result <<= 1;
Kojto 110:165afa46840b 202 result |= value & 1;
Kojto 110:165afa46840b 203 s--;
Kojto 110:165afa46840b 204 }
Kojto 110:165afa46840b 205 result <<= s; // shift when v's highest bits are zero
Kojto 110:165afa46840b 206 return(result);
Kojto 110:165afa46840b 207 }
Kojto 110:165afa46840b 208 #endif
Kojto 110:165afa46840b 209
Kojto 110:165afa46840b 210
Kojto 110:165afa46840b 211 /** \brief Count leading zeros
Kojto 110:165afa46840b 212
Kojto 110:165afa46840b 213 This function counts the number of leading zeros of a data value.
Kojto 110:165afa46840b 214
Kojto 110:165afa46840b 215 \param [in] value Value to count the leading zeros
Kojto 110:165afa46840b 216 \return number of leading zeros in value
Kojto 110:165afa46840b 217 */
Kojto 110:165afa46840b 218 #define __CLZ __clz
Kojto 110:165afa46840b 219
Kojto 110:165afa46840b 220
Kojto 110:165afa46840b 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
emilmont 80:8e73be2a2ac1 222
emilmont 80:8e73be2a2ac1 223 /** \brief LDR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 224
Kojto 110:165afa46840b 225 This function executes a exclusive LDR instruction for 8 bit value.
emilmont 80:8e73be2a2ac1 226
emilmont 80:8e73be2a2ac1 227 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 228 \return value of type uint8_t at (*ptr)
emilmont 80:8e73be2a2ac1 229 */
emilmont 80:8e73be2a2ac1 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 231
emilmont 80:8e73be2a2ac1 232
emilmont 80:8e73be2a2ac1 233 /** \brief LDR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 234
Kojto 110:165afa46840b 235 This function executes a exclusive LDR instruction for 16 bit values.
emilmont 80:8e73be2a2ac1 236
emilmont 80:8e73be2a2ac1 237 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 238 \return value of type uint16_t at (*ptr)
emilmont 80:8e73be2a2ac1 239 */
emilmont 80:8e73be2a2ac1 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 241
emilmont 80:8e73be2a2ac1 242
emilmont 80:8e73be2a2ac1 243 /** \brief LDR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 244
Kojto 110:165afa46840b 245 This function executes a exclusive LDR instruction for 32 bit values.
emilmont 80:8e73be2a2ac1 246
emilmont 80:8e73be2a2ac1 247 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 248 \return value of type uint32_t at (*ptr)
emilmont 80:8e73be2a2ac1 249 */
emilmont 80:8e73be2a2ac1 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 80:8e73be2a2ac1 251
emilmont 80:8e73be2a2ac1 252
emilmont 80:8e73be2a2ac1 253 /** \brief STR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 254
Kojto 110:165afa46840b 255 This function executes a exclusive STR instruction for 8 bit values.
emilmont 80:8e73be2a2ac1 256
emilmont 80:8e73be2a2ac1 257 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 258 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 259 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 260 \return 1 Function failed
emilmont 80:8e73be2a2ac1 261 */
emilmont 80:8e73be2a2ac1 262 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 263
emilmont 80:8e73be2a2ac1 264
emilmont 80:8e73be2a2ac1 265 /** \brief STR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 266
Kojto 110:165afa46840b 267 This function executes a exclusive STR instruction for 16 bit values.
emilmont 80:8e73be2a2ac1 268
emilmont 80:8e73be2a2ac1 269 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 270 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 271 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 272 \return 1 Function failed
emilmont 80:8e73be2a2ac1 273 */
emilmont 80:8e73be2a2ac1 274 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 275
emilmont 80:8e73be2a2ac1 276
emilmont 80:8e73be2a2ac1 277 /** \brief STR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 278
Kojto 110:165afa46840b 279 This function executes a exclusive STR instruction for 32 bit values.
emilmont 80:8e73be2a2ac1 280
emilmont 80:8e73be2a2ac1 281 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 282 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 283 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 284 \return 1 Function failed
emilmont 80:8e73be2a2ac1 285 */
emilmont 80:8e73be2a2ac1 286 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 80:8e73be2a2ac1 287
emilmont 80:8e73be2a2ac1 288
emilmont 80:8e73be2a2ac1 289 /** \brief Remove the exclusive lock
emilmont 80:8e73be2a2ac1 290
emilmont 80:8e73be2a2ac1 291 This function removes the exclusive lock which is created by LDREX.
emilmont 80:8e73be2a2ac1 292
emilmont 80:8e73be2a2ac1 293 */
emilmont 80:8e73be2a2ac1 294 #define __CLREX __clrex
emilmont 80:8e73be2a2ac1 295
emilmont 80:8e73be2a2ac1 296
emilmont 80:8e73be2a2ac1 297 /** \brief Signed Saturate
emilmont 80:8e73be2a2ac1 298
emilmont 80:8e73be2a2ac1 299 This function saturates a signed value.
emilmont 80:8e73be2a2ac1 300
emilmont 80:8e73be2a2ac1 301 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 302 \param [in] sat Bit position to saturate to (1..32)
emilmont 80:8e73be2a2ac1 303 \return Saturated value
emilmont 80:8e73be2a2ac1 304 */
emilmont 80:8e73be2a2ac1 305 #define __SSAT __ssat
emilmont 80:8e73be2a2ac1 306
emilmont 80:8e73be2a2ac1 307
emilmont 80:8e73be2a2ac1 308 /** \brief Unsigned Saturate
emilmont 80:8e73be2a2ac1 309
emilmont 80:8e73be2a2ac1 310 This function saturates an unsigned value.
emilmont 80:8e73be2a2ac1 311
emilmont 80:8e73be2a2ac1 312 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 313 \param [in] sat Bit position to saturate to (0..31)
emilmont 80:8e73be2a2ac1 314 \return Saturated value
emilmont 80:8e73be2a2ac1 315 */
emilmont 80:8e73be2a2ac1 316 #define __USAT __usat
emilmont 80:8e73be2a2ac1 317
emilmont 80:8e73be2a2ac1 318
Kojto 110:165afa46840b 319 /** \brief Rotate Right with Extend (32 bit)
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 This function moves each bit of a bitstring right by one bit.
Kojto 110:165afa46840b 322 The carry input is shifted in at the left end of the bitstring.
emilmont 80:8e73be2a2ac1 323
Kojto 110:165afa46840b 324 \param [in] value Value to rotate
Kojto 110:165afa46840b 325 \return Rotated value
Kojto 110:165afa46840b 326 */
Kojto 110:165afa46840b 327 #ifndef __NO_EMBEDDED_ASM
Kojto 110:165afa46840b 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
Kojto 110:165afa46840b 329 {
Kojto 110:165afa46840b 330 rrx r0, r0
Kojto 110:165afa46840b 331 bx lr
Kojto 110:165afa46840b 332 }
Kojto 110:165afa46840b 333 #endif
Kojto 110:165afa46840b 334
emilmont 80:8e73be2a2ac1 335
Kojto 110:165afa46840b 336 /** \brief LDRT Unprivileged (8 bit)
Kojto 110:165afa46840b 337
Kojto 110:165afa46840b 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
Kojto 110:165afa46840b 339
Kojto 110:165afa46840b 340 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 341 \return value of type uint8_t at (*ptr)
emilmont 80:8e73be2a2ac1 342 */
Kojto 110:165afa46840b 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
Kojto 110:165afa46840b 344
Kojto 110:165afa46840b 345
Kojto 110:165afa46840b 346 /** \brief LDRT Unprivileged (16 bit)
emilmont 80:8e73be2a2ac1 347
Kojto 110:165afa46840b 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
Kojto 110:165afa46840b 349
Kojto 110:165afa46840b 350 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 351 \return value of type uint16_t at (*ptr)
Kojto 110:165afa46840b 352 */
Kojto 110:165afa46840b 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
emilmont 80:8e73be2a2ac1 354
emilmont 80:8e73be2a2ac1 355
Kojto 110:165afa46840b 356 /** \brief LDRT Unprivileged (32 bit)
emilmont 80:8e73be2a2ac1 357
Kojto 110:165afa46840b 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
Kojto 110:165afa46840b 359
Kojto 110:165afa46840b 360 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 361 \return value of type uint32_t at (*ptr)
Kojto 110:165afa46840b 362 */
Kojto 110:165afa46840b 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
Kojto 110:165afa46840b 364
emilmont 80:8e73be2a2ac1 365
Kojto 110:165afa46840b 366 /** \brief STRT Unprivileged (8 bit)
Kojto 110:165afa46840b 367
Kojto 110:165afa46840b 368 This function executes a Unprivileged STRT instruction for 8 bit values.
Kojto 110:165afa46840b 369
Kojto 110:165afa46840b 370 \param [in] value Value to store
Kojto 110:165afa46840b 371 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 372 */
Kojto 110:165afa46840b 373 #define __STRBT(value, ptr) __strt(value, ptr)
emilmont 80:8e73be2a2ac1 374
emilmont 80:8e73be2a2ac1 375
Kojto 110:165afa46840b 376 /** \brief STRT Unprivileged (16 bit)
Kojto 110:165afa46840b 377
Kojto 110:165afa46840b 378 This function executes a Unprivileged STRT instruction for 16 bit values.
Kojto 110:165afa46840b 379
Kojto 110:165afa46840b 380 \param [in] value Value to store
Kojto 110:165afa46840b 381 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 382 */
Kojto 110:165afa46840b 383 #define __STRHT(value, ptr) __strt(value, ptr)
Kojto 110:165afa46840b 384
emilmont 80:8e73be2a2ac1 385
Kojto 110:165afa46840b 386 /** \brief STRT Unprivileged (32 bit)
Kojto 110:165afa46840b 387
Kojto 110:165afa46840b 388 This function executes a Unprivileged STRT instruction for 32 bit values.
Kojto 110:165afa46840b 389
Kojto 110:165afa46840b 390 \param [in] value Value to store
Kojto 110:165afa46840b 391 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 392 */
Kojto 110:165afa46840b 393 #define __STRT(value, ptr) __strt(value, ptr)
Kojto 110:165afa46840b 394
Kojto 110:165afa46840b 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
emilmont 80:8e73be2a2ac1 396
emilmont 80:8e73be2a2ac1 397
emilmont 80:8e73be2a2ac1 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 80:8e73be2a2ac1 399 /* GNU gcc specific functions */
emilmont 80:8e73be2a2ac1 400
emilmont 80:8e73be2a2ac1 401 /* Define macros for porting to both thumb1 and thumb2.
emilmont 80:8e73be2a2ac1 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
emilmont 80:8e73be2a2ac1 403 * Otherwise, use general registers, specified by constrant "r" */
emilmont 80:8e73be2a2ac1 404 #if defined (__thumb__) && !defined (__thumb2__)
emilmont 80:8e73be2a2ac1 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
emilmont 80:8e73be2a2ac1 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
emilmont 80:8e73be2a2ac1 407 #else
emilmont 80:8e73be2a2ac1 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
emilmont 80:8e73be2a2ac1 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
emilmont 80:8e73be2a2ac1 410 #endif
emilmont 80:8e73be2a2ac1 411
emilmont 80:8e73be2a2ac1 412 /** \brief No Operation
emilmont 80:8e73be2a2ac1 413
emilmont 80:8e73be2a2ac1 414 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 80:8e73be2a2ac1 415 */
Kojto 110:165afa46840b 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
emilmont 80:8e73be2a2ac1 417 {
emilmont 80:8e73be2a2ac1 418 __ASM volatile ("nop");
emilmont 80:8e73be2a2ac1 419 }
emilmont 80:8e73be2a2ac1 420
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422 /** \brief Wait For Interrupt
emilmont 80:8e73be2a2ac1 423
emilmont 80:8e73be2a2ac1 424 Wait For Interrupt is a hint instruction that suspends execution
emilmont 80:8e73be2a2ac1 425 until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 426 */
Kojto 110:165afa46840b 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
emilmont 80:8e73be2a2ac1 428 {
emilmont 80:8e73be2a2ac1 429 __ASM volatile ("wfi");
emilmont 80:8e73be2a2ac1 430 }
emilmont 80:8e73be2a2ac1 431
emilmont 80:8e73be2a2ac1 432
emilmont 80:8e73be2a2ac1 433 /** \brief Wait For Event
emilmont 80:8e73be2a2ac1 434
emilmont 80:8e73be2a2ac1 435 Wait For Event is a hint instruction that permits the processor to enter
emilmont 80:8e73be2a2ac1 436 a low-power state until one of a number of events occurs.
emilmont 80:8e73be2a2ac1 437 */
Kojto 110:165afa46840b 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
emilmont 80:8e73be2a2ac1 439 {
emilmont 80:8e73be2a2ac1 440 __ASM volatile ("wfe");
emilmont 80:8e73be2a2ac1 441 }
emilmont 80:8e73be2a2ac1 442
emilmont 80:8e73be2a2ac1 443
emilmont 80:8e73be2a2ac1 444 /** \brief Send Event
emilmont 80:8e73be2a2ac1 445
emilmont 80:8e73be2a2ac1 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 80:8e73be2a2ac1 447 */
Kojto 110:165afa46840b 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
emilmont 80:8e73be2a2ac1 449 {
emilmont 80:8e73be2a2ac1 450 __ASM volatile ("sev");
emilmont 80:8e73be2a2ac1 451 }
emilmont 80:8e73be2a2ac1 452
emilmont 80:8e73be2a2ac1 453
emilmont 80:8e73be2a2ac1 454 /** \brief Instruction Synchronization Barrier
emilmont 80:8e73be2a2ac1 455
emilmont 80:8e73be2a2ac1 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 80:8e73be2a2ac1 457 so that all instructions following the ISB are fetched from cache or
emilmont 80:8e73be2a2ac1 458 memory, after the instruction has been completed.
emilmont 80:8e73be2a2ac1 459 */
Kojto 110:165afa46840b 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
emilmont 80:8e73be2a2ac1 461 {
Kojto 110:165afa46840b 462 __ASM volatile ("isb 0xF":::"memory");
emilmont 80:8e73be2a2ac1 463 }
emilmont 80:8e73be2a2ac1 464
emilmont 80:8e73be2a2ac1 465
emilmont 80:8e73be2a2ac1 466 /** \brief Data Synchronization Barrier
emilmont 80:8e73be2a2ac1 467
emilmont 80:8e73be2a2ac1 468 This function acts as a special kind of Data Memory Barrier.
emilmont 80:8e73be2a2ac1 469 It completes when all explicit memory accesses before this instruction complete.
emilmont 80:8e73be2a2ac1 470 */
Kojto 110:165afa46840b 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
emilmont 80:8e73be2a2ac1 472 {
Kojto 110:165afa46840b 473 __ASM volatile ("dsb 0xF":::"memory");
emilmont 80:8e73be2a2ac1 474 }
emilmont 80:8e73be2a2ac1 475
emilmont 80:8e73be2a2ac1 476
emilmont 80:8e73be2a2ac1 477 /** \brief Data Memory Barrier
emilmont 80:8e73be2a2ac1 478
emilmont 80:8e73be2a2ac1 479 This function ensures the apparent order of the explicit memory operations before
emilmont 80:8e73be2a2ac1 480 and after the instruction, without ensuring their completion.
emilmont 80:8e73be2a2ac1 481 */
Kojto 110:165afa46840b 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
emilmont 80:8e73be2a2ac1 483 {
Kojto 110:165afa46840b 484 __ASM volatile ("dmb 0xF":::"memory");
emilmont 80:8e73be2a2ac1 485 }
emilmont 80:8e73be2a2ac1 486
emilmont 80:8e73be2a2ac1 487
emilmont 80:8e73be2a2ac1 488 /** \brief Reverse byte order (32 bit)
emilmont 80:8e73be2a2ac1 489
emilmont 80:8e73be2a2ac1 490 This function reverses the byte order in integer value.
emilmont 80:8e73be2a2ac1 491
emilmont 80:8e73be2a2ac1 492 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 493 \return Reversed value
emilmont 80:8e73be2a2ac1 494 */
Kojto 110:165afa46840b 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 80:8e73be2a2ac1 496 {
emilmont 80:8e73be2a2ac1 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
emilmont 80:8e73be2a2ac1 498 return __builtin_bswap32(value);
emilmont 80:8e73be2a2ac1 499 #else
emilmont 80:8e73be2a2ac1 500 uint32_t result;
emilmont 80:8e73be2a2ac1 501
emilmont 80:8e73be2a2ac1 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 503 return(result);
emilmont 80:8e73be2a2ac1 504 #endif
emilmont 80:8e73be2a2ac1 505 }
emilmont 80:8e73be2a2ac1 506
emilmont 80:8e73be2a2ac1 507
emilmont 80:8e73be2a2ac1 508 /** \brief Reverse byte order (16 bit)
emilmont 80:8e73be2a2ac1 509
emilmont 80:8e73be2a2ac1 510 This function reverses the byte order in two unsigned short values.
emilmont 80:8e73be2a2ac1 511
emilmont 80:8e73be2a2ac1 512 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 513 \return Reversed value
emilmont 80:8e73be2a2ac1 514 */
Kojto 110:165afa46840b 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 80:8e73be2a2ac1 516 {
emilmont 80:8e73be2a2ac1 517 uint32_t result;
emilmont 80:8e73be2a2ac1 518
emilmont 80:8e73be2a2ac1 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 520 return(result);
emilmont 80:8e73be2a2ac1 521 }
emilmont 80:8e73be2a2ac1 522
emilmont 80:8e73be2a2ac1 523
emilmont 80:8e73be2a2ac1 524 /** \brief Reverse byte order in signed short value
emilmont 80:8e73be2a2ac1 525
emilmont 80:8e73be2a2ac1 526 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 80:8e73be2a2ac1 527
emilmont 80:8e73be2a2ac1 528 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 529 \return Reversed value
emilmont 80:8e73be2a2ac1 530 */
Kojto 110:165afa46840b 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 80:8e73be2a2ac1 532 {
emilmont 80:8e73be2a2ac1 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 534 return (short)__builtin_bswap16(value);
emilmont 80:8e73be2a2ac1 535 #else
emilmont 80:8e73be2a2ac1 536 uint32_t result;
emilmont 80:8e73be2a2ac1 537
emilmont 80:8e73be2a2ac1 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 539 return(result);
emilmont 80:8e73be2a2ac1 540 #endif
emilmont 80:8e73be2a2ac1 541 }
emilmont 80:8e73be2a2ac1 542
emilmont 80:8e73be2a2ac1 543
emilmont 80:8e73be2a2ac1 544 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 80:8e73be2a2ac1 545
emilmont 80:8e73be2a2ac1 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 80:8e73be2a2ac1 547
emilmont 80:8e73be2a2ac1 548 \param [in] value Value to rotate
emilmont 80:8e73be2a2ac1 549 \param [in] value Number of Bits to rotate
emilmont 80:8e73be2a2ac1 550 \return Rotated value
emilmont 80:8e73be2a2ac1 551 */
Kojto 110:165afa46840b 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 80:8e73be2a2ac1 553 {
Kojto 110:165afa46840b 554 return (op1 >> op2) | (op1 << (32 - op2));
emilmont 80:8e73be2a2ac1 555 }
emilmont 80:8e73be2a2ac1 556
emilmont 80:8e73be2a2ac1 557
emilmont 80:8e73be2a2ac1 558 /** \brief Breakpoint
emilmont 80:8e73be2a2ac1 559
emilmont 80:8e73be2a2ac1 560 This function causes the processor to enter Debug state.
emilmont 80:8e73be2a2ac1 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 80:8e73be2a2ac1 562
emilmont 80:8e73be2a2ac1 563 \param [in] value is ignored by the processor.
emilmont 80:8e73be2a2ac1 564 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 80:8e73be2a2ac1 565 */
emilmont 80:8e73be2a2ac1 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 80:8e73be2a2ac1 567
emilmont 80:8e73be2a2ac1 568
emilmont 80:8e73be2a2ac1 569 /** \brief Reverse bit order of value
emilmont 80:8e73be2a2ac1 570
emilmont 80:8e73be2a2ac1 571 This function reverses the bit order of the given value.
emilmont 80:8e73be2a2ac1 572
emilmont 80:8e73be2a2ac1 573 \param [in] value Value to reverse
emilmont 80:8e73be2a2ac1 574 \return Reversed value
emilmont 80:8e73be2a2ac1 575 */
Kojto 110:165afa46840b 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 80:8e73be2a2ac1 577 {
emilmont 80:8e73be2a2ac1 578 uint32_t result;
emilmont 80:8e73be2a2ac1 579
Kojto 110:165afa46840b 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
emilmont 80:8e73be2a2ac1 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
Kojto 110:165afa46840b 582 #else
Kojto 110:165afa46840b 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
Kojto 110:165afa46840b 584
Kojto 110:165afa46840b 585 result = value; // r will be reversed bits of v; first get LSB of v
Kojto 110:165afa46840b 586 for (value >>= 1; value; value >>= 1)
Kojto 110:165afa46840b 587 {
Kojto 110:165afa46840b 588 result <<= 1;
Kojto 110:165afa46840b 589 result |= value & 1;
Kojto 110:165afa46840b 590 s--;
Kojto 110:165afa46840b 591 }
Kojto 110:165afa46840b 592 result <<= s; // shift when v's highest bits are zero
Kojto 110:165afa46840b 593 #endif
Kojto 110:165afa46840b 594 return(result);
emilmont 80:8e73be2a2ac1 595 }
emilmont 80:8e73be2a2ac1 596
emilmont 80:8e73be2a2ac1 597
Kojto 110:165afa46840b 598 /** \brief Count leading zeros
Kojto 110:165afa46840b 599
Kojto 110:165afa46840b 600 This function counts the number of leading zeros of a data value.
Kojto 110:165afa46840b 601
Kojto 110:165afa46840b 602 \param [in] value Value to count the leading zeros
Kojto 110:165afa46840b 603 \return number of leading zeros in value
Kojto 110:165afa46840b 604 */
Kojto 110:165afa46840b 605 #define __CLZ __builtin_clz
Kojto 110:165afa46840b 606
Kojto 110:165afa46840b 607
Kojto 110:165afa46840b 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Kojto 110:165afa46840b 609
emilmont 80:8e73be2a2ac1 610 /** \brief LDR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 611
Kojto 110:165afa46840b 612 This function executes a exclusive LDR instruction for 8 bit value.
emilmont 80:8e73be2a2ac1 613
emilmont 80:8e73be2a2ac1 614 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 615 \return value of type uint8_t at (*ptr)
emilmont 80:8e73be2a2ac1 616 */
Kojto 110:165afa46840b 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 80:8e73be2a2ac1 618 {
emilmont 80:8e73be2a2ac1 619 uint32_t result;
emilmont 80:8e73be2a2ac1 620
emilmont 80:8e73be2a2ac1 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 623 #else
emilmont 80:8e73be2a2ac1 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 80:8e73be2a2ac1 625 accepted by assembler. So has to use following less efficient pattern.
emilmont 80:8e73be2a2ac1 626 */
emilmont 80:8e73be2a2ac1 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 80:8e73be2a2ac1 628 #endif
Kojto 110:165afa46840b 629 return ((uint8_t) result); /* Add explicit type cast here */
emilmont 80:8e73be2a2ac1 630 }
emilmont 80:8e73be2a2ac1 631
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633 /** \brief LDR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 634
Kojto 110:165afa46840b 635 This function executes a exclusive LDR instruction for 16 bit values.
emilmont 80:8e73be2a2ac1 636
emilmont 80:8e73be2a2ac1 637 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 638 \return value of type uint16_t at (*ptr)
emilmont 80:8e73be2a2ac1 639 */
Kojto 110:165afa46840b 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 80:8e73be2a2ac1 641 {
emilmont 80:8e73be2a2ac1 642 uint32_t result;
emilmont 80:8e73be2a2ac1 643
emilmont 80:8e73be2a2ac1 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 80:8e73be2a2ac1 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 646 #else
emilmont 80:8e73be2a2ac1 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 80:8e73be2a2ac1 648 accepted by assembler. So has to use following less efficient pattern.
emilmont 80:8e73be2a2ac1 649 */
emilmont 80:8e73be2a2ac1 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 80:8e73be2a2ac1 651 #endif
Kojto 110:165afa46840b 652 return ((uint16_t) result); /* Add explicit type cast here */
emilmont 80:8e73be2a2ac1 653 }
emilmont 80:8e73be2a2ac1 654
emilmont 80:8e73be2a2ac1 655
emilmont 80:8e73be2a2ac1 656 /** \brief LDR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 657
Kojto 110:165afa46840b 658 This function executes a exclusive LDR instruction for 32 bit values.
emilmont 80:8e73be2a2ac1 659
emilmont 80:8e73be2a2ac1 660 \param [in] ptr Pointer to data
emilmont 80:8e73be2a2ac1 661 \return value of type uint32_t at (*ptr)
emilmont 80:8e73be2a2ac1 662 */
Kojto 110:165afa46840b 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 80:8e73be2a2ac1 664 {
emilmont 80:8e73be2a2ac1 665 uint32_t result;
emilmont 80:8e73be2a2ac1 666
emilmont 80:8e73be2a2ac1 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 80:8e73be2a2ac1 668 return(result);
emilmont 80:8e73be2a2ac1 669 }
emilmont 80:8e73be2a2ac1 670
emilmont 80:8e73be2a2ac1 671
emilmont 80:8e73be2a2ac1 672 /** \brief STR Exclusive (8 bit)
emilmont 80:8e73be2a2ac1 673
Kojto 110:165afa46840b 674 This function executes a exclusive STR instruction for 8 bit values.
emilmont 80:8e73be2a2ac1 675
emilmont 80:8e73be2a2ac1 676 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 677 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 678 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 679 \return 1 Function failed
emilmont 80:8e73be2a2ac1 680 */
Kojto 110:165afa46840b 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 80:8e73be2a2ac1 682 {
emilmont 80:8e73be2a2ac1 683 uint32_t result;
emilmont 80:8e73be2a2ac1 684
Kojto 110:165afa46840b 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
emilmont 80:8e73be2a2ac1 686 return(result);
emilmont 80:8e73be2a2ac1 687 }
emilmont 80:8e73be2a2ac1 688
emilmont 80:8e73be2a2ac1 689
emilmont 80:8e73be2a2ac1 690 /** \brief STR Exclusive (16 bit)
emilmont 80:8e73be2a2ac1 691
Kojto 110:165afa46840b 692 This function executes a exclusive STR instruction for 16 bit values.
emilmont 80:8e73be2a2ac1 693
emilmont 80:8e73be2a2ac1 694 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 695 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 696 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 697 \return 1 Function failed
emilmont 80:8e73be2a2ac1 698 */
Kojto 110:165afa46840b 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 80:8e73be2a2ac1 700 {
emilmont 80:8e73be2a2ac1 701 uint32_t result;
emilmont 80:8e73be2a2ac1 702
Kojto 110:165afa46840b 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
emilmont 80:8e73be2a2ac1 704 return(result);
emilmont 80:8e73be2a2ac1 705 }
emilmont 80:8e73be2a2ac1 706
emilmont 80:8e73be2a2ac1 707
emilmont 80:8e73be2a2ac1 708 /** \brief STR Exclusive (32 bit)
emilmont 80:8e73be2a2ac1 709
Kojto 110:165afa46840b 710 This function executes a exclusive STR instruction for 32 bit values.
emilmont 80:8e73be2a2ac1 711
emilmont 80:8e73be2a2ac1 712 \param [in] value Value to store
emilmont 80:8e73be2a2ac1 713 \param [in] ptr Pointer to location
emilmont 80:8e73be2a2ac1 714 \return 0 Function succeeded
emilmont 80:8e73be2a2ac1 715 \return 1 Function failed
emilmont 80:8e73be2a2ac1 716 */
Kojto 110:165afa46840b 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 80:8e73be2a2ac1 718 {
emilmont 80:8e73be2a2ac1 719 uint32_t result;
emilmont 80:8e73be2a2ac1 720
emilmont 80:8e73be2a2ac1 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 80:8e73be2a2ac1 722 return(result);
emilmont 80:8e73be2a2ac1 723 }
emilmont 80:8e73be2a2ac1 724
emilmont 80:8e73be2a2ac1 725
emilmont 80:8e73be2a2ac1 726 /** \brief Remove the exclusive lock
emilmont 80:8e73be2a2ac1 727
emilmont 80:8e73be2a2ac1 728 This function removes the exclusive lock which is created by LDREX.
emilmont 80:8e73be2a2ac1 729
emilmont 80:8e73be2a2ac1 730 */
Kojto 110:165afa46840b 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
emilmont 80:8e73be2a2ac1 732 {
emilmont 80:8e73be2a2ac1 733 __ASM volatile ("clrex" ::: "memory");
emilmont 80:8e73be2a2ac1 734 }
emilmont 80:8e73be2a2ac1 735
emilmont 80:8e73be2a2ac1 736
emilmont 80:8e73be2a2ac1 737 /** \brief Signed Saturate
emilmont 80:8e73be2a2ac1 738
emilmont 80:8e73be2a2ac1 739 This function saturates a signed value.
emilmont 80:8e73be2a2ac1 740
emilmont 80:8e73be2a2ac1 741 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 742 \param [in] sat Bit position to saturate to (1..32)
emilmont 80:8e73be2a2ac1 743 \return Saturated value
emilmont 80:8e73be2a2ac1 744 */
emilmont 80:8e73be2a2ac1 745 #define __SSAT(ARG1,ARG2) \
emilmont 80:8e73be2a2ac1 746 ({ \
emilmont 80:8e73be2a2ac1 747 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 80:8e73be2a2ac1 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 80:8e73be2a2ac1 749 __RES; \
emilmont 80:8e73be2a2ac1 750 })
emilmont 80:8e73be2a2ac1 751
emilmont 80:8e73be2a2ac1 752
emilmont 80:8e73be2a2ac1 753 /** \brief Unsigned Saturate
emilmont 80:8e73be2a2ac1 754
emilmont 80:8e73be2a2ac1 755 This function saturates an unsigned value.
emilmont 80:8e73be2a2ac1 756
emilmont 80:8e73be2a2ac1 757 \param [in] value Value to be saturated
emilmont 80:8e73be2a2ac1 758 \param [in] sat Bit position to saturate to (0..31)
emilmont 80:8e73be2a2ac1 759 \return Saturated value
emilmont 80:8e73be2a2ac1 760 */
emilmont 80:8e73be2a2ac1 761 #define __USAT(ARG1,ARG2) \
emilmont 80:8e73be2a2ac1 762 ({ \
emilmont 80:8e73be2a2ac1 763 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 80:8e73be2a2ac1 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 80:8e73be2a2ac1 765 __RES; \
emilmont 80:8e73be2a2ac1 766 })
emilmont 80:8e73be2a2ac1 767
emilmont 80:8e73be2a2ac1 768
Kojto 110:165afa46840b 769 /** \brief Rotate Right with Extend (32 bit)
emilmont 80:8e73be2a2ac1 770
Kojto 110:165afa46840b 771 This function moves each bit of a bitstring right by one bit.
Kojto 110:165afa46840b 772 The carry input is shifted in at the left end of the bitstring.
emilmont 80:8e73be2a2ac1 773
Kojto 110:165afa46840b 774 \param [in] value Value to rotate
Kojto 110:165afa46840b 775 \return Rotated value
emilmont 80:8e73be2a2ac1 776 */
Kojto 110:165afa46840b 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
emilmont 80:8e73be2a2ac1 778 {
Kojto 110:165afa46840b 779 uint32_t result;
emilmont 80:8e73be2a2ac1 780
Kojto 110:165afa46840b 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 80:8e73be2a2ac1 782 return(result);
emilmont 80:8e73be2a2ac1 783 }
emilmont 80:8e73be2a2ac1 784
Kojto 110:165afa46840b 785
Kojto 110:165afa46840b 786 /** \brief LDRT Unprivileged (8 bit)
Kojto 110:165afa46840b 787
Kojto 110:165afa46840b 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
Kojto 110:165afa46840b 789
Kojto 110:165afa46840b 790 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 791 \return value of type uint8_t at (*ptr)
Kojto 110:165afa46840b 792 */
Kojto 110:165afa46840b 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
Kojto 110:165afa46840b 794 {
Kojto 110:165afa46840b 795 uint32_t result;
Kojto 110:165afa46840b 796
Kojto 110:165afa46840b 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Kojto 110:165afa46840b 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
Kojto 110:165afa46840b 799 #else
Kojto 110:165afa46840b 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Kojto 110:165afa46840b 801 accepted by assembler. So has to use following less efficient pattern.
Kojto 110:165afa46840b 802 */
Kojto 110:165afa46840b 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Kojto 110:165afa46840b 804 #endif
Kojto 110:165afa46840b 805 return ((uint8_t) result); /* Add explicit type cast here */
Kojto 110:165afa46840b 806 }
Kojto 110:165afa46840b 807
Kojto 110:165afa46840b 808
Kojto 110:165afa46840b 809 /** \brief LDRT Unprivileged (16 bit)
Kojto 110:165afa46840b 810
Kojto 110:165afa46840b 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
Kojto 110:165afa46840b 812
Kojto 110:165afa46840b 813 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 814 \return value of type uint16_t at (*ptr)
Kojto 110:165afa46840b 815 */
Kojto 110:165afa46840b 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
Kojto 110:165afa46840b 817 {
Kojto 110:165afa46840b 818 uint32_t result;
Kojto 110:165afa46840b 819
Kojto 110:165afa46840b 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Kojto 110:165afa46840b 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
Kojto 110:165afa46840b 822 #else
Kojto 110:165afa46840b 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
Kojto 110:165afa46840b 824 accepted by assembler. So has to use following less efficient pattern.
Kojto 110:165afa46840b 825 */
Kojto 110:165afa46840b 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
Kojto 110:165afa46840b 827 #endif
Kojto 110:165afa46840b 828 return ((uint16_t) result); /* Add explicit type cast here */
Kojto 110:165afa46840b 829 }
emilmont 80:8e73be2a2ac1 830
emilmont 80:8e73be2a2ac1 831
Kojto 110:165afa46840b 832 /** \brief LDRT Unprivileged (32 bit)
Kojto 110:165afa46840b 833
Kojto 110:165afa46840b 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
Kojto 110:165afa46840b 835
Kojto 110:165afa46840b 836 \param [in] ptr Pointer to data
Kojto 110:165afa46840b 837 \return value of type uint32_t at (*ptr)
Kojto 110:165afa46840b 838 */
Kojto 110:165afa46840b 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
Kojto 110:165afa46840b 840 {
Kojto 110:165afa46840b 841 uint32_t result;
Kojto 110:165afa46840b 842
Kojto 110:165afa46840b 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
Kojto 110:165afa46840b 844 return(result);
Kojto 110:165afa46840b 845 }
Kojto 110:165afa46840b 846
Kojto 110:165afa46840b 847
Kojto 110:165afa46840b 848 /** \brief STRT Unprivileged (8 bit)
Kojto 110:165afa46840b 849
Kojto 110:165afa46840b 850 This function executes a Unprivileged STRT instruction for 8 bit values.
Kojto 110:165afa46840b 851
Kojto 110:165afa46840b 852 \param [in] value Value to store
Kojto 110:165afa46840b 853 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 854 */
Kojto 110:165afa46840b 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
Kojto 110:165afa46840b 856 {
Kojto 110:165afa46840b 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
Kojto 110:165afa46840b 858 }
Kojto 110:165afa46840b 859
Kojto 110:165afa46840b 860
Kojto 110:165afa46840b 861 /** \brief STRT Unprivileged (16 bit)
Kojto 110:165afa46840b 862
Kojto 110:165afa46840b 863 This function executes a Unprivileged STRT instruction for 16 bit values.
Kojto 110:165afa46840b 864
Kojto 110:165afa46840b 865 \param [in] value Value to store
Kojto 110:165afa46840b 866 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 867 */
Kojto 110:165afa46840b 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
Kojto 110:165afa46840b 869 {
Kojto 110:165afa46840b 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
Kojto 110:165afa46840b 871 }
Kojto 110:165afa46840b 872
Kojto 110:165afa46840b 873
Kojto 110:165afa46840b 874 /** \brief STRT Unprivileged (32 bit)
Kojto 110:165afa46840b 875
Kojto 110:165afa46840b 876 This function executes a Unprivileged STRT instruction for 32 bit values.
Kojto 110:165afa46840b 877
Kojto 110:165afa46840b 878 \param [in] value Value to store
Kojto 110:165afa46840b 879 \param [in] ptr Pointer to location
Kojto 110:165afa46840b 880 */
Kojto 110:165afa46840b 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
Kojto 110:165afa46840b 882 {
Kojto 110:165afa46840b 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
Kojto 110:165afa46840b 884 }
Kojto 110:165afa46840b 885
Kojto 110:165afa46840b 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
Kojto 110:165afa46840b 887
Kojto 110:165afa46840b 888
Kojto 110:165afa46840b 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Kojto 110:165afa46840b 890 /* IAR iccarm specific functions */
Kojto 110:165afa46840b 891 #include <cmsis_iar.h>
Kojto 110:165afa46840b 892
Kojto 110:165afa46840b 893
Kojto 110:165afa46840b 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Kojto 110:165afa46840b 895 /* TI CCS specific functions */
Kojto 110:165afa46840b 896 #include <cmsis_ccs.h>
emilmont 80:8e73be2a2ac1 897
emilmont 80:8e73be2a2ac1 898
emilmont 80:8e73be2a2ac1 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 80:8e73be2a2ac1 900 /* TASKING carm specific functions */
emilmont 80:8e73be2a2ac1 901 /*
emilmont 80:8e73be2a2ac1 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 80:8e73be2a2ac1 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 80:8e73be2a2ac1 904 * Including the CMSIS ones.
emilmont 80:8e73be2a2ac1 905 */
emilmont 80:8e73be2a2ac1 906
Kojto 110:165afa46840b 907
Kojto 110:165afa46840b 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
Kojto 110:165afa46840b 909 /* Cosmic specific functions */
Kojto 110:165afa46840b 910 #include <cmsis_csm.h>
Kojto 110:165afa46840b 911
emilmont 80:8e73be2a2ac1 912 #endif
emilmont 80:8e73be2a2ac1 913
emilmont 80:8e73be2a2ac1 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 80:8e73be2a2ac1 915
emilmont 80:8e73be2a2ac1 916 #endif /* __CORE_CMINSTR_H */