mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51822/core_cm0plus.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cm0plus.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #if defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 80:8e73be2a2ac1 40 #endif
emilmont 80:8e73be2a2ac1 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 80:8e73be2a2ac1 45 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 46 extern "C" {
emilmont 80:8e73be2a2ac1 47 #endif
emilmont 80:8e73be2a2ac1 48
emilmont 80:8e73be2a2ac1 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 80:8e73be2a2ac1 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 80:8e73be2a2ac1 51
emilmont 80:8e73be2a2ac1 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 80:8e73be2a2ac1 53 Function definitions in header files are used to allow 'inlining'.
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 80:8e73be2a2ac1 56 Unions are used for effective representation of core registers.
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 80:8e73be2a2ac1 59 Function-like macros are used to allow more efficient code.
emilmont 80:8e73be2a2ac1 60 */
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /*******************************************************************************
emilmont 80:8e73be2a2ac1 64 * CMSIS definitions
emilmont 80:8e73be2a2ac1 65 ******************************************************************************/
emilmont 80:8e73be2a2ac1 66 /** \ingroup Cortex-M0+
emilmont 80:8e73be2a2ac1 67 @{
emilmont 80:8e73be2a2ac1 68 */
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 80:8e73be2a2ac1 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emilmont 80:8e73be2a2ac1 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 80:8e73be2a2ac1 75
emilmont 80:8e73be2a2ac1 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 82 #define __STATIC_INLINE static __inline
emilmont 80:8e73be2a2ac1 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 80:8e73be2a2ac1 89 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 80:8e73be2a2ac1 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 80:8e73be2a2ac1 92 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 80:8e73be2a2ac1 96 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 97
emilmont 80:8e73be2a2ac1 98 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 101 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 80:8e73be2a2ac1 109 #endif
emilmont 80:8e73be2a2ac1 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
emilmont 80:8e73be2a2ac1 113 */
emilmont 80:8e73be2a2ac1 114 #define __FPU_USED 0
emilmont 80:8e73be2a2ac1 115
emilmont 80:8e73be2a2ac1 116 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 117 #if defined __TARGET_FPU_VFP
emilmont 80:8e73be2a2ac1 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 119 #endif
emilmont 80:8e73be2a2ac1 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
emilmont 80:8e73be2a2ac1 126 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 127 #if defined __ARMVFP__
emilmont 80:8e73be2a2ac1 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 129 #endif
emilmont 80:8e73be2a2ac1 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
emilmont 80:8e73be2a2ac1 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 134 #endif
emilmont 80:8e73be2a2ac1 135
emilmont 80:8e73be2a2ac1 136 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 137 #if defined __FPU_VFP__
emilmont 80:8e73be2a2ac1 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
emilmont 80:8e73be2a2ac1 145 #endif
emilmont 80:8e73be2a2ac1 146
emilmont 80:8e73be2a2ac1 147 #include <stdint.h> /* standard types definitions */
emilmont 80:8e73be2a2ac1 148 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 80:8e73be2a2ac1 149 #include <core_cmFunc.h> /* Core Function Access */
emilmont 80:8e73be2a2ac1 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
emilmont 80:8e73be2a2ac1 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
emilmont 80:8e73be2a2ac1 156
emilmont 80:8e73be2a2ac1 157 #ifndef __CMSIS_GENERIC
emilmont 80:8e73be2a2ac1 158
emilmont 80:8e73be2a2ac1 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emilmont 80:8e73be2a2ac1 160 #define __CORE_CM0PLUS_H_DEPENDANT
emilmont 80:8e73be2a2ac1 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
emilmont 80:8e73be2a2ac1 166 /* check device defines and use defaults */
emilmont 80:8e73be2a2ac1 167 #if defined __CHECK_DEVICE_DEFINES
emilmont 80:8e73be2a2ac1 168 #ifndef __CM0PLUS_REV
emilmont 80:8e73be2a2ac1 169 #define __CM0PLUS_REV 0x0000
emilmont 80:8e73be2a2ac1 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 171 #endif
emilmont 80:8e73be2a2ac1 172
emilmont 80:8e73be2a2ac1 173 #ifndef __MPU_PRESENT
emilmont 80:8e73be2a2ac1 174 #define __MPU_PRESENT 0
emilmont 80:8e73be2a2ac1 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 176 #endif
emilmont 80:8e73be2a2ac1 177
emilmont 80:8e73be2a2ac1 178 #ifndef __VTOR_PRESENT
emilmont 80:8e73be2a2ac1 179 #define __VTOR_PRESENT 0
emilmont 80:8e73be2a2ac1 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 181 #endif
emilmont 80:8e73be2a2ac1 182
emilmont 80:8e73be2a2ac1 183 #ifndef __NVIC_PRIO_BITS
emilmont 80:8e73be2a2ac1 184 #define __NVIC_PRIO_BITS 2
emilmont 80:8e73be2a2ac1 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 186 #endif
emilmont 80:8e73be2a2ac1 187
emilmont 80:8e73be2a2ac1 188 #ifndef __Vendor_SysTickConfig
emilmont 80:8e73be2a2ac1 189 #define __Vendor_SysTickConfig 0
emilmont 80:8e73be2a2ac1 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 191 #endif
emilmont 80:8e73be2a2ac1 192 #endif
emilmont 80:8e73be2a2ac1 193
emilmont 80:8e73be2a2ac1 194 /* IO definitions (access restrictions to peripheral registers) */
emilmont 80:8e73be2a2ac1 195 /**
emilmont 80:8e73be2a2ac1 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 80:8e73be2a2ac1 197
emilmont 80:8e73be2a2ac1 198 <strong>IO Type Qualifiers</strong> are used
emilmont 80:8e73be2a2ac1 199 \li to specify the access to peripheral variables.
emilmont 80:8e73be2a2ac1 200 \li for automatic generation of peripheral register debug information.
emilmont 80:8e73be2a2ac1 201 */
emilmont 80:8e73be2a2ac1 202 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 203 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 204 #else
emilmont 80:8e73be2a2ac1 205 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 206 #endif
emilmont 80:8e73be2a2ac1 207 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 80:8e73be2a2ac1 208 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 80:8e73be2a2ac1 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
emilmont 80:8e73be2a2ac1 218 /*@} end of group Cortex-M0+ */
emilmont 80:8e73be2a2ac1 219
emilmont 80:8e73be2a2ac1 220
emilmont 80:8e73be2a2ac1 221
emilmont 80:8e73be2a2ac1 222 /*******************************************************************************
emilmont 80:8e73be2a2ac1 223 * Register Abstraction
emilmont 80:8e73be2a2ac1 224 Core Register contain:
emilmont 80:8e73be2a2ac1 225 - Core Register
emilmont 80:8e73be2a2ac1 226 - Core NVIC Register
emilmont 80:8e73be2a2ac1 227 - Core SCB Register
emilmont 80:8e73be2a2ac1 228 - Core SysTick Register
emilmont 80:8e73be2a2ac1 229 - Core MPU Register
emilmont 80:8e73be2a2ac1 230 ******************************************************************************/
emilmont 80:8e73be2a2ac1 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 80:8e73be2a2ac1 232 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 80:8e73be2a2ac1 233 */
emilmont 80:8e73be2a2ac1 234
emilmont 80:8e73be2a2ac1 235 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 236 \defgroup CMSIS_CORE Status and Control Registers
emilmont 80:8e73be2a2ac1 237 \brief Core Register type definitions.
emilmont 80:8e73be2a2ac1 238 @{
emilmont 80:8e73be2a2ac1 239 */
emilmont 80:8e73be2a2ac1 240
emilmont 80:8e73be2a2ac1 241 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 80:8e73be2a2ac1 242 */
emilmont 80:8e73be2a2ac1 243 typedef union
emilmont 80:8e73be2a2ac1 244 {
emilmont 80:8e73be2a2ac1 245 struct
emilmont 80:8e73be2a2ac1 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
emilmont 80:8e73be2a2ac1 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 252 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 253 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 254 } APSR_Type;
emilmont 80:8e73be2a2ac1 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 80:8e73be2a2ac1 271 */
emilmont 80:8e73be2a2ac1 272 typedef union
emilmont 80:8e73be2a2ac1 273 {
emilmont 80:8e73be2a2ac1 274 struct
emilmont 80:8e73be2a2ac1 275 {
emilmont 80:8e73be2a2ac1 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 80:8e73be2a2ac1 278 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 279 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 280 } IPSR_Type;
emilmont 80:8e73be2a2ac1 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
emilmont 80:8e73be2a2ac1 286
emilmont 80:8e73be2a2ac1 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 80:8e73be2a2ac1 288 */
emilmont 80:8e73be2a2ac1 289 typedef union
emilmont 80:8e73be2a2ac1 290 {
emilmont 80:8e73be2a2ac1 291 struct
emilmont 80:8e73be2a2ac1 292 {
emilmont 80:8e73be2a2ac1 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 80:8e73be2a2ac1 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
emilmont 80:8e73be2a2ac1 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 301 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 302 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 303 } xPSR_Type;
emilmont 80:8e73be2a2ac1 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
emilmont 80:8e73be2a2ac1 324
emilmont 80:8e73be2a2ac1 325 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 80:8e73be2a2ac1 326 */
emilmont 80:8e73be2a2ac1 327 typedef union
emilmont 80:8e73be2a2ac1 328 {
emilmont 80:8e73be2a2ac1 329 struct
emilmont 80:8e73be2a2ac1 330 {
emilmont 80:8e73be2a2ac1 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 80:8e73be2a2ac1 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
emilmont 80:8e73be2a2ac1 334 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 335 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 336 } CONTROL_Type;
emilmont 80:8e73be2a2ac1 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
emilmont 80:8e73be2a2ac1 345 /*@} end of group CMSIS_CORE */
emilmont 80:8e73be2a2ac1 346
emilmont 80:8e73be2a2ac1 347
emilmont 80:8e73be2a2ac1 348 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 80:8e73be2a2ac1 350 \brief Type definitions for the NVIC Registers
emilmont 80:8e73be2a2ac1 351 @{
emilmont 80:8e73be2a2ac1 352 */
emilmont 80:8e73be2a2ac1 353
emilmont 80:8e73be2a2ac1 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 80:8e73be2a2ac1 355 */
emilmont 80:8e73be2a2ac1 356 typedef struct
emilmont 80:8e73be2a2ac1 357 {
emilmont 80:8e73be2a2ac1 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 80:8e73be2a2ac1 359 uint32_t RESERVED0[31];
emilmont 80:8e73be2a2ac1 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 80:8e73be2a2ac1 361 uint32_t RSERVED1[31];
emilmont 80:8e73be2a2ac1 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 80:8e73be2a2ac1 363 uint32_t RESERVED2[31];
emilmont 80:8e73be2a2ac1 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 80:8e73be2a2ac1 365 uint32_t RESERVED3[31];
emilmont 80:8e73be2a2ac1 366 uint32_t RESERVED4[64];
emilmont 80:8e73be2a2ac1 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 80:8e73be2a2ac1 368 } NVIC_Type;
emilmont 80:8e73be2a2ac1 369
emilmont 80:8e73be2a2ac1 370 /*@} end of group CMSIS_NVIC */
emilmont 80:8e73be2a2ac1 371
emilmont 80:8e73be2a2ac1 372
emilmont 80:8e73be2a2ac1 373 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 374 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 80:8e73be2a2ac1 375 \brief Type definitions for the System Control Block Registers
emilmont 80:8e73be2a2ac1 376 @{
emilmont 80:8e73be2a2ac1 377 */
emilmont 80:8e73be2a2ac1 378
emilmont 80:8e73be2a2ac1 379 /** \brief Structure type to access the System Control Block (SCB).
emilmont 80:8e73be2a2ac1 380 */
emilmont 80:8e73be2a2ac1 381 typedef struct
emilmont 80:8e73be2a2ac1 382 {
emilmont 80:8e73be2a2ac1 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 80:8e73be2a2ac1 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 80:8e73be2a2ac1 385 #if (__VTOR_PRESENT == 1)
emilmont 80:8e73be2a2ac1 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 80:8e73be2a2ac1 387 #else
emilmont 80:8e73be2a2ac1 388 uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 389 #endif
emilmont 80:8e73be2a2ac1 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 80:8e73be2a2ac1 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 80:8e73be2a2ac1 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 80:8e73be2a2ac1 393 uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 80:8e73be2a2ac1 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 80:8e73be2a2ac1 396 } SCB_Type;
emilmont 80:8e73be2a2ac1 397
emilmont 80:8e73be2a2ac1 398 /* SCB CPUID Register Definitions */
emilmont 80:8e73be2a2ac1 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 80:8e73be2a2ac1 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 80:8e73be2a2ac1 401
emilmont 80:8e73be2a2ac1 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 80:8e73be2a2ac1 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 80:8e73be2a2ac1 404
emilmont 80:8e73be2a2ac1 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 80:8e73be2a2ac1 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 80:8e73be2a2ac1 407
emilmont 80:8e73be2a2ac1 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 80:8e73be2a2ac1 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 80:8e73be2a2ac1 410
emilmont 80:8e73be2a2ac1 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 80:8e73be2a2ac1 413
emilmont 80:8e73be2a2ac1 414 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 80:8e73be2a2ac1 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 80:8e73be2a2ac1 417
emilmont 80:8e73be2a2ac1 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 80:8e73be2a2ac1 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 80:8e73be2a2ac1 420
emilmont 80:8e73be2a2ac1 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 80:8e73be2a2ac1 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 80:8e73be2a2ac1 423
emilmont 80:8e73be2a2ac1 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 80:8e73be2a2ac1 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 80:8e73be2a2ac1 426
emilmont 80:8e73be2a2ac1 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 80:8e73be2a2ac1 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 80:8e73be2a2ac1 429
emilmont 80:8e73be2a2ac1 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 80:8e73be2a2ac1 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 80:8e73be2a2ac1 432
emilmont 80:8e73be2a2ac1 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 80:8e73be2a2ac1 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 80:8e73be2a2ac1 435
emilmont 80:8e73be2a2ac1 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 80:8e73be2a2ac1 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 80:8e73be2a2ac1 438
emilmont 80:8e73be2a2ac1 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 80:8e73be2a2ac1 441
emilmont 80:8e73be2a2ac1 442 #if (__VTOR_PRESENT == 1)
emilmont 80:8e73be2a2ac1 443 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
emilmont 80:8e73be2a2ac1 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 80:8e73be2a2ac1 446 #endif
emilmont 80:8e73be2a2ac1 447
emilmont 80:8e73be2a2ac1 448 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 80:8e73be2a2ac1 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 80:8e73be2a2ac1 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 80:8e73be2a2ac1 451
emilmont 80:8e73be2a2ac1 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 80:8e73be2a2ac1 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 80:8e73be2a2ac1 454
emilmont 80:8e73be2a2ac1 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 80:8e73be2a2ac1 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 80:8e73be2a2ac1 457
emilmont 80:8e73be2a2ac1 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 80:8e73be2a2ac1 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 80:8e73be2a2ac1 460
emilmont 80:8e73be2a2ac1 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 80:8e73be2a2ac1 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 80:8e73be2a2ac1 463
emilmont 80:8e73be2a2ac1 464 /* SCB System Control Register Definitions */
emilmont 80:8e73be2a2ac1 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 80:8e73be2a2ac1 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 80:8e73be2a2ac1 467
emilmont 80:8e73be2a2ac1 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 80:8e73be2a2ac1 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 80:8e73be2a2ac1 470
emilmont 80:8e73be2a2ac1 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 80:8e73be2a2ac1 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 80:8e73be2a2ac1 473
emilmont 80:8e73be2a2ac1 474 /* SCB Configuration Control Register Definitions */
emilmont 80:8e73be2a2ac1 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 80:8e73be2a2ac1 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 80:8e73be2a2ac1 477
emilmont 80:8e73be2a2ac1 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 80:8e73be2a2ac1 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 80:8e73be2a2ac1 480
emilmont 80:8e73be2a2ac1 481 /* SCB System Handler Control and State Register Definitions */
emilmont 80:8e73be2a2ac1 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 80:8e73be2a2ac1 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 80:8e73be2a2ac1 484
emilmont 80:8e73be2a2ac1 485 /*@} end of group CMSIS_SCB */
emilmont 80:8e73be2a2ac1 486
emilmont 80:8e73be2a2ac1 487
emilmont 80:8e73be2a2ac1 488 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 80:8e73be2a2ac1 490 \brief Type definitions for the System Timer Registers.
emilmont 80:8e73be2a2ac1 491 @{
emilmont 80:8e73be2a2ac1 492 */
emilmont 80:8e73be2a2ac1 493
emilmont 80:8e73be2a2ac1 494 /** \brief Structure type to access the System Timer (SysTick).
emilmont 80:8e73be2a2ac1 495 */
emilmont 80:8e73be2a2ac1 496 typedef struct
emilmont 80:8e73be2a2ac1 497 {
emilmont 80:8e73be2a2ac1 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 80:8e73be2a2ac1 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 80:8e73be2a2ac1 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 80:8e73be2a2ac1 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 80:8e73be2a2ac1 502 } SysTick_Type;
emilmont 80:8e73be2a2ac1 503
emilmont 80:8e73be2a2ac1 504 /* SysTick Control / Status Register Definitions */
emilmont 80:8e73be2a2ac1 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 80:8e73be2a2ac1 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 80:8e73be2a2ac1 507
emilmont 80:8e73be2a2ac1 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 80:8e73be2a2ac1 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 80:8e73be2a2ac1 510
emilmont 80:8e73be2a2ac1 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 80:8e73be2a2ac1 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 80:8e73be2a2ac1 513
emilmont 80:8e73be2a2ac1 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 516
emilmont 80:8e73be2a2ac1 517 /* SysTick Reload Register Definitions */
emilmont 80:8e73be2a2ac1 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 80:8e73be2a2ac1 520
emilmont 80:8e73be2a2ac1 521 /* SysTick Current Register Definitions */
emilmont 80:8e73be2a2ac1 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 80:8e73be2a2ac1 524
emilmont 80:8e73be2a2ac1 525 /* SysTick Calibration Register Definitions */
emilmont 80:8e73be2a2ac1 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 80:8e73be2a2ac1 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 80:8e73be2a2ac1 528
emilmont 80:8e73be2a2ac1 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 80:8e73be2a2ac1 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 80:8e73be2a2ac1 531
emilmont 80:8e73be2a2ac1 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 80:8e73be2a2ac1 534
emilmont 80:8e73be2a2ac1 535 /*@} end of group CMSIS_SysTick */
emilmont 80:8e73be2a2ac1 536
emilmont 80:8e73be2a2ac1 537 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 538 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 540 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 541 @{
emilmont 80:8e73be2a2ac1 542 */
emilmont 80:8e73be2a2ac1 543
emilmont 80:8e73be2a2ac1 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 80:8e73be2a2ac1 545 */
emilmont 80:8e73be2a2ac1 546 typedef struct
emilmont 80:8e73be2a2ac1 547 {
emilmont 80:8e73be2a2ac1 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 80:8e73be2a2ac1 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 80:8e73be2a2ac1 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 80:8e73be2a2ac1 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 553 } MPU_Type;
emilmont 80:8e73be2a2ac1 554
emilmont 80:8e73be2a2ac1 555 /* MPU Type Register */
emilmont 80:8e73be2a2ac1 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 80:8e73be2a2ac1 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 80:8e73be2a2ac1 558
emilmont 80:8e73be2a2ac1 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 80:8e73be2a2ac1 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 80:8e73be2a2ac1 561
emilmont 80:8e73be2a2ac1 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
emilmont 80:8e73be2a2ac1 564
emilmont 80:8e73be2a2ac1 565 /* MPU Control Register */
emilmont 80:8e73be2a2ac1 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 80:8e73be2a2ac1 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 80:8e73be2a2ac1 568
emilmont 80:8e73be2a2ac1 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 80:8e73be2a2ac1 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 80:8e73be2a2ac1 571
emilmont 80:8e73be2a2ac1 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 574
emilmont 80:8e73be2a2ac1 575 /* MPU Region Number Register */
emilmont 80:8e73be2a2ac1 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
emilmont 80:8e73be2a2ac1 578
emilmont 80:8e73be2a2ac1 579 /* MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emilmont 80:8e73be2a2ac1 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 80:8e73be2a2ac1 582
emilmont 80:8e73be2a2ac1 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 80:8e73be2a2ac1 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 80:8e73be2a2ac1 585
emilmont 80:8e73be2a2ac1 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
emilmont 80:8e73be2a2ac1 588
emilmont 80:8e73be2a2ac1 589 /* MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 80:8e73be2a2ac1 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 80:8e73be2a2ac1 592
emilmont 80:8e73be2a2ac1 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 80:8e73be2a2ac1 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 80:8e73be2a2ac1 595
emilmont 80:8e73be2a2ac1 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 80:8e73be2a2ac1 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 80:8e73be2a2ac1 598
emilmont 80:8e73be2a2ac1 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 80:8e73be2a2ac1 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 80:8e73be2a2ac1 601
emilmont 80:8e73be2a2ac1 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 80:8e73be2a2ac1 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 80:8e73be2a2ac1 604
emilmont 80:8e73be2a2ac1 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 80:8e73be2a2ac1 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 80:8e73be2a2ac1 607
emilmont 80:8e73be2a2ac1 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 80:8e73be2a2ac1 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 80:8e73be2a2ac1 610
emilmont 80:8e73be2a2ac1 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 80:8e73be2a2ac1 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 80:8e73be2a2ac1 613
emilmont 80:8e73be2a2ac1 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 80:8e73be2a2ac1 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 80:8e73be2a2ac1 616
emilmont 80:8e73be2a2ac1 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 80:8e73be2a2ac1 619
emilmont 80:8e73be2a2ac1 620 /*@} end of group CMSIS_MPU */
emilmont 80:8e73be2a2ac1 621 #endif
emilmont 80:8e73be2a2ac1 622
emilmont 80:8e73be2a2ac1 623
emilmont 80:8e73be2a2ac1 624 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 80:8e73be2a2ac1 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 80:8e73be2a2ac1 627 are only accessible over DAP and not via processor. Therefore
emilmont 80:8e73be2a2ac1 628 they are not covered by the Cortex-M0 header file.
emilmont 80:8e73be2a2ac1 629 @{
emilmont 80:8e73be2a2ac1 630 */
emilmont 80:8e73be2a2ac1 631 /*@} end of group CMSIS_CoreDebug */
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633
emilmont 80:8e73be2a2ac1 634 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 635 \defgroup CMSIS_core_base Core Definitions
emilmont 80:8e73be2a2ac1 636 \brief Definitions for base addresses, unions, and structures.
emilmont 80:8e73be2a2ac1 637 @{
emilmont 80:8e73be2a2ac1 638 */
emilmont 80:8e73be2a2ac1 639
emilmont 80:8e73be2a2ac1 640 /* Memory mapping of Cortex-M0+ Hardware */
emilmont 80:8e73be2a2ac1 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 80:8e73be2a2ac1 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 80:8e73be2a2ac1 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 80:8e73be2a2ac1 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 80:8e73be2a2ac1 645
emilmont 80:8e73be2a2ac1 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 80:8e73be2a2ac1 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 80:8e73be2a2ac1 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 80:8e73be2a2ac1 649
emilmont 80:8e73be2a2ac1 650 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 653 #endif
emilmont 80:8e73be2a2ac1 654
emilmont 80:8e73be2a2ac1 655 /*@} */
emilmont 80:8e73be2a2ac1 656
emilmont 80:8e73be2a2ac1 657
emilmont 80:8e73be2a2ac1 658
emilmont 80:8e73be2a2ac1 659 /*******************************************************************************
emilmont 80:8e73be2a2ac1 660 * Hardware Abstraction Layer
emilmont 80:8e73be2a2ac1 661 Core Function Interface contains:
emilmont 80:8e73be2a2ac1 662 - Core NVIC Functions
emilmont 80:8e73be2a2ac1 663 - Core SysTick Functions
emilmont 80:8e73be2a2ac1 664 - Core Register Access Functions
emilmont 80:8e73be2a2ac1 665 ******************************************************************************/
emilmont 80:8e73be2a2ac1 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 80:8e73be2a2ac1 667 */
emilmont 80:8e73be2a2ac1 668
emilmont 80:8e73be2a2ac1 669
emilmont 80:8e73be2a2ac1 670
emilmont 80:8e73be2a2ac1 671 /* ########################## NVIC functions #################################### */
emilmont 80:8e73be2a2ac1 672 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 80:8e73be2a2ac1 674 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 80:8e73be2a2ac1 675 @{
emilmont 80:8e73be2a2ac1 676 */
emilmont 80:8e73be2a2ac1 677
emilmont 80:8e73be2a2ac1 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 80:8e73be2a2ac1 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
emilmont 80:8e73be2a2ac1 683
emilmont 80:8e73be2a2ac1 684
emilmont 80:8e73be2a2ac1 685 /** \brief Enable External Interrupt
emilmont 80:8e73be2a2ac1 686
emilmont 80:8e73be2a2ac1 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 688
emilmont 80:8e73be2a2ac1 689 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 690 */
emilmont 80:8e73be2a2ac1 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 694 }
emilmont 80:8e73be2a2ac1 695
emilmont 80:8e73be2a2ac1 696
emilmont 80:8e73be2a2ac1 697 /** \brief Disable External Interrupt
emilmont 80:8e73be2a2ac1 698
emilmont 80:8e73be2a2ac1 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 700
emilmont 80:8e73be2a2ac1 701 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 702 */
emilmont 80:8e73be2a2ac1 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
emilmont 80:8e73be2a2ac1 708 }
emilmont 80:8e73be2a2ac1 709
emilmont 80:8e73be2a2ac1 710
emilmont 80:8e73be2a2ac1 711 /** \brief Get Pending Interrupt
emilmont 80:8e73be2a2ac1 712
emilmont 80:8e73be2a2ac1 713 The function reads the pending register in the NVIC and returns the pending bit
emilmont 80:8e73be2a2ac1 714 for the specified interrupt.
emilmont 80:8e73be2a2ac1 715
emilmont 80:8e73be2a2ac1 716 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 717
emilmont 80:8e73be2a2ac1 718 \return 0 Interrupt status is not pending.
emilmont 80:8e73be2a2ac1 719 \return 1 Interrupt status is pending.
emilmont 80:8e73be2a2ac1 720 */
emilmont 80:8e73be2a2ac1 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 80:8e73be2a2ac1 724 }
emilmont 80:8e73be2a2ac1 725
emilmont 80:8e73be2a2ac1 726
emilmont 80:8e73be2a2ac1 727 /** \brief Set Pending Interrupt
emilmont 80:8e73be2a2ac1 728
emilmont 80:8e73be2a2ac1 729 The function sets the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 730
emilmont 80:8e73be2a2ac1 731 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 732 */
emilmont 80:8e73be2a2ac1 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 736 }
emilmont 80:8e73be2a2ac1 737
emilmont 80:8e73be2a2ac1 738
emilmont 80:8e73be2a2ac1 739 /** \brief Clear Pending Interrupt
emilmont 80:8e73be2a2ac1 740
emilmont 80:8e73be2a2ac1 741 The function clears the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 742
emilmont 80:8e73be2a2ac1 743 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 744 */
emilmont 80:8e73be2a2ac1 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 748 }
emilmont 80:8e73be2a2ac1 749
emilmont 80:8e73be2a2ac1 750
emilmont 80:8e73be2a2ac1 751 /** \brief Set Interrupt Priority
emilmont 80:8e73be2a2ac1 752
emilmont 80:8e73be2a2ac1 753 The function sets the priority of an interrupt.
emilmont 80:8e73be2a2ac1 754
emilmont 80:8e73be2a2ac1 755 \note The priority cannot be set for every core interrupt.
emilmont 80:8e73be2a2ac1 756
emilmont 80:8e73be2a2ac1 757 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 758 \param [in] priority Priority to set.
emilmont 80:8e73be2a2ac1 759 */
emilmont 80:8e73be2a2ac1 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 80:8e73be2a2ac1 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
emilmont 80:8e73be2a2ac1 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
emilmont 80:8e73be2a2ac1 770 }
emilmont 80:8e73be2a2ac1 771
emilmont 80:8e73be2a2ac1 772
emilmont 80:8e73be2a2ac1 773 /** \brief Get Interrupt Priority
emilmont 80:8e73be2a2ac1 774
emilmont 80:8e73be2a2ac1 775 The function reads the priority of an interrupt. The interrupt
emilmont 80:8e73be2a2ac1 776 number can be positive to specify an external (device specific)
emilmont 80:8e73be2a2ac1 777 interrupt, or negative to specify an internal (core) interrupt.
emilmont 80:8e73be2a2ac1 778
emilmont 80:8e73be2a2ac1 779
emilmont 80:8e73be2a2ac1 780 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 781 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 80:8e73be2a2ac1 782 priority bits of the microcontroller.
emilmont 80:8e73be2a2ac1 783 */
emilmont 80:8e73be2a2ac1 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 785 {
emilmont 80:8e73be2a2ac1 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
emilmont 80:8e73be2a2ac1 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
emilmont 80:8e73be2a2ac1 793 }
emilmont 80:8e73be2a2ac1 794
emilmont 80:8e73be2a2ac1 795
emilmont 80:8e73be2a2ac1 796 /** \brief System Reset
emilmont 80:8e73be2a2ac1 797
emilmont 80:8e73be2a2ac1 798 The function initiates a system reset request to reset the MCU.
emilmont 80:8e73be2a2ac1 799 */
emilmont 80:8e73be2a2ac1 800 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 80:8e73be2a2ac1 801 {
emilmont 80:8e73be2a2ac1 802 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 80:8e73be2a2ac1 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
emilmont 80:8e73be2a2ac1 805 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 80:8e73be2a2ac1 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
emilmont 80:8e73be2a2ac1 808 }
emilmont 80:8e73be2a2ac1 809
emilmont 80:8e73be2a2ac1 810 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 80:8e73be2a2ac1 811
emilmont 80:8e73be2a2ac1 812
emilmont 80:8e73be2a2ac1 813
emilmont 80:8e73be2a2ac1 814 /* ################################## SysTick function ############################################ */
emilmont 80:8e73be2a2ac1 815 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 80:8e73be2a2ac1 817 \brief Functions that configure the System.
emilmont 80:8e73be2a2ac1 818 @{
emilmont 80:8e73be2a2ac1 819 */
emilmont 80:8e73be2a2ac1 820
emilmont 80:8e73be2a2ac1 821 #if (__Vendor_SysTickConfig == 0)
emilmont 80:8e73be2a2ac1 822
emilmont 80:8e73be2a2ac1 823 /** \brief System Tick Configuration
emilmont 80:8e73be2a2ac1 824
emilmont 80:8e73be2a2ac1 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 80:8e73be2a2ac1 826 Counter is in free running mode to generate periodic interrupts.
emilmont 80:8e73be2a2ac1 827
emilmont 80:8e73be2a2ac1 828 \param [in] ticks Number of ticks between two interrupts.
emilmont 80:8e73be2a2ac1 829
emilmont 80:8e73be2a2ac1 830 \return 0 Function succeeded.
emilmont 80:8e73be2a2ac1 831 \return 1 Function failed.
emilmont 80:8e73be2a2ac1 832
emilmont 80:8e73be2a2ac1 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 80:8e73be2a2ac1 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 80:8e73be2a2ac1 835 must contain a vendor-specific implementation of this function.
emilmont 80:8e73be2a2ac1 836
emilmont 80:8e73be2a2ac1 837 */
emilmont 80:8e73be2a2ac1 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 80:8e73be2a2ac1 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
emilmont 80:8e73be2a2ac1 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 80:8e73be2a2ac1 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 80:8e73be2a2ac1 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
emilmont 80:8e73be2a2ac1 849 }
emilmont 80:8e73be2a2ac1 850
emilmont 80:8e73be2a2ac1 851 #endif
emilmont 80:8e73be2a2ac1 852
emilmont 80:8e73be2a2ac1 853 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 80:8e73be2a2ac1 854
emilmont 80:8e73be2a2ac1 855
emilmont 80:8e73be2a2ac1 856
emilmont 80:8e73be2a2ac1 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
emilmont 80:8e73be2a2ac1 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emilmont 80:8e73be2a2ac1 863
emilmont 80:8e73be2a2ac1 864 #endif /* __CMSIS_GENERIC */