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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32625MBED/core_sc300.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 /**************************************************************************//**
<> 129:0ab6a29f35bf 2 * @file core_sc300.h
<> 129:0ab6a29f35bf 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
<> 129:0ab6a29f35bf 4 * @version V4.10
<> 129:0ab6a29f35bf 5 * @date 18. March 2015
<> 129:0ab6a29f35bf 6 *
<> 129:0ab6a29f35bf 7 * @note
<> 129:0ab6a29f35bf 8 *
<> 129:0ab6a29f35bf 9 ******************************************************************************/
<> 129:0ab6a29f35bf 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 129:0ab6a29f35bf 11
<> 129:0ab6a29f35bf 12 All rights reserved.
<> 129:0ab6a29f35bf 13 Redistribution and use in source and binary forms, with or without
<> 129:0ab6a29f35bf 14 modification, are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 15 - Redistributions of source code must retain the above copyright
<> 129:0ab6a29f35bf 16 notice, this list of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 17 - Redistributions in binary form must reproduce the above copyright
<> 129:0ab6a29f35bf 18 notice, this list of conditions and the following disclaimer in the
<> 129:0ab6a29f35bf 19 documentation and/or other materials provided with the distribution.
<> 129:0ab6a29f35bf 20 - Neither the name of ARM nor the names of its contributors may be used
<> 129:0ab6a29f35bf 21 to endorse or promote products derived from this software without
<> 129:0ab6a29f35bf 22 specific prior written permission.
<> 129:0ab6a29f35bf 23 *
<> 129:0ab6a29f35bf 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 129:0ab6a29f35bf 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 129:0ab6a29f35bf 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 129:0ab6a29f35bf 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 129:0ab6a29f35bf 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 129:0ab6a29f35bf 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 129:0ab6a29f35bf 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 129:0ab6a29f35bf 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 129:0ab6a29f35bf 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 129:0ab6a29f35bf 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 129:0ab6a29f35bf 34 POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 35 ---------------------------------------------------------------------------*/
<> 129:0ab6a29f35bf 36
<> 129:0ab6a29f35bf 37
<> 129:0ab6a29f35bf 38 #if defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 129:0ab6a29f35bf 40 #endif
<> 129:0ab6a29f35bf 41
<> 129:0ab6a29f35bf 42 #ifndef __CORE_SC300_H_GENERIC
<> 129:0ab6a29f35bf 43 #define __CORE_SC300_H_GENERIC
<> 129:0ab6a29f35bf 44
<> 129:0ab6a29f35bf 45 #ifdef __cplusplus
<> 129:0ab6a29f35bf 46 extern "C" {
<> 129:0ab6a29f35bf 47 #endif
<> 129:0ab6a29f35bf 48
<> 129:0ab6a29f35bf 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 129:0ab6a29f35bf 50 CMSIS violates the following MISRA-C:2004 rules:
<> 129:0ab6a29f35bf 51
<> 129:0ab6a29f35bf 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 129:0ab6a29f35bf 53 Function definitions in header files are used to allow 'inlining'.
<> 129:0ab6a29f35bf 54
<> 129:0ab6a29f35bf 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 129:0ab6a29f35bf 56 Unions are used for effective representation of core registers.
<> 129:0ab6a29f35bf 57
<> 129:0ab6a29f35bf 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 129:0ab6a29f35bf 59 Function-like macros are used to allow more efficient code.
<> 129:0ab6a29f35bf 60 */
<> 129:0ab6a29f35bf 61
<> 129:0ab6a29f35bf 62
<> 129:0ab6a29f35bf 63 /*******************************************************************************
<> 129:0ab6a29f35bf 64 * CMSIS definitions
<> 129:0ab6a29f35bf 65 ******************************************************************************/
<> 129:0ab6a29f35bf 66 /** \ingroup SC3000
<> 129:0ab6a29f35bf 67 @{
<> 129:0ab6a29f35bf 68 */
<> 129:0ab6a29f35bf 69
<> 129:0ab6a29f35bf 70 /* CMSIS SC300 definitions */
<> 129:0ab6a29f35bf 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 129:0ab6a29f35bf 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 129:0ab6a29f35bf 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
<> 129:0ab6a29f35bf 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 129:0ab6a29f35bf 75
<> 129:0ab6a29f35bf 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
<> 129:0ab6a29f35bf 77
<> 129:0ab6a29f35bf 78
<> 129:0ab6a29f35bf 79 #if defined ( __CC_ARM )
<> 129:0ab6a29f35bf 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 129:0ab6a29f35bf 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 129:0ab6a29f35bf 82 #define __STATIC_INLINE static __inline
<> 129:0ab6a29f35bf 83
<> 129:0ab6a29f35bf 84 #elif defined ( __GNUC__ )
<> 129:0ab6a29f35bf 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 129:0ab6a29f35bf 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 129:0ab6a29f35bf 87 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 88
<> 129:0ab6a29f35bf 89 #elif defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 129:0ab6a29f35bf 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 129:0ab6a29f35bf 92 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 93
<> 129:0ab6a29f35bf 94 #elif defined ( __TMS470__ )
<> 129:0ab6a29f35bf 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 129:0ab6a29f35bf 96 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 97
<> 129:0ab6a29f35bf 98 #elif defined ( __TASKING__ )
<> 129:0ab6a29f35bf 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 129:0ab6a29f35bf 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 129:0ab6a29f35bf 101 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 102
<> 129:0ab6a29f35bf 103 #elif defined ( __CSMC__ )
<> 129:0ab6a29f35bf 104 #define __packed
<> 129:0ab6a29f35bf 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 129:0ab6a29f35bf 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 129:0ab6a29f35bf 107 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 108
<> 129:0ab6a29f35bf 109 #endif
<> 129:0ab6a29f35bf 110
<> 129:0ab6a29f35bf 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 129:0ab6a29f35bf 112 This core does not support an FPU at all
<> 129:0ab6a29f35bf 113 */
<> 129:0ab6a29f35bf 114 #define __FPU_USED 0
<> 129:0ab6a29f35bf 115
<> 129:0ab6a29f35bf 116 #if defined ( __CC_ARM )
<> 129:0ab6a29f35bf 117 #if defined __TARGET_FPU_VFP
<> 129:0ab6a29f35bf 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 119 #endif
<> 129:0ab6a29f35bf 120
<> 129:0ab6a29f35bf 121 #elif defined ( __GNUC__ )
<> 129:0ab6a29f35bf 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 129:0ab6a29f35bf 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 124 #endif
<> 129:0ab6a29f35bf 125
<> 129:0ab6a29f35bf 126 #elif defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 127 #if defined __ARMVFP__
<> 129:0ab6a29f35bf 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 129 #endif
<> 129:0ab6a29f35bf 130
<> 129:0ab6a29f35bf 131 #elif defined ( __TMS470__ )
<> 129:0ab6a29f35bf 132 #if defined __TI__VFP_SUPPORT____
<> 129:0ab6a29f35bf 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 134 #endif
<> 129:0ab6a29f35bf 135
<> 129:0ab6a29f35bf 136 #elif defined ( __TASKING__ )
<> 129:0ab6a29f35bf 137 #if defined __FPU_VFP__
<> 129:0ab6a29f35bf 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 139 #endif
<> 129:0ab6a29f35bf 140
<> 129:0ab6a29f35bf 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 129:0ab6a29f35bf 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 129:0ab6a29f35bf 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 144 #endif
<> 129:0ab6a29f35bf 145 #endif
<> 129:0ab6a29f35bf 146
<> 129:0ab6a29f35bf 147 #include <stdint.h> /* standard types definitions */
<> 129:0ab6a29f35bf 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 129:0ab6a29f35bf 149 #include <core_cmFunc.h> /* Core Function Access */
<> 129:0ab6a29f35bf 150
<> 129:0ab6a29f35bf 151 #ifdef __cplusplus
<> 129:0ab6a29f35bf 152 }
<> 129:0ab6a29f35bf 153 #endif
<> 129:0ab6a29f35bf 154
<> 129:0ab6a29f35bf 155 #endif /* __CORE_SC300_H_GENERIC */
<> 129:0ab6a29f35bf 156
<> 129:0ab6a29f35bf 157 #ifndef __CMSIS_GENERIC
<> 129:0ab6a29f35bf 158
<> 129:0ab6a29f35bf 159 #ifndef __CORE_SC300_H_DEPENDANT
<> 129:0ab6a29f35bf 160 #define __CORE_SC300_H_DEPENDANT
<> 129:0ab6a29f35bf 161
<> 129:0ab6a29f35bf 162 #ifdef __cplusplus
<> 129:0ab6a29f35bf 163 extern "C" {
<> 129:0ab6a29f35bf 164 #endif
<> 129:0ab6a29f35bf 165
<> 129:0ab6a29f35bf 166 /* check device defines and use defaults */
<> 129:0ab6a29f35bf 167 #if defined __CHECK_DEVICE_DEFINES
<> 129:0ab6a29f35bf 168 #ifndef __SC300_REV
<> 129:0ab6a29f35bf 169 #define __SC300_REV 0x0000
<> 129:0ab6a29f35bf 170 #warning "__SC300_REV not defined in device header file; using default!"
<> 129:0ab6a29f35bf 171 #endif
<> 129:0ab6a29f35bf 172
<> 129:0ab6a29f35bf 173 #ifndef __MPU_PRESENT
<> 129:0ab6a29f35bf 174 #define __MPU_PRESENT 0
<> 129:0ab6a29f35bf 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 129:0ab6a29f35bf 176 #endif
<> 129:0ab6a29f35bf 177
<> 129:0ab6a29f35bf 178 #ifndef __NVIC_PRIO_BITS
<> 129:0ab6a29f35bf 179 #define __NVIC_PRIO_BITS 4
<> 129:0ab6a29f35bf 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 129:0ab6a29f35bf 181 #endif
<> 129:0ab6a29f35bf 182
<> 129:0ab6a29f35bf 183 #ifndef __Vendor_SysTickConfig
<> 129:0ab6a29f35bf 184 #define __Vendor_SysTickConfig 0
<> 129:0ab6a29f35bf 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 129:0ab6a29f35bf 186 #endif
<> 129:0ab6a29f35bf 187 #endif
<> 129:0ab6a29f35bf 188
<> 129:0ab6a29f35bf 189 /* IO definitions (access restrictions to peripheral registers) */
<> 129:0ab6a29f35bf 190 /**
<> 129:0ab6a29f35bf 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 129:0ab6a29f35bf 192
<> 129:0ab6a29f35bf 193 <strong>IO Type Qualifiers</strong> are used
<> 129:0ab6a29f35bf 194 \li to specify the access to peripheral variables.
<> 129:0ab6a29f35bf 195 \li for automatic generation of peripheral register debug information.
<> 129:0ab6a29f35bf 196 */
<> 129:0ab6a29f35bf 197 #ifdef __cplusplus
<> 129:0ab6a29f35bf 198 #define __I volatile /*!< Defines 'read only' permissions */
<> 129:0ab6a29f35bf 199 #else
<> 129:0ab6a29f35bf 200 #define __I volatile const /*!< Defines 'read only' permissions */
<> 129:0ab6a29f35bf 201 #endif
<> 129:0ab6a29f35bf 202 #define __O volatile /*!< Defines 'write only' permissions */
<> 129:0ab6a29f35bf 203 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 129:0ab6a29f35bf 204
<> 129:0ab6a29f35bf 205 /*@} end of group SC300 */
<> 129:0ab6a29f35bf 206
<> 129:0ab6a29f35bf 207
<> 129:0ab6a29f35bf 208
<> 129:0ab6a29f35bf 209 /*******************************************************************************
<> 129:0ab6a29f35bf 210 * Register Abstraction
<> 129:0ab6a29f35bf 211 Core Register contain:
<> 129:0ab6a29f35bf 212 - Core Register
<> 129:0ab6a29f35bf 213 - Core NVIC Register
<> 129:0ab6a29f35bf 214 - Core SCB Register
<> 129:0ab6a29f35bf 215 - Core SysTick Register
<> 129:0ab6a29f35bf 216 - Core Debug Register
<> 129:0ab6a29f35bf 217 - Core MPU Register
<> 129:0ab6a29f35bf 218 ******************************************************************************/
<> 129:0ab6a29f35bf 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 129:0ab6a29f35bf 220 \brief Type definitions and defines for Cortex-M processor based devices.
<> 129:0ab6a29f35bf 221 */
<> 129:0ab6a29f35bf 222
<> 129:0ab6a29f35bf 223 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 224 \defgroup CMSIS_CORE Status and Control Registers
<> 129:0ab6a29f35bf 225 \brief Core Register type definitions.
<> 129:0ab6a29f35bf 226 @{
<> 129:0ab6a29f35bf 227 */
<> 129:0ab6a29f35bf 228
<> 129:0ab6a29f35bf 229 /** \brief Union type to access the Application Program Status Register (APSR).
<> 129:0ab6a29f35bf 230 */
<> 129:0ab6a29f35bf 231 typedef union
<> 129:0ab6a29f35bf 232 {
<> 129:0ab6a29f35bf 233 struct
<> 129:0ab6a29f35bf 234 {
<> 129:0ab6a29f35bf 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
<> 129:0ab6a29f35bf 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 129:0ab6a29f35bf 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 129:0ab6a29f35bf 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 129:0ab6a29f35bf 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 129:0ab6a29f35bf 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 129:0ab6a29f35bf 241 } b; /*!< Structure used for bit access */
<> 129:0ab6a29f35bf 242 uint32_t w; /*!< Type used for word access */
<> 129:0ab6a29f35bf 243 } APSR_Type;
<> 129:0ab6a29f35bf 244
<> 129:0ab6a29f35bf 245 /* APSR Register Definitions */
<> 129:0ab6a29f35bf 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 129:0ab6a29f35bf 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 129:0ab6a29f35bf 248
<> 129:0ab6a29f35bf 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 129:0ab6a29f35bf 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 129:0ab6a29f35bf 251
<> 129:0ab6a29f35bf 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 129:0ab6a29f35bf 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 129:0ab6a29f35bf 254
<> 129:0ab6a29f35bf 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 129:0ab6a29f35bf 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 129:0ab6a29f35bf 257
<> 129:0ab6a29f35bf 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
<> 129:0ab6a29f35bf 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 129:0ab6a29f35bf 260
<> 129:0ab6a29f35bf 261
<> 129:0ab6a29f35bf 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 129:0ab6a29f35bf 263 */
<> 129:0ab6a29f35bf 264 typedef union
<> 129:0ab6a29f35bf 265 {
<> 129:0ab6a29f35bf 266 struct
<> 129:0ab6a29f35bf 267 {
<> 129:0ab6a29f35bf 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 129:0ab6a29f35bf 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 129:0ab6a29f35bf 270 } b; /*!< Structure used for bit access */
<> 129:0ab6a29f35bf 271 uint32_t w; /*!< Type used for word access */
<> 129:0ab6a29f35bf 272 } IPSR_Type;
<> 129:0ab6a29f35bf 273
<> 129:0ab6a29f35bf 274 /* IPSR Register Definitions */
<> 129:0ab6a29f35bf 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 129:0ab6a29f35bf 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 129:0ab6a29f35bf 277
<> 129:0ab6a29f35bf 278
<> 129:0ab6a29f35bf 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 129:0ab6a29f35bf 280 */
<> 129:0ab6a29f35bf 281 typedef union
<> 129:0ab6a29f35bf 282 {
<> 129:0ab6a29f35bf 283 struct
<> 129:0ab6a29f35bf 284 {
<> 129:0ab6a29f35bf 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 129:0ab6a29f35bf 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 129:0ab6a29f35bf 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 129:0ab6a29f35bf 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
<> 129:0ab6a29f35bf 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 129:0ab6a29f35bf 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 129:0ab6a29f35bf 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 129:0ab6a29f35bf 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 129:0ab6a29f35bf 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 129:0ab6a29f35bf 294 } b; /*!< Structure used for bit access */
<> 129:0ab6a29f35bf 295 uint32_t w; /*!< Type used for word access */
<> 129:0ab6a29f35bf 296 } xPSR_Type;
<> 129:0ab6a29f35bf 297
<> 129:0ab6a29f35bf 298 /* xPSR Register Definitions */
<> 129:0ab6a29f35bf 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 129:0ab6a29f35bf 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 129:0ab6a29f35bf 301
<> 129:0ab6a29f35bf 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 129:0ab6a29f35bf 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 129:0ab6a29f35bf 304
<> 129:0ab6a29f35bf 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 129:0ab6a29f35bf 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 129:0ab6a29f35bf 307
<> 129:0ab6a29f35bf 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 129:0ab6a29f35bf 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 129:0ab6a29f35bf 310
<> 129:0ab6a29f35bf 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
<> 129:0ab6a29f35bf 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 129:0ab6a29f35bf 313
<> 129:0ab6a29f35bf 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
<> 129:0ab6a29f35bf 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
<> 129:0ab6a29f35bf 316
<> 129:0ab6a29f35bf 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 129:0ab6a29f35bf 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 129:0ab6a29f35bf 319
<> 129:0ab6a29f35bf 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 129:0ab6a29f35bf 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 129:0ab6a29f35bf 322
<> 129:0ab6a29f35bf 323
<> 129:0ab6a29f35bf 324 /** \brief Union type to access the Control Registers (CONTROL).
<> 129:0ab6a29f35bf 325 */
<> 129:0ab6a29f35bf 326 typedef union
<> 129:0ab6a29f35bf 327 {
<> 129:0ab6a29f35bf 328 struct
<> 129:0ab6a29f35bf 329 {
<> 129:0ab6a29f35bf 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 129:0ab6a29f35bf 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 129:0ab6a29f35bf 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 129:0ab6a29f35bf 333 } b; /*!< Structure used for bit access */
<> 129:0ab6a29f35bf 334 uint32_t w; /*!< Type used for word access */
<> 129:0ab6a29f35bf 335 } CONTROL_Type;
<> 129:0ab6a29f35bf 336
<> 129:0ab6a29f35bf 337 /* CONTROL Register Definitions */
<> 129:0ab6a29f35bf 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 129:0ab6a29f35bf 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 129:0ab6a29f35bf 340
<> 129:0ab6a29f35bf 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 129:0ab6a29f35bf 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 129:0ab6a29f35bf 343
<> 129:0ab6a29f35bf 344 /*@} end of group CMSIS_CORE */
<> 129:0ab6a29f35bf 345
<> 129:0ab6a29f35bf 346
<> 129:0ab6a29f35bf 347 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 129:0ab6a29f35bf 349 \brief Type definitions for the NVIC Registers
<> 129:0ab6a29f35bf 350 @{
<> 129:0ab6a29f35bf 351 */
<> 129:0ab6a29f35bf 352
<> 129:0ab6a29f35bf 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 129:0ab6a29f35bf 354 */
<> 129:0ab6a29f35bf 355 typedef struct
<> 129:0ab6a29f35bf 356 {
<> 129:0ab6a29f35bf 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 129:0ab6a29f35bf 358 uint32_t RESERVED0[24];
<> 129:0ab6a29f35bf 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 129:0ab6a29f35bf 360 uint32_t RSERVED1[24];
<> 129:0ab6a29f35bf 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 129:0ab6a29f35bf 362 uint32_t RESERVED2[24];
<> 129:0ab6a29f35bf 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 129:0ab6a29f35bf 364 uint32_t RESERVED3[24];
<> 129:0ab6a29f35bf 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
<> 129:0ab6a29f35bf 366 uint32_t RESERVED4[56];
<> 129:0ab6a29f35bf 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
<> 129:0ab6a29f35bf 368 uint32_t RESERVED5[644];
<> 129:0ab6a29f35bf 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 129:0ab6a29f35bf 370 } NVIC_Type;
<> 129:0ab6a29f35bf 371
<> 129:0ab6a29f35bf 372 /* Software Triggered Interrupt Register Definitions */
<> 129:0ab6a29f35bf 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
<> 129:0ab6a29f35bf 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 129:0ab6a29f35bf 375
<> 129:0ab6a29f35bf 376 /*@} end of group CMSIS_NVIC */
<> 129:0ab6a29f35bf 377
<> 129:0ab6a29f35bf 378
<> 129:0ab6a29f35bf 379 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 380 \defgroup CMSIS_SCB System Control Block (SCB)
<> 129:0ab6a29f35bf 381 \brief Type definitions for the System Control Block Registers
<> 129:0ab6a29f35bf 382 @{
<> 129:0ab6a29f35bf 383 */
<> 129:0ab6a29f35bf 384
<> 129:0ab6a29f35bf 385 /** \brief Structure type to access the System Control Block (SCB).
<> 129:0ab6a29f35bf 386 */
<> 129:0ab6a29f35bf 387 typedef struct
<> 129:0ab6a29f35bf 388 {
<> 129:0ab6a29f35bf 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 129:0ab6a29f35bf 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 129:0ab6a29f35bf 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 129:0ab6a29f35bf 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 129:0ab6a29f35bf 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 129:0ab6a29f35bf 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 129:0ab6a29f35bf 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
<> 129:0ab6a29f35bf 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 129:0ab6a29f35bf 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
<> 129:0ab6a29f35bf 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
<> 129:0ab6a29f35bf 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
<> 129:0ab6a29f35bf 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
<> 129:0ab6a29f35bf 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
<> 129:0ab6a29f35bf 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
<> 129:0ab6a29f35bf 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
<> 129:0ab6a29f35bf 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
<> 129:0ab6a29f35bf 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
<> 129:0ab6a29f35bf 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
<> 129:0ab6a29f35bf 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
<> 129:0ab6a29f35bf 408 uint32_t RESERVED0[5];
<> 129:0ab6a29f35bf 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 129:0ab6a29f35bf 410 uint32_t RESERVED1[129];
<> 129:0ab6a29f35bf 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
<> 129:0ab6a29f35bf 412 } SCB_Type;
<> 129:0ab6a29f35bf 413
<> 129:0ab6a29f35bf 414 /* SCB CPUID Register Definitions */
<> 129:0ab6a29f35bf 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 129:0ab6a29f35bf 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 129:0ab6a29f35bf 417
<> 129:0ab6a29f35bf 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 129:0ab6a29f35bf 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 129:0ab6a29f35bf 420
<> 129:0ab6a29f35bf 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 129:0ab6a29f35bf 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 129:0ab6a29f35bf 423
<> 129:0ab6a29f35bf 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 129:0ab6a29f35bf 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 129:0ab6a29f35bf 426
<> 129:0ab6a29f35bf 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 129:0ab6a29f35bf 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 129:0ab6a29f35bf 429
<> 129:0ab6a29f35bf 430 /* SCB Interrupt Control State Register Definitions */
<> 129:0ab6a29f35bf 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 129:0ab6a29f35bf 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 129:0ab6a29f35bf 433
<> 129:0ab6a29f35bf 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 129:0ab6a29f35bf 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 129:0ab6a29f35bf 436
<> 129:0ab6a29f35bf 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 129:0ab6a29f35bf 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 129:0ab6a29f35bf 439
<> 129:0ab6a29f35bf 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 129:0ab6a29f35bf 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 129:0ab6a29f35bf 442
<> 129:0ab6a29f35bf 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 129:0ab6a29f35bf 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 129:0ab6a29f35bf 445
<> 129:0ab6a29f35bf 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 129:0ab6a29f35bf 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 129:0ab6a29f35bf 448
<> 129:0ab6a29f35bf 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 129:0ab6a29f35bf 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 129:0ab6a29f35bf 451
<> 129:0ab6a29f35bf 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 129:0ab6a29f35bf 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 129:0ab6a29f35bf 454
<> 129:0ab6a29f35bf 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
<> 129:0ab6a29f35bf 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 129:0ab6a29f35bf 457
<> 129:0ab6a29f35bf 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 129:0ab6a29f35bf 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 129:0ab6a29f35bf 460
<> 129:0ab6a29f35bf 461 /* SCB Vector Table Offset Register Definitions */
<> 129:0ab6a29f35bf 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
<> 129:0ab6a29f35bf 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
<> 129:0ab6a29f35bf 464
<> 129:0ab6a29f35bf 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
<> 129:0ab6a29f35bf 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 129:0ab6a29f35bf 467
<> 129:0ab6a29f35bf 468 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 129:0ab6a29f35bf 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 129:0ab6a29f35bf 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 129:0ab6a29f35bf 471
<> 129:0ab6a29f35bf 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 129:0ab6a29f35bf 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 129:0ab6a29f35bf 474
<> 129:0ab6a29f35bf 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 129:0ab6a29f35bf 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 129:0ab6a29f35bf 477
<> 129:0ab6a29f35bf 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
<> 129:0ab6a29f35bf 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 129:0ab6a29f35bf 480
<> 129:0ab6a29f35bf 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 129:0ab6a29f35bf 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 129:0ab6a29f35bf 483
<> 129:0ab6a29f35bf 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 129:0ab6a29f35bf 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 129:0ab6a29f35bf 486
<> 129:0ab6a29f35bf 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
<> 129:0ab6a29f35bf 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 129:0ab6a29f35bf 489
<> 129:0ab6a29f35bf 490 /* SCB System Control Register Definitions */
<> 129:0ab6a29f35bf 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 129:0ab6a29f35bf 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 129:0ab6a29f35bf 493
<> 129:0ab6a29f35bf 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 129:0ab6a29f35bf 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 129:0ab6a29f35bf 496
<> 129:0ab6a29f35bf 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 129:0ab6a29f35bf 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 129:0ab6a29f35bf 499
<> 129:0ab6a29f35bf 500 /* SCB Configuration Control Register Definitions */
<> 129:0ab6a29f35bf 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 129:0ab6a29f35bf 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 129:0ab6a29f35bf 503
<> 129:0ab6a29f35bf 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
<> 129:0ab6a29f35bf 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 129:0ab6a29f35bf 506
<> 129:0ab6a29f35bf 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
<> 129:0ab6a29f35bf 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 129:0ab6a29f35bf 509
<> 129:0ab6a29f35bf 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 129:0ab6a29f35bf 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 129:0ab6a29f35bf 512
<> 129:0ab6a29f35bf 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
<> 129:0ab6a29f35bf 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 129:0ab6a29f35bf 515
<> 129:0ab6a29f35bf 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
<> 129:0ab6a29f35bf 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 129:0ab6a29f35bf 518
<> 129:0ab6a29f35bf 519 /* SCB System Handler Control and State Register Definitions */
<> 129:0ab6a29f35bf 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
<> 129:0ab6a29f35bf 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 129:0ab6a29f35bf 522
<> 129:0ab6a29f35bf 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
<> 129:0ab6a29f35bf 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 129:0ab6a29f35bf 525
<> 129:0ab6a29f35bf 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
<> 129:0ab6a29f35bf 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 129:0ab6a29f35bf 528
<> 129:0ab6a29f35bf 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 129:0ab6a29f35bf 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 129:0ab6a29f35bf 531
<> 129:0ab6a29f35bf 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 129:0ab6a29f35bf 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 129:0ab6a29f35bf 534
<> 129:0ab6a29f35bf 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 129:0ab6a29f35bf 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 129:0ab6a29f35bf 537
<> 129:0ab6a29f35bf 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 129:0ab6a29f35bf 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 129:0ab6a29f35bf 540
<> 129:0ab6a29f35bf 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
<> 129:0ab6a29f35bf 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 129:0ab6a29f35bf 543
<> 129:0ab6a29f35bf 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
<> 129:0ab6a29f35bf 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 129:0ab6a29f35bf 546
<> 129:0ab6a29f35bf 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
<> 129:0ab6a29f35bf 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 129:0ab6a29f35bf 549
<> 129:0ab6a29f35bf 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
<> 129:0ab6a29f35bf 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 129:0ab6a29f35bf 552
<> 129:0ab6a29f35bf 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
<> 129:0ab6a29f35bf 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 129:0ab6a29f35bf 555
<> 129:0ab6a29f35bf 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
<> 129:0ab6a29f35bf 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 129:0ab6a29f35bf 558
<> 129:0ab6a29f35bf 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
<> 129:0ab6a29f35bf 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 129:0ab6a29f35bf 561
<> 129:0ab6a29f35bf 562 /* SCB Configurable Fault Status Registers Definitions */
<> 129:0ab6a29f35bf 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
<> 129:0ab6a29f35bf 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 129:0ab6a29f35bf 565
<> 129:0ab6a29f35bf 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
<> 129:0ab6a29f35bf 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 129:0ab6a29f35bf 568
<> 129:0ab6a29f35bf 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 129:0ab6a29f35bf 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 129:0ab6a29f35bf 571
<> 129:0ab6a29f35bf 572 /* SCB Hard Fault Status Registers Definitions */
<> 129:0ab6a29f35bf 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
<> 129:0ab6a29f35bf 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 129:0ab6a29f35bf 575
<> 129:0ab6a29f35bf 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
<> 129:0ab6a29f35bf 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 129:0ab6a29f35bf 578
<> 129:0ab6a29f35bf 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
<> 129:0ab6a29f35bf 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 129:0ab6a29f35bf 581
<> 129:0ab6a29f35bf 582 /* SCB Debug Fault Status Register Definitions */
<> 129:0ab6a29f35bf 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
<> 129:0ab6a29f35bf 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 129:0ab6a29f35bf 585
<> 129:0ab6a29f35bf 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
<> 129:0ab6a29f35bf 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 129:0ab6a29f35bf 588
<> 129:0ab6a29f35bf 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
<> 129:0ab6a29f35bf 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 129:0ab6a29f35bf 591
<> 129:0ab6a29f35bf 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
<> 129:0ab6a29f35bf 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 129:0ab6a29f35bf 594
<> 129:0ab6a29f35bf 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
<> 129:0ab6a29f35bf 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 129:0ab6a29f35bf 597
<> 129:0ab6a29f35bf 598 /*@} end of group CMSIS_SCB */
<> 129:0ab6a29f35bf 599
<> 129:0ab6a29f35bf 600
<> 129:0ab6a29f35bf 601 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<> 129:0ab6a29f35bf 603 \brief Type definitions for the System Control and ID Register not in the SCB
<> 129:0ab6a29f35bf 604 @{
<> 129:0ab6a29f35bf 605 */
<> 129:0ab6a29f35bf 606
<> 129:0ab6a29f35bf 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
<> 129:0ab6a29f35bf 608 */
<> 129:0ab6a29f35bf 609 typedef struct
<> 129:0ab6a29f35bf 610 {
<> 129:0ab6a29f35bf 611 uint32_t RESERVED0[1];
<> 129:0ab6a29f35bf 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
<> 129:0ab6a29f35bf 613 uint32_t RESERVED1[1];
<> 129:0ab6a29f35bf 614 } SCnSCB_Type;
<> 129:0ab6a29f35bf 615
<> 129:0ab6a29f35bf 616 /* Interrupt Controller Type Register Definitions */
<> 129:0ab6a29f35bf 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
<> 129:0ab6a29f35bf 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 129:0ab6a29f35bf 619
<> 129:0ab6a29f35bf 620 /*@} end of group CMSIS_SCnotSCB */
<> 129:0ab6a29f35bf 621
<> 129:0ab6a29f35bf 622
<> 129:0ab6a29f35bf 623 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 129:0ab6a29f35bf 625 \brief Type definitions for the System Timer Registers.
<> 129:0ab6a29f35bf 626 @{
<> 129:0ab6a29f35bf 627 */
<> 129:0ab6a29f35bf 628
<> 129:0ab6a29f35bf 629 /** \brief Structure type to access the System Timer (SysTick).
<> 129:0ab6a29f35bf 630 */
<> 129:0ab6a29f35bf 631 typedef struct
<> 129:0ab6a29f35bf 632 {
<> 129:0ab6a29f35bf 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 129:0ab6a29f35bf 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 129:0ab6a29f35bf 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 129:0ab6a29f35bf 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 129:0ab6a29f35bf 637 } SysTick_Type;
<> 129:0ab6a29f35bf 638
<> 129:0ab6a29f35bf 639 /* SysTick Control / Status Register Definitions */
<> 129:0ab6a29f35bf 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 129:0ab6a29f35bf 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 129:0ab6a29f35bf 642
<> 129:0ab6a29f35bf 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 129:0ab6a29f35bf 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 129:0ab6a29f35bf 645
<> 129:0ab6a29f35bf 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 129:0ab6a29f35bf 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 129:0ab6a29f35bf 648
<> 129:0ab6a29f35bf 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 129:0ab6a29f35bf 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 129:0ab6a29f35bf 651
<> 129:0ab6a29f35bf 652 /* SysTick Reload Register Definitions */
<> 129:0ab6a29f35bf 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 129:0ab6a29f35bf 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 129:0ab6a29f35bf 655
<> 129:0ab6a29f35bf 656 /* SysTick Current Register Definitions */
<> 129:0ab6a29f35bf 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 129:0ab6a29f35bf 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 129:0ab6a29f35bf 659
<> 129:0ab6a29f35bf 660 /* SysTick Calibration Register Definitions */
<> 129:0ab6a29f35bf 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 129:0ab6a29f35bf 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 129:0ab6a29f35bf 663
<> 129:0ab6a29f35bf 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 129:0ab6a29f35bf 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 129:0ab6a29f35bf 666
<> 129:0ab6a29f35bf 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 129:0ab6a29f35bf 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 129:0ab6a29f35bf 669
<> 129:0ab6a29f35bf 670 /*@} end of group CMSIS_SysTick */
<> 129:0ab6a29f35bf 671
<> 129:0ab6a29f35bf 672
<> 129:0ab6a29f35bf 673 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<> 129:0ab6a29f35bf 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 129:0ab6a29f35bf 676 @{
<> 129:0ab6a29f35bf 677 */
<> 129:0ab6a29f35bf 678
<> 129:0ab6a29f35bf 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 129:0ab6a29f35bf 680 */
<> 129:0ab6a29f35bf 681 typedef struct
<> 129:0ab6a29f35bf 682 {
<> 129:0ab6a29f35bf 683 __O union
<> 129:0ab6a29f35bf 684 {
<> 129:0ab6a29f35bf 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
<> 129:0ab6a29f35bf 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
<> 129:0ab6a29f35bf 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
<> 129:0ab6a29f35bf 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
<> 129:0ab6a29f35bf 689 uint32_t RESERVED0[864];
<> 129:0ab6a29f35bf 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
<> 129:0ab6a29f35bf 691 uint32_t RESERVED1[15];
<> 129:0ab6a29f35bf 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
<> 129:0ab6a29f35bf 693 uint32_t RESERVED2[15];
<> 129:0ab6a29f35bf 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
<> 129:0ab6a29f35bf 695 uint32_t RESERVED3[29];
<> 129:0ab6a29f35bf 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
<> 129:0ab6a29f35bf 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
<> 129:0ab6a29f35bf 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
<> 129:0ab6a29f35bf 699 uint32_t RESERVED4[43];
<> 129:0ab6a29f35bf 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
<> 129:0ab6a29f35bf 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
<> 129:0ab6a29f35bf 702 uint32_t RESERVED5[6];
<> 129:0ab6a29f35bf 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
<> 129:0ab6a29f35bf 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
<> 129:0ab6a29f35bf 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
<> 129:0ab6a29f35bf 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
<> 129:0ab6a29f35bf 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
<> 129:0ab6a29f35bf 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
<> 129:0ab6a29f35bf 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
<> 129:0ab6a29f35bf 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
<> 129:0ab6a29f35bf 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
<> 129:0ab6a29f35bf 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
<> 129:0ab6a29f35bf 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
<> 129:0ab6a29f35bf 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 129:0ab6a29f35bf 715 } ITM_Type;
<> 129:0ab6a29f35bf 716
<> 129:0ab6a29f35bf 717 /* ITM Trace Privilege Register Definitions */
<> 129:0ab6a29f35bf 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
<> 129:0ab6a29f35bf 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 129:0ab6a29f35bf 720
<> 129:0ab6a29f35bf 721 /* ITM Trace Control Register Definitions */
<> 129:0ab6a29f35bf 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
<> 129:0ab6a29f35bf 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 129:0ab6a29f35bf 724
<> 129:0ab6a29f35bf 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
<> 129:0ab6a29f35bf 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 129:0ab6a29f35bf 727
<> 129:0ab6a29f35bf 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
<> 129:0ab6a29f35bf 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 129:0ab6a29f35bf 730
<> 129:0ab6a29f35bf 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
<> 129:0ab6a29f35bf 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 129:0ab6a29f35bf 733
<> 129:0ab6a29f35bf 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
<> 129:0ab6a29f35bf 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 129:0ab6a29f35bf 736
<> 129:0ab6a29f35bf 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
<> 129:0ab6a29f35bf 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 129:0ab6a29f35bf 739
<> 129:0ab6a29f35bf 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
<> 129:0ab6a29f35bf 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 129:0ab6a29f35bf 742
<> 129:0ab6a29f35bf 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
<> 129:0ab6a29f35bf 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 129:0ab6a29f35bf 745
<> 129:0ab6a29f35bf 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
<> 129:0ab6a29f35bf 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 129:0ab6a29f35bf 748
<> 129:0ab6a29f35bf 749 /* ITM Integration Write Register Definitions */
<> 129:0ab6a29f35bf 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
<> 129:0ab6a29f35bf 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 129:0ab6a29f35bf 752
<> 129:0ab6a29f35bf 753 /* ITM Integration Read Register Definitions */
<> 129:0ab6a29f35bf 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
<> 129:0ab6a29f35bf 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 129:0ab6a29f35bf 756
<> 129:0ab6a29f35bf 757 /* ITM Integration Mode Control Register Definitions */
<> 129:0ab6a29f35bf 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
<> 129:0ab6a29f35bf 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 129:0ab6a29f35bf 760
<> 129:0ab6a29f35bf 761 /* ITM Lock Status Register Definitions */
<> 129:0ab6a29f35bf 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
<> 129:0ab6a29f35bf 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 129:0ab6a29f35bf 764
<> 129:0ab6a29f35bf 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
<> 129:0ab6a29f35bf 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 129:0ab6a29f35bf 767
<> 129:0ab6a29f35bf 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
<> 129:0ab6a29f35bf 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 129:0ab6a29f35bf 770
<> 129:0ab6a29f35bf 771 /*@}*/ /* end of group CMSIS_ITM */
<> 129:0ab6a29f35bf 772
<> 129:0ab6a29f35bf 773
<> 129:0ab6a29f35bf 774 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<> 129:0ab6a29f35bf 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 129:0ab6a29f35bf 777 @{
<> 129:0ab6a29f35bf 778 */
<> 129:0ab6a29f35bf 779
<> 129:0ab6a29f35bf 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 129:0ab6a29f35bf 781 */
<> 129:0ab6a29f35bf 782 typedef struct
<> 129:0ab6a29f35bf 783 {
<> 129:0ab6a29f35bf 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
<> 129:0ab6a29f35bf 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
<> 129:0ab6a29f35bf 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
<> 129:0ab6a29f35bf 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
<> 129:0ab6a29f35bf 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
<> 129:0ab6a29f35bf 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
<> 129:0ab6a29f35bf 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
<> 129:0ab6a29f35bf 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
<> 129:0ab6a29f35bf 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
<> 129:0ab6a29f35bf 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
<> 129:0ab6a29f35bf 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
<> 129:0ab6a29f35bf 795 uint32_t RESERVED0[1];
<> 129:0ab6a29f35bf 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
<> 129:0ab6a29f35bf 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
<> 129:0ab6a29f35bf 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
<> 129:0ab6a29f35bf 799 uint32_t RESERVED1[1];
<> 129:0ab6a29f35bf 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
<> 129:0ab6a29f35bf 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
<> 129:0ab6a29f35bf 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
<> 129:0ab6a29f35bf 803 uint32_t RESERVED2[1];
<> 129:0ab6a29f35bf 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
<> 129:0ab6a29f35bf 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
<> 129:0ab6a29f35bf 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 129:0ab6a29f35bf 807 } DWT_Type;
<> 129:0ab6a29f35bf 808
<> 129:0ab6a29f35bf 809 /* DWT Control Register Definitions */
<> 129:0ab6a29f35bf 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
<> 129:0ab6a29f35bf 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 129:0ab6a29f35bf 812
<> 129:0ab6a29f35bf 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
<> 129:0ab6a29f35bf 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 129:0ab6a29f35bf 815
<> 129:0ab6a29f35bf 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
<> 129:0ab6a29f35bf 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 129:0ab6a29f35bf 818
<> 129:0ab6a29f35bf 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
<> 129:0ab6a29f35bf 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 129:0ab6a29f35bf 821
<> 129:0ab6a29f35bf 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
<> 129:0ab6a29f35bf 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 129:0ab6a29f35bf 824
<> 129:0ab6a29f35bf 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
<> 129:0ab6a29f35bf 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 129:0ab6a29f35bf 827
<> 129:0ab6a29f35bf 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
<> 129:0ab6a29f35bf 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 129:0ab6a29f35bf 830
<> 129:0ab6a29f35bf 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
<> 129:0ab6a29f35bf 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 129:0ab6a29f35bf 833
<> 129:0ab6a29f35bf 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
<> 129:0ab6a29f35bf 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 129:0ab6a29f35bf 836
<> 129:0ab6a29f35bf 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
<> 129:0ab6a29f35bf 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 129:0ab6a29f35bf 839
<> 129:0ab6a29f35bf 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
<> 129:0ab6a29f35bf 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 129:0ab6a29f35bf 842
<> 129:0ab6a29f35bf 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
<> 129:0ab6a29f35bf 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 129:0ab6a29f35bf 845
<> 129:0ab6a29f35bf 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
<> 129:0ab6a29f35bf 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 129:0ab6a29f35bf 848
<> 129:0ab6a29f35bf 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
<> 129:0ab6a29f35bf 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 129:0ab6a29f35bf 851
<> 129:0ab6a29f35bf 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
<> 129:0ab6a29f35bf 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 129:0ab6a29f35bf 854
<> 129:0ab6a29f35bf 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
<> 129:0ab6a29f35bf 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 129:0ab6a29f35bf 857
<> 129:0ab6a29f35bf 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
<> 129:0ab6a29f35bf 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 129:0ab6a29f35bf 860
<> 129:0ab6a29f35bf 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
<> 129:0ab6a29f35bf 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 129:0ab6a29f35bf 863
<> 129:0ab6a29f35bf 864 /* DWT CPI Count Register Definitions */
<> 129:0ab6a29f35bf 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
<> 129:0ab6a29f35bf 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 129:0ab6a29f35bf 867
<> 129:0ab6a29f35bf 868 /* DWT Exception Overhead Count Register Definitions */
<> 129:0ab6a29f35bf 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
<> 129:0ab6a29f35bf 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 129:0ab6a29f35bf 871
<> 129:0ab6a29f35bf 872 /* DWT Sleep Count Register Definitions */
<> 129:0ab6a29f35bf 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 129:0ab6a29f35bf 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 129:0ab6a29f35bf 875
<> 129:0ab6a29f35bf 876 /* DWT LSU Count Register Definitions */
<> 129:0ab6a29f35bf 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
<> 129:0ab6a29f35bf 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 129:0ab6a29f35bf 879
<> 129:0ab6a29f35bf 880 /* DWT Folded-instruction Count Register Definitions */
<> 129:0ab6a29f35bf 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
<> 129:0ab6a29f35bf 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 129:0ab6a29f35bf 883
<> 129:0ab6a29f35bf 884 /* DWT Comparator Mask Register Definitions */
<> 129:0ab6a29f35bf 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
<> 129:0ab6a29f35bf 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 129:0ab6a29f35bf 887
<> 129:0ab6a29f35bf 888 /* DWT Comparator Function Register Definitions */
<> 129:0ab6a29f35bf 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
<> 129:0ab6a29f35bf 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 129:0ab6a29f35bf 891
<> 129:0ab6a29f35bf 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 129:0ab6a29f35bf 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 129:0ab6a29f35bf 894
<> 129:0ab6a29f35bf 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 129:0ab6a29f35bf 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 129:0ab6a29f35bf 897
<> 129:0ab6a29f35bf 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
<> 129:0ab6a29f35bf 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 129:0ab6a29f35bf 900
<> 129:0ab6a29f35bf 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
<> 129:0ab6a29f35bf 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 129:0ab6a29f35bf 903
<> 129:0ab6a29f35bf 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
<> 129:0ab6a29f35bf 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 129:0ab6a29f35bf 906
<> 129:0ab6a29f35bf 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
<> 129:0ab6a29f35bf 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 129:0ab6a29f35bf 909
<> 129:0ab6a29f35bf 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
<> 129:0ab6a29f35bf 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 129:0ab6a29f35bf 912
<> 129:0ab6a29f35bf 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
<> 129:0ab6a29f35bf 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 129:0ab6a29f35bf 915
<> 129:0ab6a29f35bf 916 /*@}*/ /* end of group CMSIS_DWT */
<> 129:0ab6a29f35bf 917
<> 129:0ab6a29f35bf 918
<> 129:0ab6a29f35bf 919 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
<> 129:0ab6a29f35bf 921 \brief Type definitions for the Trace Port Interface (TPI)
<> 129:0ab6a29f35bf 922 @{
<> 129:0ab6a29f35bf 923 */
<> 129:0ab6a29f35bf 924
<> 129:0ab6a29f35bf 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
<> 129:0ab6a29f35bf 926 */
<> 129:0ab6a29f35bf 927 typedef struct
<> 129:0ab6a29f35bf 928 {
<> 129:0ab6a29f35bf 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
<> 129:0ab6a29f35bf 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
<> 129:0ab6a29f35bf 931 uint32_t RESERVED0[2];
<> 129:0ab6a29f35bf 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
<> 129:0ab6a29f35bf 933 uint32_t RESERVED1[55];
<> 129:0ab6a29f35bf 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
<> 129:0ab6a29f35bf 935 uint32_t RESERVED2[131];
<> 129:0ab6a29f35bf 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
<> 129:0ab6a29f35bf 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
<> 129:0ab6a29f35bf 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
<> 129:0ab6a29f35bf 939 uint32_t RESERVED3[759];
<> 129:0ab6a29f35bf 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
<> 129:0ab6a29f35bf 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
<> 129:0ab6a29f35bf 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
<> 129:0ab6a29f35bf 943 uint32_t RESERVED4[1];
<> 129:0ab6a29f35bf 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
<> 129:0ab6a29f35bf 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
<> 129:0ab6a29f35bf 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
<> 129:0ab6a29f35bf 947 uint32_t RESERVED5[39];
<> 129:0ab6a29f35bf 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
<> 129:0ab6a29f35bf 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
<> 129:0ab6a29f35bf 950 uint32_t RESERVED7[8];
<> 129:0ab6a29f35bf 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
<> 129:0ab6a29f35bf 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 129:0ab6a29f35bf 953 } TPI_Type;
<> 129:0ab6a29f35bf 954
<> 129:0ab6a29f35bf 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
<> 129:0ab6a29f35bf 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
<> 129:0ab6a29f35bf 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 129:0ab6a29f35bf 958
<> 129:0ab6a29f35bf 959 /* TPI Selected Pin Protocol Register Definitions */
<> 129:0ab6a29f35bf 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
<> 129:0ab6a29f35bf 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 129:0ab6a29f35bf 962
<> 129:0ab6a29f35bf 963 /* TPI Formatter and Flush Status Register Definitions */
<> 129:0ab6a29f35bf 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
<> 129:0ab6a29f35bf 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 129:0ab6a29f35bf 966
<> 129:0ab6a29f35bf 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
<> 129:0ab6a29f35bf 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 129:0ab6a29f35bf 969
<> 129:0ab6a29f35bf 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
<> 129:0ab6a29f35bf 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 129:0ab6a29f35bf 972
<> 129:0ab6a29f35bf 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
<> 129:0ab6a29f35bf 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 129:0ab6a29f35bf 975
<> 129:0ab6a29f35bf 976 /* TPI Formatter and Flush Control Register Definitions */
<> 129:0ab6a29f35bf 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
<> 129:0ab6a29f35bf 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 129:0ab6a29f35bf 979
<> 129:0ab6a29f35bf 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
<> 129:0ab6a29f35bf 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 129:0ab6a29f35bf 982
<> 129:0ab6a29f35bf 983 /* TPI TRIGGER Register Definitions */
<> 129:0ab6a29f35bf 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
<> 129:0ab6a29f35bf 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 129:0ab6a29f35bf 986
<> 129:0ab6a29f35bf 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
<> 129:0ab6a29f35bf 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
<> 129:0ab6a29f35bf 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 129:0ab6a29f35bf 990
<> 129:0ab6a29f35bf 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
<> 129:0ab6a29f35bf 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 129:0ab6a29f35bf 993
<> 129:0ab6a29f35bf 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
<> 129:0ab6a29f35bf 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 129:0ab6a29f35bf 996
<> 129:0ab6a29f35bf 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
<> 129:0ab6a29f35bf 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 129:0ab6a29f35bf 999
<> 129:0ab6a29f35bf 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
<> 129:0ab6a29f35bf 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 129:0ab6a29f35bf 1002
<> 129:0ab6a29f35bf 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
<> 129:0ab6a29f35bf 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 129:0ab6a29f35bf 1005
<> 129:0ab6a29f35bf 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
<> 129:0ab6a29f35bf 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 129:0ab6a29f35bf 1008
<> 129:0ab6a29f35bf 1009 /* TPI ITATBCTR2 Register Definitions */
<> 129:0ab6a29f35bf 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
<> 129:0ab6a29f35bf 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 129:0ab6a29f35bf 1012
<> 129:0ab6a29f35bf 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
<> 129:0ab6a29f35bf 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
<> 129:0ab6a29f35bf 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 129:0ab6a29f35bf 1016
<> 129:0ab6a29f35bf 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
<> 129:0ab6a29f35bf 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 129:0ab6a29f35bf 1019
<> 129:0ab6a29f35bf 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
<> 129:0ab6a29f35bf 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 129:0ab6a29f35bf 1022
<> 129:0ab6a29f35bf 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
<> 129:0ab6a29f35bf 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 129:0ab6a29f35bf 1025
<> 129:0ab6a29f35bf 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
<> 129:0ab6a29f35bf 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 129:0ab6a29f35bf 1028
<> 129:0ab6a29f35bf 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
<> 129:0ab6a29f35bf 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 129:0ab6a29f35bf 1031
<> 129:0ab6a29f35bf 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
<> 129:0ab6a29f35bf 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 129:0ab6a29f35bf 1034
<> 129:0ab6a29f35bf 1035 /* TPI ITATBCTR0 Register Definitions */
<> 129:0ab6a29f35bf 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
<> 129:0ab6a29f35bf 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 129:0ab6a29f35bf 1038
<> 129:0ab6a29f35bf 1039 /* TPI Integration Mode Control Register Definitions */
<> 129:0ab6a29f35bf 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
<> 129:0ab6a29f35bf 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 129:0ab6a29f35bf 1042
<> 129:0ab6a29f35bf 1043 /* TPI DEVID Register Definitions */
<> 129:0ab6a29f35bf 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
<> 129:0ab6a29f35bf 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 129:0ab6a29f35bf 1046
<> 129:0ab6a29f35bf 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
<> 129:0ab6a29f35bf 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 129:0ab6a29f35bf 1049
<> 129:0ab6a29f35bf 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
<> 129:0ab6a29f35bf 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 129:0ab6a29f35bf 1052
<> 129:0ab6a29f35bf 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
<> 129:0ab6a29f35bf 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 129:0ab6a29f35bf 1055
<> 129:0ab6a29f35bf 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
<> 129:0ab6a29f35bf 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 129:0ab6a29f35bf 1058
<> 129:0ab6a29f35bf 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
<> 129:0ab6a29f35bf 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 129:0ab6a29f35bf 1061
<> 129:0ab6a29f35bf 1062 /* TPI DEVTYPE Register Definitions */
<> 129:0ab6a29f35bf 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
<> 129:0ab6a29f35bf 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 129:0ab6a29f35bf 1065
<> 129:0ab6a29f35bf 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
<> 129:0ab6a29f35bf 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 129:0ab6a29f35bf 1068
<> 129:0ab6a29f35bf 1069 /*@}*/ /* end of group CMSIS_TPI */
<> 129:0ab6a29f35bf 1070
<> 129:0ab6a29f35bf 1071
<> 129:0ab6a29f35bf 1072 #if (__MPU_PRESENT == 1)
<> 129:0ab6a29f35bf 1073 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 129:0ab6a29f35bf 1075 \brief Type definitions for the Memory Protection Unit (MPU)
<> 129:0ab6a29f35bf 1076 @{
<> 129:0ab6a29f35bf 1077 */
<> 129:0ab6a29f35bf 1078
<> 129:0ab6a29f35bf 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 129:0ab6a29f35bf 1080 */
<> 129:0ab6a29f35bf 1081 typedef struct
<> 129:0ab6a29f35bf 1082 {
<> 129:0ab6a29f35bf 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 129:0ab6a29f35bf 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 129:0ab6a29f35bf 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 129:0ab6a29f35bf 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 129:0ab6a29f35bf 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 129:0ab6a29f35bf 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
<> 129:0ab6a29f35bf 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
<> 129:0ab6a29f35bf 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
<> 129:0ab6a29f35bf 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
<> 129:0ab6a29f35bf 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
<> 129:0ab6a29f35bf 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 129:0ab6a29f35bf 1094 } MPU_Type;
<> 129:0ab6a29f35bf 1095
<> 129:0ab6a29f35bf 1096 /* MPU Type Register */
<> 129:0ab6a29f35bf 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 129:0ab6a29f35bf 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 129:0ab6a29f35bf 1099
<> 129:0ab6a29f35bf 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 129:0ab6a29f35bf 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 129:0ab6a29f35bf 1102
<> 129:0ab6a29f35bf 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 129:0ab6a29f35bf 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 129:0ab6a29f35bf 1105
<> 129:0ab6a29f35bf 1106 /* MPU Control Register */
<> 129:0ab6a29f35bf 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 129:0ab6a29f35bf 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 129:0ab6a29f35bf 1109
<> 129:0ab6a29f35bf 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 129:0ab6a29f35bf 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 129:0ab6a29f35bf 1112
<> 129:0ab6a29f35bf 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 129:0ab6a29f35bf 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 129:0ab6a29f35bf 1115
<> 129:0ab6a29f35bf 1116 /* MPU Region Number Register */
<> 129:0ab6a29f35bf 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 129:0ab6a29f35bf 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 129:0ab6a29f35bf 1119
<> 129:0ab6a29f35bf 1120 /* MPU Region Base Address Register */
<> 129:0ab6a29f35bf 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
<> 129:0ab6a29f35bf 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 129:0ab6a29f35bf 1123
<> 129:0ab6a29f35bf 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 129:0ab6a29f35bf 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 129:0ab6a29f35bf 1126
<> 129:0ab6a29f35bf 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 129:0ab6a29f35bf 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 129:0ab6a29f35bf 1129
<> 129:0ab6a29f35bf 1130 /* MPU Region Attribute and Size Register */
<> 129:0ab6a29f35bf 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 129:0ab6a29f35bf 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 129:0ab6a29f35bf 1133
<> 129:0ab6a29f35bf 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 129:0ab6a29f35bf 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 129:0ab6a29f35bf 1136
<> 129:0ab6a29f35bf 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 129:0ab6a29f35bf 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 129:0ab6a29f35bf 1139
<> 129:0ab6a29f35bf 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 129:0ab6a29f35bf 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 129:0ab6a29f35bf 1142
<> 129:0ab6a29f35bf 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 129:0ab6a29f35bf 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 129:0ab6a29f35bf 1145
<> 129:0ab6a29f35bf 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 129:0ab6a29f35bf 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 129:0ab6a29f35bf 1148
<> 129:0ab6a29f35bf 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 129:0ab6a29f35bf 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 129:0ab6a29f35bf 1151
<> 129:0ab6a29f35bf 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 129:0ab6a29f35bf 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 129:0ab6a29f35bf 1154
<> 129:0ab6a29f35bf 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 129:0ab6a29f35bf 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 129:0ab6a29f35bf 1157
<> 129:0ab6a29f35bf 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 129:0ab6a29f35bf 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 129:0ab6a29f35bf 1160
<> 129:0ab6a29f35bf 1161 /*@} end of group CMSIS_MPU */
<> 129:0ab6a29f35bf 1162 #endif
<> 129:0ab6a29f35bf 1163
<> 129:0ab6a29f35bf 1164
<> 129:0ab6a29f35bf 1165 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 129:0ab6a29f35bf 1167 \brief Type definitions for the Core Debug Registers
<> 129:0ab6a29f35bf 1168 @{
<> 129:0ab6a29f35bf 1169 */
<> 129:0ab6a29f35bf 1170
<> 129:0ab6a29f35bf 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
<> 129:0ab6a29f35bf 1172 */
<> 129:0ab6a29f35bf 1173 typedef struct
<> 129:0ab6a29f35bf 1174 {
<> 129:0ab6a29f35bf 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
<> 129:0ab6a29f35bf 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
<> 129:0ab6a29f35bf 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
<> 129:0ab6a29f35bf 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 129:0ab6a29f35bf 1179 } CoreDebug_Type;
<> 129:0ab6a29f35bf 1180
<> 129:0ab6a29f35bf 1181 /* Debug Halting Control and Status Register */
<> 129:0ab6a29f35bf 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
<> 129:0ab6a29f35bf 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 129:0ab6a29f35bf 1184
<> 129:0ab6a29f35bf 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 129:0ab6a29f35bf 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 129:0ab6a29f35bf 1187
<> 129:0ab6a29f35bf 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 129:0ab6a29f35bf 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 129:0ab6a29f35bf 1190
<> 129:0ab6a29f35bf 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 129:0ab6a29f35bf 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 129:0ab6a29f35bf 1193
<> 129:0ab6a29f35bf 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 129:0ab6a29f35bf 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 129:0ab6a29f35bf 1196
<> 129:0ab6a29f35bf 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
<> 129:0ab6a29f35bf 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 129:0ab6a29f35bf 1199
<> 129:0ab6a29f35bf 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 129:0ab6a29f35bf 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 129:0ab6a29f35bf 1202
<> 129:0ab6a29f35bf 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 129:0ab6a29f35bf 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 129:0ab6a29f35bf 1205
<> 129:0ab6a29f35bf 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 129:0ab6a29f35bf 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 129:0ab6a29f35bf 1208
<> 129:0ab6a29f35bf 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
<> 129:0ab6a29f35bf 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 129:0ab6a29f35bf 1211
<> 129:0ab6a29f35bf 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
<> 129:0ab6a29f35bf 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 129:0ab6a29f35bf 1214
<> 129:0ab6a29f35bf 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 129:0ab6a29f35bf 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 129:0ab6a29f35bf 1217
<> 129:0ab6a29f35bf 1218 /* Debug Core Register Selector Register */
<> 129:0ab6a29f35bf 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
<> 129:0ab6a29f35bf 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 129:0ab6a29f35bf 1221
<> 129:0ab6a29f35bf 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
<> 129:0ab6a29f35bf 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 129:0ab6a29f35bf 1224
<> 129:0ab6a29f35bf 1225 /* Debug Exception and Monitor Control Register */
<> 129:0ab6a29f35bf 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
<> 129:0ab6a29f35bf 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 129:0ab6a29f35bf 1228
<> 129:0ab6a29f35bf 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
<> 129:0ab6a29f35bf 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 129:0ab6a29f35bf 1231
<> 129:0ab6a29f35bf 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
<> 129:0ab6a29f35bf 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 129:0ab6a29f35bf 1234
<> 129:0ab6a29f35bf 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
<> 129:0ab6a29f35bf 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 129:0ab6a29f35bf 1237
<> 129:0ab6a29f35bf 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
<> 129:0ab6a29f35bf 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 129:0ab6a29f35bf 1240
<> 129:0ab6a29f35bf 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 129:0ab6a29f35bf 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 129:0ab6a29f35bf 1243
<> 129:0ab6a29f35bf 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 129:0ab6a29f35bf 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 129:0ab6a29f35bf 1246
<> 129:0ab6a29f35bf 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 129:0ab6a29f35bf 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 129:0ab6a29f35bf 1249
<> 129:0ab6a29f35bf 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 129:0ab6a29f35bf 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 129:0ab6a29f35bf 1252
<> 129:0ab6a29f35bf 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 129:0ab6a29f35bf 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 129:0ab6a29f35bf 1255
<> 129:0ab6a29f35bf 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 129:0ab6a29f35bf 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 129:0ab6a29f35bf 1258
<> 129:0ab6a29f35bf 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 129:0ab6a29f35bf 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 129:0ab6a29f35bf 1261
<> 129:0ab6a29f35bf 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 129:0ab6a29f35bf 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 129:0ab6a29f35bf 1264
<> 129:0ab6a29f35bf 1265 /*@} end of group CMSIS_CoreDebug */
<> 129:0ab6a29f35bf 1266
<> 129:0ab6a29f35bf 1267
<> 129:0ab6a29f35bf 1268 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 1269 \defgroup CMSIS_core_base Core Definitions
<> 129:0ab6a29f35bf 1270 \brief Definitions for base addresses, unions, and structures.
<> 129:0ab6a29f35bf 1271 @{
<> 129:0ab6a29f35bf 1272 */
<> 129:0ab6a29f35bf 1273
<> 129:0ab6a29f35bf 1274 /* Memory mapping of Cortex-M3 Hardware */
<> 129:0ab6a29f35bf 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 129:0ab6a29f35bf 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
<> 129:0ab6a29f35bf 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
<> 129:0ab6a29f35bf 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
<> 129:0ab6a29f35bf 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
<> 129:0ab6a29f35bf 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 129:0ab6a29f35bf 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 129:0ab6a29f35bf 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 129:0ab6a29f35bf 1283
<> 129:0ab6a29f35bf 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
<> 129:0ab6a29f35bf 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 129:0ab6a29f35bf 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 129:0ab6a29f35bf 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 129:0ab6a29f35bf 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
<> 129:0ab6a29f35bf 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
<> 129:0ab6a29f35bf 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
<> 129:0ab6a29f35bf 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 129:0ab6a29f35bf 1292
<> 129:0ab6a29f35bf 1293 #if (__MPU_PRESENT == 1)
<> 129:0ab6a29f35bf 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 129:0ab6a29f35bf 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 129:0ab6a29f35bf 1296 #endif
<> 129:0ab6a29f35bf 1297
<> 129:0ab6a29f35bf 1298 /*@} */
<> 129:0ab6a29f35bf 1299
<> 129:0ab6a29f35bf 1300
<> 129:0ab6a29f35bf 1301
<> 129:0ab6a29f35bf 1302 /*******************************************************************************
<> 129:0ab6a29f35bf 1303 * Hardware Abstraction Layer
<> 129:0ab6a29f35bf 1304 Core Function Interface contains:
<> 129:0ab6a29f35bf 1305 - Core NVIC Functions
<> 129:0ab6a29f35bf 1306 - Core SysTick Functions
<> 129:0ab6a29f35bf 1307 - Core Debug Functions
<> 129:0ab6a29f35bf 1308 - Core Register Access Functions
<> 129:0ab6a29f35bf 1309 ******************************************************************************/
<> 129:0ab6a29f35bf 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 129:0ab6a29f35bf 1311 */
<> 129:0ab6a29f35bf 1312
<> 129:0ab6a29f35bf 1313
<> 129:0ab6a29f35bf 1314
<> 129:0ab6a29f35bf 1315 /* ########################## NVIC functions #################################### */
<> 129:0ab6a29f35bf 1316 /** \ingroup CMSIS_Core_FunctionInterface
<> 129:0ab6a29f35bf 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 129:0ab6a29f35bf 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 129:0ab6a29f35bf 1319 @{
<> 129:0ab6a29f35bf 1320 */
<> 129:0ab6a29f35bf 1321
<> 129:0ab6a29f35bf 1322 /** \brief Set Priority Grouping
<> 129:0ab6a29f35bf 1323
<> 129:0ab6a29f35bf 1324 The function sets the priority grouping field using the required unlock sequence.
<> 129:0ab6a29f35bf 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<> 129:0ab6a29f35bf 1326 Only values from 0..7 are used.
<> 129:0ab6a29f35bf 1327 In case of a conflict between priority grouping and available
<> 129:0ab6a29f35bf 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 129:0ab6a29f35bf 1329
<> 129:0ab6a29f35bf 1330 \param [in] PriorityGroup Priority grouping field.
<> 129:0ab6a29f35bf 1331 */
<> 129:0ab6a29f35bf 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 129:0ab6a29f35bf 1333 {
<> 129:0ab6a29f35bf 1334 uint32_t reg_value;
<> 129:0ab6a29f35bf 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 129:0ab6a29f35bf 1336
<> 129:0ab6a29f35bf 1337 reg_value = SCB->AIRCR; /* read old register configuration */
<> 129:0ab6a29f35bf 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 129:0ab6a29f35bf 1339 reg_value = (reg_value |
<> 129:0ab6a29f35bf 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 129:0ab6a29f35bf 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<> 129:0ab6a29f35bf 1342 SCB->AIRCR = reg_value;
<> 129:0ab6a29f35bf 1343 }
<> 129:0ab6a29f35bf 1344
<> 129:0ab6a29f35bf 1345
<> 129:0ab6a29f35bf 1346 /** \brief Get Priority Grouping
<> 129:0ab6a29f35bf 1347
<> 129:0ab6a29f35bf 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
<> 129:0ab6a29f35bf 1349
<> 129:0ab6a29f35bf 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 129:0ab6a29f35bf 1351 */
<> 129:0ab6a29f35bf 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<> 129:0ab6a29f35bf 1353 {
<> 129:0ab6a29f35bf 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 129:0ab6a29f35bf 1355 }
<> 129:0ab6a29f35bf 1356
<> 129:0ab6a29f35bf 1357
<> 129:0ab6a29f35bf 1358 /** \brief Enable External Interrupt
<> 129:0ab6a29f35bf 1359
<> 129:0ab6a29f35bf 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 129:0ab6a29f35bf 1361
<> 129:0ab6a29f35bf 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 129:0ab6a29f35bf 1363 */
<> 129:0ab6a29f35bf 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1365 {
<> 129:0ab6a29f35bf 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 129:0ab6a29f35bf 1367 }
<> 129:0ab6a29f35bf 1368
<> 129:0ab6a29f35bf 1369
<> 129:0ab6a29f35bf 1370 /** \brief Disable External Interrupt
<> 129:0ab6a29f35bf 1371
<> 129:0ab6a29f35bf 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 129:0ab6a29f35bf 1373
<> 129:0ab6a29f35bf 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 129:0ab6a29f35bf 1375 */
<> 129:0ab6a29f35bf 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1377 {
<> 129:0ab6a29f35bf 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1379 __DSB();
<> 131:faff56e089b2 1380 __ISB();
<> 129:0ab6a29f35bf 1381 }
<> 129:0ab6a29f35bf 1382
<> 129:0ab6a29f35bf 1383
<> 129:0ab6a29f35bf 1384 /** \brief Get Pending Interrupt
<> 129:0ab6a29f35bf 1385
<> 129:0ab6a29f35bf 1386 The function reads the pending register in the NVIC and returns the pending bit
<> 129:0ab6a29f35bf 1387 for the specified interrupt.
<> 129:0ab6a29f35bf 1388
<> 129:0ab6a29f35bf 1389 \param [in] IRQn Interrupt number.
<> 129:0ab6a29f35bf 1390
<> 129:0ab6a29f35bf 1391 \return 0 Interrupt status is not pending.
<> 129:0ab6a29f35bf 1392 \return 1 Interrupt status is pending.
<> 129:0ab6a29f35bf 1393 */
<> 129:0ab6a29f35bf 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1395 {
<> 129:0ab6a29f35bf 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 129:0ab6a29f35bf 1397 }
<> 129:0ab6a29f35bf 1398
<> 129:0ab6a29f35bf 1399
<> 129:0ab6a29f35bf 1400 /** \brief Set Pending Interrupt
<> 129:0ab6a29f35bf 1401
<> 129:0ab6a29f35bf 1402 The function sets the pending bit of an external interrupt.
<> 129:0ab6a29f35bf 1403
<> 129:0ab6a29f35bf 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 129:0ab6a29f35bf 1405 */
<> 129:0ab6a29f35bf 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1407 {
<> 129:0ab6a29f35bf 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 129:0ab6a29f35bf 1409 }
<> 129:0ab6a29f35bf 1410
<> 129:0ab6a29f35bf 1411
<> 129:0ab6a29f35bf 1412 /** \brief Clear Pending Interrupt
<> 129:0ab6a29f35bf 1413
<> 129:0ab6a29f35bf 1414 The function clears the pending bit of an external interrupt.
<> 129:0ab6a29f35bf 1415
<> 129:0ab6a29f35bf 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 129:0ab6a29f35bf 1417 */
<> 129:0ab6a29f35bf 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1419 {
<> 129:0ab6a29f35bf 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 129:0ab6a29f35bf 1421 }
<> 129:0ab6a29f35bf 1422
<> 129:0ab6a29f35bf 1423
<> 129:0ab6a29f35bf 1424 /** \brief Get Active Interrupt
<> 129:0ab6a29f35bf 1425
<> 129:0ab6a29f35bf 1426 The function reads the active register in NVIC and returns the active bit.
<> 129:0ab6a29f35bf 1427
<> 129:0ab6a29f35bf 1428 \param [in] IRQn Interrupt number.
<> 129:0ab6a29f35bf 1429
<> 129:0ab6a29f35bf 1430 \return 0 Interrupt status is not active.
<> 129:0ab6a29f35bf 1431 \return 1 Interrupt status is active.
<> 129:0ab6a29f35bf 1432 */
<> 129:0ab6a29f35bf 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1434 {
<> 129:0ab6a29f35bf 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 129:0ab6a29f35bf 1436 }
<> 129:0ab6a29f35bf 1437
<> 129:0ab6a29f35bf 1438
<> 129:0ab6a29f35bf 1439 /** \brief Set Interrupt Priority
<> 129:0ab6a29f35bf 1440
<> 129:0ab6a29f35bf 1441 The function sets the priority of an interrupt.
<> 129:0ab6a29f35bf 1442
<> 129:0ab6a29f35bf 1443 \note The priority cannot be set for every core interrupt.
<> 129:0ab6a29f35bf 1444
<> 129:0ab6a29f35bf 1445 \param [in] IRQn Interrupt number.
<> 129:0ab6a29f35bf 1446 \param [in] priority Priority to set.
<> 129:0ab6a29f35bf 1447 */
<> 129:0ab6a29f35bf 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 129:0ab6a29f35bf 1449 {
<> 129:0ab6a29f35bf 1450 if((int32_t)IRQn < 0) {
<> 129:0ab6a29f35bf 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 129:0ab6a29f35bf 1452 }
<> 129:0ab6a29f35bf 1453 else {
<> 129:0ab6a29f35bf 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<> 129:0ab6a29f35bf 1455 }
<> 129:0ab6a29f35bf 1456 }
<> 129:0ab6a29f35bf 1457
<> 129:0ab6a29f35bf 1458
<> 129:0ab6a29f35bf 1459 /** \brief Get Interrupt Priority
<> 129:0ab6a29f35bf 1460
<> 129:0ab6a29f35bf 1461 The function reads the priority of an interrupt. The interrupt
<> 129:0ab6a29f35bf 1462 number can be positive to specify an external (device specific)
<> 129:0ab6a29f35bf 1463 interrupt, or negative to specify an internal (core) interrupt.
<> 129:0ab6a29f35bf 1464
<> 129:0ab6a29f35bf 1465
<> 129:0ab6a29f35bf 1466 \param [in] IRQn Interrupt number.
<> 129:0ab6a29f35bf 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 129:0ab6a29f35bf 1468 priority bits of the microcontroller.
<> 129:0ab6a29f35bf 1469 */
<> 129:0ab6a29f35bf 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 129:0ab6a29f35bf 1471 {
<> 129:0ab6a29f35bf 1472
<> 129:0ab6a29f35bf 1473 if((int32_t)IRQn < 0) {
<> 129:0ab6a29f35bf 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<> 129:0ab6a29f35bf 1475 }
<> 129:0ab6a29f35bf 1476 else {
<> 129:0ab6a29f35bf 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<> 129:0ab6a29f35bf 1478 }
<> 129:0ab6a29f35bf 1479 }
<> 129:0ab6a29f35bf 1480
<> 129:0ab6a29f35bf 1481
<> 129:0ab6a29f35bf 1482 /** \brief Encode Priority
<> 129:0ab6a29f35bf 1483
<> 129:0ab6a29f35bf 1484 The function encodes the priority for an interrupt with the given priority group,
<> 129:0ab6a29f35bf 1485 preemptive priority value, and subpriority value.
<> 129:0ab6a29f35bf 1486 In case of a conflict between priority grouping and available
<> 129:0ab6a29f35bf 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<> 129:0ab6a29f35bf 1488
<> 129:0ab6a29f35bf 1489 \param [in] PriorityGroup Used priority group.
<> 129:0ab6a29f35bf 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
<> 129:0ab6a29f35bf 1491 \param [in] SubPriority Subpriority value (starting from 0).
<> 129:0ab6a29f35bf 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 129:0ab6a29f35bf 1493 */
<> 129:0ab6a29f35bf 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 129:0ab6a29f35bf 1495 {
<> 129:0ab6a29f35bf 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 129:0ab6a29f35bf 1497 uint32_t PreemptPriorityBits;
<> 129:0ab6a29f35bf 1498 uint32_t SubPriorityBits;
<> 129:0ab6a29f35bf 1499
<> 129:0ab6a29f35bf 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 129:0ab6a29f35bf 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 129:0ab6a29f35bf 1502
<> 129:0ab6a29f35bf 1503 return (
<> 129:0ab6a29f35bf 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 129:0ab6a29f35bf 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 129:0ab6a29f35bf 1506 );
<> 129:0ab6a29f35bf 1507 }
<> 129:0ab6a29f35bf 1508
<> 129:0ab6a29f35bf 1509
<> 129:0ab6a29f35bf 1510 /** \brief Decode Priority
<> 129:0ab6a29f35bf 1511
<> 129:0ab6a29f35bf 1512 The function decodes an interrupt priority value with a given priority group to
<> 129:0ab6a29f35bf 1513 preemptive priority value and subpriority value.
<> 129:0ab6a29f35bf 1514 In case of a conflict between priority grouping and available
<> 129:0ab6a29f35bf 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<> 129:0ab6a29f35bf 1516
<> 129:0ab6a29f35bf 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<> 129:0ab6a29f35bf 1518 \param [in] PriorityGroup Used priority group.
<> 129:0ab6a29f35bf 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
<> 129:0ab6a29f35bf 1520 \param [out] pSubPriority Subpriority value (starting from 0).
<> 129:0ab6a29f35bf 1521 */
<> 129:0ab6a29f35bf 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 129:0ab6a29f35bf 1523 {
<> 129:0ab6a29f35bf 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 129:0ab6a29f35bf 1525 uint32_t PreemptPriorityBits;
<> 129:0ab6a29f35bf 1526 uint32_t SubPriorityBits;
<> 129:0ab6a29f35bf 1527
<> 129:0ab6a29f35bf 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 129:0ab6a29f35bf 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 129:0ab6a29f35bf 1530
<> 129:0ab6a29f35bf 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 129:0ab6a29f35bf 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 129:0ab6a29f35bf 1533 }
<> 129:0ab6a29f35bf 1534
<> 129:0ab6a29f35bf 1535
<> 129:0ab6a29f35bf 1536 /** \brief System Reset
<> 129:0ab6a29f35bf 1537
<> 129:0ab6a29f35bf 1538 The function initiates a system reset request to reset the MCU.
<> 129:0ab6a29f35bf 1539 */
<> 129:0ab6a29f35bf 1540 __STATIC_INLINE void NVIC_SystemReset(void)
<> 129:0ab6a29f35bf 1541 {
<> 129:0ab6a29f35bf 1542 __DSB(); /* Ensure all outstanding memory accesses included
<> 129:0ab6a29f35bf 1543 buffered write are completed before reset */
<> 129:0ab6a29f35bf 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 129:0ab6a29f35bf 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 129:0ab6a29f35bf 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 129:0ab6a29f35bf 1547 __DSB(); /* Ensure completion of memory access */
<> 129:0ab6a29f35bf 1548 while(1) { __NOP(); } /* wait until reset */
<> 129:0ab6a29f35bf 1549 }
<> 129:0ab6a29f35bf 1550
<> 129:0ab6a29f35bf 1551 /*@} end of CMSIS_Core_NVICFunctions */
<> 129:0ab6a29f35bf 1552
<> 129:0ab6a29f35bf 1553
<> 129:0ab6a29f35bf 1554
<> 129:0ab6a29f35bf 1555 /* ################################## SysTick function ############################################ */
<> 129:0ab6a29f35bf 1556 /** \ingroup CMSIS_Core_FunctionInterface
<> 129:0ab6a29f35bf 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 129:0ab6a29f35bf 1558 \brief Functions that configure the System.
<> 129:0ab6a29f35bf 1559 @{
<> 129:0ab6a29f35bf 1560 */
<> 129:0ab6a29f35bf 1561
<> 129:0ab6a29f35bf 1562 #if (__Vendor_SysTickConfig == 0)
<> 129:0ab6a29f35bf 1563
<> 129:0ab6a29f35bf 1564 /** \brief System Tick Configuration
<> 129:0ab6a29f35bf 1565
<> 129:0ab6a29f35bf 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 129:0ab6a29f35bf 1567 Counter is in free running mode to generate periodic interrupts.
<> 129:0ab6a29f35bf 1568
<> 129:0ab6a29f35bf 1569 \param [in] ticks Number of ticks between two interrupts.
<> 129:0ab6a29f35bf 1570
<> 129:0ab6a29f35bf 1571 \return 0 Function succeeded.
<> 129:0ab6a29f35bf 1572 \return 1 Function failed.
<> 129:0ab6a29f35bf 1573
<> 129:0ab6a29f35bf 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 129:0ab6a29f35bf 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 129:0ab6a29f35bf 1576 must contain a vendor-specific implementation of this function.
<> 129:0ab6a29f35bf 1577
<> 129:0ab6a29f35bf 1578 */
<> 129:0ab6a29f35bf 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 129:0ab6a29f35bf 1580 {
<> 129:0ab6a29f35bf 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<> 129:0ab6a29f35bf 1582
<> 129:0ab6a29f35bf 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 129:0ab6a29f35bf 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 129:0ab6a29f35bf 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 129:0ab6a29f35bf 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 129:0ab6a29f35bf 1587 SysTick_CTRL_TICKINT_Msk |
<> 129:0ab6a29f35bf 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 129:0ab6a29f35bf 1589 return (0UL); /* Function successful */
<> 129:0ab6a29f35bf 1590 }
<> 129:0ab6a29f35bf 1591
<> 129:0ab6a29f35bf 1592 #endif
<> 129:0ab6a29f35bf 1593
<> 129:0ab6a29f35bf 1594 /*@} end of CMSIS_Core_SysTickFunctions */
<> 129:0ab6a29f35bf 1595
<> 129:0ab6a29f35bf 1596
<> 129:0ab6a29f35bf 1597
<> 129:0ab6a29f35bf 1598 /* ##################################### Debug In/Output function ########################################### */
<> 129:0ab6a29f35bf 1599 /** \ingroup CMSIS_Core_FunctionInterface
<> 129:0ab6a29f35bf 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
<> 129:0ab6a29f35bf 1601 \brief Functions that access the ITM debug interface.
<> 129:0ab6a29f35bf 1602 @{
<> 129:0ab6a29f35bf 1603 */
<> 129:0ab6a29f35bf 1604
<> 129:0ab6a29f35bf 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
<> 129:0ab6a29f35bf 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 129:0ab6a29f35bf 1607
<> 129:0ab6a29f35bf 1608
<> 129:0ab6a29f35bf 1609 /** \brief ITM Send Character
<> 129:0ab6a29f35bf 1610
<> 129:0ab6a29f35bf 1611 The function transmits a character via the ITM channel 0, and
<> 129:0ab6a29f35bf 1612 \li Just returns when no debugger is connected that has booked the output.
<> 129:0ab6a29f35bf 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<> 129:0ab6a29f35bf 1614
<> 129:0ab6a29f35bf 1615 \param [in] ch Character to transmit.
<> 129:0ab6a29f35bf 1616
<> 129:0ab6a29f35bf 1617 \returns Character to transmit.
<> 129:0ab6a29f35bf 1618 */
<> 129:0ab6a29f35bf 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 129:0ab6a29f35bf 1620 {
<> 129:0ab6a29f35bf 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 129:0ab6a29f35bf 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 129:0ab6a29f35bf 1623 {
<> 129:0ab6a29f35bf 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<> 129:0ab6a29f35bf 1625 ITM->PORT[0].u8 = (uint8_t)ch;
<> 129:0ab6a29f35bf 1626 }
<> 129:0ab6a29f35bf 1627 return (ch);
<> 129:0ab6a29f35bf 1628 }
<> 129:0ab6a29f35bf 1629
<> 129:0ab6a29f35bf 1630
<> 129:0ab6a29f35bf 1631 /** \brief ITM Receive Character
<> 129:0ab6a29f35bf 1632
<> 129:0ab6a29f35bf 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
<> 129:0ab6a29f35bf 1634
<> 129:0ab6a29f35bf 1635 \return Received character.
<> 129:0ab6a29f35bf 1636 \return -1 No character pending.
<> 129:0ab6a29f35bf 1637 */
<> 129:0ab6a29f35bf 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<> 129:0ab6a29f35bf 1639 int32_t ch = -1; /* no character available */
<> 129:0ab6a29f35bf 1640
<> 129:0ab6a29f35bf 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<> 129:0ab6a29f35bf 1642 ch = ITM_RxBuffer;
<> 129:0ab6a29f35bf 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 129:0ab6a29f35bf 1644 }
<> 129:0ab6a29f35bf 1645
<> 129:0ab6a29f35bf 1646 return (ch);
<> 129:0ab6a29f35bf 1647 }
<> 129:0ab6a29f35bf 1648
<> 129:0ab6a29f35bf 1649
<> 129:0ab6a29f35bf 1650 /** \brief ITM Check Character
<> 129:0ab6a29f35bf 1651
<> 129:0ab6a29f35bf 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<> 129:0ab6a29f35bf 1653
<> 129:0ab6a29f35bf 1654 \return 0 No character available.
<> 129:0ab6a29f35bf 1655 \return 1 Character available.
<> 129:0ab6a29f35bf 1656 */
<> 129:0ab6a29f35bf 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
<> 129:0ab6a29f35bf 1658
<> 129:0ab6a29f35bf 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<> 129:0ab6a29f35bf 1660 return (0); /* no character available */
<> 129:0ab6a29f35bf 1661 } else {
<> 129:0ab6a29f35bf 1662 return (1); /* character available */
<> 129:0ab6a29f35bf 1663 }
<> 129:0ab6a29f35bf 1664 }
<> 129:0ab6a29f35bf 1665
<> 129:0ab6a29f35bf 1666 /*@} end of CMSIS_core_DebugFunctions */
<> 129:0ab6a29f35bf 1667
<> 129:0ab6a29f35bf 1668
<> 129:0ab6a29f35bf 1669
<> 129:0ab6a29f35bf 1670
<> 129:0ab6a29f35bf 1671 #ifdef __cplusplus
<> 129:0ab6a29f35bf 1672 }
<> 129:0ab6a29f35bf 1673 #endif
<> 129:0ab6a29f35bf 1674
<> 129:0ab6a29f35bf 1675 #endif /* __CORE_SC300_H_DEPENDANT */
<> 129:0ab6a29f35bf 1676
<> 129:0ab6a29f35bf 1677 #endif /* __CMSIS_GENERIC */