mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32625MBED/core_cmSimd.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
129:0ab6a29f35bf 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 /**************************************************************************//**
<> 129:0ab6a29f35bf 2 * @file core_cmSimd.h
<> 129:0ab6a29f35bf 3 * @brief CMSIS Cortex-M SIMD Header File
<> 129:0ab6a29f35bf 4 * @version V4.10
<> 129:0ab6a29f35bf 5 * @date 18. March 2015
<> 129:0ab6a29f35bf 6 *
<> 129:0ab6a29f35bf 7 * @note
<> 129:0ab6a29f35bf 8 *
<> 129:0ab6a29f35bf 9 ******************************************************************************/
<> 129:0ab6a29f35bf 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 129:0ab6a29f35bf 11
<> 129:0ab6a29f35bf 12 All rights reserved.
<> 129:0ab6a29f35bf 13 Redistribution and use in source and binary forms, with or without
<> 129:0ab6a29f35bf 14 modification, are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 15 - Redistributions of source code must retain the above copyright
<> 129:0ab6a29f35bf 16 notice, this list of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 17 - Redistributions in binary form must reproduce the above copyright
<> 129:0ab6a29f35bf 18 notice, this list of conditions and the following disclaimer in the
<> 129:0ab6a29f35bf 19 documentation and/or other materials provided with the distribution.
<> 129:0ab6a29f35bf 20 - Neither the name of ARM nor the names of its contributors may be used
<> 129:0ab6a29f35bf 21 to endorse or promote products derived from this software without
<> 129:0ab6a29f35bf 22 specific prior written permission.
<> 129:0ab6a29f35bf 23 *
<> 129:0ab6a29f35bf 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 129:0ab6a29f35bf 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 129:0ab6a29f35bf 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 129:0ab6a29f35bf 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 129:0ab6a29f35bf 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 129:0ab6a29f35bf 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 129:0ab6a29f35bf 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 129:0ab6a29f35bf 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 129:0ab6a29f35bf 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 129:0ab6a29f35bf 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 129:0ab6a29f35bf 34 POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 35 ---------------------------------------------------------------------------*/
<> 129:0ab6a29f35bf 36
<> 129:0ab6a29f35bf 37
<> 129:0ab6a29f35bf 38 #if defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 129:0ab6a29f35bf 40 #endif
<> 129:0ab6a29f35bf 41
<> 129:0ab6a29f35bf 42 #ifndef __CORE_CMSIMD_H
<> 129:0ab6a29f35bf 43 #define __CORE_CMSIMD_H
<> 129:0ab6a29f35bf 44
<> 129:0ab6a29f35bf 45 #ifdef __cplusplus
<> 129:0ab6a29f35bf 46 extern "C" {
<> 129:0ab6a29f35bf 47 #endif
<> 129:0ab6a29f35bf 48
<> 129:0ab6a29f35bf 49
<> 129:0ab6a29f35bf 50 /*******************************************************************************
<> 129:0ab6a29f35bf 51 * Hardware Abstraction Layer
<> 129:0ab6a29f35bf 52 ******************************************************************************/
<> 129:0ab6a29f35bf 53
<> 129:0ab6a29f35bf 54
<> 129:0ab6a29f35bf 55 /* ################### Compiler specific Intrinsics ########################### */
<> 129:0ab6a29f35bf 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 129:0ab6a29f35bf 57 Access to dedicated SIMD instructions
<> 129:0ab6a29f35bf 58 @{
<> 129:0ab6a29f35bf 59 */
<> 129:0ab6a29f35bf 60
<> 129:0ab6a29f35bf 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 129:0ab6a29f35bf 62 /* ARM armcc specific functions */
<> 129:0ab6a29f35bf 63 #define __SADD8 __sadd8
<> 129:0ab6a29f35bf 64 #define __QADD8 __qadd8
<> 129:0ab6a29f35bf 65 #define __SHADD8 __shadd8
<> 129:0ab6a29f35bf 66 #define __UADD8 __uadd8
<> 129:0ab6a29f35bf 67 #define __UQADD8 __uqadd8
<> 129:0ab6a29f35bf 68 #define __UHADD8 __uhadd8
<> 129:0ab6a29f35bf 69 #define __SSUB8 __ssub8
<> 129:0ab6a29f35bf 70 #define __QSUB8 __qsub8
<> 129:0ab6a29f35bf 71 #define __SHSUB8 __shsub8
<> 129:0ab6a29f35bf 72 #define __USUB8 __usub8
<> 129:0ab6a29f35bf 73 #define __UQSUB8 __uqsub8
<> 129:0ab6a29f35bf 74 #define __UHSUB8 __uhsub8
<> 129:0ab6a29f35bf 75 #define __SADD16 __sadd16
<> 129:0ab6a29f35bf 76 #define __QADD16 __qadd16
<> 129:0ab6a29f35bf 77 #define __SHADD16 __shadd16
<> 129:0ab6a29f35bf 78 #define __UADD16 __uadd16
<> 129:0ab6a29f35bf 79 #define __UQADD16 __uqadd16
<> 129:0ab6a29f35bf 80 #define __UHADD16 __uhadd16
<> 129:0ab6a29f35bf 81 #define __SSUB16 __ssub16
<> 129:0ab6a29f35bf 82 #define __QSUB16 __qsub16
<> 129:0ab6a29f35bf 83 #define __SHSUB16 __shsub16
<> 129:0ab6a29f35bf 84 #define __USUB16 __usub16
<> 129:0ab6a29f35bf 85 #define __UQSUB16 __uqsub16
<> 129:0ab6a29f35bf 86 #define __UHSUB16 __uhsub16
<> 129:0ab6a29f35bf 87 #define __SASX __sasx
<> 129:0ab6a29f35bf 88 #define __QASX __qasx
<> 129:0ab6a29f35bf 89 #define __SHASX __shasx
<> 129:0ab6a29f35bf 90 #define __UASX __uasx
<> 129:0ab6a29f35bf 91 #define __UQASX __uqasx
<> 129:0ab6a29f35bf 92 #define __UHASX __uhasx
<> 129:0ab6a29f35bf 93 #define __SSAX __ssax
<> 129:0ab6a29f35bf 94 #define __QSAX __qsax
<> 129:0ab6a29f35bf 95 #define __SHSAX __shsax
<> 129:0ab6a29f35bf 96 #define __USAX __usax
<> 129:0ab6a29f35bf 97 #define __UQSAX __uqsax
<> 129:0ab6a29f35bf 98 #define __UHSAX __uhsax
<> 129:0ab6a29f35bf 99 #define __USAD8 __usad8
<> 129:0ab6a29f35bf 100 #define __USADA8 __usada8
<> 129:0ab6a29f35bf 101 #define __SSAT16 __ssat16
<> 129:0ab6a29f35bf 102 #define __USAT16 __usat16
<> 129:0ab6a29f35bf 103 #define __UXTB16 __uxtb16
<> 129:0ab6a29f35bf 104 #define __UXTAB16 __uxtab16
<> 129:0ab6a29f35bf 105 #define __SXTB16 __sxtb16
<> 129:0ab6a29f35bf 106 #define __SXTAB16 __sxtab16
<> 129:0ab6a29f35bf 107 #define __SMUAD __smuad
<> 129:0ab6a29f35bf 108 #define __SMUADX __smuadx
<> 129:0ab6a29f35bf 109 #define __SMLAD __smlad
<> 129:0ab6a29f35bf 110 #define __SMLADX __smladx
<> 129:0ab6a29f35bf 111 #define __SMLALD __smlald
<> 129:0ab6a29f35bf 112 #define __SMLALDX __smlaldx
<> 129:0ab6a29f35bf 113 #define __SMUSD __smusd
<> 129:0ab6a29f35bf 114 #define __SMUSDX __smusdx
<> 129:0ab6a29f35bf 115 #define __SMLSD __smlsd
<> 129:0ab6a29f35bf 116 #define __SMLSDX __smlsdx
<> 129:0ab6a29f35bf 117 #define __SMLSLD __smlsld
<> 129:0ab6a29f35bf 118 #define __SMLSLDX __smlsldx
<> 129:0ab6a29f35bf 119 #define __SEL __sel
<> 129:0ab6a29f35bf 120 #define __QADD __qadd
<> 129:0ab6a29f35bf 121 #define __QSUB __qsub
<> 129:0ab6a29f35bf 122
<> 129:0ab6a29f35bf 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 129:0ab6a29f35bf 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 129:0ab6a29f35bf 125
<> 129:0ab6a29f35bf 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 129:0ab6a29f35bf 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 129:0ab6a29f35bf 128
<> 129:0ab6a29f35bf 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 129:0ab6a29f35bf 130 ((int64_t)(ARG3) << 32) ) >> 32))
<> 129:0ab6a29f35bf 131
<> 129:0ab6a29f35bf 132
<> 129:0ab6a29f35bf 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 129:0ab6a29f35bf 134 /* GNU gcc specific functions */
<> 129:0ab6a29f35bf 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 136 {
<> 129:0ab6a29f35bf 137 uint32_t result;
<> 129:0ab6a29f35bf 138
<> 129:0ab6a29f35bf 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 140 return(result);
<> 129:0ab6a29f35bf 141 }
<> 129:0ab6a29f35bf 142
<> 129:0ab6a29f35bf 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 144 {
<> 129:0ab6a29f35bf 145 uint32_t result;
<> 129:0ab6a29f35bf 146
<> 129:0ab6a29f35bf 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 148 return(result);
<> 129:0ab6a29f35bf 149 }
<> 129:0ab6a29f35bf 150
<> 129:0ab6a29f35bf 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 152 {
<> 129:0ab6a29f35bf 153 uint32_t result;
<> 129:0ab6a29f35bf 154
<> 129:0ab6a29f35bf 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 156 return(result);
<> 129:0ab6a29f35bf 157 }
<> 129:0ab6a29f35bf 158
<> 129:0ab6a29f35bf 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 160 {
<> 129:0ab6a29f35bf 161 uint32_t result;
<> 129:0ab6a29f35bf 162
<> 129:0ab6a29f35bf 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 164 return(result);
<> 129:0ab6a29f35bf 165 }
<> 129:0ab6a29f35bf 166
<> 129:0ab6a29f35bf 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 168 {
<> 129:0ab6a29f35bf 169 uint32_t result;
<> 129:0ab6a29f35bf 170
<> 129:0ab6a29f35bf 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 172 return(result);
<> 129:0ab6a29f35bf 173 }
<> 129:0ab6a29f35bf 174
<> 129:0ab6a29f35bf 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 176 {
<> 129:0ab6a29f35bf 177 uint32_t result;
<> 129:0ab6a29f35bf 178
<> 129:0ab6a29f35bf 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 180 return(result);
<> 129:0ab6a29f35bf 181 }
<> 129:0ab6a29f35bf 182
<> 129:0ab6a29f35bf 183
<> 129:0ab6a29f35bf 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 185 {
<> 129:0ab6a29f35bf 186 uint32_t result;
<> 129:0ab6a29f35bf 187
<> 129:0ab6a29f35bf 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 189 return(result);
<> 129:0ab6a29f35bf 190 }
<> 129:0ab6a29f35bf 191
<> 129:0ab6a29f35bf 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 193 {
<> 129:0ab6a29f35bf 194 uint32_t result;
<> 129:0ab6a29f35bf 195
<> 129:0ab6a29f35bf 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 197 return(result);
<> 129:0ab6a29f35bf 198 }
<> 129:0ab6a29f35bf 199
<> 129:0ab6a29f35bf 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 201 {
<> 129:0ab6a29f35bf 202 uint32_t result;
<> 129:0ab6a29f35bf 203
<> 129:0ab6a29f35bf 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 205 return(result);
<> 129:0ab6a29f35bf 206 }
<> 129:0ab6a29f35bf 207
<> 129:0ab6a29f35bf 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 209 {
<> 129:0ab6a29f35bf 210 uint32_t result;
<> 129:0ab6a29f35bf 211
<> 129:0ab6a29f35bf 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 213 return(result);
<> 129:0ab6a29f35bf 214 }
<> 129:0ab6a29f35bf 215
<> 129:0ab6a29f35bf 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 217 {
<> 129:0ab6a29f35bf 218 uint32_t result;
<> 129:0ab6a29f35bf 219
<> 129:0ab6a29f35bf 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 221 return(result);
<> 129:0ab6a29f35bf 222 }
<> 129:0ab6a29f35bf 223
<> 129:0ab6a29f35bf 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 225 {
<> 129:0ab6a29f35bf 226 uint32_t result;
<> 129:0ab6a29f35bf 227
<> 129:0ab6a29f35bf 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 229 return(result);
<> 129:0ab6a29f35bf 230 }
<> 129:0ab6a29f35bf 231
<> 129:0ab6a29f35bf 232
<> 129:0ab6a29f35bf 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 234 {
<> 129:0ab6a29f35bf 235 uint32_t result;
<> 129:0ab6a29f35bf 236
<> 129:0ab6a29f35bf 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 238 return(result);
<> 129:0ab6a29f35bf 239 }
<> 129:0ab6a29f35bf 240
<> 129:0ab6a29f35bf 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 242 {
<> 129:0ab6a29f35bf 243 uint32_t result;
<> 129:0ab6a29f35bf 244
<> 129:0ab6a29f35bf 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 246 return(result);
<> 129:0ab6a29f35bf 247 }
<> 129:0ab6a29f35bf 248
<> 129:0ab6a29f35bf 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 250 {
<> 129:0ab6a29f35bf 251 uint32_t result;
<> 129:0ab6a29f35bf 252
<> 129:0ab6a29f35bf 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 254 return(result);
<> 129:0ab6a29f35bf 255 }
<> 129:0ab6a29f35bf 256
<> 129:0ab6a29f35bf 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 258 {
<> 129:0ab6a29f35bf 259 uint32_t result;
<> 129:0ab6a29f35bf 260
<> 129:0ab6a29f35bf 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 262 return(result);
<> 129:0ab6a29f35bf 263 }
<> 129:0ab6a29f35bf 264
<> 129:0ab6a29f35bf 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 266 {
<> 129:0ab6a29f35bf 267 uint32_t result;
<> 129:0ab6a29f35bf 268
<> 129:0ab6a29f35bf 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 270 return(result);
<> 129:0ab6a29f35bf 271 }
<> 129:0ab6a29f35bf 272
<> 129:0ab6a29f35bf 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 274 {
<> 129:0ab6a29f35bf 275 uint32_t result;
<> 129:0ab6a29f35bf 276
<> 129:0ab6a29f35bf 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 278 return(result);
<> 129:0ab6a29f35bf 279 }
<> 129:0ab6a29f35bf 280
<> 129:0ab6a29f35bf 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 282 {
<> 129:0ab6a29f35bf 283 uint32_t result;
<> 129:0ab6a29f35bf 284
<> 129:0ab6a29f35bf 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 286 return(result);
<> 129:0ab6a29f35bf 287 }
<> 129:0ab6a29f35bf 288
<> 129:0ab6a29f35bf 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 290 {
<> 129:0ab6a29f35bf 291 uint32_t result;
<> 129:0ab6a29f35bf 292
<> 129:0ab6a29f35bf 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 294 return(result);
<> 129:0ab6a29f35bf 295 }
<> 129:0ab6a29f35bf 296
<> 129:0ab6a29f35bf 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 298 {
<> 129:0ab6a29f35bf 299 uint32_t result;
<> 129:0ab6a29f35bf 300
<> 129:0ab6a29f35bf 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 302 return(result);
<> 129:0ab6a29f35bf 303 }
<> 129:0ab6a29f35bf 304
<> 129:0ab6a29f35bf 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 306 {
<> 129:0ab6a29f35bf 307 uint32_t result;
<> 129:0ab6a29f35bf 308
<> 129:0ab6a29f35bf 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 310 return(result);
<> 129:0ab6a29f35bf 311 }
<> 129:0ab6a29f35bf 312
<> 129:0ab6a29f35bf 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 314 {
<> 129:0ab6a29f35bf 315 uint32_t result;
<> 129:0ab6a29f35bf 316
<> 129:0ab6a29f35bf 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 318 return(result);
<> 129:0ab6a29f35bf 319 }
<> 129:0ab6a29f35bf 320
<> 129:0ab6a29f35bf 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 322 {
<> 129:0ab6a29f35bf 323 uint32_t result;
<> 129:0ab6a29f35bf 324
<> 129:0ab6a29f35bf 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 326 return(result);
<> 129:0ab6a29f35bf 327 }
<> 129:0ab6a29f35bf 328
<> 129:0ab6a29f35bf 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 330 {
<> 129:0ab6a29f35bf 331 uint32_t result;
<> 129:0ab6a29f35bf 332
<> 129:0ab6a29f35bf 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 334 return(result);
<> 129:0ab6a29f35bf 335 }
<> 129:0ab6a29f35bf 336
<> 129:0ab6a29f35bf 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 338 {
<> 129:0ab6a29f35bf 339 uint32_t result;
<> 129:0ab6a29f35bf 340
<> 129:0ab6a29f35bf 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 342 return(result);
<> 129:0ab6a29f35bf 343 }
<> 129:0ab6a29f35bf 344
<> 129:0ab6a29f35bf 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 346 {
<> 129:0ab6a29f35bf 347 uint32_t result;
<> 129:0ab6a29f35bf 348
<> 129:0ab6a29f35bf 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 350 return(result);
<> 129:0ab6a29f35bf 351 }
<> 129:0ab6a29f35bf 352
<> 129:0ab6a29f35bf 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 354 {
<> 129:0ab6a29f35bf 355 uint32_t result;
<> 129:0ab6a29f35bf 356
<> 129:0ab6a29f35bf 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 358 return(result);
<> 129:0ab6a29f35bf 359 }
<> 129:0ab6a29f35bf 360
<> 129:0ab6a29f35bf 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 362 {
<> 129:0ab6a29f35bf 363 uint32_t result;
<> 129:0ab6a29f35bf 364
<> 129:0ab6a29f35bf 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 366 return(result);
<> 129:0ab6a29f35bf 367 }
<> 129:0ab6a29f35bf 368
<> 129:0ab6a29f35bf 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 370 {
<> 129:0ab6a29f35bf 371 uint32_t result;
<> 129:0ab6a29f35bf 372
<> 129:0ab6a29f35bf 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 374 return(result);
<> 129:0ab6a29f35bf 375 }
<> 129:0ab6a29f35bf 376
<> 129:0ab6a29f35bf 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 378 {
<> 129:0ab6a29f35bf 379 uint32_t result;
<> 129:0ab6a29f35bf 380
<> 129:0ab6a29f35bf 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 382 return(result);
<> 129:0ab6a29f35bf 383 }
<> 129:0ab6a29f35bf 384
<> 129:0ab6a29f35bf 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 386 {
<> 129:0ab6a29f35bf 387 uint32_t result;
<> 129:0ab6a29f35bf 388
<> 129:0ab6a29f35bf 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 390 return(result);
<> 129:0ab6a29f35bf 391 }
<> 129:0ab6a29f35bf 392
<> 129:0ab6a29f35bf 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 394 {
<> 129:0ab6a29f35bf 395 uint32_t result;
<> 129:0ab6a29f35bf 396
<> 129:0ab6a29f35bf 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 398 return(result);
<> 129:0ab6a29f35bf 399 }
<> 129:0ab6a29f35bf 400
<> 129:0ab6a29f35bf 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 402 {
<> 129:0ab6a29f35bf 403 uint32_t result;
<> 129:0ab6a29f35bf 404
<> 129:0ab6a29f35bf 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 406 return(result);
<> 129:0ab6a29f35bf 407 }
<> 129:0ab6a29f35bf 408
<> 129:0ab6a29f35bf 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 410 {
<> 129:0ab6a29f35bf 411 uint32_t result;
<> 129:0ab6a29f35bf 412
<> 129:0ab6a29f35bf 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 414 return(result);
<> 129:0ab6a29f35bf 415 }
<> 129:0ab6a29f35bf 416
<> 129:0ab6a29f35bf 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 418 {
<> 129:0ab6a29f35bf 419 uint32_t result;
<> 129:0ab6a29f35bf 420
<> 129:0ab6a29f35bf 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 422 return(result);
<> 129:0ab6a29f35bf 423 }
<> 129:0ab6a29f35bf 424
<> 129:0ab6a29f35bf 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 426 {
<> 129:0ab6a29f35bf 427 uint32_t result;
<> 129:0ab6a29f35bf 428
<> 129:0ab6a29f35bf 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 430 return(result);
<> 129:0ab6a29f35bf 431 }
<> 129:0ab6a29f35bf 432
<> 129:0ab6a29f35bf 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 129:0ab6a29f35bf 434 {
<> 129:0ab6a29f35bf 435 uint32_t result;
<> 129:0ab6a29f35bf 436
<> 129:0ab6a29f35bf 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 438 return(result);
<> 129:0ab6a29f35bf 439 }
<> 129:0ab6a29f35bf 440
<> 129:0ab6a29f35bf 441 #define __SSAT16(ARG1,ARG2) \
<> 129:0ab6a29f35bf 442 ({ \
<> 129:0ab6a29f35bf 443 uint32_t __RES, __ARG1 = (ARG1); \
<> 129:0ab6a29f35bf 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 129:0ab6a29f35bf 445 __RES; \
<> 129:0ab6a29f35bf 446 })
<> 129:0ab6a29f35bf 447
<> 129:0ab6a29f35bf 448 #define __USAT16(ARG1,ARG2) \
<> 129:0ab6a29f35bf 449 ({ \
<> 129:0ab6a29f35bf 450 uint32_t __RES, __ARG1 = (ARG1); \
<> 129:0ab6a29f35bf 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 129:0ab6a29f35bf 452 __RES; \
<> 129:0ab6a29f35bf 453 })
<> 129:0ab6a29f35bf 454
<> 129:0ab6a29f35bf 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 129:0ab6a29f35bf 456 {
<> 129:0ab6a29f35bf 457 uint32_t result;
<> 129:0ab6a29f35bf 458
<> 129:0ab6a29f35bf 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 129:0ab6a29f35bf 460 return(result);
<> 129:0ab6a29f35bf 461 }
<> 129:0ab6a29f35bf 462
<> 129:0ab6a29f35bf 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 464 {
<> 129:0ab6a29f35bf 465 uint32_t result;
<> 129:0ab6a29f35bf 466
<> 129:0ab6a29f35bf 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 468 return(result);
<> 129:0ab6a29f35bf 469 }
<> 129:0ab6a29f35bf 470
<> 129:0ab6a29f35bf 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 129:0ab6a29f35bf 472 {
<> 129:0ab6a29f35bf 473 uint32_t result;
<> 129:0ab6a29f35bf 474
<> 129:0ab6a29f35bf 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 129:0ab6a29f35bf 476 return(result);
<> 129:0ab6a29f35bf 477 }
<> 129:0ab6a29f35bf 478
<> 129:0ab6a29f35bf 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 480 {
<> 129:0ab6a29f35bf 481 uint32_t result;
<> 129:0ab6a29f35bf 482
<> 129:0ab6a29f35bf 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 484 return(result);
<> 129:0ab6a29f35bf 485 }
<> 129:0ab6a29f35bf 486
<> 129:0ab6a29f35bf 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 488 {
<> 129:0ab6a29f35bf 489 uint32_t result;
<> 129:0ab6a29f35bf 490
<> 129:0ab6a29f35bf 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 492 return(result);
<> 129:0ab6a29f35bf 493 }
<> 129:0ab6a29f35bf 494
<> 129:0ab6a29f35bf 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 496 {
<> 129:0ab6a29f35bf 497 uint32_t result;
<> 129:0ab6a29f35bf 498
<> 129:0ab6a29f35bf 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 500 return(result);
<> 129:0ab6a29f35bf 501 }
<> 129:0ab6a29f35bf 502
<> 129:0ab6a29f35bf 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 129:0ab6a29f35bf 504 {
<> 129:0ab6a29f35bf 505 uint32_t result;
<> 129:0ab6a29f35bf 506
<> 129:0ab6a29f35bf 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 508 return(result);
<> 129:0ab6a29f35bf 509 }
<> 129:0ab6a29f35bf 510
<> 129:0ab6a29f35bf 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 129:0ab6a29f35bf 512 {
<> 129:0ab6a29f35bf 513 uint32_t result;
<> 129:0ab6a29f35bf 514
<> 129:0ab6a29f35bf 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 516 return(result);
<> 129:0ab6a29f35bf 517 }
<> 129:0ab6a29f35bf 518
<> 129:0ab6a29f35bf 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 129:0ab6a29f35bf 520 {
<> 129:0ab6a29f35bf 521 union llreg_u{
<> 129:0ab6a29f35bf 522 uint32_t w32[2];
<> 129:0ab6a29f35bf 523 uint64_t w64;
<> 129:0ab6a29f35bf 524 } llr;
<> 129:0ab6a29f35bf 525 llr.w64 = acc;
<> 129:0ab6a29f35bf 526
<> 129:0ab6a29f35bf 527 #ifndef __ARMEB__ // Little endian
<> 129:0ab6a29f35bf 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 129:0ab6a29f35bf 529 #else // Big endian
<> 129:0ab6a29f35bf 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 129:0ab6a29f35bf 531 #endif
<> 129:0ab6a29f35bf 532
<> 129:0ab6a29f35bf 533 return(llr.w64);
<> 129:0ab6a29f35bf 534 }
<> 129:0ab6a29f35bf 535
<> 129:0ab6a29f35bf 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 129:0ab6a29f35bf 537 {
<> 129:0ab6a29f35bf 538 union llreg_u{
<> 129:0ab6a29f35bf 539 uint32_t w32[2];
<> 129:0ab6a29f35bf 540 uint64_t w64;
<> 129:0ab6a29f35bf 541 } llr;
<> 129:0ab6a29f35bf 542 llr.w64 = acc;
<> 129:0ab6a29f35bf 543
<> 129:0ab6a29f35bf 544 #ifndef __ARMEB__ // Little endian
<> 129:0ab6a29f35bf 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 129:0ab6a29f35bf 546 #else // Big endian
<> 129:0ab6a29f35bf 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 129:0ab6a29f35bf 548 #endif
<> 129:0ab6a29f35bf 549
<> 129:0ab6a29f35bf 550 return(llr.w64);
<> 129:0ab6a29f35bf 551 }
<> 129:0ab6a29f35bf 552
<> 129:0ab6a29f35bf 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 554 {
<> 129:0ab6a29f35bf 555 uint32_t result;
<> 129:0ab6a29f35bf 556
<> 129:0ab6a29f35bf 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 558 return(result);
<> 129:0ab6a29f35bf 559 }
<> 129:0ab6a29f35bf 560
<> 129:0ab6a29f35bf 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 562 {
<> 129:0ab6a29f35bf 563 uint32_t result;
<> 129:0ab6a29f35bf 564
<> 129:0ab6a29f35bf 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 566 return(result);
<> 129:0ab6a29f35bf 567 }
<> 129:0ab6a29f35bf 568
<> 129:0ab6a29f35bf 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 129:0ab6a29f35bf 570 {
<> 129:0ab6a29f35bf 571 uint32_t result;
<> 129:0ab6a29f35bf 572
<> 129:0ab6a29f35bf 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 574 return(result);
<> 129:0ab6a29f35bf 575 }
<> 129:0ab6a29f35bf 576
<> 129:0ab6a29f35bf 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 129:0ab6a29f35bf 578 {
<> 129:0ab6a29f35bf 579 uint32_t result;
<> 129:0ab6a29f35bf 580
<> 129:0ab6a29f35bf 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 582 return(result);
<> 129:0ab6a29f35bf 583 }
<> 129:0ab6a29f35bf 584
<> 129:0ab6a29f35bf 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 129:0ab6a29f35bf 586 {
<> 129:0ab6a29f35bf 587 union llreg_u{
<> 129:0ab6a29f35bf 588 uint32_t w32[2];
<> 129:0ab6a29f35bf 589 uint64_t w64;
<> 129:0ab6a29f35bf 590 } llr;
<> 129:0ab6a29f35bf 591 llr.w64 = acc;
<> 129:0ab6a29f35bf 592
<> 129:0ab6a29f35bf 593 #ifndef __ARMEB__ // Little endian
<> 129:0ab6a29f35bf 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 129:0ab6a29f35bf 595 #else // Big endian
<> 129:0ab6a29f35bf 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 129:0ab6a29f35bf 597 #endif
<> 129:0ab6a29f35bf 598
<> 129:0ab6a29f35bf 599 return(llr.w64);
<> 129:0ab6a29f35bf 600 }
<> 129:0ab6a29f35bf 601
<> 129:0ab6a29f35bf 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 129:0ab6a29f35bf 603 {
<> 129:0ab6a29f35bf 604 union llreg_u{
<> 129:0ab6a29f35bf 605 uint32_t w32[2];
<> 129:0ab6a29f35bf 606 uint64_t w64;
<> 129:0ab6a29f35bf 607 } llr;
<> 129:0ab6a29f35bf 608 llr.w64 = acc;
<> 129:0ab6a29f35bf 609
<> 129:0ab6a29f35bf 610 #ifndef __ARMEB__ // Little endian
<> 129:0ab6a29f35bf 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 129:0ab6a29f35bf 612 #else // Big endian
<> 129:0ab6a29f35bf 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 129:0ab6a29f35bf 614 #endif
<> 129:0ab6a29f35bf 615
<> 129:0ab6a29f35bf 616 return(llr.w64);
<> 129:0ab6a29f35bf 617 }
<> 129:0ab6a29f35bf 618
<> 129:0ab6a29f35bf 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 620 {
<> 129:0ab6a29f35bf 621 uint32_t result;
<> 129:0ab6a29f35bf 622
<> 129:0ab6a29f35bf 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 624 return(result);
<> 129:0ab6a29f35bf 625 }
<> 129:0ab6a29f35bf 626
<> 129:0ab6a29f35bf 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 628 {
<> 129:0ab6a29f35bf 629 uint32_t result;
<> 129:0ab6a29f35bf 630
<> 129:0ab6a29f35bf 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 632 return(result);
<> 129:0ab6a29f35bf 633 }
<> 129:0ab6a29f35bf 634
<> 129:0ab6a29f35bf 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 129:0ab6a29f35bf 636 {
<> 129:0ab6a29f35bf 637 uint32_t result;
<> 129:0ab6a29f35bf 638
<> 129:0ab6a29f35bf 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 129:0ab6a29f35bf 640 return(result);
<> 129:0ab6a29f35bf 641 }
<> 129:0ab6a29f35bf 642
<> 129:0ab6a29f35bf 643 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 129:0ab6a29f35bf 644 ({ \
<> 129:0ab6a29f35bf 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 129:0ab6a29f35bf 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 129:0ab6a29f35bf 647 __RES; \
<> 129:0ab6a29f35bf 648 })
<> 129:0ab6a29f35bf 649
<> 129:0ab6a29f35bf 650 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 129:0ab6a29f35bf 651 ({ \
<> 129:0ab6a29f35bf 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 129:0ab6a29f35bf 653 if (ARG3 == 0) \
<> 129:0ab6a29f35bf 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 129:0ab6a29f35bf 655 else \
<> 129:0ab6a29f35bf 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 129:0ab6a29f35bf 657 __RES; \
<> 129:0ab6a29f35bf 658 })
<> 129:0ab6a29f35bf 659
<> 129:0ab6a29f35bf 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 129:0ab6a29f35bf 661 {
<> 129:0ab6a29f35bf 662 int32_t result;
<> 129:0ab6a29f35bf 663
<> 129:0ab6a29f35bf 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 129:0ab6a29f35bf 665 return(result);
<> 129:0ab6a29f35bf 666 }
<> 129:0ab6a29f35bf 667
<> 129:0ab6a29f35bf 668
<> 129:0ab6a29f35bf 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 129:0ab6a29f35bf 670 /* IAR iccarm specific functions */
<> 129:0ab6a29f35bf 671 #include <cmsis_iar.h>
<> 129:0ab6a29f35bf 672
<> 129:0ab6a29f35bf 673
<> 129:0ab6a29f35bf 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 129:0ab6a29f35bf 675 /* TI CCS specific functions */
<> 129:0ab6a29f35bf 676 #include <cmsis_ccs.h>
<> 129:0ab6a29f35bf 677
<> 129:0ab6a29f35bf 678
<> 129:0ab6a29f35bf 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 129:0ab6a29f35bf 680 /* TASKING carm specific functions */
<> 129:0ab6a29f35bf 681 /* not yet supported */
<> 129:0ab6a29f35bf 682
<> 129:0ab6a29f35bf 683
<> 129:0ab6a29f35bf 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 129:0ab6a29f35bf 685 /* Cosmic specific functions */
<> 129:0ab6a29f35bf 686 #include <cmsis_csm.h>
<> 129:0ab6a29f35bf 687
<> 129:0ab6a29f35bf 688 #endif
<> 129:0ab6a29f35bf 689
<> 129:0ab6a29f35bf 690 /*@} end of group CMSIS_SIMD_intrinsics */
<> 129:0ab6a29f35bf 691
<> 129:0ab6a29f35bf 692
<> 129:0ab6a29f35bf 693 #ifdef __cplusplus
<> 129:0ab6a29f35bf 694 }
<> 129:0ab6a29f35bf 695 #endif
<> 129:0ab6a29f35bf 696
<> 129:0ab6a29f35bf 697 #endif /* __CORE_CMSIMD_H */