mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KL46Z/core_cm0.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 73:1efda918f0ba 1 /**************************************************************************//**
bogdanm 73:1efda918f0ba 2 * @file core_cm0.h
bogdanm 73:1efda918f0ba 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 73:1efda918f0ba 6 *
bogdanm 73:1efda918f0ba 7 * @note
bogdanm 73:1efda918f0ba 8 *
bogdanm 73:1efda918f0ba 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 73:1efda918f0ba 11
bogdanm 73:1efda918f0ba 12 All rights reserved.
bogdanm 73:1efda918f0ba 13 Redistribution and use in source and binary forms, with or without
bogdanm 73:1efda918f0ba 14 modification, are permitted provided that the following conditions are met:
bogdanm 73:1efda918f0ba 15 - Redistributions of source code must retain the above copyright
bogdanm 73:1efda918f0ba 16 notice, this list of conditions and the following disclaimer.
bogdanm 73:1efda918f0ba 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 73:1efda918f0ba 18 notice, this list of conditions and the following disclaimer in the
bogdanm 73:1efda918f0ba 19 documentation and/or other materials provided with the distribution.
bogdanm 73:1efda918f0ba 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 73:1efda918f0ba 21 to endorse or promote products derived from this software without
bogdanm 73:1efda918f0ba 22 specific prior written permission.
bogdanm 73:1efda918f0ba 23 *
bogdanm 73:1efda918f0ba 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 73:1efda918f0ba 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 73:1efda918f0ba 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 73:1efda918f0ba 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 73:1efda918f0ba 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 73:1efda918f0ba 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 73:1efda918f0ba 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 73:1efda918f0ba 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 73:1efda918f0ba 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 73:1efda918f0ba 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 73:1efda918f0ba 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 73:1efda918f0ba 35 ---------------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 36
bogdanm 73:1efda918f0ba 37
bogdanm 73:1efda918f0ba 38 #if defined ( __ICCARM__ )
bogdanm 73:1efda918f0ba 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 73:1efda918f0ba 40 #endif
bogdanm 73:1efda918f0ba 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 73:1efda918f0ba 45 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 46 extern "C" {
bogdanm 73:1efda918f0ba 47 #endif
bogdanm 73:1efda918f0ba 48
bogdanm 73:1efda918f0ba 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 73:1efda918f0ba 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 73:1efda918f0ba 51
bogdanm 73:1efda918f0ba 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 73:1efda918f0ba 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 73:1efda918f0ba 54
bogdanm 73:1efda918f0ba 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 73:1efda918f0ba 56 Unions are used for effective representation of core registers.
bogdanm 73:1efda918f0ba 57
bogdanm 73:1efda918f0ba 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 73:1efda918f0ba 59 Function-like macros are used to allow more efficient code.
bogdanm 73:1efda918f0ba 60 */
bogdanm 73:1efda918f0ba 61
bogdanm 73:1efda918f0ba 62
bogdanm 73:1efda918f0ba 63 /*******************************************************************************
bogdanm 73:1efda918f0ba 64 * CMSIS definitions
bogdanm 73:1efda918f0ba 65 ******************************************************************************/
bogdanm 73:1efda918f0ba 66 /** \ingroup Cortex_M0
bogdanm 73:1efda918f0ba 67 @{
bogdanm 73:1efda918f0ba 68 */
bogdanm 73:1efda918f0ba 69
bogdanm 73:1efda918f0ba 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 73:1efda918f0ba 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
bogdanm 73:1efda918f0ba 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 73:1efda918f0ba 75
bogdanm 73:1efda918f0ba 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 73:1efda918f0ba 77
bogdanm 73:1efda918f0ba 78
bogdanm 73:1efda918f0ba 79 #if defined ( __CC_ARM )
bogdanm 73:1efda918f0ba 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 73:1efda918f0ba 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 73:1efda918f0ba 82 #define __STATIC_INLINE static __inline
bogdanm 73:1efda918f0ba 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 73:1efda918f0ba 89 #elif defined ( __ICCARM__ )
bogdanm 73:1efda918f0ba 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 73:1efda918f0ba 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 73:1efda918f0ba 92 #define __STATIC_INLINE static inline
bogdanm 73:1efda918f0ba 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 73:1efda918f0ba 96 #define __STATIC_INLINE static inline
bogdanm 73:1efda918f0ba 97
bogdanm 73:1efda918f0ba 98 #elif defined ( __TASKING__ )
bogdanm 73:1efda918f0ba 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 73:1efda918f0ba 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 73:1efda918f0ba 101 #define __STATIC_INLINE static inline
bogdanm 73:1efda918f0ba 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 73:1efda918f0ba 109 #endif
bogdanm 73:1efda918f0ba 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 73:1efda918f0ba 113 */
bogdanm 73:1efda918f0ba 114 #define __FPU_USED 0
bogdanm 73:1efda918f0ba 115
bogdanm 73:1efda918f0ba 116 #if defined ( __CC_ARM )
bogdanm 73:1efda918f0ba 117 #if defined __TARGET_FPU_VFP
bogdanm 73:1efda918f0ba 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 73:1efda918f0ba 119 #endif
bogdanm 73:1efda918f0ba 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 73:1efda918f0ba 126 #elif defined ( __ICCARM__ )
bogdanm 73:1efda918f0ba 127 #if defined __ARMVFP__
bogdanm 73:1efda918f0ba 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 73:1efda918f0ba 129 #endif
bogdanm 73:1efda918f0ba 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 73:1efda918f0ba 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 73:1efda918f0ba 134 #endif
bogdanm 73:1efda918f0ba 135
bogdanm 73:1efda918f0ba 136 #elif defined ( __TASKING__ )
bogdanm 73:1efda918f0ba 137 #if defined __FPU_VFP__
bogdanm 73:1efda918f0ba 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 73:1efda918f0ba 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 73:1efda918f0ba 145 #endif
bogdanm 73:1efda918f0ba 146
bogdanm 73:1efda918f0ba 147 #include <stdint.h> /* standard types definitions */
bogdanm 73:1efda918f0ba 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 73:1efda918f0ba 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 73:1efda918f0ba 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 73:1efda918f0ba 155 #endif /* __CORE_CM0_H_GENERIC */
bogdanm 73:1efda918f0ba 156
bogdanm 73:1efda918f0ba 157 #ifndef __CMSIS_GENERIC
bogdanm 73:1efda918f0ba 158
bogdanm 73:1efda918f0ba 159 #ifndef __CORE_CM0_H_DEPENDANT
bogdanm 73:1efda918f0ba 160 #define __CORE_CM0_H_DEPENDANT
bogdanm 73:1efda918f0ba 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 73:1efda918f0ba 166 /* check device defines and use defaults */
bogdanm 73:1efda918f0ba 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 73:1efda918f0ba 168 #ifndef __CM0_REV
bogdanm 73:1efda918f0ba 169 #define __CM0_REV 0x0000
bogdanm 73:1efda918f0ba 170 #warning "__CM0_REV not defined in device header file; using default!"
bogdanm 73:1efda918f0ba 171 #endif
bogdanm 73:1efda918f0ba 172
bogdanm 73:1efda918f0ba 173 #ifndef __NVIC_PRIO_BITS
bogdanm 73:1efda918f0ba 174 #define __NVIC_PRIO_BITS 2
bogdanm 73:1efda918f0ba 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 73:1efda918f0ba 176 #endif
bogdanm 73:1efda918f0ba 177
bogdanm 73:1efda918f0ba 178 #ifndef __Vendor_SysTickConfig
bogdanm 73:1efda918f0ba 179 #define __Vendor_SysTickConfig 0
bogdanm 73:1efda918f0ba 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 73:1efda918f0ba 181 #endif
bogdanm 73:1efda918f0ba 182 #endif
bogdanm 73:1efda918f0ba 183
bogdanm 73:1efda918f0ba 184 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 73:1efda918f0ba 185 /**
bogdanm 73:1efda918f0ba 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 73:1efda918f0ba 187
bogdanm 73:1efda918f0ba 188 <strong>IO Type Qualifiers</strong> are used
bogdanm 73:1efda918f0ba 189 \li to specify the access to peripheral variables.
bogdanm 73:1efda918f0ba 190 \li for automatic generation of peripheral register debug information.
bogdanm 73:1efda918f0ba 191 */
bogdanm 73:1efda918f0ba 192 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 193 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 73:1efda918f0ba 194 #else
bogdanm 73:1efda918f0ba 195 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 73:1efda918f0ba 196 #endif
bogdanm 73:1efda918f0ba 197 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 73:1efda918f0ba 198 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 73:1efda918f0ba 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
bogdanm 73:1efda918f0ba 208 /*@} end of group Cortex_M0 */
bogdanm 73:1efda918f0ba 209
bogdanm 73:1efda918f0ba 210
bogdanm 73:1efda918f0ba 211
bogdanm 73:1efda918f0ba 212 /*******************************************************************************
bogdanm 73:1efda918f0ba 213 * Register Abstraction
bogdanm 73:1efda918f0ba 214 Core Register contain:
bogdanm 73:1efda918f0ba 215 - Core Register
bogdanm 73:1efda918f0ba 216 - Core NVIC Register
bogdanm 73:1efda918f0ba 217 - Core SCB Register
bogdanm 73:1efda918f0ba 218 - Core SysTick Register
bogdanm 73:1efda918f0ba 219 ******************************************************************************/
bogdanm 73:1efda918f0ba 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 73:1efda918f0ba 221 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 73:1efda918f0ba 222 */
bogdanm 73:1efda918f0ba 223
bogdanm 73:1efda918f0ba 224 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 225 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 73:1efda918f0ba 226 \brief Core Register type definitions.
bogdanm 73:1efda918f0ba 227 @{
bogdanm 73:1efda918f0ba 228 */
bogdanm 73:1efda918f0ba 229
bogdanm 73:1efda918f0ba 230 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 73:1efda918f0ba 231 */
bogdanm 73:1efda918f0ba 232 typedef union
bogdanm 73:1efda918f0ba 233 {
bogdanm 73:1efda918f0ba 234 struct
bogdanm 73:1efda918f0ba 235 {
Kojto 110:165afa46840b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 73:1efda918f0ba 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 73:1efda918f0ba 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 73:1efda918f0ba 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 73:1efda918f0ba 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 73:1efda918f0ba 241 } b; /*!< Structure used for bit access */
bogdanm 73:1efda918f0ba 242 uint32_t w; /*!< Type used for word access */
bogdanm 73:1efda918f0ba 243 } APSR_Type;
bogdanm 73:1efda918f0ba 244
Kojto 110:165afa46840b 245 /* APSR Register Definitions */
Kojto 110:165afa46840b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 257
bogdanm 73:1efda918f0ba 258
bogdanm 73:1efda918f0ba 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 73:1efda918f0ba 260 */
bogdanm 73:1efda918f0ba 261 typedef union
bogdanm 73:1efda918f0ba 262 {
bogdanm 73:1efda918f0ba 263 struct
bogdanm 73:1efda918f0ba 264 {
bogdanm 73:1efda918f0ba 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 73:1efda918f0ba 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 73:1efda918f0ba 267 } b; /*!< Structure used for bit access */
bogdanm 73:1efda918f0ba 268 uint32_t w; /*!< Type used for word access */
bogdanm 73:1efda918f0ba 269 } IPSR_Type;
bogdanm 73:1efda918f0ba 270
Kojto 110:165afa46840b 271 /* IPSR Register Definitions */
Kojto 110:165afa46840b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 274
bogdanm 73:1efda918f0ba 275
bogdanm 73:1efda918f0ba 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 73:1efda918f0ba 277 */
bogdanm 73:1efda918f0ba 278 typedef union
bogdanm 73:1efda918f0ba 279 {
bogdanm 73:1efda918f0ba 280 struct
bogdanm 73:1efda918f0ba 281 {
bogdanm 73:1efda918f0ba 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 73:1efda918f0ba 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 73:1efda918f0ba 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 73:1efda918f0ba 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 73:1efda918f0ba 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 73:1efda918f0ba 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 73:1efda918f0ba 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 73:1efda918f0ba 290 } b; /*!< Structure used for bit access */
bogdanm 73:1efda918f0ba 291 uint32_t w; /*!< Type used for word access */
bogdanm 73:1efda918f0ba 292 } xPSR_Type;
bogdanm 73:1efda918f0ba 293
Kojto 110:165afa46840b 294 /* xPSR Register Definitions */
Kojto 110:165afa46840b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 312
bogdanm 73:1efda918f0ba 313
bogdanm 73:1efda918f0ba 314 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 73:1efda918f0ba 315 */
bogdanm 73:1efda918f0ba 316 typedef union
bogdanm 73:1efda918f0ba 317 {
bogdanm 73:1efda918f0ba 318 struct
bogdanm 73:1efda918f0ba 319 {
Kojto 110:165afa46840b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
bogdanm 73:1efda918f0ba 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 73:1efda918f0ba 323 } b; /*!< Structure used for bit access */
bogdanm 73:1efda918f0ba 324 uint32_t w; /*!< Type used for word access */
bogdanm 73:1efda918f0ba 325 } CONTROL_Type;
bogdanm 73:1efda918f0ba 326
Kojto 110:165afa46840b 327 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 330
bogdanm 73:1efda918f0ba 331 /*@} end of group CMSIS_CORE */
bogdanm 73:1efda918f0ba 332
bogdanm 73:1efda918f0ba 333
bogdanm 73:1efda918f0ba 334 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 73:1efda918f0ba 336 \brief Type definitions for the NVIC Registers
bogdanm 73:1efda918f0ba 337 @{
bogdanm 73:1efda918f0ba 338 */
bogdanm 73:1efda918f0ba 339
bogdanm 73:1efda918f0ba 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 73:1efda918f0ba 341 */
bogdanm 73:1efda918f0ba 342 typedef struct
bogdanm 73:1efda918f0ba 343 {
bogdanm 73:1efda918f0ba 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 73:1efda918f0ba 345 uint32_t RESERVED0[31];
bogdanm 73:1efda918f0ba 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 73:1efda918f0ba 347 uint32_t RSERVED1[31];
bogdanm 73:1efda918f0ba 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 73:1efda918f0ba 349 uint32_t RESERVED2[31];
bogdanm 73:1efda918f0ba 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 73:1efda918f0ba 351 uint32_t RESERVED3[31];
bogdanm 73:1efda918f0ba 352 uint32_t RESERVED4[64];
bogdanm 73:1efda918f0ba 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 73:1efda918f0ba 354 } NVIC_Type;
bogdanm 73:1efda918f0ba 355
bogdanm 73:1efda918f0ba 356 /*@} end of group CMSIS_NVIC */
bogdanm 73:1efda918f0ba 357
bogdanm 73:1efda918f0ba 358
bogdanm 73:1efda918f0ba 359 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 360 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 73:1efda918f0ba 361 \brief Type definitions for the System Control Block Registers
bogdanm 73:1efda918f0ba 362 @{
bogdanm 73:1efda918f0ba 363 */
bogdanm 73:1efda918f0ba 364
bogdanm 73:1efda918f0ba 365 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 73:1efda918f0ba 366 */
bogdanm 73:1efda918f0ba 367 typedef struct
bogdanm 73:1efda918f0ba 368 {
bogdanm 73:1efda918f0ba 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 73:1efda918f0ba 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 73:1efda918f0ba 371 uint32_t RESERVED0;
bogdanm 73:1efda918f0ba 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 73:1efda918f0ba 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 73:1efda918f0ba 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 73:1efda918f0ba 375 uint32_t RESERVED1;
bogdanm 73:1efda918f0ba 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 73:1efda918f0ba 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 73:1efda918f0ba 378 } SCB_Type;
bogdanm 73:1efda918f0ba 379
bogdanm 73:1efda918f0ba 380 /* SCB CPUID Register Definitions */
bogdanm 73:1efda918f0ba 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 73:1efda918f0ba 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 73:1efda918f0ba 383
bogdanm 73:1efda918f0ba 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 73:1efda918f0ba 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 73:1efda918f0ba 386
bogdanm 73:1efda918f0ba 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 73:1efda918f0ba 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 73:1efda918f0ba 389
bogdanm 73:1efda918f0ba 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 73:1efda918f0ba 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 73:1efda918f0ba 392
bogdanm 73:1efda918f0ba 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 73:1efda918f0ba 395
bogdanm 73:1efda918f0ba 396 /* SCB Interrupt Control State Register Definitions */
bogdanm 73:1efda918f0ba 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 73:1efda918f0ba 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 73:1efda918f0ba 399
bogdanm 73:1efda918f0ba 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 73:1efda918f0ba 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 73:1efda918f0ba 402
bogdanm 73:1efda918f0ba 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 73:1efda918f0ba 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 73:1efda918f0ba 405
bogdanm 73:1efda918f0ba 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 73:1efda918f0ba 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 73:1efda918f0ba 408
bogdanm 73:1efda918f0ba 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 73:1efda918f0ba 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 73:1efda918f0ba 411
bogdanm 73:1efda918f0ba 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 73:1efda918f0ba 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 73:1efda918f0ba 414
bogdanm 73:1efda918f0ba 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 73:1efda918f0ba 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 73:1efda918f0ba 417
bogdanm 73:1efda918f0ba 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 73:1efda918f0ba 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 73:1efda918f0ba 420
bogdanm 73:1efda918f0ba 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 73:1efda918f0ba 423
bogdanm 73:1efda918f0ba 424 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 73:1efda918f0ba 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 73:1efda918f0ba 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 73:1efda918f0ba 427
bogdanm 73:1efda918f0ba 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 73:1efda918f0ba 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 73:1efda918f0ba 430
bogdanm 73:1efda918f0ba 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 73:1efda918f0ba 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 73:1efda918f0ba 433
bogdanm 73:1efda918f0ba 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 73:1efda918f0ba 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 73:1efda918f0ba 436
bogdanm 73:1efda918f0ba 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 73:1efda918f0ba 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 73:1efda918f0ba 439
bogdanm 73:1efda918f0ba 440 /* SCB System Control Register Definitions */
bogdanm 73:1efda918f0ba 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 73:1efda918f0ba 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 73:1efda918f0ba 443
bogdanm 73:1efda918f0ba 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 73:1efda918f0ba 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 73:1efda918f0ba 446
bogdanm 73:1efda918f0ba 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 73:1efda918f0ba 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 73:1efda918f0ba 449
bogdanm 73:1efda918f0ba 450 /* SCB Configuration Control Register Definitions */
bogdanm 73:1efda918f0ba 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 73:1efda918f0ba 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 73:1efda918f0ba 453
bogdanm 73:1efda918f0ba 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 73:1efda918f0ba 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 73:1efda918f0ba 456
bogdanm 73:1efda918f0ba 457 /* SCB System Handler Control and State Register Definitions */
bogdanm 73:1efda918f0ba 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 73:1efda918f0ba 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 73:1efda918f0ba 460
bogdanm 73:1efda918f0ba 461 /*@} end of group CMSIS_SCB */
bogdanm 73:1efda918f0ba 462
bogdanm 73:1efda918f0ba 463
bogdanm 73:1efda918f0ba 464 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 73:1efda918f0ba 466 \brief Type definitions for the System Timer Registers.
bogdanm 73:1efda918f0ba 467 @{
bogdanm 73:1efda918f0ba 468 */
bogdanm 73:1efda918f0ba 469
bogdanm 73:1efda918f0ba 470 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 73:1efda918f0ba 471 */
bogdanm 73:1efda918f0ba 472 typedef struct
bogdanm 73:1efda918f0ba 473 {
bogdanm 73:1efda918f0ba 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 73:1efda918f0ba 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 73:1efda918f0ba 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 73:1efda918f0ba 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 73:1efda918f0ba 478 } SysTick_Type;
bogdanm 73:1efda918f0ba 479
bogdanm 73:1efda918f0ba 480 /* SysTick Control / Status Register Definitions */
bogdanm 73:1efda918f0ba 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 73:1efda918f0ba 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 73:1efda918f0ba 483
bogdanm 73:1efda918f0ba 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 73:1efda918f0ba 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 73:1efda918f0ba 486
bogdanm 73:1efda918f0ba 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 73:1efda918f0ba 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 73:1efda918f0ba 489
bogdanm 73:1efda918f0ba 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 73:1efda918f0ba 492
bogdanm 73:1efda918f0ba 493 /* SysTick Reload Register Definitions */
bogdanm 73:1efda918f0ba 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 73:1efda918f0ba 496
bogdanm 73:1efda918f0ba 497 /* SysTick Current Register Definitions */
bogdanm 73:1efda918f0ba 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 73:1efda918f0ba 500
bogdanm 73:1efda918f0ba 501 /* SysTick Calibration Register Definitions */
bogdanm 73:1efda918f0ba 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 73:1efda918f0ba 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 73:1efda918f0ba 504
bogdanm 73:1efda918f0ba 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 73:1efda918f0ba 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 73:1efda918f0ba 507
bogdanm 73:1efda918f0ba 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 73:1efda918f0ba 510
bogdanm 73:1efda918f0ba 511 /*@} end of group CMSIS_SysTick */
bogdanm 73:1efda918f0ba 512
bogdanm 73:1efda918f0ba 513
bogdanm 73:1efda918f0ba 514 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 73:1efda918f0ba 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 73:1efda918f0ba 517 are only accessible over DAP and not via processor. Therefore
bogdanm 73:1efda918f0ba 518 they are not covered by the Cortex-M0 header file.
bogdanm 73:1efda918f0ba 519 @{
bogdanm 73:1efda918f0ba 520 */
bogdanm 73:1efda918f0ba 521 /*@} end of group CMSIS_CoreDebug */
bogdanm 73:1efda918f0ba 522
bogdanm 73:1efda918f0ba 523
bogdanm 73:1efda918f0ba 524 /** \ingroup CMSIS_core_register
bogdanm 73:1efda918f0ba 525 \defgroup CMSIS_core_base Core Definitions
bogdanm 73:1efda918f0ba 526 \brief Definitions for base addresses, unions, and structures.
bogdanm 73:1efda918f0ba 527 @{
bogdanm 73:1efda918f0ba 528 */
bogdanm 73:1efda918f0ba 529
bogdanm 73:1efda918f0ba 530 /* Memory mapping of Cortex-M0 Hardware */
bogdanm 73:1efda918f0ba 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 73:1efda918f0ba 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 73:1efda918f0ba 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 73:1efda918f0ba 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 73:1efda918f0ba 535
bogdanm 73:1efda918f0ba 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 73:1efda918f0ba 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 73:1efda918f0ba 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 73:1efda918f0ba 539
bogdanm 73:1efda918f0ba 540
bogdanm 73:1efda918f0ba 541 /*@} */
bogdanm 73:1efda918f0ba 542
bogdanm 73:1efda918f0ba 543
bogdanm 73:1efda918f0ba 544
bogdanm 73:1efda918f0ba 545 /*******************************************************************************
bogdanm 73:1efda918f0ba 546 * Hardware Abstraction Layer
bogdanm 73:1efda918f0ba 547 Core Function Interface contains:
bogdanm 73:1efda918f0ba 548 - Core NVIC Functions
bogdanm 73:1efda918f0ba 549 - Core SysTick Functions
bogdanm 73:1efda918f0ba 550 - Core Register Access Functions
bogdanm 73:1efda918f0ba 551 ******************************************************************************/
bogdanm 73:1efda918f0ba 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 73:1efda918f0ba 553 */
bogdanm 73:1efda918f0ba 554
bogdanm 73:1efda918f0ba 555
bogdanm 73:1efda918f0ba 556
bogdanm 73:1efda918f0ba 557 /* ########################## NVIC functions #################################### */
bogdanm 73:1efda918f0ba 558 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 73:1efda918f0ba 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 73:1efda918f0ba 560 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 73:1efda918f0ba 561 @{
bogdanm 73:1efda918f0ba 562 */
bogdanm 73:1efda918f0ba 563
bogdanm 73:1efda918f0ba 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 73:1efda918f0ba 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 73:1efda918f0ba 569
bogdanm 73:1efda918f0ba 570
bogdanm 73:1efda918f0ba 571 /** \brief Enable External Interrupt
bogdanm 73:1efda918f0ba 572
bogdanm 73:1efda918f0ba 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 73:1efda918f0ba 574
bogdanm 73:1efda918f0ba 575 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 73:1efda918f0ba 576 */
bogdanm 73:1efda918f0ba 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 578 {
Kojto 110:165afa46840b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 73:1efda918f0ba 580 }
bogdanm 73:1efda918f0ba 581
bogdanm 73:1efda918f0ba 582
bogdanm 73:1efda918f0ba 583 /** \brief Disable External Interrupt
bogdanm 73:1efda918f0ba 584
bogdanm 73:1efda918f0ba 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 73:1efda918f0ba 586
bogdanm 73:1efda918f0ba 587 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 73:1efda918f0ba 588 */
bogdanm 73:1efda918f0ba 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 590 {
Kojto 110:165afa46840b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
bogdanm 73:1efda918f0ba 594 }
bogdanm 73:1efda918f0ba 595
bogdanm 73:1efda918f0ba 596
bogdanm 73:1efda918f0ba 597 /** \brief Get Pending Interrupt
bogdanm 73:1efda918f0ba 598
bogdanm 73:1efda918f0ba 599 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 73:1efda918f0ba 600 for the specified interrupt.
bogdanm 73:1efda918f0ba 601
bogdanm 73:1efda918f0ba 602 \param [in] IRQn Interrupt number.
bogdanm 73:1efda918f0ba 603
bogdanm 73:1efda918f0ba 604 \return 0 Interrupt status is not pending.
bogdanm 73:1efda918f0ba 605 \return 1 Interrupt status is pending.
bogdanm 73:1efda918f0ba 606 */
bogdanm 73:1efda918f0ba 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 608 {
Kojto 110:165afa46840b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 73:1efda918f0ba 610 }
bogdanm 73:1efda918f0ba 611
bogdanm 73:1efda918f0ba 612
bogdanm 73:1efda918f0ba 613 /** \brief Set Pending Interrupt
bogdanm 73:1efda918f0ba 614
bogdanm 73:1efda918f0ba 615 The function sets the pending bit of an external interrupt.
bogdanm 73:1efda918f0ba 616
bogdanm 73:1efda918f0ba 617 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 73:1efda918f0ba 618 */
bogdanm 73:1efda918f0ba 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 620 {
Kojto 110:165afa46840b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 73:1efda918f0ba 622 }
bogdanm 73:1efda918f0ba 623
bogdanm 73:1efda918f0ba 624
bogdanm 73:1efda918f0ba 625 /** \brief Clear Pending Interrupt
bogdanm 73:1efda918f0ba 626
bogdanm 73:1efda918f0ba 627 The function clears the pending bit of an external interrupt.
bogdanm 73:1efda918f0ba 628
bogdanm 73:1efda918f0ba 629 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 73:1efda918f0ba 630 */
bogdanm 73:1efda918f0ba 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 632 {
Kojto 110:165afa46840b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 73:1efda918f0ba 634 }
bogdanm 73:1efda918f0ba 635
bogdanm 73:1efda918f0ba 636
bogdanm 73:1efda918f0ba 637 /** \brief Set Interrupt Priority
bogdanm 73:1efda918f0ba 638
bogdanm 73:1efda918f0ba 639 The function sets the priority of an interrupt.
bogdanm 73:1efda918f0ba 640
bogdanm 73:1efda918f0ba 641 \note The priority cannot be set for every core interrupt.
bogdanm 73:1efda918f0ba 642
bogdanm 73:1efda918f0ba 643 \param [in] IRQn Interrupt number.
bogdanm 73:1efda918f0ba 644 \param [in] priority Priority to set.
bogdanm 73:1efda918f0ba 645 */
bogdanm 73:1efda918f0ba 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 73:1efda918f0ba 647 {
Kojto 110:165afa46840b 648 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 651 }
bogdanm 73:1efda918f0ba 652 else {
Kojto 110:165afa46840b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 655 }
bogdanm 73:1efda918f0ba 656 }
bogdanm 73:1efda918f0ba 657
bogdanm 73:1efda918f0ba 658
bogdanm 73:1efda918f0ba 659 /** \brief Get Interrupt Priority
bogdanm 73:1efda918f0ba 660
bogdanm 73:1efda918f0ba 661 The function reads the priority of an interrupt. The interrupt
bogdanm 73:1efda918f0ba 662 number can be positive to specify an external (device specific)
bogdanm 73:1efda918f0ba 663 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 73:1efda918f0ba 664
bogdanm 73:1efda918f0ba 665
bogdanm 73:1efda918f0ba 666 \param [in] IRQn Interrupt number.
bogdanm 73:1efda918f0ba 667 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 73:1efda918f0ba 668 priority bits of the microcontroller.
bogdanm 73:1efda918f0ba 669 */
bogdanm 73:1efda918f0ba 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 73:1efda918f0ba 671 {
bogdanm 73:1efda918f0ba 672
Kojto 110:165afa46840b 673 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 675 }
bogdanm 73:1efda918f0ba 676 else {
Kojto 110:165afa46840b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 678 }
bogdanm 73:1efda918f0ba 679 }
bogdanm 73:1efda918f0ba 680
bogdanm 73:1efda918f0ba 681
bogdanm 73:1efda918f0ba 682 /** \brief System Reset
bogdanm 73:1efda918f0ba 683
bogdanm 73:1efda918f0ba 684 The function initiates a system reset request to reset the MCU.
bogdanm 73:1efda918f0ba 685 */
bogdanm 73:1efda918f0ba 686 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 73:1efda918f0ba 687 {
bogdanm 73:1efda918f0ba 688 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 73:1efda918f0ba 689 buffered write are completed before reset */
Kojto 110:165afa46840b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 73:1efda918f0ba 691 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 73:1efda918f0ba 692 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 693 while(1) { __NOP(); } /* wait until reset */
bogdanm 73:1efda918f0ba 694 }
bogdanm 73:1efda918f0ba 695
bogdanm 73:1efda918f0ba 696 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 73:1efda918f0ba 697
bogdanm 73:1efda918f0ba 698
bogdanm 73:1efda918f0ba 699
bogdanm 73:1efda918f0ba 700 /* ################################## SysTick function ############################################ */
bogdanm 73:1efda918f0ba 701 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 73:1efda918f0ba 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 73:1efda918f0ba 703 \brief Functions that configure the System.
bogdanm 73:1efda918f0ba 704 @{
bogdanm 73:1efda918f0ba 705 */
bogdanm 73:1efda918f0ba 706
bogdanm 73:1efda918f0ba 707 #if (__Vendor_SysTickConfig == 0)
bogdanm 73:1efda918f0ba 708
bogdanm 73:1efda918f0ba 709 /** \brief System Tick Configuration
bogdanm 73:1efda918f0ba 710
bogdanm 73:1efda918f0ba 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 73:1efda918f0ba 712 Counter is in free running mode to generate periodic interrupts.
bogdanm 73:1efda918f0ba 713
bogdanm 73:1efda918f0ba 714 \param [in] ticks Number of ticks between two interrupts.
bogdanm 73:1efda918f0ba 715
bogdanm 73:1efda918f0ba 716 \return 0 Function succeeded.
bogdanm 73:1efda918f0ba 717 \return 1 Function failed.
bogdanm 73:1efda918f0ba 718
bogdanm 73:1efda918f0ba 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 73:1efda918f0ba 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 73:1efda918f0ba 721 must contain a vendor-specific implementation of this function.
bogdanm 73:1efda918f0ba 722
bogdanm 73:1efda918f0ba 723 */
bogdanm 73:1efda918f0ba 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 73:1efda918f0ba 725 {
Kojto 110:165afa46840b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 73:1efda918f0ba 727
Kojto 110:165afa46840b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 73:1efda918f0ba 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 73:1efda918f0ba 732 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 734 return (0UL); /* Function successful */
bogdanm 73:1efda918f0ba 735 }
bogdanm 73:1efda918f0ba 736
bogdanm 73:1efda918f0ba 737 #endif
bogdanm 73:1efda918f0ba 738
bogdanm 73:1efda918f0ba 739 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 73:1efda918f0ba 740
bogdanm 73:1efda918f0ba 741
bogdanm 73:1efda918f0ba 742
bogdanm 73:1efda918f0ba 743
Kojto 110:165afa46840b 744 #ifdef __cplusplus
Kojto 110:165afa46840b 745 }
Kojto 110:165afa46840b 746 #endif
Kojto 110:165afa46840b 747
bogdanm 73:1efda918f0ba 748 #endif /* __CORE_CM0_H_DEPENDANT */
bogdanm 73:1efda918f0ba 749
bogdanm 73:1efda918f0ba 750 #endif /* __CMSIS_GENERIC */