mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KL05Z/core_cm3.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /**************************************************************************//**
emilmont 78:ed8466a608b4 2 * @file core_cm3.h
emilmont 78:ed8466a608b4 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 78:ed8466a608b4 6 *
emilmont 78:ed8466a608b4 7 * @note
emilmont 78:ed8466a608b4 8 *
emilmont 78:ed8466a608b4 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 78:ed8466a608b4 11
emilmont 78:ed8466a608b4 12 All rights reserved.
emilmont 78:ed8466a608b4 13 Redistribution and use in source and binary forms, with or without
emilmont 78:ed8466a608b4 14 modification, are permitted provided that the following conditions are met:
emilmont 78:ed8466a608b4 15 - Redistributions of source code must retain the above copyright
emilmont 78:ed8466a608b4 16 notice, this list of conditions and the following disclaimer.
emilmont 78:ed8466a608b4 17 - Redistributions in binary form must reproduce the above copyright
emilmont 78:ed8466a608b4 18 notice, this list of conditions and the following disclaimer in the
emilmont 78:ed8466a608b4 19 documentation and/or other materials provided with the distribution.
emilmont 78:ed8466a608b4 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 78:ed8466a608b4 21 to endorse or promote products derived from this software without
emilmont 78:ed8466a608b4 22 specific prior written permission.
emilmont 78:ed8466a608b4 23 *
emilmont 78:ed8466a608b4 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 78:ed8466a608b4 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 78:ed8466a608b4 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 78:ed8466a608b4 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 78:ed8466a608b4 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 78:ed8466a608b4 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 78:ed8466a608b4 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 78:ed8466a608b4 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 78:ed8466a608b4 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 78:ed8466a608b4 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 78:ed8466a608b4 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 78:ed8466a608b4 35 ---------------------------------------------------------------------------*/
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37
emilmont 78:ed8466a608b4 38 #if defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 78:ed8466a608b4 40 #endif
emilmont 78:ed8466a608b4 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM3_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 78:ed8466a608b4 45 #ifdef __cplusplus
emilmont 78:ed8466a608b4 46 extern "C" {
emilmont 78:ed8466a608b4 47 #endif
emilmont 78:ed8466a608b4 48
emilmont 78:ed8466a608b4 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 78:ed8466a608b4 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 78:ed8466a608b4 51
emilmont 78:ed8466a608b4 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 78:ed8466a608b4 53 Function definitions in header files are used to allow 'inlining'.
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 78:ed8466a608b4 56 Unions are used for effective representation of core registers.
emilmont 78:ed8466a608b4 57
emilmont 78:ed8466a608b4 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 78:ed8466a608b4 59 Function-like macros are used to allow more efficient code.
emilmont 78:ed8466a608b4 60 */
emilmont 78:ed8466a608b4 61
emilmont 78:ed8466a608b4 62
emilmont 78:ed8466a608b4 63 /*******************************************************************************
emilmont 78:ed8466a608b4 64 * CMSIS definitions
emilmont 78:ed8466a608b4 65 ******************************************************************************/
emilmont 78:ed8466a608b4 66 /** \ingroup Cortex_M3
emilmont 78:ed8466a608b4 67 @{
emilmont 78:ed8466a608b4 68 */
emilmont 78:ed8466a608b4 69
emilmont 78:ed8466a608b4 70 /* CMSIS CM3 definitions */
Kojto 110:165afa46840b 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 78:ed8466a608b4 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
emilmont 78:ed8466a608b4 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 78:ed8466a608b4 75
emilmont 78:ed8466a608b4 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
emilmont 78:ed8466a608b4 77
emilmont 78:ed8466a608b4 78
emilmont 78:ed8466a608b4 79 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 78:ed8466a608b4 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 78:ed8466a608b4 82 #define __STATIC_INLINE static __inline
emilmont 78:ed8466a608b4 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 78:ed8466a608b4 89 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 78:ed8466a608b4 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 78:ed8466a608b4 92 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 93
emilmont 78:ed8466a608b4 94 #elif defined ( __TMS470__ )
emilmont 78:ed8466a608b4 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 78:ed8466a608b4 96 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 97
emilmont 78:ed8466a608b4 98 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 101 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 78:ed8466a608b4 109 #endif
emilmont 78:ed8466a608b4 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
emilmont 78:ed8466a608b4 113 */
emilmont 78:ed8466a608b4 114 #define __FPU_USED 0
emilmont 78:ed8466a608b4 115
emilmont 78:ed8466a608b4 116 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 117 #if defined __TARGET_FPU_VFP
emilmont 78:ed8466a608b4 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 119 #endif
emilmont 78:ed8466a608b4 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
emilmont 78:ed8466a608b4 126 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 127 #if defined __ARMVFP__
emilmont 78:ed8466a608b4 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 129 #endif
emilmont 78:ed8466a608b4 130
emilmont 78:ed8466a608b4 131 #elif defined ( __TMS470__ )
emilmont 78:ed8466a608b4 132 #if defined __TI__VFP_SUPPORT____
emilmont 78:ed8466a608b4 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 134 #endif
emilmont 78:ed8466a608b4 135
Kojto 110:165afa46840b 136 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 137 #if defined __FPU_VFP__
Kojto 110:165afa46840b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 139 #endif
emilmont 78:ed8466a608b4 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
emilmont 78:ed8466a608b4 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 144 #endif
emilmont 78:ed8466a608b4 145 #endif
emilmont 78:ed8466a608b4 146
emilmont 78:ed8466a608b4 147 #include <stdint.h> /* standard types definitions */
emilmont 78:ed8466a608b4 148 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 78:ed8466a608b4 149 #include <core_cmFunc.h> /* Core Function Access */
emilmont 78:ed8466a608b4 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
emilmont 78:ed8466a608b4 155 #endif /* __CORE_CM3_H_GENERIC */
emilmont 78:ed8466a608b4 156
emilmont 78:ed8466a608b4 157 #ifndef __CMSIS_GENERIC
emilmont 78:ed8466a608b4 158
emilmont 78:ed8466a608b4 159 #ifndef __CORE_CM3_H_DEPENDANT
emilmont 78:ed8466a608b4 160 #define __CORE_CM3_H_DEPENDANT
emilmont 78:ed8466a608b4 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
emilmont 78:ed8466a608b4 166 /* check device defines and use defaults */
emilmont 78:ed8466a608b4 167 #if defined __CHECK_DEVICE_DEFINES
emilmont 78:ed8466a608b4 168 #ifndef __CM3_REV
emilmont 78:ed8466a608b4 169 #define __CM3_REV 0x0200
emilmont 78:ed8466a608b4 170 #warning "__CM3_REV not defined in device header file; using default!"
emilmont 78:ed8466a608b4 171 #endif
emilmont 78:ed8466a608b4 172
emilmont 78:ed8466a608b4 173 #ifndef __MPU_PRESENT
emilmont 78:ed8466a608b4 174 #define __MPU_PRESENT 0
emilmont 78:ed8466a608b4 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 78:ed8466a608b4 176 #endif
emilmont 78:ed8466a608b4 177
emilmont 78:ed8466a608b4 178 #ifndef __NVIC_PRIO_BITS
emilmont 78:ed8466a608b4 179 #define __NVIC_PRIO_BITS 4
emilmont 78:ed8466a608b4 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 78:ed8466a608b4 181 #endif
emilmont 78:ed8466a608b4 182
emilmont 78:ed8466a608b4 183 #ifndef __Vendor_SysTickConfig
emilmont 78:ed8466a608b4 184 #define __Vendor_SysTickConfig 0
emilmont 78:ed8466a608b4 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 78:ed8466a608b4 186 #endif
emilmont 78:ed8466a608b4 187 #endif
emilmont 78:ed8466a608b4 188
emilmont 78:ed8466a608b4 189 /* IO definitions (access restrictions to peripheral registers) */
emilmont 78:ed8466a608b4 190 /**
emilmont 78:ed8466a608b4 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 78:ed8466a608b4 192
emilmont 78:ed8466a608b4 193 <strong>IO Type Qualifiers</strong> are used
emilmont 78:ed8466a608b4 194 \li to specify the access to peripheral variables.
emilmont 78:ed8466a608b4 195 \li for automatic generation of peripheral register debug information.
emilmont 78:ed8466a608b4 196 */
emilmont 78:ed8466a608b4 197 #ifdef __cplusplus
emilmont 78:ed8466a608b4 198 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 199 #else
emilmont 78:ed8466a608b4 200 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 201 #endif
emilmont 78:ed8466a608b4 202 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 78:ed8466a608b4 203 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 78:ed8466a608b4 204
<> 128:9bcdf88f62b0 205 #ifdef __cplusplus
<> 128:9bcdf88f62b0 206 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 207 #else
<> 128:9bcdf88f62b0 208 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 209 #endif
<> 128:9bcdf88f62b0 210 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 212
emilmont 78:ed8466a608b4 213 /*@} end of group Cortex_M3 */
emilmont 78:ed8466a608b4 214
emilmont 78:ed8466a608b4 215
emilmont 78:ed8466a608b4 216
emilmont 78:ed8466a608b4 217 /*******************************************************************************
emilmont 78:ed8466a608b4 218 * Register Abstraction
emilmont 78:ed8466a608b4 219 Core Register contain:
emilmont 78:ed8466a608b4 220 - Core Register
emilmont 78:ed8466a608b4 221 - Core NVIC Register
emilmont 78:ed8466a608b4 222 - Core SCB Register
emilmont 78:ed8466a608b4 223 - Core SysTick Register
emilmont 78:ed8466a608b4 224 - Core Debug Register
emilmont 78:ed8466a608b4 225 - Core MPU Register
emilmont 78:ed8466a608b4 226 ******************************************************************************/
emilmont 78:ed8466a608b4 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 78:ed8466a608b4 228 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 78:ed8466a608b4 229 */
emilmont 78:ed8466a608b4 230
emilmont 78:ed8466a608b4 231 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 232 \defgroup CMSIS_CORE Status and Control Registers
emilmont 78:ed8466a608b4 233 \brief Core Register type definitions.
emilmont 78:ed8466a608b4 234 @{
emilmont 78:ed8466a608b4 235 */
emilmont 78:ed8466a608b4 236
emilmont 78:ed8466a608b4 237 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 78:ed8466a608b4 238 */
emilmont 78:ed8466a608b4 239 typedef union
emilmont 78:ed8466a608b4 240 {
emilmont 78:ed8466a608b4 241 struct
emilmont 78:ed8466a608b4 242 {
emilmont 78:ed8466a608b4 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 78:ed8466a608b4 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 249 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 250 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 251 } APSR_Type;
emilmont 78:ed8466a608b4 252
Kojto 110:165afa46840b 253 /* APSR Register Definitions */
Kojto 110:165afa46840b 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 256
Kojto 110:165afa46840b 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 110:165afa46840b 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 110:165afa46840b 268
emilmont 78:ed8466a608b4 269
emilmont 78:ed8466a608b4 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 78:ed8466a608b4 271 */
emilmont 78:ed8466a608b4 272 typedef union
emilmont 78:ed8466a608b4 273 {
emilmont 78:ed8466a608b4 274 struct
emilmont 78:ed8466a608b4 275 {
emilmont 78:ed8466a608b4 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 78:ed8466a608b4 278 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 279 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 280 } IPSR_Type;
emilmont 78:ed8466a608b4 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
emilmont 78:ed8466a608b4 286
emilmont 78:ed8466a608b4 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 78:ed8466a608b4 288 */
emilmont 78:ed8466a608b4 289 typedef union
emilmont 78:ed8466a608b4 290 {
emilmont 78:ed8466a608b4 291 struct
emilmont 78:ed8466a608b4 292 {
emilmont 78:ed8466a608b4 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 78:ed8466a608b4 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 78:ed8466a608b4 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 78:ed8466a608b4 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 302 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 303 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 304 } xPSR_Type;
emilmont 78:ed8466a608b4 305
Kojto 110:165afa46840b 306 /* xPSR Register Definitions */
Kojto 110:165afa46840b 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 315
Kojto 110:165afa46840b 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 318
Kojto 110:165afa46840b 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 110:165afa46840b 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 110:165afa46840b 321
Kojto 110:165afa46840b 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 110:165afa46840b 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 110:165afa46840b 324
Kojto 110:165afa46840b 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 327
Kojto 110:165afa46840b 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 330
emilmont 78:ed8466a608b4 331
emilmont 78:ed8466a608b4 332 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 78:ed8466a608b4 333 */
emilmont 78:ed8466a608b4 334 typedef union
emilmont 78:ed8466a608b4 335 {
emilmont 78:ed8466a608b4 336 struct
emilmont 78:ed8466a608b4 337 {
emilmont 78:ed8466a608b4 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 78:ed8466a608b4 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
emilmont 78:ed8466a608b4 341 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 342 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 343 } CONTROL_Type;
emilmont 78:ed8466a608b4 344
Kojto 110:165afa46840b 345 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 348
Kojto 110:165afa46840b 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 351
emilmont 78:ed8466a608b4 352 /*@} end of group CMSIS_CORE */
emilmont 78:ed8466a608b4 353
emilmont 78:ed8466a608b4 354
emilmont 78:ed8466a608b4 355 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 78:ed8466a608b4 357 \brief Type definitions for the NVIC Registers
emilmont 78:ed8466a608b4 358 @{
emilmont 78:ed8466a608b4 359 */
emilmont 78:ed8466a608b4 360
emilmont 78:ed8466a608b4 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 78:ed8466a608b4 362 */
emilmont 78:ed8466a608b4 363 typedef struct
emilmont 78:ed8466a608b4 364 {
emilmont 78:ed8466a608b4 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 78:ed8466a608b4 366 uint32_t RESERVED0[24];
emilmont 78:ed8466a608b4 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 78:ed8466a608b4 368 uint32_t RSERVED1[24];
emilmont 78:ed8466a608b4 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 78:ed8466a608b4 370 uint32_t RESERVED2[24];
emilmont 78:ed8466a608b4 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 78:ed8466a608b4 372 uint32_t RESERVED3[24];
emilmont 78:ed8466a608b4 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
emilmont 78:ed8466a608b4 374 uint32_t RESERVED4[56];
emilmont 78:ed8466a608b4 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
emilmont 78:ed8466a608b4 376 uint32_t RESERVED5[644];
emilmont 78:ed8466a608b4 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
emilmont 78:ed8466a608b4 378 } NVIC_Type;
emilmont 78:ed8466a608b4 379
emilmont 78:ed8466a608b4 380 /* Software Triggered Interrupt Register Definitions */
emilmont 78:ed8466a608b4 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 110:165afa46840b 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
emilmont 78:ed8466a608b4 383
emilmont 78:ed8466a608b4 384 /*@} end of group CMSIS_NVIC */
emilmont 78:ed8466a608b4 385
emilmont 78:ed8466a608b4 386
emilmont 78:ed8466a608b4 387 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 388 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 78:ed8466a608b4 389 \brief Type definitions for the System Control Block Registers
emilmont 78:ed8466a608b4 390 @{
emilmont 78:ed8466a608b4 391 */
emilmont 78:ed8466a608b4 392
emilmont 78:ed8466a608b4 393 /** \brief Structure type to access the System Control Block (SCB).
emilmont 78:ed8466a608b4 394 */
emilmont 78:ed8466a608b4 395 typedef struct
emilmont 78:ed8466a608b4 396 {
emilmont 78:ed8466a608b4 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 78:ed8466a608b4 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 78:ed8466a608b4 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 78:ed8466a608b4 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 78:ed8466a608b4 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 78:ed8466a608b4 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 78:ed8466a608b4 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
emilmont 78:ed8466a608b4 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 78:ed8466a608b4 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
emilmont 78:ed8466a608b4 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
emilmont 78:ed8466a608b4 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
emilmont 78:ed8466a608b4 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
emilmont 78:ed8466a608b4 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
emilmont 78:ed8466a608b4 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
emilmont 78:ed8466a608b4 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
emilmont 78:ed8466a608b4 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
emilmont 78:ed8466a608b4 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
emilmont 78:ed8466a608b4 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
emilmont 78:ed8466a608b4 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
emilmont 78:ed8466a608b4 416 uint32_t RESERVED0[5];
emilmont 78:ed8466a608b4 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
emilmont 78:ed8466a608b4 418 } SCB_Type;
emilmont 78:ed8466a608b4 419
emilmont 78:ed8466a608b4 420 /* SCB CPUID Register Definitions */
emilmont 78:ed8466a608b4 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 78:ed8466a608b4 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 78:ed8466a608b4 423
emilmont 78:ed8466a608b4 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 78:ed8466a608b4 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 78:ed8466a608b4 426
emilmont 78:ed8466a608b4 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 78:ed8466a608b4 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 78:ed8466a608b4 429
emilmont 78:ed8466a608b4 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 78:ed8466a608b4 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 78:ed8466a608b4 432
emilmont 78:ed8466a608b4 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 78:ed8466a608b4 435
emilmont 78:ed8466a608b4 436 /* SCB Interrupt Control State Register Definitions */
emilmont 78:ed8466a608b4 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 78:ed8466a608b4 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 78:ed8466a608b4 439
emilmont 78:ed8466a608b4 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 78:ed8466a608b4 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 78:ed8466a608b4 442
emilmont 78:ed8466a608b4 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 78:ed8466a608b4 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 78:ed8466a608b4 445
emilmont 78:ed8466a608b4 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 78:ed8466a608b4 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 78:ed8466a608b4 448
emilmont 78:ed8466a608b4 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 78:ed8466a608b4 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 78:ed8466a608b4 451
emilmont 78:ed8466a608b4 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 78:ed8466a608b4 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 78:ed8466a608b4 454
emilmont 78:ed8466a608b4 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 78:ed8466a608b4 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 78:ed8466a608b4 457
emilmont 78:ed8466a608b4 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 78:ed8466a608b4 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 78:ed8466a608b4 460
emilmont 78:ed8466a608b4 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
emilmont 78:ed8466a608b4 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
emilmont 78:ed8466a608b4 463
emilmont 78:ed8466a608b4 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 78:ed8466a608b4 466
emilmont 78:ed8466a608b4 467 /* SCB Vector Table Offset Register Definitions */
emilmont 78:ed8466a608b4 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont 78:ed8466a608b4 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
emilmont 78:ed8466a608b4 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
emilmont 78:ed8466a608b4 471
emilmont 78:ed8466a608b4 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 78:ed8466a608b4 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 78:ed8466a608b4 474 #else
emilmont 78:ed8466a608b4 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 78:ed8466a608b4 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 78:ed8466a608b4 477 #endif
emilmont 78:ed8466a608b4 478
emilmont 78:ed8466a608b4 479 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 78:ed8466a608b4 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 78:ed8466a608b4 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 78:ed8466a608b4 482
emilmont 78:ed8466a608b4 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 78:ed8466a608b4 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 78:ed8466a608b4 485
emilmont 78:ed8466a608b4 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 78:ed8466a608b4 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 78:ed8466a608b4 488
emilmont 78:ed8466a608b4 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
emilmont 78:ed8466a608b4 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
emilmont 78:ed8466a608b4 491
emilmont 78:ed8466a608b4 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 78:ed8466a608b4 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 78:ed8466a608b4 494
emilmont 78:ed8466a608b4 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 78:ed8466a608b4 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 78:ed8466a608b4 497
emilmont 78:ed8466a608b4 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 110:165afa46840b 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
emilmont 78:ed8466a608b4 500
emilmont 78:ed8466a608b4 501 /* SCB System Control Register Definitions */
emilmont 78:ed8466a608b4 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 78:ed8466a608b4 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 78:ed8466a608b4 504
emilmont 78:ed8466a608b4 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 78:ed8466a608b4 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 78:ed8466a608b4 507
emilmont 78:ed8466a608b4 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 78:ed8466a608b4 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 78:ed8466a608b4 510
emilmont 78:ed8466a608b4 511 /* SCB Configuration Control Register Definitions */
emilmont 78:ed8466a608b4 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 78:ed8466a608b4 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 78:ed8466a608b4 514
emilmont 78:ed8466a608b4 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
emilmont 78:ed8466a608b4 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
emilmont 78:ed8466a608b4 517
emilmont 78:ed8466a608b4 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
emilmont 78:ed8466a608b4 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
emilmont 78:ed8466a608b4 520
emilmont 78:ed8466a608b4 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 78:ed8466a608b4 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 78:ed8466a608b4 523
emilmont 78:ed8466a608b4 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
emilmont 78:ed8466a608b4 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
emilmont 78:ed8466a608b4 526
emilmont 78:ed8466a608b4 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 110:165afa46840b 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
emilmont 78:ed8466a608b4 529
emilmont 78:ed8466a608b4 530 /* SCB System Handler Control and State Register Definitions */
emilmont 78:ed8466a608b4 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
emilmont 78:ed8466a608b4 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
emilmont 78:ed8466a608b4 533
emilmont 78:ed8466a608b4 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
emilmont 78:ed8466a608b4 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
emilmont 78:ed8466a608b4 536
emilmont 78:ed8466a608b4 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
emilmont 78:ed8466a608b4 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
emilmont 78:ed8466a608b4 539
emilmont 78:ed8466a608b4 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 78:ed8466a608b4 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 78:ed8466a608b4 542
emilmont 78:ed8466a608b4 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
emilmont 78:ed8466a608b4 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
emilmont 78:ed8466a608b4 545
emilmont 78:ed8466a608b4 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
emilmont 78:ed8466a608b4 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
emilmont 78:ed8466a608b4 548
emilmont 78:ed8466a608b4 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
emilmont 78:ed8466a608b4 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
emilmont 78:ed8466a608b4 551
emilmont 78:ed8466a608b4 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
emilmont 78:ed8466a608b4 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
emilmont 78:ed8466a608b4 554
emilmont 78:ed8466a608b4 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
emilmont 78:ed8466a608b4 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
emilmont 78:ed8466a608b4 557
emilmont 78:ed8466a608b4 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
emilmont 78:ed8466a608b4 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
emilmont 78:ed8466a608b4 560
emilmont 78:ed8466a608b4 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
emilmont 78:ed8466a608b4 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
emilmont 78:ed8466a608b4 563
emilmont 78:ed8466a608b4 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
emilmont 78:ed8466a608b4 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
emilmont 78:ed8466a608b4 566
emilmont 78:ed8466a608b4 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
emilmont 78:ed8466a608b4 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
emilmont 78:ed8466a608b4 569
emilmont 78:ed8466a608b4 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 110:165afa46840b 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
emilmont 78:ed8466a608b4 572
emilmont 78:ed8466a608b4 573 /* SCB Configurable Fault Status Registers Definitions */
emilmont 78:ed8466a608b4 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
emilmont 78:ed8466a608b4 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
emilmont 78:ed8466a608b4 576
emilmont 78:ed8466a608b4 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
emilmont 78:ed8466a608b4 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
emilmont 78:ed8466a608b4 579
emilmont 78:ed8466a608b4 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 110:165afa46840b 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
emilmont 78:ed8466a608b4 582
emilmont 78:ed8466a608b4 583 /* SCB Hard Fault Status Registers Definitions */
emilmont 78:ed8466a608b4 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
emilmont 78:ed8466a608b4 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
emilmont 78:ed8466a608b4 586
emilmont 78:ed8466a608b4 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
emilmont 78:ed8466a608b4 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
emilmont 78:ed8466a608b4 589
emilmont 78:ed8466a608b4 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
emilmont 78:ed8466a608b4 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
emilmont 78:ed8466a608b4 592
emilmont 78:ed8466a608b4 593 /* SCB Debug Fault Status Register Definitions */
emilmont 78:ed8466a608b4 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
emilmont 78:ed8466a608b4 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
emilmont 78:ed8466a608b4 596
emilmont 78:ed8466a608b4 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
emilmont 78:ed8466a608b4 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
emilmont 78:ed8466a608b4 599
emilmont 78:ed8466a608b4 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
emilmont 78:ed8466a608b4 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
emilmont 78:ed8466a608b4 602
emilmont 78:ed8466a608b4 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
emilmont 78:ed8466a608b4 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
emilmont 78:ed8466a608b4 605
emilmont 78:ed8466a608b4 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 110:165afa46840b 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
emilmont 78:ed8466a608b4 608
emilmont 78:ed8466a608b4 609 /*@} end of group CMSIS_SCB */
emilmont 78:ed8466a608b4 610
emilmont 78:ed8466a608b4 611
emilmont 78:ed8466a608b4 612 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont 78:ed8466a608b4 614 \brief Type definitions for the System Control and ID Register not in the SCB
emilmont 78:ed8466a608b4 615 @{
emilmont 78:ed8466a608b4 616 */
emilmont 78:ed8466a608b4 617
emilmont 78:ed8466a608b4 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont 78:ed8466a608b4 619 */
emilmont 78:ed8466a608b4 620 typedef struct
emilmont 78:ed8466a608b4 621 {
emilmont 78:ed8466a608b4 622 uint32_t RESERVED0[1];
emilmont 78:ed8466a608b4 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
emilmont 78:ed8466a608b4 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont 78:ed8466a608b4 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
emilmont 78:ed8466a608b4 626 #else
emilmont 78:ed8466a608b4 627 uint32_t RESERVED1[1];
emilmont 78:ed8466a608b4 628 #endif
emilmont 78:ed8466a608b4 629 } SCnSCB_Type;
emilmont 78:ed8466a608b4 630
emilmont 78:ed8466a608b4 631 /* Interrupt Controller Type Register Definitions */
emilmont 78:ed8466a608b4 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 110:165afa46840b 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
emilmont 78:ed8466a608b4 634
emilmont 78:ed8466a608b4 635 /* Auxiliary Control Register Definitions */
emilmont 78:ed8466a608b4 636
emilmont 78:ed8466a608b4 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
emilmont 78:ed8466a608b4 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
emilmont 78:ed8466a608b4 639
emilmont 78:ed8466a608b4 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
emilmont 78:ed8466a608b4 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
emilmont 78:ed8466a608b4 642
emilmont 78:ed8466a608b4 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 110:165afa46840b 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
emilmont 78:ed8466a608b4 645
emilmont 78:ed8466a608b4 646 /*@} end of group CMSIS_SCnotSCB */
emilmont 78:ed8466a608b4 647
emilmont 78:ed8466a608b4 648
emilmont 78:ed8466a608b4 649 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 78:ed8466a608b4 651 \brief Type definitions for the System Timer Registers.
emilmont 78:ed8466a608b4 652 @{
emilmont 78:ed8466a608b4 653 */
emilmont 78:ed8466a608b4 654
emilmont 78:ed8466a608b4 655 /** \brief Structure type to access the System Timer (SysTick).
emilmont 78:ed8466a608b4 656 */
emilmont 78:ed8466a608b4 657 typedef struct
emilmont 78:ed8466a608b4 658 {
emilmont 78:ed8466a608b4 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 78:ed8466a608b4 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 78:ed8466a608b4 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 78:ed8466a608b4 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 78:ed8466a608b4 663 } SysTick_Type;
emilmont 78:ed8466a608b4 664
emilmont 78:ed8466a608b4 665 /* SysTick Control / Status Register Definitions */
emilmont 78:ed8466a608b4 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 78:ed8466a608b4 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 78:ed8466a608b4 668
emilmont 78:ed8466a608b4 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 78:ed8466a608b4 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 78:ed8466a608b4 671
emilmont 78:ed8466a608b4 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 78:ed8466a608b4 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 78:ed8466a608b4 674
emilmont 78:ed8466a608b4 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 677
emilmont 78:ed8466a608b4 678 /* SysTick Reload Register Definitions */
emilmont 78:ed8466a608b4 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 78:ed8466a608b4 681
emilmont 78:ed8466a608b4 682 /* SysTick Current Register Definitions */
emilmont 78:ed8466a608b4 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 78:ed8466a608b4 685
emilmont 78:ed8466a608b4 686 /* SysTick Calibration Register Definitions */
emilmont 78:ed8466a608b4 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 78:ed8466a608b4 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 78:ed8466a608b4 689
emilmont 78:ed8466a608b4 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 78:ed8466a608b4 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 78:ed8466a608b4 692
emilmont 78:ed8466a608b4 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 78:ed8466a608b4 695
emilmont 78:ed8466a608b4 696 /*@} end of group CMSIS_SysTick */
emilmont 78:ed8466a608b4 697
emilmont 78:ed8466a608b4 698
emilmont 78:ed8466a608b4 699 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont 78:ed8466a608b4 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont 78:ed8466a608b4 702 @{
emilmont 78:ed8466a608b4 703 */
emilmont 78:ed8466a608b4 704
emilmont 78:ed8466a608b4 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont 78:ed8466a608b4 706 */
emilmont 78:ed8466a608b4 707 typedef struct
emilmont 78:ed8466a608b4 708 {
emilmont 78:ed8466a608b4 709 __O union
emilmont 78:ed8466a608b4 710 {
emilmont 78:ed8466a608b4 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
emilmont 78:ed8466a608b4 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
emilmont 78:ed8466a608b4 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
emilmont 78:ed8466a608b4 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
emilmont 78:ed8466a608b4 715 uint32_t RESERVED0[864];
emilmont 78:ed8466a608b4 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
emilmont 78:ed8466a608b4 717 uint32_t RESERVED1[15];
emilmont 78:ed8466a608b4 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
emilmont 78:ed8466a608b4 719 uint32_t RESERVED2[15];
emilmont 78:ed8466a608b4 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
emilmont 78:ed8466a608b4 721 uint32_t RESERVED3[29];
emilmont 78:ed8466a608b4 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
emilmont 78:ed8466a608b4 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
emilmont 78:ed8466a608b4 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
emilmont 78:ed8466a608b4 725 uint32_t RESERVED4[43];
emilmont 78:ed8466a608b4 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
emilmont 78:ed8466a608b4 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
emilmont 78:ed8466a608b4 728 uint32_t RESERVED5[6];
emilmont 78:ed8466a608b4 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
emilmont 78:ed8466a608b4 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
emilmont 78:ed8466a608b4 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
emilmont 78:ed8466a608b4 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
emilmont 78:ed8466a608b4 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
emilmont 78:ed8466a608b4 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
emilmont 78:ed8466a608b4 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
emilmont 78:ed8466a608b4 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
emilmont 78:ed8466a608b4 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
emilmont 78:ed8466a608b4 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
emilmont 78:ed8466a608b4 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
emilmont 78:ed8466a608b4 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
emilmont 78:ed8466a608b4 741 } ITM_Type;
emilmont 78:ed8466a608b4 742
emilmont 78:ed8466a608b4 743 /* ITM Trace Privilege Register Definitions */
emilmont 78:ed8466a608b4 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 110:165afa46840b 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
emilmont 78:ed8466a608b4 746
emilmont 78:ed8466a608b4 747 /* ITM Trace Control Register Definitions */
emilmont 78:ed8466a608b4 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
emilmont 78:ed8466a608b4 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
emilmont 78:ed8466a608b4 750
emilmont 78:ed8466a608b4 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
emilmont 78:ed8466a608b4 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
emilmont 78:ed8466a608b4 753
emilmont 78:ed8466a608b4 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
emilmont 78:ed8466a608b4 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
emilmont 78:ed8466a608b4 756
emilmont 78:ed8466a608b4 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
emilmont 78:ed8466a608b4 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
emilmont 78:ed8466a608b4 759
emilmont 78:ed8466a608b4 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
emilmont 78:ed8466a608b4 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
emilmont 78:ed8466a608b4 762
emilmont 78:ed8466a608b4 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
emilmont 78:ed8466a608b4 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
emilmont 78:ed8466a608b4 765
emilmont 78:ed8466a608b4 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
emilmont 78:ed8466a608b4 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
emilmont 78:ed8466a608b4 768
emilmont 78:ed8466a608b4 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
emilmont 78:ed8466a608b4 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
emilmont 78:ed8466a608b4 771
emilmont 78:ed8466a608b4 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 110:165afa46840b 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
emilmont 78:ed8466a608b4 774
emilmont 78:ed8466a608b4 775 /* ITM Integration Write Register Definitions */
emilmont 78:ed8466a608b4 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 110:165afa46840b 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
emilmont 78:ed8466a608b4 778
emilmont 78:ed8466a608b4 779 /* ITM Integration Read Register Definitions */
emilmont 78:ed8466a608b4 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 110:165afa46840b 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
emilmont 78:ed8466a608b4 782
emilmont 78:ed8466a608b4 783 /* ITM Integration Mode Control Register Definitions */
emilmont 78:ed8466a608b4 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 110:165afa46840b 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
emilmont 78:ed8466a608b4 786
emilmont 78:ed8466a608b4 787 /* ITM Lock Status Register Definitions */
emilmont 78:ed8466a608b4 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
emilmont 78:ed8466a608b4 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
emilmont 78:ed8466a608b4 790
emilmont 78:ed8466a608b4 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
emilmont 78:ed8466a608b4 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
emilmont 78:ed8466a608b4 793
emilmont 78:ed8466a608b4 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 110:165afa46840b 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
emilmont 78:ed8466a608b4 796
emilmont 78:ed8466a608b4 797 /*@}*/ /* end of group CMSIS_ITM */
emilmont 78:ed8466a608b4 798
emilmont 78:ed8466a608b4 799
emilmont 78:ed8466a608b4 800 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont 78:ed8466a608b4 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont 78:ed8466a608b4 803 @{
emilmont 78:ed8466a608b4 804 */
emilmont 78:ed8466a608b4 805
emilmont 78:ed8466a608b4 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont 78:ed8466a608b4 807 */
emilmont 78:ed8466a608b4 808 typedef struct
emilmont 78:ed8466a608b4 809 {
emilmont 78:ed8466a608b4 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
emilmont 78:ed8466a608b4 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
emilmont 78:ed8466a608b4 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
emilmont 78:ed8466a608b4 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
emilmont 78:ed8466a608b4 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
emilmont 78:ed8466a608b4 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
emilmont 78:ed8466a608b4 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
emilmont 78:ed8466a608b4 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
emilmont 78:ed8466a608b4 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
emilmont 78:ed8466a608b4 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
emilmont 78:ed8466a608b4 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
emilmont 78:ed8466a608b4 821 uint32_t RESERVED0[1];
emilmont 78:ed8466a608b4 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
emilmont 78:ed8466a608b4 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
emilmont 78:ed8466a608b4 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
emilmont 78:ed8466a608b4 825 uint32_t RESERVED1[1];
emilmont 78:ed8466a608b4 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
emilmont 78:ed8466a608b4 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
emilmont 78:ed8466a608b4 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
emilmont 78:ed8466a608b4 829 uint32_t RESERVED2[1];
emilmont 78:ed8466a608b4 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
emilmont 78:ed8466a608b4 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
emilmont 78:ed8466a608b4 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
emilmont 78:ed8466a608b4 833 } DWT_Type;
emilmont 78:ed8466a608b4 834
emilmont 78:ed8466a608b4 835 /* DWT Control Register Definitions */
emilmont 78:ed8466a608b4 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
emilmont 78:ed8466a608b4 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
emilmont 78:ed8466a608b4 838
emilmont 78:ed8466a608b4 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
emilmont 78:ed8466a608b4 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
emilmont 78:ed8466a608b4 841
emilmont 78:ed8466a608b4 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
emilmont 78:ed8466a608b4 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
emilmont 78:ed8466a608b4 844
emilmont 78:ed8466a608b4 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
emilmont 78:ed8466a608b4 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
emilmont 78:ed8466a608b4 847
emilmont 78:ed8466a608b4 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
emilmont 78:ed8466a608b4 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
emilmont 78:ed8466a608b4 850
emilmont 78:ed8466a608b4 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
emilmont 78:ed8466a608b4 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
emilmont 78:ed8466a608b4 853
emilmont 78:ed8466a608b4 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
emilmont 78:ed8466a608b4 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
emilmont 78:ed8466a608b4 856
emilmont 78:ed8466a608b4 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
emilmont 78:ed8466a608b4 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
emilmont 78:ed8466a608b4 859
emilmont 78:ed8466a608b4 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
emilmont 78:ed8466a608b4 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
emilmont 78:ed8466a608b4 862
emilmont 78:ed8466a608b4 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
emilmont 78:ed8466a608b4 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
emilmont 78:ed8466a608b4 865
emilmont 78:ed8466a608b4 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
emilmont 78:ed8466a608b4 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
emilmont 78:ed8466a608b4 868
emilmont 78:ed8466a608b4 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
emilmont 78:ed8466a608b4 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
emilmont 78:ed8466a608b4 871
emilmont 78:ed8466a608b4 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
emilmont 78:ed8466a608b4 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
emilmont 78:ed8466a608b4 874
emilmont 78:ed8466a608b4 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
emilmont 78:ed8466a608b4 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
emilmont 78:ed8466a608b4 877
emilmont 78:ed8466a608b4 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
emilmont 78:ed8466a608b4 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
emilmont 78:ed8466a608b4 880
emilmont 78:ed8466a608b4 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
emilmont 78:ed8466a608b4 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
emilmont 78:ed8466a608b4 883
emilmont 78:ed8466a608b4 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
emilmont 78:ed8466a608b4 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
emilmont 78:ed8466a608b4 886
emilmont 78:ed8466a608b4 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 110:165afa46840b 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
emilmont 78:ed8466a608b4 889
emilmont 78:ed8466a608b4 890 /* DWT CPI Count Register Definitions */
emilmont 78:ed8466a608b4 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 110:165afa46840b 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
emilmont 78:ed8466a608b4 893
emilmont 78:ed8466a608b4 894 /* DWT Exception Overhead Count Register Definitions */
emilmont 78:ed8466a608b4 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 110:165afa46840b 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
emilmont 78:ed8466a608b4 897
emilmont 78:ed8466a608b4 898 /* DWT Sleep Count Register Definitions */
emilmont 78:ed8466a608b4 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 110:165afa46840b 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
emilmont 78:ed8466a608b4 901
emilmont 78:ed8466a608b4 902 /* DWT LSU Count Register Definitions */
emilmont 78:ed8466a608b4 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 110:165afa46840b 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
emilmont 78:ed8466a608b4 905
emilmont 78:ed8466a608b4 906 /* DWT Folded-instruction Count Register Definitions */
emilmont 78:ed8466a608b4 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 110:165afa46840b 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
emilmont 78:ed8466a608b4 909
emilmont 78:ed8466a608b4 910 /* DWT Comparator Mask Register Definitions */
emilmont 78:ed8466a608b4 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 110:165afa46840b 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
emilmont 78:ed8466a608b4 913
emilmont 78:ed8466a608b4 914 /* DWT Comparator Function Register Definitions */
emilmont 78:ed8466a608b4 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
emilmont 78:ed8466a608b4 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
emilmont 78:ed8466a608b4 917
emilmont 78:ed8466a608b4 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
emilmont 78:ed8466a608b4 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
emilmont 78:ed8466a608b4 920
emilmont 78:ed8466a608b4 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
emilmont 78:ed8466a608b4 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
emilmont 78:ed8466a608b4 923
emilmont 78:ed8466a608b4 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
emilmont 78:ed8466a608b4 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
emilmont 78:ed8466a608b4 926
emilmont 78:ed8466a608b4 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
emilmont 78:ed8466a608b4 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
emilmont 78:ed8466a608b4 929
emilmont 78:ed8466a608b4 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
emilmont 78:ed8466a608b4 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
emilmont 78:ed8466a608b4 932
emilmont 78:ed8466a608b4 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
emilmont 78:ed8466a608b4 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
emilmont 78:ed8466a608b4 935
emilmont 78:ed8466a608b4 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
emilmont 78:ed8466a608b4 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
emilmont 78:ed8466a608b4 938
emilmont 78:ed8466a608b4 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 110:165afa46840b 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
emilmont 78:ed8466a608b4 941
emilmont 78:ed8466a608b4 942 /*@}*/ /* end of group CMSIS_DWT */
emilmont 78:ed8466a608b4 943
emilmont 78:ed8466a608b4 944
emilmont 78:ed8466a608b4 945 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont 78:ed8466a608b4 947 \brief Type definitions for the Trace Port Interface (TPI)
emilmont 78:ed8466a608b4 948 @{
emilmont 78:ed8466a608b4 949 */
emilmont 78:ed8466a608b4 950
emilmont 78:ed8466a608b4 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont 78:ed8466a608b4 952 */
emilmont 78:ed8466a608b4 953 typedef struct
emilmont 78:ed8466a608b4 954 {
emilmont 78:ed8466a608b4 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
emilmont 78:ed8466a608b4 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
emilmont 78:ed8466a608b4 957 uint32_t RESERVED0[2];
emilmont 78:ed8466a608b4 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
emilmont 78:ed8466a608b4 959 uint32_t RESERVED1[55];
emilmont 78:ed8466a608b4 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
emilmont 78:ed8466a608b4 961 uint32_t RESERVED2[131];
emilmont 78:ed8466a608b4 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
emilmont 78:ed8466a608b4 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
emilmont 78:ed8466a608b4 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
emilmont 78:ed8466a608b4 965 uint32_t RESERVED3[759];
emilmont 78:ed8466a608b4 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
emilmont 78:ed8466a608b4 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
emilmont 78:ed8466a608b4 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
emilmont 78:ed8466a608b4 969 uint32_t RESERVED4[1];
emilmont 78:ed8466a608b4 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
emilmont 78:ed8466a608b4 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
emilmont 78:ed8466a608b4 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
emilmont 78:ed8466a608b4 973 uint32_t RESERVED5[39];
emilmont 78:ed8466a608b4 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
emilmont 78:ed8466a608b4 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
emilmont 78:ed8466a608b4 976 uint32_t RESERVED7[8];
emilmont 78:ed8466a608b4 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
emilmont 78:ed8466a608b4 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
emilmont 78:ed8466a608b4 979 } TPI_Type;
emilmont 78:ed8466a608b4 980
emilmont 78:ed8466a608b4 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont 78:ed8466a608b4 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 110:165afa46840b 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
emilmont 78:ed8466a608b4 984
emilmont 78:ed8466a608b4 985 /* TPI Selected Pin Protocol Register Definitions */
emilmont 78:ed8466a608b4 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 110:165afa46840b 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
emilmont 78:ed8466a608b4 988
emilmont 78:ed8466a608b4 989 /* TPI Formatter and Flush Status Register Definitions */
emilmont 78:ed8466a608b4 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
emilmont 78:ed8466a608b4 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
emilmont 78:ed8466a608b4 992
emilmont 78:ed8466a608b4 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
emilmont 78:ed8466a608b4 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
emilmont 78:ed8466a608b4 995
emilmont 78:ed8466a608b4 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
emilmont 78:ed8466a608b4 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
emilmont 78:ed8466a608b4 998
emilmont 78:ed8466a608b4 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 110:165afa46840b 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
emilmont 78:ed8466a608b4 1001
emilmont 78:ed8466a608b4 1002 /* TPI Formatter and Flush Control Register Definitions */
emilmont 78:ed8466a608b4 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
emilmont 78:ed8466a608b4 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
emilmont 78:ed8466a608b4 1005
emilmont 78:ed8466a608b4 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
emilmont 78:ed8466a608b4 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
emilmont 78:ed8466a608b4 1008
emilmont 78:ed8466a608b4 1009 /* TPI TRIGGER Register Definitions */
emilmont 78:ed8466a608b4 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 110:165afa46840b 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
emilmont 78:ed8466a608b4 1012
emilmont 78:ed8466a608b4 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont 78:ed8466a608b4 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
emilmont 78:ed8466a608b4 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
emilmont 78:ed8466a608b4 1016
emilmont 78:ed8466a608b4 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
emilmont 78:ed8466a608b4 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
emilmont 78:ed8466a608b4 1019
emilmont 78:ed8466a608b4 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
emilmont 78:ed8466a608b4 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
emilmont 78:ed8466a608b4 1022
emilmont 78:ed8466a608b4 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
emilmont 78:ed8466a608b4 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
emilmont 78:ed8466a608b4 1025
emilmont 78:ed8466a608b4 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
emilmont 78:ed8466a608b4 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
emilmont 78:ed8466a608b4 1028
emilmont 78:ed8466a608b4 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
emilmont 78:ed8466a608b4 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
emilmont 78:ed8466a608b4 1031
emilmont 78:ed8466a608b4 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 110:165afa46840b 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
emilmont 78:ed8466a608b4 1034
emilmont 78:ed8466a608b4 1035 /* TPI ITATBCTR2 Register Definitions */
emilmont 78:ed8466a608b4 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 110:165afa46840b 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
emilmont 78:ed8466a608b4 1038
emilmont 78:ed8466a608b4 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont 78:ed8466a608b4 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
emilmont 78:ed8466a608b4 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
emilmont 78:ed8466a608b4 1042
emilmont 78:ed8466a608b4 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
emilmont 78:ed8466a608b4 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
emilmont 78:ed8466a608b4 1045
emilmont 78:ed8466a608b4 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
emilmont 78:ed8466a608b4 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
emilmont 78:ed8466a608b4 1048
emilmont 78:ed8466a608b4 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
emilmont 78:ed8466a608b4 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
emilmont 78:ed8466a608b4 1051
emilmont 78:ed8466a608b4 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
emilmont 78:ed8466a608b4 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
emilmont 78:ed8466a608b4 1054
emilmont 78:ed8466a608b4 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
emilmont 78:ed8466a608b4 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
emilmont 78:ed8466a608b4 1057
emilmont 78:ed8466a608b4 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 110:165afa46840b 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
emilmont 78:ed8466a608b4 1060
emilmont 78:ed8466a608b4 1061 /* TPI ITATBCTR0 Register Definitions */
emilmont 78:ed8466a608b4 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 110:165afa46840b 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
emilmont 78:ed8466a608b4 1064
emilmont 78:ed8466a608b4 1065 /* TPI Integration Mode Control Register Definitions */
emilmont 78:ed8466a608b4 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 110:165afa46840b 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
emilmont 78:ed8466a608b4 1068
emilmont 78:ed8466a608b4 1069 /* TPI DEVID Register Definitions */
emilmont 78:ed8466a608b4 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
emilmont 78:ed8466a608b4 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
emilmont 78:ed8466a608b4 1072
emilmont 78:ed8466a608b4 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
emilmont 78:ed8466a608b4 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
emilmont 78:ed8466a608b4 1075
emilmont 78:ed8466a608b4 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
emilmont 78:ed8466a608b4 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
emilmont 78:ed8466a608b4 1078
emilmont 78:ed8466a608b4 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
emilmont 78:ed8466a608b4 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
emilmont 78:ed8466a608b4 1081
emilmont 78:ed8466a608b4 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
emilmont 78:ed8466a608b4 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
emilmont 78:ed8466a608b4 1084
emilmont 78:ed8466a608b4 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 110:165afa46840b 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
emilmont 78:ed8466a608b4 1087
emilmont 78:ed8466a608b4 1088 /* TPI DEVTYPE Register Definitions */
emilmont 78:ed8466a608b4 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
emilmont 78:ed8466a608b4 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
emilmont 78:ed8466a608b4 1091
Kojto 110:165afa46840b 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 110:165afa46840b 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 110:165afa46840b 1094
emilmont 78:ed8466a608b4 1095 /*@}*/ /* end of group CMSIS_TPI */
emilmont 78:ed8466a608b4 1096
emilmont 78:ed8466a608b4 1097
emilmont 78:ed8466a608b4 1098 #if (__MPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1099 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 78:ed8466a608b4 1101 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 78:ed8466a608b4 1102 @{
emilmont 78:ed8466a608b4 1103 */
emilmont 78:ed8466a608b4 1104
emilmont 78:ed8466a608b4 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 78:ed8466a608b4 1106 */
emilmont 78:ed8466a608b4 1107 typedef struct
emilmont 78:ed8466a608b4 1108 {
emilmont 78:ed8466a608b4 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 78:ed8466a608b4 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 78:ed8466a608b4 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 78:ed8466a608b4 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 78:ed8466a608b4 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
emilmont 78:ed8466a608b4 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
emilmont 78:ed8466a608b4 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
emilmont 78:ed8466a608b4 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1120 } MPU_Type;
emilmont 78:ed8466a608b4 1121
emilmont 78:ed8466a608b4 1122 /* MPU Type Register */
emilmont 78:ed8466a608b4 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 78:ed8466a608b4 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 78:ed8466a608b4 1125
emilmont 78:ed8466a608b4 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 78:ed8466a608b4 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 78:ed8466a608b4 1128
emilmont 78:ed8466a608b4 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
emilmont 78:ed8466a608b4 1131
emilmont 78:ed8466a608b4 1132 /* MPU Control Register */
emilmont 78:ed8466a608b4 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 78:ed8466a608b4 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 78:ed8466a608b4 1135
emilmont 78:ed8466a608b4 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 78:ed8466a608b4 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 78:ed8466a608b4 1138
emilmont 78:ed8466a608b4 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 1141
emilmont 78:ed8466a608b4 1142 /* MPU Region Number Register */
emilmont 78:ed8466a608b4 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
emilmont 78:ed8466a608b4 1145
emilmont 78:ed8466a608b4 1146 /* MPU Region Base Address Register */
emilmont 78:ed8466a608b4 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
emilmont 78:ed8466a608b4 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 78:ed8466a608b4 1149
emilmont 78:ed8466a608b4 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 78:ed8466a608b4 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 78:ed8466a608b4 1152
emilmont 78:ed8466a608b4 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
emilmont 78:ed8466a608b4 1155
emilmont 78:ed8466a608b4 1156 /* MPU Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 78:ed8466a608b4 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 78:ed8466a608b4 1159
emilmont 78:ed8466a608b4 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 78:ed8466a608b4 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 78:ed8466a608b4 1162
emilmont 78:ed8466a608b4 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 78:ed8466a608b4 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 78:ed8466a608b4 1165
emilmont 78:ed8466a608b4 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 78:ed8466a608b4 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 78:ed8466a608b4 1168
emilmont 78:ed8466a608b4 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 78:ed8466a608b4 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 78:ed8466a608b4 1171
emilmont 78:ed8466a608b4 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 78:ed8466a608b4 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 78:ed8466a608b4 1174
emilmont 78:ed8466a608b4 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 78:ed8466a608b4 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 78:ed8466a608b4 1177
emilmont 78:ed8466a608b4 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 78:ed8466a608b4 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 78:ed8466a608b4 1180
emilmont 78:ed8466a608b4 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 78:ed8466a608b4 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 78:ed8466a608b4 1183
emilmont 78:ed8466a608b4 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 78:ed8466a608b4 1186
emilmont 78:ed8466a608b4 1187 /*@} end of group CMSIS_MPU */
emilmont 78:ed8466a608b4 1188 #endif
emilmont 78:ed8466a608b4 1189
emilmont 78:ed8466a608b4 1190
emilmont 78:ed8466a608b4 1191 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 78:ed8466a608b4 1193 \brief Type definitions for the Core Debug Registers
emilmont 78:ed8466a608b4 1194 @{
emilmont 78:ed8466a608b4 1195 */
emilmont 78:ed8466a608b4 1196
emilmont 78:ed8466a608b4 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont 78:ed8466a608b4 1198 */
emilmont 78:ed8466a608b4 1199 typedef struct
emilmont 78:ed8466a608b4 1200 {
emilmont 78:ed8466a608b4 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
emilmont 78:ed8466a608b4 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
emilmont 78:ed8466a608b4 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
emilmont 78:ed8466a608b4 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
emilmont 78:ed8466a608b4 1205 } CoreDebug_Type;
emilmont 78:ed8466a608b4 1206
emilmont 78:ed8466a608b4 1207 /* Debug Halting Control and Status Register */
emilmont 78:ed8466a608b4 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
emilmont 78:ed8466a608b4 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
emilmont 78:ed8466a608b4 1210
emilmont 78:ed8466a608b4 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
emilmont 78:ed8466a608b4 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
emilmont 78:ed8466a608b4 1213
emilmont 78:ed8466a608b4 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
emilmont 78:ed8466a608b4 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
emilmont 78:ed8466a608b4 1216
emilmont 78:ed8466a608b4 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
emilmont 78:ed8466a608b4 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
emilmont 78:ed8466a608b4 1219
emilmont 78:ed8466a608b4 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
emilmont 78:ed8466a608b4 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
emilmont 78:ed8466a608b4 1222
emilmont 78:ed8466a608b4 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
emilmont 78:ed8466a608b4 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
emilmont 78:ed8466a608b4 1225
emilmont 78:ed8466a608b4 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
emilmont 78:ed8466a608b4 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
emilmont 78:ed8466a608b4 1228
emilmont 78:ed8466a608b4 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
emilmont 78:ed8466a608b4 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
emilmont 78:ed8466a608b4 1231
emilmont 78:ed8466a608b4 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
emilmont 78:ed8466a608b4 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
emilmont 78:ed8466a608b4 1234
emilmont 78:ed8466a608b4 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
emilmont 78:ed8466a608b4 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
emilmont 78:ed8466a608b4 1237
emilmont 78:ed8466a608b4 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
emilmont 78:ed8466a608b4 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
emilmont 78:ed8466a608b4 1240
emilmont 78:ed8466a608b4 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 110:165afa46840b 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
emilmont 78:ed8466a608b4 1243
emilmont 78:ed8466a608b4 1244 /* Debug Core Register Selector Register */
emilmont 78:ed8466a608b4 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
emilmont 78:ed8466a608b4 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
emilmont 78:ed8466a608b4 1247
emilmont 78:ed8466a608b4 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 110:165afa46840b 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
emilmont 78:ed8466a608b4 1250
emilmont 78:ed8466a608b4 1251 /* Debug Exception and Monitor Control Register */
emilmont 78:ed8466a608b4 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
emilmont 78:ed8466a608b4 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
emilmont 78:ed8466a608b4 1254
emilmont 78:ed8466a608b4 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
emilmont 78:ed8466a608b4 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
emilmont 78:ed8466a608b4 1257
emilmont 78:ed8466a608b4 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
emilmont 78:ed8466a608b4 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
emilmont 78:ed8466a608b4 1260
emilmont 78:ed8466a608b4 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
emilmont 78:ed8466a608b4 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
emilmont 78:ed8466a608b4 1263
emilmont 78:ed8466a608b4 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
emilmont 78:ed8466a608b4 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
emilmont 78:ed8466a608b4 1266
emilmont 78:ed8466a608b4 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
emilmont 78:ed8466a608b4 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
emilmont 78:ed8466a608b4 1269
emilmont 78:ed8466a608b4 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
emilmont 78:ed8466a608b4 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
emilmont 78:ed8466a608b4 1272
emilmont 78:ed8466a608b4 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
emilmont 78:ed8466a608b4 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
emilmont 78:ed8466a608b4 1275
emilmont 78:ed8466a608b4 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
emilmont 78:ed8466a608b4 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
emilmont 78:ed8466a608b4 1278
emilmont 78:ed8466a608b4 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
emilmont 78:ed8466a608b4 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
emilmont 78:ed8466a608b4 1281
emilmont 78:ed8466a608b4 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
emilmont 78:ed8466a608b4 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
emilmont 78:ed8466a608b4 1284
emilmont 78:ed8466a608b4 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
emilmont 78:ed8466a608b4 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
emilmont 78:ed8466a608b4 1287
emilmont 78:ed8466a608b4 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 110:165afa46840b 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
emilmont 78:ed8466a608b4 1290
emilmont 78:ed8466a608b4 1291 /*@} end of group CMSIS_CoreDebug */
emilmont 78:ed8466a608b4 1292
emilmont 78:ed8466a608b4 1293
emilmont 78:ed8466a608b4 1294 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1295 \defgroup CMSIS_core_base Core Definitions
emilmont 78:ed8466a608b4 1296 \brief Definitions for base addresses, unions, and structures.
emilmont 78:ed8466a608b4 1297 @{
emilmont 78:ed8466a608b4 1298 */
emilmont 78:ed8466a608b4 1299
emilmont 78:ed8466a608b4 1300 /* Memory mapping of Cortex-M3 Hardware */
emilmont 78:ed8466a608b4 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 78:ed8466a608b4 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
emilmont 78:ed8466a608b4 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
emilmont 78:ed8466a608b4 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
emilmont 78:ed8466a608b4 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
emilmont 78:ed8466a608b4 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 78:ed8466a608b4 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 78:ed8466a608b4 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 78:ed8466a608b4 1309
emilmont 78:ed8466a608b4 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
emilmont 78:ed8466a608b4 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 78:ed8466a608b4 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 78:ed8466a608b4 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 78:ed8466a608b4 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
emilmont 78:ed8466a608b4 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
emilmont 78:ed8466a608b4 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
emilmont 78:ed8466a608b4 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
emilmont 78:ed8466a608b4 1318
emilmont 78:ed8466a608b4 1319 #if (__MPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 78:ed8466a608b4 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 78:ed8466a608b4 1322 #endif
emilmont 78:ed8466a608b4 1323
emilmont 78:ed8466a608b4 1324 /*@} */
emilmont 78:ed8466a608b4 1325
emilmont 78:ed8466a608b4 1326
emilmont 78:ed8466a608b4 1327
emilmont 78:ed8466a608b4 1328 /*******************************************************************************
emilmont 78:ed8466a608b4 1329 * Hardware Abstraction Layer
emilmont 78:ed8466a608b4 1330 Core Function Interface contains:
emilmont 78:ed8466a608b4 1331 - Core NVIC Functions
emilmont 78:ed8466a608b4 1332 - Core SysTick Functions
emilmont 78:ed8466a608b4 1333 - Core Debug Functions
emilmont 78:ed8466a608b4 1334 - Core Register Access Functions
emilmont 78:ed8466a608b4 1335 ******************************************************************************/
emilmont 78:ed8466a608b4 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 78:ed8466a608b4 1337 */
emilmont 78:ed8466a608b4 1338
emilmont 78:ed8466a608b4 1339
emilmont 78:ed8466a608b4 1340
emilmont 78:ed8466a608b4 1341 /* ########################## NVIC functions #################################### */
emilmont 78:ed8466a608b4 1342 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 78:ed8466a608b4 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 78:ed8466a608b4 1345 @{
emilmont 78:ed8466a608b4 1346 */
emilmont 78:ed8466a608b4 1347
<> 127:25aea2a3f4e3 1348 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1351 #endif
<> 127:25aea2a3f4e3 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1353 #else
<> 127:25aea2a3f4e3 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 127:25aea2a3f4e3 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1361 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1362 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1363 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1364 #define NVIC_SystemReset __NVIC_SystemReset
<> 127:25aea2a3f4e3 1365 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1366
<> 127:25aea2a3f4e3 1367 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1370 #endif
<> 127:25aea2a3f4e3 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1372 #else
<> 127:25aea2a3f4e3 1373 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1374 #define NVIC_GetVector __NVIC_GetVector
<> 127:25aea2a3f4e3 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 127:25aea2a3f4e3 1376
emilmont 78:ed8466a608b4 1377 /** \brief Set Priority Grouping
emilmont 78:ed8466a608b4 1378
emilmont 78:ed8466a608b4 1379 The function sets the priority grouping field using the required unlock sequence.
emilmont 78:ed8466a608b4 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont 78:ed8466a608b4 1381 Only values from 0..7 are used.
emilmont 78:ed8466a608b4 1382 In case of a conflict between priority grouping and available
emilmont 78:ed8466a608b4 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1384
emilmont 78:ed8466a608b4 1385 \param [in] PriorityGroup Priority grouping field.
emilmont 78:ed8466a608b4 1386 */
<> 127:25aea2a3f4e3 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont 78:ed8466a608b4 1388 {
emilmont 78:ed8466a608b4 1389 uint32_t reg_value;
Kojto 110:165afa46840b 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1391
emilmont 78:ed8466a608b4 1392 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 110:165afa46840b 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 110:165afa46840b 1394 reg_value = (reg_value |
Kojto 110:165afa46840b 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
emilmont 78:ed8466a608b4 1397 SCB->AIRCR = reg_value;
emilmont 78:ed8466a608b4 1398 }
emilmont 78:ed8466a608b4 1399
emilmont 78:ed8466a608b4 1400
emilmont 78:ed8466a608b4 1401 /** \brief Get Priority Grouping
emilmont 78:ed8466a608b4 1402
emilmont 78:ed8466a608b4 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont 78:ed8466a608b4 1404
emilmont 78:ed8466a608b4 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont 78:ed8466a608b4 1406 */
<> 127:25aea2a3f4e3 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
emilmont 78:ed8466a608b4 1408 {
Kojto 110:165afa46840b 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
emilmont 78:ed8466a608b4 1410 }
emilmont 78:ed8466a608b4 1411
emilmont 78:ed8466a608b4 1412
emilmont 78:ed8466a608b4 1413 /** \brief Enable External Interrupt
emilmont 78:ed8466a608b4 1414
emilmont 78:ed8466a608b4 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 1416
emilmont 78:ed8466a608b4 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1418 */
<> 127:25aea2a3f4e3 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1420 {
Kojto 110:165afa46840b 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1422 }
emilmont 78:ed8466a608b4 1423
emilmont 78:ed8466a608b4 1424
emilmont 78:ed8466a608b4 1425 /** \brief Disable External Interrupt
emilmont 78:ed8466a608b4 1426
emilmont 78:ed8466a608b4 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 1428
emilmont 78:ed8466a608b4 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1430 */
<> 127:25aea2a3f4e3 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1432 {
Kojto 110:165afa46840b 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1434 __DSB();
<> 131:faff56e089b2 1435 __ISB();
emilmont 78:ed8466a608b4 1436 }
emilmont 78:ed8466a608b4 1437
emilmont 78:ed8466a608b4 1438
emilmont 78:ed8466a608b4 1439 /** \brief Get Pending Interrupt
emilmont 78:ed8466a608b4 1440
emilmont 78:ed8466a608b4 1441 The function reads the pending register in the NVIC and returns the pending bit
emilmont 78:ed8466a608b4 1442 for the specified interrupt.
emilmont 78:ed8466a608b4 1443
emilmont 78:ed8466a608b4 1444 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1445
emilmont 78:ed8466a608b4 1446 \return 0 Interrupt status is not pending.
emilmont 78:ed8466a608b4 1447 \return 1 Interrupt status is pending.
emilmont 78:ed8466a608b4 1448 */
<> 127:25aea2a3f4e3 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1450 {
Kojto 110:165afa46840b 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 78:ed8466a608b4 1452 }
emilmont 78:ed8466a608b4 1453
emilmont 78:ed8466a608b4 1454
emilmont 78:ed8466a608b4 1455 /** \brief Set Pending Interrupt
emilmont 78:ed8466a608b4 1456
emilmont 78:ed8466a608b4 1457 The function sets the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 1458
emilmont 78:ed8466a608b4 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1460 */
<> 127:25aea2a3f4e3 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1462 {
Kojto 110:165afa46840b 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1464 }
emilmont 78:ed8466a608b4 1465
emilmont 78:ed8466a608b4 1466
emilmont 78:ed8466a608b4 1467 /** \brief Clear Pending Interrupt
emilmont 78:ed8466a608b4 1468
emilmont 78:ed8466a608b4 1469 The function clears the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 1470
emilmont 78:ed8466a608b4 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1472 */
<> 127:25aea2a3f4e3 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1474 {
Kojto 110:165afa46840b 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1476 }
emilmont 78:ed8466a608b4 1477
emilmont 78:ed8466a608b4 1478
emilmont 78:ed8466a608b4 1479 /** \brief Get Active Interrupt
emilmont 78:ed8466a608b4 1480
emilmont 78:ed8466a608b4 1481 The function reads the active register in NVIC and returns the active bit.
emilmont 78:ed8466a608b4 1482
emilmont 78:ed8466a608b4 1483 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1484
emilmont 78:ed8466a608b4 1485 \return 0 Interrupt status is not active.
emilmont 78:ed8466a608b4 1486 \return 1 Interrupt status is active.
emilmont 78:ed8466a608b4 1487 */
<> 127:25aea2a3f4e3 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1489 {
Kojto 110:165afa46840b 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 78:ed8466a608b4 1491 }
emilmont 78:ed8466a608b4 1492
emilmont 78:ed8466a608b4 1493
emilmont 78:ed8466a608b4 1494 /** \brief Set Interrupt Priority
emilmont 78:ed8466a608b4 1495
emilmont 78:ed8466a608b4 1496 The function sets the priority of an interrupt.
emilmont 78:ed8466a608b4 1497
emilmont 78:ed8466a608b4 1498 \note The priority cannot be set for every core interrupt.
emilmont 78:ed8466a608b4 1499
emilmont 78:ed8466a608b4 1500 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1501 \param [in] priority Priority to set.
emilmont 78:ed8466a608b4 1502 */
<> 127:25aea2a3f4e3 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 78:ed8466a608b4 1504 {
Kojto 110:165afa46840b 1505 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1507 }
emilmont 78:ed8466a608b4 1508 else {
Kojto 110:165afa46840b 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1510 }
emilmont 78:ed8466a608b4 1511 }
emilmont 78:ed8466a608b4 1512
emilmont 78:ed8466a608b4 1513
emilmont 78:ed8466a608b4 1514 /** \brief Get Interrupt Priority
emilmont 78:ed8466a608b4 1515
emilmont 78:ed8466a608b4 1516 The function reads the priority of an interrupt. The interrupt
emilmont 78:ed8466a608b4 1517 number can be positive to specify an external (device specific)
emilmont 78:ed8466a608b4 1518 interrupt, or negative to specify an internal (core) interrupt.
emilmont 78:ed8466a608b4 1519
emilmont 78:ed8466a608b4 1520
emilmont 78:ed8466a608b4 1521 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 78:ed8466a608b4 1523 priority bits of the microcontroller.
emilmont 78:ed8466a608b4 1524 */
<> 127:25aea2a3f4e3 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1526 {
emilmont 78:ed8466a608b4 1527
Kojto 110:165afa46840b 1528 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1530 }
emilmont 78:ed8466a608b4 1531 else {
Kojto 110:165afa46840b 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1533 }
emilmont 78:ed8466a608b4 1534 }
emilmont 78:ed8466a608b4 1535
emilmont 78:ed8466a608b4 1536
emilmont 78:ed8466a608b4 1537 /** \brief Encode Priority
emilmont 78:ed8466a608b4 1538
emilmont 78:ed8466a608b4 1539 The function encodes the priority for an interrupt with the given priority group,
emilmont 78:ed8466a608b4 1540 preemptive priority value, and subpriority value.
emilmont 78:ed8466a608b4 1541 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1543
emilmont 78:ed8466a608b4 1544 \param [in] PriorityGroup Used priority group.
emilmont 78:ed8466a608b4 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont 78:ed8466a608b4 1546 \param [in] SubPriority Subpriority value (starting from 0).
emilmont 78:ed8466a608b4 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont 78:ed8466a608b4 1548 */
emilmont 78:ed8466a608b4 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont 78:ed8466a608b4 1550 {
Kojto 110:165afa46840b 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1552 uint32_t PreemptPriorityBits;
emilmont 78:ed8466a608b4 1553 uint32_t SubPriorityBits;
emilmont 78:ed8466a608b4 1554
Kojto 110:165afa46840b 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont 78:ed8466a608b4 1557
emilmont 78:ed8466a608b4 1558 return (
Kojto 110:165afa46840b 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 110:165afa46840b 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
emilmont 78:ed8466a608b4 1561 );
emilmont 78:ed8466a608b4 1562 }
emilmont 78:ed8466a608b4 1563
emilmont 78:ed8466a608b4 1564
emilmont 78:ed8466a608b4 1565 /** \brief Decode Priority
emilmont 78:ed8466a608b4 1566
emilmont 78:ed8466a608b4 1567 The function decodes an interrupt priority value with a given priority group to
emilmont 78:ed8466a608b4 1568 preemptive priority value and subpriority value.
emilmont 78:ed8466a608b4 1569 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1571
emilmont 78:ed8466a608b4 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont 78:ed8466a608b4 1573 \param [in] PriorityGroup Used priority group.
emilmont 78:ed8466a608b4 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont 78:ed8466a608b4 1575 \param [out] pSubPriority Subpriority value (starting from 0).
emilmont 78:ed8466a608b4 1576 */
emilmont 78:ed8466a608b4 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont 78:ed8466a608b4 1578 {
Kojto 110:165afa46840b 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1580 uint32_t PreemptPriorityBits;
emilmont 78:ed8466a608b4 1581 uint32_t SubPriorityBits;
emilmont 78:ed8466a608b4 1582
Kojto 110:165afa46840b 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont 78:ed8466a608b4 1585
Kojto 110:165afa46840b 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 110:165afa46840b 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
emilmont 78:ed8466a608b4 1588 }
emilmont 78:ed8466a608b4 1589
emilmont 78:ed8466a608b4 1590
emilmont 78:ed8466a608b4 1591 /** \brief System Reset
emilmont 78:ed8466a608b4 1592
emilmont 78:ed8466a608b4 1593 The function initiates a system reset request to reset the MCU.
emilmont 78:ed8466a608b4 1594 */
<> 128:9bcdf88f62b0 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
emilmont 78:ed8466a608b4 1596 {
Kojto 110:165afa46840b 1597 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 110:165afa46840b 1598 buffered write are completed before reset */
Kojto 110:165afa46840b 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 110:165afa46840b 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 110:165afa46840b 1602 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 1603 while(1) { __NOP(); } /* wait until reset */
emilmont 78:ed8466a608b4 1604 }
emilmont 78:ed8466a608b4 1605
emilmont 78:ed8466a608b4 1606 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 78:ed8466a608b4 1607
emilmont 78:ed8466a608b4 1608
emilmont 78:ed8466a608b4 1609
emilmont 78:ed8466a608b4 1610 /* ################################## SysTick function ############################################ */
emilmont 78:ed8466a608b4 1611 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 78:ed8466a608b4 1613 \brief Functions that configure the System.
emilmont 78:ed8466a608b4 1614 @{
emilmont 78:ed8466a608b4 1615 */
emilmont 78:ed8466a608b4 1616
emilmont 78:ed8466a608b4 1617 #if (__Vendor_SysTickConfig == 0)
emilmont 78:ed8466a608b4 1618
emilmont 78:ed8466a608b4 1619 /** \brief System Tick Configuration
emilmont 78:ed8466a608b4 1620
emilmont 78:ed8466a608b4 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 78:ed8466a608b4 1622 Counter is in free running mode to generate periodic interrupts.
emilmont 78:ed8466a608b4 1623
emilmont 78:ed8466a608b4 1624 \param [in] ticks Number of ticks between two interrupts.
emilmont 78:ed8466a608b4 1625
emilmont 78:ed8466a608b4 1626 \return 0 Function succeeded.
emilmont 78:ed8466a608b4 1627 \return 1 Function failed.
emilmont 78:ed8466a608b4 1628
emilmont 78:ed8466a608b4 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 78:ed8466a608b4 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 78:ed8466a608b4 1631 must contain a vendor-specific implementation of this function.
emilmont 78:ed8466a608b4 1632
emilmont 78:ed8466a608b4 1633 */
emilmont 78:ed8466a608b4 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 78:ed8466a608b4 1635 {
Kojto 110:165afa46840b 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont 78:ed8466a608b4 1637
Kojto 110:165afa46840b 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 78:ed8466a608b4 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 78:ed8466a608b4 1642 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 1644 return (0UL); /* Function successful */
emilmont 78:ed8466a608b4 1645 }
emilmont 78:ed8466a608b4 1646
emilmont 78:ed8466a608b4 1647 #endif
emilmont 78:ed8466a608b4 1648
emilmont 78:ed8466a608b4 1649 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 78:ed8466a608b4 1650
emilmont 78:ed8466a608b4 1651
emilmont 78:ed8466a608b4 1652
emilmont 78:ed8466a608b4 1653 /* ##################################### Debug In/Output function ########################################### */
emilmont 78:ed8466a608b4 1654 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont 78:ed8466a608b4 1656 \brief Functions that access the ITM debug interface.
emilmont 78:ed8466a608b4 1657 @{
emilmont 78:ed8466a608b4 1658 */
emilmont 78:ed8466a608b4 1659
emilmont 78:ed8466a608b4 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
emilmont 78:ed8466a608b4 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
emilmont 78:ed8466a608b4 1662
emilmont 78:ed8466a608b4 1663
emilmont 78:ed8466a608b4 1664 /** \brief ITM Send Character
emilmont 78:ed8466a608b4 1665
emilmont 78:ed8466a608b4 1666 The function transmits a character via the ITM channel 0, and
emilmont 78:ed8466a608b4 1667 \li Just returns when no debugger is connected that has booked the output.
emilmont 78:ed8466a608b4 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont 78:ed8466a608b4 1669
emilmont 78:ed8466a608b4 1670 \param [in] ch Character to transmit.
emilmont 78:ed8466a608b4 1671
emilmont 78:ed8466a608b4 1672 \returns Character to transmit.
emilmont 78:ed8466a608b4 1673 */
emilmont 78:ed8466a608b4 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont 78:ed8466a608b4 1675 {
Kojto 110:165afa46840b 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 110:165afa46840b 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
emilmont 78:ed8466a608b4 1678 {
Kojto 110:165afa46840b 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 110:165afa46840b 1680 ITM->PORT[0].u8 = (uint8_t)ch;
emilmont 78:ed8466a608b4 1681 }
emilmont 78:ed8466a608b4 1682 return (ch);
emilmont 78:ed8466a608b4 1683 }
emilmont 78:ed8466a608b4 1684
emilmont 78:ed8466a608b4 1685
emilmont 78:ed8466a608b4 1686 /** \brief ITM Receive Character
emilmont 78:ed8466a608b4 1687
emilmont 78:ed8466a608b4 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont 78:ed8466a608b4 1689
emilmont 78:ed8466a608b4 1690 \return Received character.
emilmont 78:ed8466a608b4 1691 \return -1 No character pending.
emilmont 78:ed8466a608b4 1692 */
emilmont 78:ed8466a608b4 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont 78:ed8466a608b4 1694 int32_t ch = -1; /* no character available */
emilmont 78:ed8466a608b4 1695
emilmont 78:ed8466a608b4 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont 78:ed8466a608b4 1697 ch = ITM_RxBuffer;
emilmont 78:ed8466a608b4 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont 78:ed8466a608b4 1699 }
emilmont 78:ed8466a608b4 1700
emilmont 78:ed8466a608b4 1701 return (ch);
emilmont 78:ed8466a608b4 1702 }
emilmont 78:ed8466a608b4 1703
emilmont 78:ed8466a608b4 1704
emilmont 78:ed8466a608b4 1705 /** \brief ITM Check Character
emilmont 78:ed8466a608b4 1706
emilmont 78:ed8466a608b4 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont 78:ed8466a608b4 1708
emilmont 78:ed8466a608b4 1709 \return 0 No character available.
emilmont 78:ed8466a608b4 1710 \return 1 Character available.
emilmont 78:ed8466a608b4 1711 */
emilmont 78:ed8466a608b4 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont 78:ed8466a608b4 1713
emilmont 78:ed8466a608b4 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont 78:ed8466a608b4 1715 return (0); /* no character available */
emilmont 78:ed8466a608b4 1716 } else {
emilmont 78:ed8466a608b4 1717 return (1); /* character available */
emilmont 78:ed8466a608b4 1718 }
emilmont 78:ed8466a608b4 1719 }
emilmont 78:ed8466a608b4 1720
emilmont 78:ed8466a608b4 1721 /*@} end of CMSIS_core_DebugFunctions */
emilmont 78:ed8466a608b4 1722
emilmont 78:ed8466a608b4 1723
Kojto 110:165afa46840b 1724
emilmont 78:ed8466a608b4 1725
emilmont 78:ed8466a608b4 1726 #ifdef __cplusplus
emilmont 78:ed8466a608b4 1727 }
emilmont 78:ed8466a608b4 1728 #endif
Kojto 110:165afa46840b 1729
Kojto 110:165afa46840b 1730 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 110:165afa46840b 1731
Kojto 110:165afa46840b 1732 #endif /* __CMSIS_GENERIC */